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1// SPDX-License-Identifier: GPL-2.0-only2/*3 * ALSA SoC TWL4030 codec driver4 *5 * Author: Steve Sakoman, <steve@sakoman.com>6 */7 8#include <linux/module.h>9#include <linux/moduleparam.h>10#include <linux/init.h>11#include <linux/delay.h>12#include <linux/pm.h>13#include <linux/i2c.h>14#include <linux/platform_device.h>15#include <linux/of.h>16#include <linux/of_gpio.h>17#include <linux/mfd/twl.h>18#include <linux/slab.h>19#include <linux/gpio.h>20#include <sound/core.h>21#include <sound/pcm.h>22#include <sound/pcm_params.h>23#include <sound/soc.h>24#include <sound/initval.h>25#include <sound/tlv.h>26 27/* Register descriptions are here */28#include <linux/mfd/twl4030-audio.h>29 30/* TWL4030 PMBR1 Register */31#define TWL4030_PMBR1_REG 0x0D32/* TWL4030 PMBR1 Register GPIO6 mux bits */33#define TWL4030_GPIO6_PWM0_MUTE(value) ((value & 0x03) << 2)34 35#define TWL4030_CACHEREGNUM (TWL4030_REG_MISC_SET_2 + 1)36 37struct twl4030_board_params {38 unsigned int digimic_delay; /* in ms */39 unsigned int ramp_delay_value;40 unsigned int offset_cncl_path;41 unsigned int hs_extmute:1;42 int hs_extmute_gpio;43};44 45/* codec private data */46struct twl4030_priv {47 unsigned int codec_powered;48 49 /* reference counts of AIF/APLL users */50 unsigned int apll_enabled;51 52 struct snd_pcm_substream *master_substream;53 struct snd_pcm_substream *slave_substream;54 55 unsigned int configured;56 unsigned int rate;57 unsigned int sample_bits;58 unsigned int channels;59 60 unsigned int sysclk;61 62 /* Output (with associated amp) states */63 u8 hsl_enabled, hsr_enabled;64 u8 earpiece_enabled;65 u8 predrivel_enabled, predriver_enabled;66 u8 carkitl_enabled, carkitr_enabled;67 u8 ctl_cache[TWL4030_REG_PRECKR_CTL - TWL4030_REG_EAR_CTL + 1];68 69 struct twl4030_board_params *board_params;70};71 72static void tw4030_init_ctl_cache(struct twl4030_priv *twl4030)73{74 int i;75 u8 byte;76 77 for (i = TWL4030_REG_EAR_CTL; i <= TWL4030_REG_PRECKR_CTL; i++) {78 twl_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE, &byte, i);79 twl4030->ctl_cache[i - TWL4030_REG_EAR_CTL] = byte;80 }81}82 83static unsigned int twl4030_read(struct snd_soc_component *component, unsigned int reg)84{85 struct twl4030_priv *twl4030 = snd_soc_component_get_drvdata(component);86 u8 value = 0;87 88 if (reg >= TWL4030_CACHEREGNUM)89 return -EIO;90 91 switch (reg) {92 case TWL4030_REG_EAR_CTL:93 case TWL4030_REG_PREDL_CTL:94 case TWL4030_REG_PREDR_CTL:95 case TWL4030_REG_PRECKL_CTL:96 case TWL4030_REG_PRECKR_CTL:97 case TWL4030_REG_HS_GAIN_SET:98 value = twl4030->ctl_cache[reg - TWL4030_REG_EAR_CTL];99 break;100 default:101 twl_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE, &value, reg);102 break;103 }104 105 return value;106}107 108static bool twl4030_can_write_to_chip(struct twl4030_priv *twl4030,109 unsigned int reg)110{111 bool write_to_reg = false;112 113 /* Decide if the given register can be written */114 switch (reg) {115 case TWL4030_REG_EAR_CTL:116 if (twl4030->earpiece_enabled)117 write_to_reg = true;118 break;119 case TWL4030_REG_PREDL_CTL:120 if (twl4030->predrivel_enabled)121 write_to_reg = true;122 break;123 case TWL4030_REG_PREDR_CTL:124 if (twl4030->predriver_enabled)125 write_to_reg = true;126 break;127 case TWL4030_REG_PRECKL_CTL:128 if (twl4030->carkitl_enabled)129 write_to_reg = true;130 break;131 case TWL4030_REG_PRECKR_CTL:132 if (twl4030->carkitr_enabled)133 write_to_reg = true;134 break;135 case TWL4030_REG_HS_GAIN_SET:136 if (twl4030->hsl_enabled || twl4030->hsr_enabled)137 write_to_reg = true;138 break;139 default:140 /* All other register can be written */141 write_to_reg = true;142 break;143 }144 145 return write_to_reg;146}147 148static int twl4030_write(struct snd_soc_component *component, unsigned int reg,149 unsigned int value)150{151 struct twl4030_priv *twl4030 = snd_soc_component_get_drvdata(component);152 153 /* Update the ctl cache */154 switch (reg) {155 case TWL4030_REG_EAR_CTL:156 case TWL4030_REG_PREDL_CTL:157 case TWL4030_REG_PREDR_CTL:158 case TWL4030_REG_PRECKL_CTL:159 case TWL4030_REG_PRECKR_CTL:160 case TWL4030_REG_HS_GAIN_SET:161 twl4030->ctl_cache[reg - TWL4030_REG_EAR_CTL] = value;162 break;163 default:164 break;165 }166 167 if (twl4030_can_write_to_chip(twl4030, reg))168 return twl_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, value, reg);169 170 return 0;171}172 173static inline void twl4030_wait_ms(int time)174{175 if (time < 60) {176 time *= 1000;177 usleep_range(time, time + 500);178 } else {179 msleep(time);180 }181}182 183static void twl4030_codec_enable(struct snd_soc_component *component, int enable)184{185 struct twl4030_priv *twl4030 = snd_soc_component_get_drvdata(component);186 int mode;187 188 if (enable == twl4030->codec_powered)189 return;190 191 if (enable)192 mode = twl4030_audio_enable_resource(TWL4030_AUDIO_RES_POWER);193 else194 mode = twl4030_audio_disable_resource(TWL4030_AUDIO_RES_POWER);195 196 if (mode >= 0)197 twl4030->codec_powered = enable;198 199 /* REVISIT: this delay is present in TI sample drivers */200 /* but there seems to be no TRM requirement for it */201 udelay(10);202}203 204static void205twl4030_get_board_param_values(struct twl4030_board_params *board_params,206 struct device_node *node)207{208 int value;209 210 of_property_read_u32(node, "ti,digimic_delay", &board_params->digimic_delay);211 of_property_read_u32(node, "ti,ramp_delay_value", &board_params->ramp_delay_value);212 of_property_read_u32(node, "ti,offset_cncl_path", &board_params->offset_cncl_path);213 if (!of_property_read_u32(node, "ti,hs_extmute", &value))214 board_params->hs_extmute = value;215 216 board_params->hs_extmute_gpio = of_get_named_gpio(node, "ti,hs_extmute_gpio", 0);217 if (gpio_is_valid(board_params->hs_extmute_gpio))218 board_params->hs_extmute = 1;219}220 221static struct twl4030_board_params*222twl4030_get_board_params(struct snd_soc_component *component)223{224 struct twl4030_board_params *board_params = NULL;225 struct device_node *twl4030_codec_node = NULL;226 227 twl4030_codec_node = of_get_child_by_name(component->dev->parent->of_node,228 "codec");229 230 if (twl4030_codec_node) {231 board_params = devm_kzalloc(component->dev,232 sizeof(struct twl4030_board_params),233 GFP_KERNEL);234 if (!board_params) {235 of_node_put(twl4030_codec_node);236 return NULL;237 }238 twl4030_get_board_param_values(board_params, twl4030_codec_node);239 of_node_put(twl4030_codec_node);240 }241 242 return board_params;243}244 245static void twl4030_init_chip(struct snd_soc_component *component)246{247 struct twl4030_board_params *board_params;248 struct twl4030_priv *twl4030 = snd_soc_component_get_drvdata(component);249 u8 reg, byte;250 int i = 0;251 252 board_params = twl4030_get_board_params(component);253 254 if (board_params && board_params->hs_extmute) {255 if (gpio_is_valid(board_params->hs_extmute_gpio)) {256 int ret;257 258 if (!board_params->hs_extmute_gpio)259 dev_warn(component->dev,260 "Extmute GPIO is 0 is this correct?\n");261 262 ret = gpio_request_one(board_params->hs_extmute_gpio,263 GPIOF_OUT_INIT_LOW,264 "hs_extmute");265 if (ret) {266 dev_err(component->dev,267 "Failed to get hs_extmute GPIO\n");268 board_params->hs_extmute_gpio = -1;269 }270 } else {271 u8 pin_mux;272 273 /* Set TWL4030 GPIO6 as EXTMUTE signal */274 twl_i2c_read_u8(TWL4030_MODULE_INTBR, &pin_mux,275 TWL4030_PMBR1_REG);276 pin_mux &= ~TWL4030_GPIO6_PWM0_MUTE(0x03);277 pin_mux |= TWL4030_GPIO6_PWM0_MUTE(0x02);278 twl_i2c_write_u8(TWL4030_MODULE_INTBR, pin_mux,279 TWL4030_PMBR1_REG);280 }281 }282 283 /* Initialize the local ctl register cache */284 tw4030_init_ctl_cache(twl4030);285 286 /* anti-pop when changing analog gain */287 reg = twl4030_read(component, TWL4030_REG_MISC_SET_1);288 twl4030_write(component, TWL4030_REG_MISC_SET_1,289 reg | TWL4030_SMOOTH_ANAVOL_EN);290 291 twl4030_write(component, TWL4030_REG_OPTION,292 TWL4030_ATXL1_EN | TWL4030_ATXR1_EN |293 TWL4030_ARXL2_EN | TWL4030_ARXR2_EN);294 295 /* REG_ARXR2_APGA_CTL reset according to the TRM: 0dB, DA_EN */296 twl4030_write(component, TWL4030_REG_ARXR2_APGA_CTL, 0x32);297 298 /* Machine dependent setup */299 if (!board_params)300 return;301 302 twl4030->board_params = board_params;303 304 reg = twl4030_read(component, TWL4030_REG_HS_POPN_SET);305 reg &= ~TWL4030_RAMP_DELAY;306 reg |= (board_params->ramp_delay_value << 2);307 twl4030_write(component, TWL4030_REG_HS_POPN_SET, reg);308 309 /* initiate offset cancellation */310 twl4030_codec_enable(component, 1);311 312 reg = twl4030_read(component, TWL4030_REG_ANAMICL);313 reg &= ~TWL4030_OFFSET_CNCL_SEL;314 reg |= board_params->offset_cncl_path;315 twl4030_write(component, TWL4030_REG_ANAMICL,316 reg | TWL4030_CNCL_OFFSET_START);317 318 /*319 * Wait for offset cancellation to complete.320 * Since this takes a while, do not slam the i2c.321 * Start polling the status after ~20ms.322 */323 msleep(20);324 do {325 usleep_range(1000, 2000);326 twl_set_regcache_bypass(TWL4030_MODULE_AUDIO_VOICE, true);327 twl_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE, &byte,328 TWL4030_REG_ANAMICL);329 twl_set_regcache_bypass(TWL4030_MODULE_AUDIO_VOICE, false);330 } while ((i++ < 100) &&331 ((byte & TWL4030_CNCL_OFFSET_START) ==332 TWL4030_CNCL_OFFSET_START));333 334 twl4030_codec_enable(component, 0);335}336 337static void twl4030_apll_enable(struct snd_soc_component *component, int enable)338{339 struct twl4030_priv *twl4030 = snd_soc_component_get_drvdata(component);340 341 if (enable) {342 twl4030->apll_enabled++;343 if (twl4030->apll_enabled == 1)344 twl4030_audio_enable_resource(345 TWL4030_AUDIO_RES_APLL);346 } else {347 twl4030->apll_enabled--;348 if (!twl4030->apll_enabled)349 twl4030_audio_disable_resource(350 TWL4030_AUDIO_RES_APLL);351 }352}353 354/* Earpiece */355static const struct snd_kcontrol_new twl4030_dapm_earpiece_controls[] = {356 SOC_DAPM_SINGLE("Voice", TWL4030_REG_EAR_CTL, 0, 1, 0),357 SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_EAR_CTL, 1, 1, 0),358 SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_EAR_CTL, 2, 1, 0),359 SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_EAR_CTL, 3, 1, 0),360};361 362/* PreDrive Left */363static const struct snd_kcontrol_new twl4030_dapm_predrivel_controls[] = {364 SOC_DAPM_SINGLE("Voice", TWL4030_REG_PREDL_CTL, 0, 1, 0),365 SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_PREDL_CTL, 1, 1, 0),366 SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_PREDL_CTL, 2, 1, 0),367 SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_PREDL_CTL, 3, 1, 0),368};369 370/* PreDrive Right */371static const struct snd_kcontrol_new twl4030_dapm_predriver_controls[] = {372 SOC_DAPM_SINGLE("Voice", TWL4030_REG_PREDR_CTL, 0, 1, 0),373 SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_PREDR_CTL, 1, 1, 0),374 SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_PREDR_CTL, 2, 1, 0),375 SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_PREDR_CTL, 3, 1, 0),376};377 378/* Headset Left */379static const struct snd_kcontrol_new twl4030_dapm_hsol_controls[] = {380 SOC_DAPM_SINGLE("Voice", TWL4030_REG_HS_SEL, 0, 1, 0),381 SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_HS_SEL, 1, 1, 0),382 SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_HS_SEL, 2, 1, 0),383};384 385/* Headset Right */386static const struct snd_kcontrol_new twl4030_dapm_hsor_controls[] = {387 SOC_DAPM_SINGLE("Voice", TWL4030_REG_HS_SEL, 3, 1, 0),388 SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_HS_SEL, 4, 1, 0),389 SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_HS_SEL, 5, 1, 0),390};391 392/* Carkit Left */393static const struct snd_kcontrol_new twl4030_dapm_carkitl_controls[] = {394 SOC_DAPM_SINGLE("Voice", TWL4030_REG_PRECKL_CTL, 0, 1, 0),395 SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_PRECKL_CTL, 1, 1, 0),396 SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_PRECKL_CTL, 2, 1, 0),397};398 399/* Carkit Right */400static const struct snd_kcontrol_new twl4030_dapm_carkitr_controls[] = {401 SOC_DAPM_SINGLE("Voice", TWL4030_REG_PRECKR_CTL, 0, 1, 0),402 SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_PRECKR_CTL, 1, 1, 0),403 SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_PRECKR_CTL, 2, 1, 0),404};405 406/* Handsfree Left */407static const char *twl4030_handsfreel_texts[] =408 {"Voice", "AudioL1", "AudioL2", "AudioR2"};409 410static SOC_ENUM_SINGLE_DECL(twl4030_handsfreel_enum,411 TWL4030_REG_HFL_CTL, 0,412 twl4030_handsfreel_texts);413 414static const struct snd_kcontrol_new twl4030_dapm_handsfreel_control =415SOC_DAPM_ENUM("Route", twl4030_handsfreel_enum);416 417/* Handsfree Left virtual mute */418static const struct snd_kcontrol_new twl4030_dapm_handsfreelmute_control =419 SOC_DAPM_SINGLE_VIRT("Switch", 1);420 421/* Handsfree Right */422static const char *twl4030_handsfreer_texts[] =423 {"Voice", "AudioR1", "AudioR2", "AudioL2"};424 425static SOC_ENUM_SINGLE_DECL(twl4030_handsfreer_enum,426 TWL4030_REG_HFR_CTL, 0,427 twl4030_handsfreer_texts);428 429static const struct snd_kcontrol_new twl4030_dapm_handsfreer_control =430SOC_DAPM_ENUM("Route", twl4030_handsfreer_enum);431 432/* Handsfree Right virtual mute */433static const struct snd_kcontrol_new twl4030_dapm_handsfreermute_control =434 SOC_DAPM_SINGLE_VIRT("Switch", 1);435 436/* Vibra */437/* Vibra audio path selection */438static const char *twl4030_vibra_texts[] =439 {"AudioL1", "AudioR1", "AudioL2", "AudioR2"};440 441static SOC_ENUM_SINGLE_DECL(twl4030_vibra_enum,442 TWL4030_REG_VIBRA_CTL, 2,443 twl4030_vibra_texts);444 445static const struct snd_kcontrol_new twl4030_dapm_vibra_control =446SOC_DAPM_ENUM("Route", twl4030_vibra_enum);447 448/* Vibra path selection: local vibrator (PWM) or audio driven */449static const char *twl4030_vibrapath_texts[] =450 {"Local vibrator", "Audio"};451 452static SOC_ENUM_SINGLE_DECL(twl4030_vibrapath_enum,453 TWL4030_REG_VIBRA_CTL, 4,454 twl4030_vibrapath_texts);455 456static const struct snd_kcontrol_new twl4030_dapm_vibrapath_control =457SOC_DAPM_ENUM("Route", twl4030_vibrapath_enum);458 459/* Left analog microphone selection */460static const struct snd_kcontrol_new twl4030_dapm_analoglmic_controls[] = {461 SOC_DAPM_SINGLE("Main Mic Capture Switch",462 TWL4030_REG_ANAMICL, 0, 1, 0),463 SOC_DAPM_SINGLE("Headset Mic Capture Switch",464 TWL4030_REG_ANAMICL, 1, 1, 0),465 SOC_DAPM_SINGLE("AUXL Capture Switch",466 TWL4030_REG_ANAMICL, 2, 1, 0),467 SOC_DAPM_SINGLE("Carkit Mic Capture Switch",468 TWL4030_REG_ANAMICL, 3, 1, 0),469};470 471/* Right analog microphone selection */472static const struct snd_kcontrol_new twl4030_dapm_analogrmic_controls[] = {473 SOC_DAPM_SINGLE("Sub Mic Capture Switch", TWL4030_REG_ANAMICR, 0, 1, 0),474 SOC_DAPM_SINGLE("AUXR Capture Switch", TWL4030_REG_ANAMICR, 2, 1, 0),475};476 477/* TX1 L/R Analog/Digital microphone selection */478static const char *twl4030_micpathtx1_texts[] =479 {"Analog", "Digimic0"};480 481static SOC_ENUM_SINGLE_DECL(twl4030_micpathtx1_enum,482 TWL4030_REG_ADCMICSEL, 0,483 twl4030_micpathtx1_texts);484 485static const struct snd_kcontrol_new twl4030_dapm_micpathtx1_control =486SOC_DAPM_ENUM("Route", twl4030_micpathtx1_enum);487 488/* TX2 L/R Analog/Digital microphone selection */489static const char *twl4030_micpathtx2_texts[] =490 {"Analog", "Digimic1"};491 492static SOC_ENUM_SINGLE_DECL(twl4030_micpathtx2_enum,493 TWL4030_REG_ADCMICSEL, 2,494 twl4030_micpathtx2_texts);495 496static const struct snd_kcontrol_new twl4030_dapm_micpathtx2_control =497SOC_DAPM_ENUM("Route", twl4030_micpathtx2_enum);498 499/* Analog bypass for AudioR1 */500static const struct snd_kcontrol_new twl4030_dapm_abypassr1_control =501 SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXR1_APGA_CTL, 2, 1, 0);502 503/* Analog bypass for AudioL1 */504static const struct snd_kcontrol_new twl4030_dapm_abypassl1_control =505 SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXL1_APGA_CTL, 2, 1, 0);506 507/* Analog bypass for AudioR2 */508static const struct snd_kcontrol_new twl4030_dapm_abypassr2_control =509 SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXR2_APGA_CTL, 2, 1, 0);510 511/* Analog bypass for AudioL2 */512static const struct snd_kcontrol_new twl4030_dapm_abypassl2_control =513 SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXL2_APGA_CTL, 2, 1, 0);514 515/* Analog bypass for Voice */516static const struct snd_kcontrol_new twl4030_dapm_abypassv_control =517 SOC_DAPM_SINGLE("Switch", TWL4030_REG_VDL_APGA_CTL, 2, 1, 0);518 519/* Digital bypass gain, mute instead of -30dB */520static const DECLARE_TLV_DB_RANGE(twl4030_dapm_dbypass_tlv,521 0, 1, TLV_DB_SCALE_ITEM(-3000, 600, 1),522 2, 3, TLV_DB_SCALE_ITEM(-2400, 0, 0),523 4, 7, TLV_DB_SCALE_ITEM(-1800, 600, 0)524);525 526/* Digital bypass left (TX1L -> RX2L) */527static const struct snd_kcontrol_new twl4030_dapm_dbypassl_control =528 SOC_DAPM_SINGLE_TLV("Volume",529 TWL4030_REG_ATX2ARXPGA, 3, 7, 0,530 twl4030_dapm_dbypass_tlv);531 532/* Digital bypass right (TX1R -> RX2R) */533static const struct snd_kcontrol_new twl4030_dapm_dbypassr_control =534 SOC_DAPM_SINGLE_TLV("Volume",535 TWL4030_REG_ATX2ARXPGA, 0, 7, 0,536 twl4030_dapm_dbypass_tlv);537 538/*539 * Voice Sidetone GAIN volume control:540 * from -51 to -10 dB in 1 dB steps (mute instead of -51 dB)541 */542static DECLARE_TLV_DB_SCALE(twl4030_dapm_dbypassv_tlv, -5100, 100, 1);543 544/* Digital bypass voice: sidetone (VUL -> VDL)*/545static const struct snd_kcontrol_new twl4030_dapm_dbypassv_control =546 SOC_DAPM_SINGLE_TLV("Volume",547 TWL4030_REG_VSTPGA, 0, 0x29, 0,548 twl4030_dapm_dbypassv_tlv);549 550/*551 * Output PGA builder:552 * Handle the muting and unmuting of the given output (turning off the553 * amplifier associated with the output pin)554 * On mute bypass the reg_cache and write 0 to the register555 * On unmute: restore the register content from the reg_cache556 * Outputs handled in this way: Earpiece, PreDrivL/R, CarkitL/R557 */558#define TWL4030_OUTPUT_PGA(pin_name, reg, mask) \559static int pin_name##pga_event(struct snd_soc_dapm_widget *w, \560 struct snd_kcontrol *kcontrol, int event) \561{ \562 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); \563 struct twl4030_priv *twl4030 = snd_soc_component_get_drvdata(component); \564 \565 switch (event) { \566 case SND_SOC_DAPM_POST_PMU: \567 twl4030->pin_name##_enabled = 1; \568 twl4030_write(component, reg, twl4030_read(component, reg)); \569 break; \570 case SND_SOC_DAPM_POST_PMD: \571 twl4030->pin_name##_enabled = 0; \572 twl_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, 0, reg); \573 break; \574 } \575 return 0; \576}577 578TWL4030_OUTPUT_PGA(earpiece, TWL4030_REG_EAR_CTL, TWL4030_EAR_GAIN);579TWL4030_OUTPUT_PGA(predrivel, TWL4030_REG_PREDL_CTL, TWL4030_PREDL_GAIN);580TWL4030_OUTPUT_PGA(predriver, TWL4030_REG_PREDR_CTL, TWL4030_PREDR_GAIN);581TWL4030_OUTPUT_PGA(carkitl, TWL4030_REG_PRECKL_CTL, TWL4030_PRECKL_GAIN);582TWL4030_OUTPUT_PGA(carkitr, TWL4030_REG_PRECKR_CTL, TWL4030_PRECKR_GAIN);583 584static void handsfree_ramp(struct snd_soc_component *component, int reg, int ramp)585{586 unsigned char hs_ctl;587 588 hs_ctl = twl4030_read(component, reg);589 590 if (ramp) {591 /* HF ramp-up */592 hs_ctl |= TWL4030_HF_CTL_REF_EN;593 twl4030_write(component, reg, hs_ctl);594 udelay(10);595 hs_ctl |= TWL4030_HF_CTL_RAMP_EN;596 twl4030_write(component, reg, hs_ctl);597 udelay(40);598 hs_ctl |= TWL4030_HF_CTL_LOOP_EN;599 hs_ctl |= TWL4030_HF_CTL_HB_EN;600 twl4030_write(component, reg, hs_ctl);601 } else {602 /* HF ramp-down */603 hs_ctl &= ~TWL4030_HF_CTL_LOOP_EN;604 hs_ctl &= ~TWL4030_HF_CTL_HB_EN;605 twl4030_write(component, reg, hs_ctl);606 hs_ctl &= ~TWL4030_HF_CTL_RAMP_EN;607 twl4030_write(component, reg, hs_ctl);608 udelay(40);609 hs_ctl &= ~TWL4030_HF_CTL_REF_EN;610 twl4030_write(component, reg, hs_ctl);611 }612}613 614static int handsfreelpga_event(struct snd_soc_dapm_widget *w,615 struct snd_kcontrol *kcontrol, int event)616{617 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);618 619 switch (event) {620 case SND_SOC_DAPM_POST_PMU:621 handsfree_ramp(component, TWL4030_REG_HFL_CTL, 1);622 break;623 case SND_SOC_DAPM_POST_PMD:624 handsfree_ramp(component, TWL4030_REG_HFL_CTL, 0);625 break;626 }627 return 0;628}629 630static int handsfreerpga_event(struct snd_soc_dapm_widget *w,631 struct snd_kcontrol *kcontrol, int event)632{633 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);634 635 switch (event) {636 case SND_SOC_DAPM_POST_PMU:637 handsfree_ramp(component, TWL4030_REG_HFR_CTL, 1);638 break;639 case SND_SOC_DAPM_POST_PMD:640 handsfree_ramp(component, TWL4030_REG_HFR_CTL, 0);641 break;642 }643 return 0;644}645 646static int vibramux_event(struct snd_soc_dapm_widget *w,647 struct snd_kcontrol *kcontrol, int event)648{649 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);650 651 twl4030_write(component, TWL4030_REG_VIBRA_SET, 0xff);652 return 0;653}654 655static int apll_event(struct snd_soc_dapm_widget *w,656 struct snd_kcontrol *kcontrol, int event)657{658 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);659 660 switch (event) {661 case SND_SOC_DAPM_PRE_PMU:662 twl4030_apll_enable(component, 1);663 break;664 case SND_SOC_DAPM_POST_PMD:665 twl4030_apll_enable(component, 0);666 break;667 }668 return 0;669}670 671static int aif_event(struct snd_soc_dapm_widget *w,672 struct snd_kcontrol *kcontrol, int event)673{674 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);675 u8 audio_if;676 677 audio_if = twl4030_read(component, TWL4030_REG_AUDIO_IF);678 switch (event) {679 case SND_SOC_DAPM_PRE_PMU:680 /* Enable AIF */681 /* enable the PLL before we use it to clock the DAI */682 twl4030_apll_enable(component, 1);683 684 twl4030_write(component, TWL4030_REG_AUDIO_IF,685 audio_if | TWL4030_AIF_EN);686 break;687 case SND_SOC_DAPM_POST_PMD:688 /* disable the DAI before we stop it's source PLL */689 twl4030_write(component, TWL4030_REG_AUDIO_IF,690 audio_if & ~TWL4030_AIF_EN);691 twl4030_apll_enable(component, 0);692 break;693 }694 return 0;695}696 697static void headset_ramp(struct snd_soc_component *component, int ramp)698{699 unsigned char hs_gain, hs_pop;700 struct twl4030_priv *twl4030 = snd_soc_component_get_drvdata(component);701 struct twl4030_board_params *board_params = twl4030->board_params;702 /* Base values for ramp delay calculation: 2^19 - 2^26 */703 static const unsigned int ramp_base[] = {704 524288, 1048576, 2097152, 4194304,705 8388608, 16777216, 33554432, 67108864706 };707 unsigned int delay;708 709 hs_gain = twl4030_read(component, TWL4030_REG_HS_GAIN_SET);710 hs_pop = twl4030_read(component, TWL4030_REG_HS_POPN_SET);711 delay = (ramp_base[(hs_pop & TWL4030_RAMP_DELAY) >> 2] /712 twl4030->sysclk) + 1;713 714 /* Enable external mute control, this dramatically reduces715 * the pop-noise */716 if (board_params && board_params->hs_extmute) {717 if (gpio_is_valid(board_params->hs_extmute_gpio)) {718 gpio_set_value(board_params->hs_extmute_gpio, 1);719 } else {720 hs_pop |= TWL4030_EXTMUTE;721 twl4030_write(component, TWL4030_REG_HS_POPN_SET, hs_pop);722 }723 }724 725 if (ramp) {726 /* Headset ramp-up according to the TRM */727 hs_pop |= TWL4030_VMID_EN;728 twl4030_write(component, TWL4030_REG_HS_POPN_SET, hs_pop);729 /* Actually write to the register */730 twl_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, hs_gain,731 TWL4030_REG_HS_GAIN_SET);732 hs_pop |= TWL4030_RAMP_EN;733 twl4030_write(component, TWL4030_REG_HS_POPN_SET, hs_pop);734 /* Wait ramp delay time + 1, so the VMID can settle */735 twl4030_wait_ms(delay);736 } else {737 /* Headset ramp-down _not_ according to738 * the TRM, but in a way that it is working */739 hs_pop &= ~TWL4030_RAMP_EN;740 twl4030_write(component, TWL4030_REG_HS_POPN_SET, hs_pop);741 /* Wait ramp delay time + 1, so the VMID can settle */742 twl4030_wait_ms(delay);743 /* Bypass the reg_cache to mute the headset */744 twl_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, hs_gain & (~0x0f),745 TWL4030_REG_HS_GAIN_SET);746 747 hs_pop &= ~TWL4030_VMID_EN;748 twl4030_write(component, TWL4030_REG_HS_POPN_SET, hs_pop);749 }750 751 /* Disable external mute */752 if (board_params && board_params->hs_extmute) {753 if (gpio_is_valid(board_params->hs_extmute_gpio)) {754 gpio_set_value(board_params->hs_extmute_gpio, 0);755 } else {756 hs_pop &= ~TWL4030_EXTMUTE;757 twl4030_write(component, TWL4030_REG_HS_POPN_SET, hs_pop);758 }759 }760}761 762static int headsetlpga_event(struct snd_soc_dapm_widget *w,763 struct snd_kcontrol *kcontrol, int event)764{765 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);766 struct twl4030_priv *twl4030 = snd_soc_component_get_drvdata(component);767 768 switch (event) {769 case SND_SOC_DAPM_POST_PMU:770 /* Do the ramp-up only once */771 if (!twl4030->hsr_enabled)772 headset_ramp(component, 1);773 774 twl4030->hsl_enabled = 1;775 break;776 case SND_SOC_DAPM_POST_PMD:777 /* Do the ramp-down only if both headsetL/R is disabled */778 if (!twl4030->hsr_enabled)779 headset_ramp(component, 0);780 781 twl4030->hsl_enabled = 0;782 break;783 }784 return 0;785}786 787static int headsetrpga_event(struct snd_soc_dapm_widget *w,788 struct snd_kcontrol *kcontrol, int event)789{790 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);791 struct twl4030_priv *twl4030 = snd_soc_component_get_drvdata(component);792 793 switch (event) {794 case SND_SOC_DAPM_POST_PMU:795 /* Do the ramp-up only once */796 if (!twl4030->hsl_enabled)797 headset_ramp(component, 1);798 799 twl4030->hsr_enabled = 1;800 break;801 case SND_SOC_DAPM_POST_PMD:802 /* Do the ramp-down only if both headsetL/R is disabled */803 if (!twl4030->hsl_enabled)804 headset_ramp(component, 0);805 806 twl4030->hsr_enabled = 0;807 break;808 }809 return 0;810}811 812static int digimic_event(struct snd_soc_dapm_widget *w,813 struct snd_kcontrol *kcontrol, int event)814{815 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);816 struct twl4030_priv *twl4030 = snd_soc_component_get_drvdata(component);817 struct twl4030_board_params *board_params = twl4030->board_params;818 819 if (board_params && board_params->digimic_delay)820 twl4030_wait_ms(board_params->digimic_delay);821 return 0;822}823 824/*825 * Some of the gain controls in TWL (mostly those which are associated with826 * the outputs) are implemented in an interesting way:827 * 0x0 : Power down (mute)828 * 0x1 : 6dB829 * 0x2 : 0 dB830 * 0x3 : -6 dB831 * Inverting not going to help with these.832 * Custom volsw and volsw_2r get/put functions to handle these gain bits.833 */834static int snd_soc_get_volsw_twl4030(struct snd_kcontrol *kcontrol,835 struct snd_ctl_elem_value *ucontrol)836{837 struct soc_mixer_control *mc =838 (struct soc_mixer_control *)kcontrol->private_value;839 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);840 unsigned int reg = mc->reg;841 unsigned int shift = mc->shift;842 unsigned int rshift = mc->rshift;843 int max = mc->max;844 int mask = (1 << fls(max)) - 1;845 846 ucontrol->value.integer.value[0] =847 (twl4030_read(component, reg) >> shift) & mask;848 if (ucontrol->value.integer.value[0])849 ucontrol->value.integer.value[0] =850 max + 1 - ucontrol->value.integer.value[0];851 852 if (shift != rshift) {853 ucontrol->value.integer.value[1] =854 (twl4030_read(component, reg) >> rshift) & mask;855 if (ucontrol->value.integer.value[1])856 ucontrol->value.integer.value[1] =857 max + 1 - ucontrol->value.integer.value[1];858 }859 860 return 0;861}862 863static int snd_soc_put_volsw_twl4030(struct snd_kcontrol *kcontrol,864 struct snd_ctl_elem_value *ucontrol)865{866 struct soc_mixer_control *mc =867 (struct soc_mixer_control *)kcontrol->private_value;868 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);869 unsigned int reg = mc->reg;870 unsigned int shift = mc->shift;871 unsigned int rshift = mc->rshift;872 int max = mc->max;873 int mask = (1 << fls(max)) - 1;874 unsigned short val, val2, val_mask;875 876 val = (ucontrol->value.integer.value[0] & mask);877 878 val_mask = mask << shift;879 if (val)880 val = max + 1 - val;881 val = val << shift;882 if (shift != rshift) {883 val2 = (ucontrol->value.integer.value[1] & mask);884 val_mask |= mask << rshift;885 if (val2)886 val2 = max + 1 - val2;887 val |= val2 << rshift;888 }889 return snd_soc_component_update_bits(component, reg, val_mask, val);890}891 892static int snd_soc_get_volsw_r2_twl4030(struct snd_kcontrol *kcontrol,893 struct snd_ctl_elem_value *ucontrol)894{895 struct soc_mixer_control *mc =896 (struct soc_mixer_control *)kcontrol->private_value;897 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);898 unsigned int reg = mc->reg;899 unsigned int reg2 = mc->rreg;900 unsigned int shift = mc->shift;901 int max = mc->max;902 int mask = (1<<fls(max))-1;903 904 ucontrol->value.integer.value[0] =905 (twl4030_read(component, reg) >> shift) & mask;906 ucontrol->value.integer.value[1] =907 (twl4030_read(component, reg2) >> shift) & mask;908 909 if (ucontrol->value.integer.value[0])910 ucontrol->value.integer.value[0] =911 max + 1 - ucontrol->value.integer.value[0];912 if (ucontrol->value.integer.value[1])913 ucontrol->value.integer.value[1] =914 max + 1 - ucontrol->value.integer.value[1];915 916 return 0;917}918 919static int snd_soc_put_volsw_r2_twl4030(struct snd_kcontrol *kcontrol,920 struct snd_ctl_elem_value *ucontrol)921{922 struct soc_mixer_control *mc =923 (struct soc_mixer_control *)kcontrol->private_value;924 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);925 unsigned int reg = mc->reg;926 unsigned int reg2 = mc->rreg;927 unsigned int shift = mc->shift;928 int max = mc->max;929 int mask = (1 << fls(max)) - 1;930 int err;931 unsigned short val, val2, val_mask;932 933 val_mask = mask << shift;934 val = (ucontrol->value.integer.value[0] & mask);935 val2 = (ucontrol->value.integer.value[1] & mask);936 937 if (val)938 val = max + 1 - val;939 if (val2)940 val2 = max + 1 - val2;941 942 val = val << shift;943 val2 = val2 << shift;944 945 err = snd_soc_component_update_bits(component, reg, val_mask, val);946 if (err < 0)947 return err;948 949 err = snd_soc_component_update_bits(component, reg2, val_mask, val2);950 return err;951}952 953/* Codec operation modes */954static const char *twl4030_op_modes_texts[] = {955 "Option 2 (voice/audio)", "Option 1 (audio)"956};957 958static SOC_ENUM_SINGLE_DECL(twl4030_op_modes_enum,959 TWL4030_REG_CODEC_MODE, 0,960 twl4030_op_modes_texts);961 962static int snd_soc_put_twl4030_opmode_enum_double(struct snd_kcontrol *kcontrol,963 struct snd_ctl_elem_value *ucontrol)964{965 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);966 struct twl4030_priv *twl4030 = snd_soc_component_get_drvdata(component);967 968 if (twl4030->configured) {969 dev_err(component->dev,970 "operation mode cannot be changed on-the-fly\n");971 return -EBUSY;972 }973 974 return snd_soc_put_enum_double(kcontrol, ucontrol);975}976 977/*978 * FGAIN volume control:979 * from -62 to 0 dB in 1 dB steps (mute instead of -63 dB)980 */981static DECLARE_TLV_DB_SCALE(digital_fine_tlv, -6300, 100, 1);982 983/*984 * CGAIN volume control:985 * 0 dB to 12 dB in 6 dB steps986 * value 2 and 3 means 12 dB987 */988static DECLARE_TLV_DB_SCALE(digital_coarse_tlv, 0, 600, 0);989 990/*991 * Voice Downlink GAIN volume control:992 * from -37 to 12 dB in 1 dB steps (mute instead of -37 dB)993 */994static DECLARE_TLV_DB_SCALE(digital_voice_downlink_tlv, -3700, 100, 1);995 996/*997 * Analog playback gain998 * -24 dB to 12 dB in 2 dB steps999 */1000static DECLARE_TLV_DB_SCALE(analog_tlv, -2400, 200, 0);1001 1002/*1003 * Gain controls tied to outputs1004 * -6 dB to 6 dB in 6 dB steps (mute instead of -12)1005 */1006static DECLARE_TLV_DB_SCALE(output_tvl, -1200, 600, 1);1007 1008/*1009 * Gain control for earpiece amplifier1010 * 0 dB to 12 dB in 6 dB steps (mute instead of -6)1011 */1012static DECLARE_TLV_DB_SCALE(output_ear_tvl, -600, 600, 1);1013 1014/*1015 * Capture gain after the ADCs1016 * from 0 dB to 31 dB in 1 dB steps1017 */1018static DECLARE_TLV_DB_SCALE(digital_capture_tlv, 0, 100, 0);1019 1020/*1021 * Gain control for input amplifiers1022 * 0 dB to 30 dB in 6 dB steps1023 */1024static DECLARE_TLV_DB_SCALE(input_gain_tlv, 0, 600, 0);1025 1026/* AVADC clock priority */1027static const char *twl4030_avadc_clk_priority_texts[] = {1028 "Voice high priority", "HiFi high priority"1029};1030 1031static SOC_ENUM_SINGLE_DECL(twl4030_avadc_clk_priority_enum,1032 TWL4030_REG_AVADC_CTL, 2,1033 twl4030_avadc_clk_priority_texts);1034 1035static const char *twl4030_rampdelay_texts[] = {1036 "27/20/14 ms", "55/40/27 ms", "109/81/55 ms", "218/161/109 ms",1037 "437/323/218 ms", "874/645/437 ms", "1748/1291/874 ms",1038 "3495/2581/1748 ms"1039};1040 1041static SOC_ENUM_SINGLE_DECL(twl4030_rampdelay_enum,1042 TWL4030_REG_HS_POPN_SET, 2,1043 twl4030_rampdelay_texts);1044 1045/* Vibra H-bridge direction mode */1046static const char *twl4030_vibradirmode_texts[] = {1047 "Vibra H-bridge direction", "Audio data MSB",1048};1049 1050static SOC_ENUM_SINGLE_DECL(twl4030_vibradirmode_enum,1051 TWL4030_REG_VIBRA_CTL, 5,1052 twl4030_vibradirmode_texts);1053 1054/* Vibra H-bridge direction */1055static const char *twl4030_vibradir_texts[] = {1056 "Positive polarity", "Negative polarity",1057};1058 1059static SOC_ENUM_SINGLE_DECL(twl4030_vibradir_enum,1060 TWL4030_REG_VIBRA_CTL, 1,1061 twl4030_vibradir_texts);1062 1063/* Digimic Left and right swapping */1064static const char *twl4030_digimicswap_texts[] = {1065 "Not swapped", "Swapped",1066};1067 1068static SOC_ENUM_SINGLE_DECL(twl4030_digimicswap_enum,1069 TWL4030_REG_MISC_SET_1, 0,1070 twl4030_digimicswap_texts);1071 1072static const struct snd_kcontrol_new twl4030_snd_controls[] = {1073 /* Codec operation mode control */1074 SOC_ENUM_EXT("Codec Operation Mode", twl4030_op_modes_enum,1075 snd_soc_get_enum_double,1076 snd_soc_put_twl4030_opmode_enum_double),1077 1078 /* Common playback gain controls */1079 SOC_DOUBLE_R_TLV("DAC1 Digital Fine Playback Volume",1080 TWL4030_REG_ARXL1PGA, TWL4030_REG_ARXR1PGA,1081 0, 0x3f, 0, digital_fine_tlv),1082 SOC_DOUBLE_R_TLV("DAC2 Digital Fine Playback Volume",1083 TWL4030_REG_ARXL2PGA, TWL4030_REG_ARXR2PGA,1084 0, 0x3f, 0, digital_fine_tlv),1085 1086 SOC_DOUBLE_R_TLV("DAC1 Digital Coarse Playback Volume",1087 TWL4030_REG_ARXL1PGA, TWL4030_REG_ARXR1PGA,1088 6, 0x2, 0, digital_coarse_tlv),1089 SOC_DOUBLE_R_TLV("DAC2 Digital Coarse Playback Volume",1090 TWL4030_REG_ARXL2PGA, TWL4030_REG_ARXR2PGA,1091 6, 0x2, 0, digital_coarse_tlv),1092 1093 SOC_DOUBLE_R_TLV("DAC1 Analog Playback Volume",1094 TWL4030_REG_ARXL1_APGA_CTL, TWL4030_REG_ARXR1_APGA_CTL,1095 3, 0x12, 1, analog_tlv),1096 SOC_DOUBLE_R_TLV("DAC2 Analog Playback Volume",1097 TWL4030_REG_ARXL2_APGA_CTL, TWL4030_REG_ARXR2_APGA_CTL,1098 3, 0x12, 1, analog_tlv),1099 SOC_DOUBLE_R("DAC1 Analog Playback Switch",1100 TWL4030_REG_ARXL1_APGA_CTL, TWL4030_REG_ARXR1_APGA_CTL,1101 1, 1, 0),1102 SOC_DOUBLE_R("DAC2 Analog Playback Switch",1103 TWL4030_REG_ARXL2_APGA_CTL, TWL4030_REG_ARXR2_APGA_CTL,1104 1, 1, 0),1105 1106 /* Common voice downlink gain controls */1107 SOC_SINGLE_TLV("DAC Voice Digital Downlink Volume",1108 TWL4030_REG_VRXPGA, 0, 0x31, 0, digital_voice_downlink_tlv),1109 1110 SOC_SINGLE_TLV("DAC Voice Analog Downlink Volume",1111 TWL4030_REG_VDL_APGA_CTL, 3, 0x12, 1, analog_tlv),1112 1113 SOC_SINGLE("DAC Voice Analog Downlink Switch",1114 TWL4030_REG_VDL_APGA_CTL, 1, 1, 0),1115 1116 /* Separate output gain controls */1117 SOC_DOUBLE_R_EXT_TLV("PreDriv Playback Volume",1118 TWL4030_REG_PREDL_CTL, TWL4030_REG_PREDR_CTL,1119 4, 3, 0, snd_soc_get_volsw_r2_twl4030,1120 snd_soc_put_volsw_r2_twl4030, output_tvl),1121 1122 SOC_DOUBLE_EXT_TLV("Headset Playback Volume",1123 TWL4030_REG_HS_GAIN_SET, 0, 2, 3, 0, snd_soc_get_volsw_twl4030,1124 snd_soc_put_volsw_twl4030, output_tvl),1125 1126 SOC_DOUBLE_R_EXT_TLV("Carkit Playback Volume",1127 TWL4030_REG_PRECKL_CTL, TWL4030_REG_PRECKR_CTL,1128 4, 3, 0, snd_soc_get_volsw_r2_twl4030,1129 snd_soc_put_volsw_r2_twl4030, output_tvl),1130 1131 SOC_SINGLE_EXT_TLV("Earpiece Playback Volume",1132 TWL4030_REG_EAR_CTL, 4, 3, 0, snd_soc_get_volsw_twl4030,1133 snd_soc_put_volsw_twl4030, output_ear_tvl),1134 1135 /* Common capture gain controls */1136 SOC_DOUBLE_R_TLV("TX1 Digital Capture Volume",1137 TWL4030_REG_ATXL1PGA, TWL4030_REG_ATXR1PGA,1138 0, 0x1f, 0, digital_capture_tlv),1139 SOC_DOUBLE_R_TLV("TX2 Digital Capture Volume",1140 TWL4030_REG_AVTXL2PGA, TWL4030_REG_AVTXR2PGA,1141 0, 0x1f, 0, digital_capture_tlv),1142 1143 SOC_DOUBLE_TLV("Analog Capture Volume", TWL4030_REG_ANAMIC_GAIN,1144 0, 3, 5, 0, input_gain_tlv),1145 1146 SOC_ENUM("AVADC Clock Priority", twl4030_avadc_clk_priority_enum),1147 1148 SOC_ENUM("HS ramp delay", twl4030_rampdelay_enum),1149 1150 SOC_ENUM("Vibra H-bridge mode", twl4030_vibradirmode_enum),1151 SOC_ENUM("Vibra H-bridge direction", twl4030_vibradir_enum),1152 1153 SOC_ENUM("Digimic LR Swap", twl4030_digimicswap_enum),1154};1155 1156static const struct snd_soc_dapm_widget twl4030_dapm_widgets[] = {1157 /* Left channel inputs */1158 SND_SOC_DAPM_INPUT("MAINMIC"),1159 SND_SOC_DAPM_INPUT("HSMIC"),1160 SND_SOC_DAPM_INPUT("AUXL"),1161 SND_SOC_DAPM_INPUT("CARKITMIC"),1162 /* Right channel inputs */1163 SND_SOC_DAPM_INPUT("SUBMIC"),1164 SND_SOC_DAPM_INPUT("AUXR"),1165 /* Digital microphones (Stereo) */1166 SND_SOC_DAPM_INPUT("DIGIMIC0"),1167 SND_SOC_DAPM_INPUT("DIGIMIC1"),1168 1169 /* Outputs */1170 SND_SOC_DAPM_OUTPUT("EARPIECE"),1171 SND_SOC_DAPM_OUTPUT("PREDRIVEL"),1172 SND_SOC_DAPM_OUTPUT("PREDRIVER"),1173 SND_SOC_DAPM_OUTPUT("HSOL"),1174 SND_SOC_DAPM_OUTPUT("HSOR"),1175 SND_SOC_DAPM_OUTPUT("CARKITL"),1176 SND_SOC_DAPM_OUTPUT("CARKITR"),1177 SND_SOC_DAPM_OUTPUT("HFL"),1178 SND_SOC_DAPM_OUTPUT("HFR"),1179 SND_SOC_DAPM_OUTPUT("VIBRA"),1180 1181 /* AIF and APLL clocks for running DAIs (including loopback) */1182 SND_SOC_DAPM_OUTPUT("Virtual HiFi OUT"),1183 SND_SOC_DAPM_INPUT("Virtual HiFi IN"),1184 SND_SOC_DAPM_OUTPUT("Virtual Voice OUT"),1185 1186 /* DACs */1187 SND_SOC_DAPM_DAC("DAC Right1", NULL, SND_SOC_NOPM, 0, 0),1188 SND_SOC_DAPM_DAC("DAC Left1", NULL, SND_SOC_NOPM, 0, 0),1189 SND_SOC_DAPM_DAC("DAC Right2", NULL, SND_SOC_NOPM, 0, 0),1190 SND_SOC_DAPM_DAC("DAC Left2", NULL, SND_SOC_NOPM, 0, 0),1191 SND_SOC_DAPM_DAC("DAC Voice", NULL, SND_SOC_NOPM, 0, 0),1192 1193 SND_SOC_DAPM_AIF_IN("VAIFIN", "Voice Playback", 0,1194 TWL4030_REG_VOICE_IF, 6, 0),1195 1196 /* Analog bypasses */1197 SND_SOC_DAPM_SWITCH("Right1 Analog Loopback", SND_SOC_NOPM, 0, 0,1198 &twl4030_dapm_abypassr1_control),1199 SND_SOC_DAPM_SWITCH("Left1 Analog Loopback", SND_SOC_NOPM, 0, 0,1200 &twl4030_dapm_abypassl1_control),1201 SND_SOC_DAPM_SWITCH("Right2 Analog Loopback", SND_SOC_NOPM, 0, 0,1202 &twl4030_dapm_abypassr2_control),1203 SND_SOC_DAPM_SWITCH("Left2 Analog Loopback", SND_SOC_NOPM, 0, 0,1204 &twl4030_dapm_abypassl2_control),1205 SND_SOC_DAPM_SWITCH("Voice Analog Loopback", SND_SOC_NOPM, 0, 0,1206 &twl4030_dapm_abypassv_control),1207 1208 /* Master analog loopback switch */1209 SND_SOC_DAPM_SUPPLY("FM Loop Enable", TWL4030_REG_MISC_SET_1, 5, 0,1210 NULL, 0),1211 1212 /* Digital bypasses */1213 SND_SOC_DAPM_SWITCH("Left Digital Loopback", SND_SOC_NOPM, 0, 0,1214 &twl4030_dapm_dbypassl_control),1215 SND_SOC_DAPM_SWITCH("Right Digital Loopback", SND_SOC_NOPM, 0, 0,1216 &twl4030_dapm_dbypassr_control),1217 SND_SOC_DAPM_SWITCH("Voice Digital Loopback", SND_SOC_NOPM, 0, 0,1218 &twl4030_dapm_dbypassv_control),1219 1220 /* Digital mixers, power control for the physical DACs */1221 SND_SOC_DAPM_MIXER("Digital R1 Playback Mixer",1222 TWL4030_REG_AVDAC_CTL, 0, 0, NULL, 0),1223 SND_SOC_DAPM_MIXER("Digital L1 Playback Mixer",1224 TWL4030_REG_AVDAC_CTL, 1, 0, NULL, 0),1225 SND_SOC_DAPM_MIXER("Digital R2 Playback Mixer",1226 TWL4030_REG_AVDAC_CTL, 2, 0, NULL, 0),1227 SND_SOC_DAPM_MIXER("Digital L2 Playback Mixer",1228 TWL4030_REG_AVDAC_CTL, 3, 0, NULL, 0),1229 SND_SOC_DAPM_MIXER("Digital Voice Playback Mixer",1230 TWL4030_REG_AVDAC_CTL, 4, 0, NULL, 0),1231 1232 /* Analog mixers, power control for the physical PGAs */1233 SND_SOC_DAPM_MIXER("Analog R1 Playback Mixer",1234 TWL4030_REG_ARXR1_APGA_CTL, 0, 0, NULL, 0),1235 SND_SOC_DAPM_MIXER("Analog L1 Playback Mixer",1236 TWL4030_REG_ARXL1_APGA_CTL, 0, 0, NULL, 0),1237 SND_SOC_DAPM_MIXER("Analog R2 Playback Mixer",1238 TWL4030_REG_ARXR2_APGA_CTL, 0, 0, NULL, 0),1239 SND_SOC_DAPM_MIXER("Analog L2 Playback Mixer",1240 TWL4030_REG_ARXL2_APGA_CTL, 0, 0, NULL, 0),1241 SND_SOC_DAPM_MIXER("Analog Voice Playback Mixer",1242 TWL4030_REG_VDL_APGA_CTL, 0, 0, NULL, 0),1243 1244 SND_SOC_DAPM_SUPPLY("APLL Enable", SND_SOC_NOPM, 0, 0, apll_event,1245 SND_SOC_DAPM_PRE_PMU|SND_SOC_DAPM_POST_PMD),1246 1247 SND_SOC_DAPM_SUPPLY("AIF Enable", SND_SOC_NOPM, 0, 0, aif_event,1248 SND_SOC_DAPM_PRE_PMU|SND_SOC_DAPM_POST_PMD),1249 1250 /* Output MIXER controls */1251 /* Earpiece */1252 SND_SOC_DAPM_MIXER("Earpiece Mixer", SND_SOC_NOPM, 0, 0,1253 &twl4030_dapm_earpiece_controls[0],1254 ARRAY_SIZE(twl4030_dapm_earpiece_controls)),1255 SND_SOC_DAPM_PGA_E("Earpiece PGA", SND_SOC_NOPM,1256 0, 0, NULL, 0, earpiecepga_event,1257 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),1258 /* PreDrivL/R */1259 SND_SOC_DAPM_MIXER("PredriveL Mixer", SND_SOC_NOPM, 0, 0,1260 &twl4030_dapm_predrivel_controls[0],1261 ARRAY_SIZE(twl4030_dapm_predrivel_controls)),1262 SND_SOC_DAPM_PGA_E("PredriveL PGA", SND_SOC_NOPM,1263 0, 0, NULL, 0, predrivelpga_event,1264 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),1265 SND_SOC_DAPM_MIXER("PredriveR Mixer", SND_SOC_NOPM, 0, 0,1266 &twl4030_dapm_predriver_controls[0],1267 ARRAY_SIZE(twl4030_dapm_predriver_controls)),1268 SND_SOC_DAPM_PGA_E("PredriveR PGA", SND_SOC_NOPM,1269 0, 0, NULL, 0, predriverpga_event,1270 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),1271 /* HeadsetL/R */1272 SND_SOC_DAPM_MIXER("HeadsetL Mixer", SND_SOC_NOPM, 0, 0,1273 &twl4030_dapm_hsol_controls[0],1274 ARRAY_SIZE(twl4030_dapm_hsol_controls)),1275 SND_SOC_DAPM_PGA_E("HeadsetL PGA", SND_SOC_NOPM,1276 0, 0, NULL, 0, headsetlpga_event,1277 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),1278 SND_SOC_DAPM_MIXER("HeadsetR Mixer", SND_SOC_NOPM, 0, 0,1279 &twl4030_dapm_hsor_controls[0],1280 ARRAY_SIZE(twl4030_dapm_hsor_controls)),1281 SND_SOC_DAPM_PGA_E("HeadsetR PGA", SND_SOC_NOPM,1282 0, 0, NULL, 0, headsetrpga_event,1283 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),1284 /* CarkitL/R */1285 SND_SOC_DAPM_MIXER("CarkitL Mixer", SND_SOC_NOPM, 0, 0,1286 &twl4030_dapm_carkitl_controls[0],1287 ARRAY_SIZE(twl4030_dapm_carkitl_controls)),1288 SND_SOC_DAPM_PGA_E("CarkitL PGA", SND_SOC_NOPM,1289 0, 0, NULL, 0, carkitlpga_event,1290 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),1291 SND_SOC_DAPM_MIXER("CarkitR Mixer", SND_SOC_NOPM, 0, 0,1292 &twl4030_dapm_carkitr_controls[0],1293 ARRAY_SIZE(twl4030_dapm_carkitr_controls)),1294 SND_SOC_DAPM_PGA_E("CarkitR PGA", SND_SOC_NOPM,1295 0, 0, NULL, 0, carkitrpga_event,1296 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),1297 1298 /* Output MUX controls */1299 /* HandsfreeL/R */1300 SND_SOC_DAPM_MUX("HandsfreeL Mux", SND_SOC_NOPM, 0, 0,1301 &twl4030_dapm_handsfreel_control),1302 SND_SOC_DAPM_SWITCH("HandsfreeL", SND_SOC_NOPM, 0, 0,1303 &twl4030_dapm_handsfreelmute_control),1304 SND_SOC_DAPM_PGA_E("HandsfreeL PGA", SND_SOC_NOPM,1305 0, 0, NULL, 0, handsfreelpga_event,1306 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),1307 SND_SOC_DAPM_MUX("HandsfreeR Mux", SND_SOC_NOPM, 5, 0,1308 &twl4030_dapm_handsfreer_control),1309 SND_SOC_DAPM_SWITCH("HandsfreeR", SND_SOC_NOPM, 0, 0,1310 &twl4030_dapm_handsfreermute_control),1311 SND_SOC_DAPM_PGA_E("HandsfreeR PGA", SND_SOC_NOPM,1312 0, 0, NULL, 0, handsfreerpga_event,1313 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),1314 /* Vibra */1315 SND_SOC_DAPM_MUX_E("Vibra Mux", TWL4030_REG_VIBRA_CTL, 0, 0,1316 &twl4030_dapm_vibra_control, vibramux_event,1317 SND_SOC_DAPM_PRE_PMU),1318 SND_SOC_DAPM_MUX("Vibra Route", SND_SOC_NOPM, 0, 0,1319 &twl4030_dapm_vibrapath_control),1320 1321 /* Introducing four virtual ADC, since TWL4030 have four channel for1322 capture */1323 SND_SOC_DAPM_ADC("ADC Virtual Left1", NULL, SND_SOC_NOPM, 0, 0),1324 SND_SOC_DAPM_ADC("ADC Virtual Right1", NULL, SND_SOC_NOPM, 0, 0),1325 SND_SOC_DAPM_ADC("ADC Virtual Left2", NULL, SND_SOC_NOPM, 0, 0),1326 SND_SOC_DAPM_ADC("ADC Virtual Right2", NULL, SND_SOC_NOPM, 0, 0),1327 1328 SND_SOC_DAPM_AIF_OUT("VAIFOUT", "Voice Capture", 0,1329 TWL4030_REG_VOICE_IF, 5, 0),1330 1331 /* Analog/Digital mic path selection.1332 TX1 Left/Right: either analog Left/Right or Digimic01333 TX2 Left/Right: either analog Left/Right or Digimic1 */1334 SND_SOC_DAPM_MUX("TX1 Capture Route", SND_SOC_NOPM, 0, 0,1335 &twl4030_dapm_micpathtx1_control),1336 SND_SOC_DAPM_MUX("TX2 Capture Route", SND_SOC_NOPM, 0, 0,1337 &twl4030_dapm_micpathtx2_control),1338 1339 /* Analog input mixers for the capture amplifiers */1340 SND_SOC_DAPM_MIXER("Analog Left",1341 TWL4030_REG_ANAMICL, 4, 0,1342 &twl4030_dapm_analoglmic_controls[0],1343 ARRAY_SIZE(twl4030_dapm_analoglmic_controls)),1344 SND_SOC_DAPM_MIXER("Analog Right",1345 TWL4030_REG_ANAMICR, 4, 0,1346 &twl4030_dapm_analogrmic_controls[0],1347 ARRAY_SIZE(twl4030_dapm_analogrmic_controls)),1348 1349 SND_SOC_DAPM_PGA("ADC Physical Left",1350 TWL4030_REG_AVADC_CTL, 3, 0, NULL, 0),1351 SND_SOC_DAPM_PGA("ADC Physical Right",1352 TWL4030_REG_AVADC_CTL, 1, 0, NULL, 0),1353 1354 SND_SOC_DAPM_PGA_E("Digimic0 Enable",1355 TWL4030_REG_ADCMICSEL, 1, 0, NULL, 0,1356 digimic_event, SND_SOC_DAPM_POST_PMU),1357 SND_SOC_DAPM_PGA_E("Digimic1 Enable",1358 TWL4030_REG_ADCMICSEL, 3, 0, NULL, 0,1359 digimic_event, SND_SOC_DAPM_POST_PMU),1360 1361 SND_SOC_DAPM_SUPPLY("micbias1 select", TWL4030_REG_MICBIAS_CTL, 5, 0,1362 NULL, 0),1363 SND_SOC_DAPM_SUPPLY("micbias2 select", TWL4030_REG_MICBIAS_CTL, 6, 0,1364 NULL, 0),1365 1366 /* Microphone bias */1367 SND_SOC_DAPM_SUPPLY("Mic Bias 1",1368 TWL4030_REG_MICBIAS_CTL, 0, 0, NULL, 0),1369 SND_SOC_DAPM_SUPPLY("Mic Bias 2",1370 TWL4030_REG_MICBIAS_CTL, 1, 0, NULL, 0),1371 SND_SOC_DAPM_SUPPLY("Headset Mic Bias",1372 TWL4030_REG_MICBIAS_CTL, 2, 0, NULL, 0),1373 1374 SND_SOC_DAPM_SUPPLY("VIF Enable", TWL4030_REG_VOICE_IF, 0, 0, NULL, 0),1375};1376 1377static const struct snd_soc_dapm_route intercon[] = {1378 /* Stream -> DAC mapping */1379 {"DAC Right1", NULL, "HiFi Playback"},1380 {"DAC Left1", NULL, "HiFi Playback"},1381 {"DAC Right2", NULL, "HiFi Playback"},1382 {"DAC Left2", NULL, "HiFi Playback"},1383 {"DAC Voice", NULL, "VAIFIN"},1384 1385 /* ADC -> Stream mapping */1386 {"HiFi Capture", NULL, "ADC Virtual Left1"},1387 {"HiFi Capture", NULL, "ADC Virtual Right1"},1388 {"HiFi Capture", NULL, "ADC Virtual Left2"},1389 {"HiFi Capture", NULL, "ADC Virtual Right2"},1390 {"VAIFOUT", NULL, "ADC Virtual Left2"},1391 {"VAIFOUT", NULL, "ADC Virtual Right2"},1392 {"VAIFOUT", NULL, "VIF Enable"},1393 1394 {"Digital L1 Playback Mixer", NULL, "DAC Left1"},1395 {"Digital R1 Playback Mixer", NULL, "DAC Right1"},1396 {"Digital L2 Playback Mixer", NULL, "DAC Left2"},1397 {"Digital R2 Playback Mixer", NULL, "DAC Right2"},1398 {"Digital Voice Playback Mixer", NULL, "DAC Voice"},1399 1400 /* Supply for the digital part (APLL) */1401 {"Digital Voice Playback Mixer", NULL, "APLL Enable"},1402 1403 {"DAC Left1", NULL, "AIF Enable"},1404 {"DAC Right1", NULL, "AIF Enable"},1405 {"DAC Left2", NULL, "AIF Enable"},1406 {"DAC Right1", NULL, "AIF Enable"},1407 {"DAC Voice", NULL, "VIF Enable"},1408 1409 {"Digital R2 Playback Mixer", NULL, "AIF Enable"},1410 {"Digital L2 Playback Mixer", NULL, "AIF Enable"},1411 1412 {"Analog L1 Playback Mixer", NULL, "Digital L1 Playback Mixer"},1413 {"Analog R1 Playback Mixer", NULL, "Digital R1 Playback Mixer"},1414 {"Analog L2 Playback Mixer", NULL, "Digital L2 Playback Mixer"},1415 {"Analog R2 Playback Mixer", NULL, "Digital R2 Playback Mixer"},1416 {"Analog Voice Playback Mixer", NULL, "Digital Voice Playback Mixer"},1417 1418 /* Internal playback routings */1419 /* Earpiece */1420 {"Earpiece Mixer", "Voice", "Analog Voice Playback Mixer"},1421 {"Earpiece Mixer", "AudioL1", "Analog L1 Playback Mixer"},1422 {"Earpiece Mixer", "AudioL2", "Analog L2 Playback Mixer"},1423 {"Earpiece Mixer", "AudioR1", "Analog R1 Playback Mixer"},1424 {"Earpiece PGA", NULL, "Earpiece Mixer"},1425 /* PreDrivL */1426 {"PredriveL Mixer", "Voice", "Analog Voice Playback Mixer"},1427 {"PredriveL Mixer", "AudioL1", "Analog L1 Playback Mixer"},1428 {"PredriveL Mixer", "AudioL2", "Analog L2 Playback Mixer"},1429 {"PredriveL Mixer", "AudioR2", "Analog R2 Playback Mixer"},1430 {"PredriveL PGA", NULL, "PredriveL Mixer"},1431 /* PreDrivR */1432 {"PredriveR Mixer", "Voice", "Analog Voice Playback Mixer"},1433 {"PredriveR Mixer", "AudioR1", "Analog R1 Playback Mixer"},1434 {"PredriveR Mixer", "AudioR2", "Analog R2 Playback Mixer"},1435 {"PredriveR Mixer", "AudioL2", "Analog L2 Playback Mixer"},1436 {"PredriveR PGA", NULL, "PredriveR Mixer"},1437 /* HeadsetL */1438 {"HeadsetL Mixer", "Voice", "Analog Voice Playback Mixer"},1439 {"HeadsetL Mixer", "AudioL1", "Analog L1 Playback Mixer"},1440 {"HeadsetL Mixer", "AudioL2", "Analog L2 Playback Mixer"},1441 {"HeadsetL PGA", NULL, "HeadsetL Mixer"},1442 /* HeadsetR */1443 {"HeadsetR Mixer", "Voice", "Analog Voice Playback Mixer"},1444 {"HeadsetR Mixer", "AudioR1", "Analog R1 Playback Mixer"},1445 {"HeadsetR Mixer", "AudioR2", "Analog R2 Playback Mixer"},1446 {"HeadsetR PGA", NULL, "HeadsetR Mixer"},1447 /* CarkitL */1448 {"CarkitL Mixer", "Voice", "Analog Voice Playback Mixer"},1449 {"CarkitL Mixer", "AudioL1", "Analog L1 Playback Mixer"},1450 {"CarkitL Mixer", "AudioL2", "Analog L2 Playback Mixer"},1451 {"CarkitL PGA", NULL, "CarkitL Mixer"},1452 /* CarkitR */1453 {"CarkitR Mixer", "Voice", "Analog Voice Playback Mixer"},1454 {"CarkitR Mixer", "AudioR1", "Analog R1 Playback Mixer"},1455 {"CarkitR Mixer", "AudioR2", "Analog R2 Playback Mixer"},1456 {"CarkitR PGA", NULL, "CarkitR Mixer"},1457 /* HandsfreeL */1458 {"HandsfreeL Mux", "Voice", "Analog Voice Playback Mixer"},1459 {"HandsfreeL Mux", "AudioL1", "Analog L1 Playback Mixer"},1460 {"HandsfreeL Mux", "AudioL2", "Analog L2 Playback Mixer"},1461 {"HandsfreeL Mux", "AudioR2", "Analog R2 Playback Mixer"},1462 {"HandsfreeL", "Switch", "HandsfreeL Mux"},1463 {"HandsfreeL PGA", NULL, "HandsfreeL"},1464 /* HandsfreeR */1465 {"HandsfreeR Mux", "Voice", "Analog Voice Playback Mixer"},1466 {"HandsfreeR Mux", "AudioR1", "Analog R1 Playback Mixer"},1467 {"HandsfreeR Mux", "AudioR2", "Analog R2 Playback Mixer"},1468 {"HandsfreeR Mux", "AudioL2", "Analog L2 Playback Mixer"},1469 {"HandsfreeR", "Switch", "HandsfreeR Mux"},1470 {"HandsfreeR PGA", NULL, "HandsfreeR"},1471 /* Vibra */1472 {"Vibra Mux", "AudioL1", "DAC Left1"},1473 {"Vibra Mux", "AudioR1", "DAC Right1"},1474 {"Vibra Mux", "AudioL2", "DAC Left2"},1475 {"Vibra Mux", "AudioR2", "DAC Right2"},1476 1477 /* outputs */1478 /* Must be always connected (for AIF and APLL) */1479 {"Virtual HiFi OUT", NULL, "DAC Left1"},1480 {"Virtual HiFi OUT", NULL, "DAC Right1"},1481 {"Virtual HiFi OUT", NULL, "DAC Left2"},1482 {"Virtual HiFi OUT", NULL, "DAC Right2"},1483 /* Must be always connected (for APLL) */1484 {"Virtual Voice OUT", NULL, "Digital Voice Playback Mixer"},1485 /* Physical outputs */1486 {"EARPIECE", NULL, "Earpiece PGA"},1487 {"PREDRIVEL", NULL, "PredriveL PGA"},1488 {"PREDRIVER", NULL, "PredriveR PGA"},1489 {"HSOL", NULL, "HeadsetL PGA"},1490 {"HSOR", NULL, "HeadsetR PGA"},1491 {"CARKITL", NULL, "CarkitL PGA"},1492 {"CARKITR", NULL, "CarkitR PGA"},1493 {"HFL", NULL, "HandsfreeL PGA"},1494 {"HFR", NULL, "HandsfreeR PGA"},1495 {"Vibra Route", "Audio", "Vibra Mux"},1496 {"VIBRA", NULL, "Vibra Route"},1497 1498 /* Capture path */1499 /* Must be always connected (for AIF and APLL) */1500 {"ADC Virtual Left1", NULL, "Virtual HiFi IN"},1501 {"ADC Virtual Right1", NULL, "Virtual HiFi IN"},1502 {"ADC Virtual Left2", NULL, "Virtual HiFi IN"},1503 {"ADC Virtual Right2", NULL, "Virtual HiFi IN"},1504 /* Physical inputs */1505 {"Analog Left", "Main Mic Capture Switch", "MAINMIC"},1506 {"Analog Left", "Headset Mic Capture Switch", "HSMIC"},1507 {"Analog Left", "AUXL Capture Switch", "AUXL"},1508 {"Analog Left", "Carkit Mic Capture Switch", "CARKITMIC"},1509 1510 {"Analog Right", "Sub Mic Capture Switch", "SUBMIC"},1511 {"Analog Right", "AUXR Capture Switch", "AUXR"},1512 1513 {"ADC Physical Left", NULL, "Analog Left"},1514 {"ADC Physical Right", NULL, "Analog Right"},1515 1516 {"Digimic0 Enable", NULL, "DIGIMIC0"},1517 {"Digimic1 Enable", NULL, "DIGIMIC1"},1518 1519 {"DIGIMIC0", NULL, "micbias1 select"},1520 {"DIGIMIC1", NULL, "micbias2 select"},1521 1522 /* TX1 Left capture path */1523 {"TX1 Capture Route", "Analog", "ADC Physical Left"},1524 {"TX1 Capture Route", "Digimic0", "Digimic0 Enable"},1525 /* TX1 Right capture path */1526 {"TX1 Capture Route", "Analog", "ADC Physical Right"},1527 {"TX1 Capture Route", "Digimic0", "Digimic0 Enable"},1528 /* TX2 Left capture path */1529 {"TX2 Capture Route", "Analog", "ADC Physical Left"},1530 {"TX2 Capture Route", "Digimic1", "Digimic1 Enable"},1531 /* TX2 Right capture path */1532 {"TX2 Capture Route", "Analog", "ADC Physical Right"},1533 {"TX2 Capture Route", "Digimic1", "Digimic1 Enable"},1534 1535 {"ADC Virtual Left1", NULL, "TX1 Capture Route"},1536 {"ADC Virtual Right1", NULL, "TX1 Capture Route"},1537 {"ADC Virtual Left2", NULL, "TX2 Capture Route"},1538 {"ADC Virtual Right2", NULL, "TX2 Capture Route"},1539 1540 {"ADC Virtual Left1", NULL, "AIF Enable"},1541 {"ADC Virtual Right1", NULL, "AIF Enable"},1542 {"ADC Virtual Left2", NULL, "AIF Enable"},1543 {"ADC Virtual Right2", NULL, "AIF Enable"},1544 1545 /* Analog bypass routes */1546 {"Right1 Analog Loopback", "Switch", "Analog Right"},1547 {"Left1 Analog Loopback", "Switch", "Analog Left"},1548 {"Right2 Analog Loopback", "Switch", "Analog Right"},1549 {"Left2 Analog Loopback", "Switch", "Analog Left"},1550 {"Voice Analog Loopback", "Switch", "Analog Left"},1551 1552 /* Supply for the Analog loopbacks */1553 {"Right1 Analog Loopback", NULL, "FM Loop Enable"},1554 {"Left1 Analog Loopback", NULL, "FM Loop Enable"},1555 {"Right2 Analog Loopback", NULL, "FM Loop Enable"},1556 {"Left2 Analog Loopback", NULL, "FM Loop Enable"},1557 {"Voice Analog Loopback", NULL, "FM Loop Enable"},1558 1559 {"Analog R1 Playback Mixer", NULL, "Right1 Analog Loopback"},1560 {"Analog L1 Playback Mixer", NULL, "Left1 Analog Loopback"},1561 {"Analog R2 Playback Mixer", NULL, "Right2 Analog Loopback"},1562 {"Analog L2 Playback Mixer", NULL, "Left2 Analog Loopback"},1563 {"Analog Voice Playback Mixer", NULL, "Voice Analog Loopback"},1564 1565 /* Digital bypass routes */1566 {"Right Digital Loopback", "Volume", "TX1 Capture Route"},1567 {"Left Digital Loopback", "Volume", "TX1 Capture Route"},1568 {"Voice Digital Loopback", "Volume", "TX2 Capture Route"},1569 1570 {"Digital R2 Playback Mixer", NULL, "Right Digital Loopback"},1571 {"Digital L2 Playback Mixer", NULL, "Left Digital Loopback"},1572 {"Digital Voice Playback Mixer", NULL, "Voice Digital Loopback"},1573 1574};1575 1576static int twl4030_set_bias_level(struct snd_soc_component *component,1577 enum snd_soc_bias_level level)1578{1579 switch (level) {1580 case SND_SOC_BIAS_ON:1581 break;1582 case SND_SOC_BIAS_PREPARE:1583 break;1584 case SND_SOC_BIAS_STANDBY:1585 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF)1586 twl4030_codec_enable(component, 1);1587 break;1588 case SND_SOC_BIAS_OFF:1589 twl4030_codec_enable(component, 0);1590 break;1591 }1592 1593 return 0;1594}1595 1596static void twl4030_constraints(struct twl4030_priv *twl4030,1597 struct snd_pcm_substream *mst_substream)1598{1599 struct snd_pcm_substream *slv_substream;1600 1601 /* Pick the stream, which need to be constrained */1602 if (mst_substream == twl4030->master_substream)1603 slv_substream = twl4030->slave_substream;1604 else if (mst_substream == twl4030->slave_substream)1605 slv_substream = twl4030->master_substream;1606 else /* This should not happen.. */1607 return;1608 1609 /* Set the constraints according to the already configured stream */1610 snd_pcm_hw_constraint_single(slv_substream->runtime,1611 SNDRV_PCM_HW_PARAM_RATE,1612 twl4030->rate);1613 1614 snd_pcm_hw_constraint_single(slv_substream->runtime,1615 SNDRV_PCM_HW_PARAM_SAMPLE_BITS,1616 twl4030->sample_bits);1617 1618 snd_pcm_hw_constraint_single(slv_substream->runtime,1619 SNDRV_PCM_HW_PARAM_CHANNELS,1620 twl4030->channels);1621}1622 1623/* In case of 4 channel mode, the RX1 L/R for playback and the TX2 L/R for1624 * capture has to be enabled/disabled. */1625static void twl4030_tdm_enable(struct snd_soc_component *component, int direction,1626 int enable)1627{1628 u8 reg, mask;1629 1630 reg = twl4030_read(component, TWL4030_REG_OPTION);1631 1632 if (direction == SNDRV_PCM_STREAM_PLAYBACK)1633 mask = TWL4030_ARXL1_VRX_EN | TWL4030_ARXR1_EN;1634 else1635 mask = TWL4030_ATXL2_VTXL_EN | TWL4030_ATXR2_VTXR_EN;1636 1637 if (enable)1638 reg |= mask;1639 else1640 reg &= ~mask;1641 1642 twl4030_write(component, TWL4030_REG_OPTION, reg);1643}1644 1645static int twl4030_startup(struct snd_pcm_substream *substream,1646 struct snd_soc_dai *dai)1647{1648 struct snd_soc_component *component = dai->component;1649 struct twl4030_priv *twl4030 = snd_soc_component_get_drvdata(component);1650 1651 if (twl4030->master_substream) {1652 twl4030->slave_substream = substream;1653 /* The DAI has one configuration for playback and capture, so1654 * if the DAI has been already configured then constrain this1655 * substream to match it. */1656 if (twl4030->configured)1657 twl4030_constraints(twl4030, twl4030->master_substream);1658 } else {1659 if (!(twl4030_read(component, TWL4030_REG_CODEC_MODE) &1660 TWL4030_OPTION_1)) {1661 /* In option2 4 channel is not supported, set the1662 * constraint for the first stream for channels, the1663 * second stream will 'inherit' this cosntraint */1664 snd_pcm_hw_constraint_single(substream->runtime,1665 SNDRV_PCM_HW_PARAM_CHANNELS,1666 2);1667 }1668 twl4030->master_substream = substream;1669 }1670 1671 return 0;1672}1673 1674static void twl4030_shutdown(struct snd_pcm_substream *substream,1675 struct snd_soc_dai *dai)1676{1677 struct snd_soc_component *component = dai->component;1678 struct twl4030_priv *twl4030 = snd_soc_component_get_drvdata(component);1679 1680 if (twl4030->master_substream == substream)1681 twl4030->master_substream = twl4030->slave_substream;1682 1683 twl4030->slave_substream = NULL;1684 1685 /* If all streams are closed, or the remaining stream has not yet1686 * been configured than set the DAI as not configured. */1687 if (!twl4030->master_substream)1688 twl4030->configured = 0;1689 else if (!twl4030->master_substream->runtime->channels)1690 twl4030->configured = 0;1691 1692 /* If the closing substream had 4 channel, do the necessary cleanup */1693 if (substream->runtime->channels == 4)1694 twl4030_tdm_enable(component, substream->stream, 0);1695}1696 1697static int twl4030_hw_params(struct snd_pcm_substream *substream,1698 struct snd_pcm_hw_params *params,1699 struct snd_soc_dai *dai)1700{1701 struct snd_soc_component *component = dai->component;1702 struct twl4030_priv *twl4030 = snd_soc_component_get_drvdata(component);1703 u8 mode, old_mode, format, old_format;1704 1705 /* If the substream has 4 channel, do the necessary setup */1706 if (params_channels(params) == 4) {1707 format = twl4030_read(component, TWL4030_REG_AUDIO_IF);1708 mode = twl4030_read(component, TWL4030_REG_CODEC_MODE);1709 1710 /* Safety check: are we in the correct operating mode and1711 * the interface is in TDM mode? */1712 if ((mode & TWL4030_OPTION_1) &&1713 ((format & TWL4030_AIF_FORMAT) == TWL4030_AIF_FORMAT_TDM))1714 twl4030_tdm_enable(component, substream->stream, 1);1715 else1716 return -EINVAL;1717 }1718 1719 if (twl4030->configured)1720 /* Ignoring hw_params for already configured DAI */1721 return 0;1722 1723 /* bit rate */1724 old_mode = twl4030_read(component,1725 TWL4030_REG_CODEC_MODE) & ~TWL4030_CODECPDZ;1726 mode = old_mode & ~TWL4030_APLL_RATE;1727 1728 switch (params_rate(params)) {1729 case 8000:1730 mode |= TWL4030_APLL_RATE_8000;1731 break;1732 case 11025:1733 mode |= TWL4030_APLL_RATE_11025;1734 break;1735 case 12000:1736 mode |= TWL4030_APLL_RATE_12000;1737 break;1738 case 16000:1739 mode |= TWL4030_APLL_RATE_16000;1740 break;1741 case 22050:1742 mode |= TWL4030_APLL_RATE_22050;1743 break;1744 case 24000:1745 mode |= TWL4030_APLL_RATE_24000;1746 break;1747 case 32000:1748 mode |= TWL4030_APLL_RATE_32000;1749 break;1750 case 44100:1751 mode |= TWL4030_APLL_RATE_44100;1752 break;1753 case 48000:1754 mode |= TWL4030_APLL_RATE_48000;1755 break;1756 case 96000:1757 mode |= TWL4030_APLL_RATE_96000;1758 break;1759 default:1760 dev_err(component->dev, "%s: unknown rate %d\n", __func__,1761 params_rate(params));1762 return -EINVAL;1763 }1764 1765 /* sample size */1766 old_format = twl4030_read(component, TWL4030_REG_AUDIO_IF);1767 format = old_format;1768 format &= ~TWL4030_DATA_WIDTH;1769 switch (params_width(params)) {1770 case 16:1771 format |= TWL4030_DATA_WIDTH_16S_16W;1772 break;1773 case 32:1774 format |= TWL4030_DATA_WIDTH_32S_24W;1775 break;1776 default:1777 dev_err(component->dev, "%s: unsupported bits/sample %d\n",1778 __func__, params_width(params));1779 return -EINVAL;1780 }1781 1782 if (format != old_format || mode != old_mode) {1783 if (twl4030->codec_powered) {1784 /*1785 * If the codec is powered, than we need to toggle the1786 * codec power.1787 */1788 twl4030_codec_enable(component, 0);1789 twl4030_write(component, TWL4030_REG_CODEC_MODE, mode);1790 twl4030_write(component, TWL4030_REG_AUDIO_IF, format);1791 twl4030_codec_enable(component, 1);1792 } else {1793 twl4030_write(component, TWL4030_REG_CODEC_MODE, mode);1794 twl4030_write(component, TWL4030_REG_AUDIO_IF, format);1795 }1796 }1797 1798 /* Store the important parameters for the DAI configuration and set1799 * the DAI as configured */1800 twl4030->configured = 1;1801 twl4030->rate = params_rate(params);1802 twl4030->sample_bits = hw_param_interval(params,1803 SNDRV_PCM_HW_PARAM_SAMPLE_BITS)->min;1804 twl4030->channels = params_channels(params);1805 1806 /* If both playback and capture streams are open, and one of them1807 * is setting the hw parameters right now (since we are here), set1808 * constraints to the other stream to match the current one. */1809 if (twl4030->slave_substream)1810 twl4030_constraints(twl4030, substream);1811 1812 return 0;1813}1814 1815static int twl4030_set_dai_sysclk(struct snd_soc_dai *codec_dai, int clk_id,1816 unsigned int freq, int dir)1817{1818 struct snd_soc_component *component = codec_dai->component;1819 struct twl4030_priv *twl4030 = snd_soc_component_get_drvdata(component);1820 1821 switch (freq) {1822 case 19200000:1823 case 26000000:1824 case 38400000:1825 break;1826 default:1827 dev_err(component->dev, "Unsupported HFCLKIN: %u\n", freq);1828 return -EINVAL;1829 }1830 1831 if ((freq / 1000) != twl4030->sysclk) {1832 dev_err(component->dev,1833 "Mismatch in HFCLKIN: %u (configured: %u)\n",1834 freq, twl4030->sysclk * 1000);1835 return -EINVAL;1836 }1837 1838 return 0;1839}1840 1841static int twl4030_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)1842{1843 struct snd_soc_component *component = codec_dai->component;1844 struct twl4030_priv *twl4030 = snd_soc_component_get_drvdata(component);1845 u8 old_format, format;1846 1847 /* get format */1848 old_format = twl4030_read(component, TWL4030_REG_AUDIO_IF);1849 format = old_format;1850 1851 switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {1852 case SND_SOC_DAIFMT_CBP_CFP:1853 format &= ~(TWL4030_AIF_SLAVE_EN);1854 format &= ~(TWL4030_CLK256FS_EN);1855 break;1856 case SND_SOC_DAIFMT_CBC_CFC:1857 format |= TWL4030_AIF_SLAVE_EN;1858 format |= TWL4030_CLK256FS_EN;1859 break;1860 default:1861 return -EINVAL;1862 }1863 1864 /* interface format */1865 format &= ~TWL4030_AIF_FORMAT;1866 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {1867 case SND_SOC_DAIFMT_I2S:1868 format |= TWL4030_AIF_FORMAT_CODEC;1869 break;1870 case SND_SOC_DAIFMT_DSP_A:1871 format |= TWL4030_AIF_FORMAT_TDM;1872 break;1873 default:1874 return -EINVAL;1875 }1876 1877 if (format != old_format) {1878 if (twl4030->codec_powered) {1879 /*1880 * If the codec is powered, than we need to toggle the1881 * codec power.1882 */1883 twl4030_codec_enable(component, 0);1884 twl4030_write(component, TWL4030_REG_AUDIO_IF, format);1885 twl4030_codec_enable(component, 1);1886 } else {1887 twl4030_write(component, TWL4030_REG_AUDIO_IF, format);1888 }1889 }1890 1891 return 0;1892}1893 1894static int twl4030_set_tristate(struct snd_soc_dai *dai, int tristate)1895{1896 struct snd_soc_component *component = dai->component;1897 u8 reg = twl4030_read(component, TWL4030_REG_AUDIO_IF);1898 1899 if (tristate)1900 reg |= TWL4030_AIF_TRI_EN;1901 else1902 reg &= ~TWL4030_AIF_TRI_EN;1903 1904 return twl4030_write(component, TWL4030_REG_AUDIO_IF, reg);1905}1906 1907/* In case of voice mode, the RX1 L(VRX) for downlink and the TX2 L/R1908 * (VTXL, VTXR) for uplink has to be enabled/disabled. */1909static void twl4030_voice_enable(struct snd_soc_component *component, int direction,1910 int enable)1911{1912 u8 reg, mask;1913 1914 reg = twl4030_read(component, TWL4030_REG_OPTION);1915 1916 if (direction == SNDRV_PCM_STREAM_PLAYBACK)1917 mask = TWL4030_ARXL1_VRX_EN;1918 else1919 mask = TWL4030_ATXL2_VTXL_EN | TWL4030_ATXR2_VTXR_EN;1920 1921 if (enable)1922 reg |= mask;1923 else1924 reg &= ~mask;1925 1926 twl4030_write(component, TWL4030_REG_OPTION, reg);1927}1928 1929static int twl4030_voice_startup(struct snd_pcm_substream *substream,1930 struct snd_soc_dai *dai)1931{1932 struct snd_soc_component *component = dai->component;1933 struct twl4030_priv *twl4030 = snd_soc_component_get_drvdata(component);1934 u8 mode;1935 1936 /* If the system master clock is not 26MHz, the voice PCM interface is1937 * not available.1938 */1939 if (twl4030->sysclk != 26000) {1940 dev_err(component->dev,1941 "%s: HFCLKIN is %u KHz, voice interface needs 26MHz\n",1942 __func__, twl4030->sysclk);1943 return -EINVAL;1944 }1945 1946 /* If the codec mode is not option2, the voice PCM interface is not1947 * available.1948 */1949 mode = twl4030_read(component, TWL4030_REG_CODEC_MODE)1950 & TWL4030_OPT_MODE;1951 1952 if (mode != TWL4030_OPTION_2) {1953 dev_err(component->dev, "%s: the codec mode is not option2\n",1954 __func__);1955 return -EINVAL;1956 }1957 1958 return 0;1959}1960 1961static void twl4030_voice_shutdown(struct snd_pcm_substream *substream,1962 struct snd_soc_dai *dai)1963{1964 struct snd_soc_component *component = dai->component;1965 1966 /* Enable voice digital filters */1967 twl4030_voice_enable(component, substream->stream, 0);1968}1969 1970static int twl4030_voice_hw_params(struct snd_pcm_substream *substream,1971 struct snd_pcm_hw_params *params,1972 struct snd_soc_dai *dai)1973{1974 struct snd_soc_component *component = dai->component;1975 struct twl4030_priv *twl4030 = snd_soc_component_get_drvdata(component);1976 u8 old_mode, mode;1977 1978 /* Enable voice digital filters */1979 twl4030_voice_enable(component, substream->stream, 1);1980 1981 /* bit rate */1982 old_mode = twl4030_read(component,1983 TWL4030_REG_CODEC_MODE) & ~TWL4030_CODECPDZ;1984 mode = old_mode;1985 1986 switch (params_rate(params)) {1987 case 8000:1988 mode &= ~(TWL4030_SEL_16K);1989 break;1990 case 16000:1991 mode |= TWL4030_SEL_16K;1992 break;1993 default:1994 dev_err(component->dev, "%s: unknown rate %d\n", __func__,1995 params_rate(params));1996 return -EINVAL;1997 }1998 1999 if (mode != old_mode) {2000 if (twl4030->codec_powered) {2001 /*2002 * If the codec is powered, than we need to toggle the2003 * codec power.2004 */2005 twl4030_codec_enable(component, 0);2006 twl4030_write(component, TWL4030_REG_CODEC_MODE, mode);2007 twl4030_codec_enable(component, 1);2008 } else {2009 twl4030_write(component, TWL4030_REG_CODEC_MODE, mode);2010 }2011 }2012 2013 return 0;2014}2015 2016static int twl4030_voice_set_dai_sysclk(struct snd_soc_dai *codec_dai,2017 int clk_id, unsigned int freq, int dir)2018{2019 struct snd_soc_component *component = codec_dai->component;2020 struct twl4030_priv *twl4030 = snd_soc_component_get_drvdata(component);2021 2022 if (freq != 26000000) {2023 dev_err(component->dev,2024 "%s: HFCLKIN is %u KHz, voice interface needs 26MHz\n",2025 __func__, freq / 1000);2026 return -EINVAL;2027 }2028 if ((freq / 1000) != twl4030->sysclk) {2029 dev_err(component->dev,2030 "Mismatch in HFCLKIN: %u (configured: %u)\n",2031 freq, twl4030->sysclk * 1000);2032 return -EINVAL;2033 }2034 return 0;2035}2036 2037static int twl4030_voice_set_dai_fmt(struct snd_soc_dai *codec_dai,2038 unsigned int fmt)2039{2040 struct snd_soc_component *component = codec_dai->component;2041 struct twl4030_priv *twl4030 = snd_soc_component_get_drvdata(component);2042 u8 old_format, format;2043 2044 /* get format */2045 old_format = twl4030_read(component, TWL4030_REG_VOICE_IF);2046 format = old_format;2047 2048 switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {2049 case SND_SOC_DAIFMT_CBP_CFP:2050 format &= ~(TWL4030_VIF_SLAVE_EN);2051 break;2052 case SND_SOC_DAIFMT_CBS_CFS:2053 format |= TWL4030_VIF_SLAVE_EN;2054 break;2055 default:2056 return -EINVAL;2057 }2058 2059 /* clock inversion */2060 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {2061 case SND_SOC_DAIFMT_IB_NF:2062 format &= ~(TWL4030_VIF_FORMAT);2063 break;2064 case SND_SOC_DAIFMT_NB_IF:2065 format |= TWL4030_VIF_FORMAT;2066 break;2067 default:2068 return -EINVAL;2069 }2070 2071 if (format != old_format) {2072 if (twl4030->codec_powered) {2073 /*2074 * If the codec is powered, than we need to toggle the2075 * codec power.2076 */2077 twl4030_codec_enable(component, 0);2078 twl4030_write(component, TWL4030_REG_VOICE_IF, format);2079 twl4030_codec_enable(component, 1);2080 } else {2081 twl4030_write(component, TWL4030_REG_VOICE_IF, format);2082 }2083 }2084 2085 return 0;2086}2087 2088static int twl4030_voice_set_tristate(struct snd_soc_dai *dai, int tristate)2089{2090 struct snd_soc_component *component = dai->component;2091 u8 reg = twl4030_read(component, TWL4030_REG_VOICE_IF);2092 2093 if (tristate)2094 reg |= TWL4030_VIF_TRI_EN;2095 else2096 reg &= ~TWL4030_VIF_TRI_EN;2097 2098 return twl4030_write(component, TWL4030_REG_VOICE_IF, reg);2099}2100 2101#define TWL4030_RATES (SNDRV_PCM_RATE_8000_48000)2102#define TWL4030_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE)2103 2104static const struct snd_soc_dai_ops twl4030_dai_hifi_ops = {2105 .startup = twl4030_startup,2106 .shutdown = twl4030_shutdown,2107 .hw_params = twl4030_hw_params,2108 .set_sysclk = twl4030_set_dai_sysclk,2109 .set_fmt = twl4030_set_dai_fmt,2110 .set_tristate = twl4030_set_tristate,2111};2112 2113static const struct snd_soc_dai_ops twl4030_dai_voice_ops = {2114 .startup = twl4030_voice_startup,2115 .shutdown = twl4030_voice_shutdown,2116 .hw_params = twl4030_voice_hw_params,2117 .set_sysclk = twl4030_voice_set_dai_sysclk,2118 .set_fmt = twl4030_voice_set_dai_fmt,2119 .set_tristate = twl4030_voice_set_tristate,2120};2121 2122static struct snd_soc_dai_driver twl4030_dai[] = {2123{2124 .name = "twl4030-hifi",2125 .playback = {2126 .stream_name = "HiFi Playback",2127 .channels_min = 2,2128 .channels_max = 4,2129 .rates = TWL4030_RATES | SNDRV_PCM_RATE_96000,2130 .formats = TWL4030_FORMATS,2131 .sig_bits = 24,},2132 .capture = {2133 .stream_name = "HiFi Capture",2134 .channels_min = 2,2135 .channels_max = 4,2136 .rates = TWL4030_RATES,2137 .formats = TWL4030_FORMATS,2138 .sig_bits = 24,},2139 .ops = &twl4030_dai_hifi_ops,2140},2141{2142 .name = "twl4030-voice",2143 .playback = {2144 .stream_name = "Voice Playback",2145 .channels_min = 1,2146 .channels_max = 1,2147 .rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000,2148 .formats = SNDRV_PCM_FMTBIT_S16_LE,},2149 .capture = {2150 .stream_name = "Voice Capture",2151 .channels_min = 1,2152 .channels_max = 2,2153 .rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000,2154 .formats = SNDRV_PCM_FMTBIT_S16_LE,},2155 .ops = &twl4030_dai_voice_ops,2156},2157};2158 2159static int twl4030_soc_probe(struct snd_soc_component *component)2160{2161 struct twl4030_priv *twl4030;2162 2163 twl4030 = devm_kzalloc(component->dev, sizeof(struct twl4030_priv),2164 GFP_KERNEL);2165 if (!twl4030)2166 return -ENOMEM;2167 snd_soc_component_set_drvdata(component, twl4030);2168 /* Set the defaults, and power up the codec */2169 twl4030->sysclk = twl4030_audio_get_mclk() / 1000;2170 2171 twl4030_init_chip(component);2172 2173 return 0;2174}2175 2176static void twl4030_soc_remove(struct snd_soc_component *component)2177{2178 struct twl4030_priv *twl4030 = snd_soc_component_get_drvdata(component);2179 struct twl4030_board_params *board_params = twl4030->board_params;2180 2181 if (board_params && board_params->hs_extmute &&2182 gpio_is_valid(board_params->hs_extmute_gpio))2183 gpio_free(board_params->hs_extmute_gpio);2184}2185 2186static const struct snd_soc_component_driver soc_component_dev_twl4030 = {2187 .probe = twl4030_soc_probe,2188 .remove = twl4030_soc_remove,2189 .read = twl4030_read,2190 .write = twl4030_write,2191 .set_bias_level = twl4030_set_bias_level,2192 .controls = twl4030_snd_controls,2193 .num_controls = ARRAY_SIZE(twl4030_snd_controls),2194 .dapm_widgets = twl4030_dapm_widgets,2195 .num_dapm_widgets = ARRAY_SIZE(twl4030_dapm_widgets),2196 .dapm_routes = intercon,2197 .num_dapm_routes = ARRAY_SIZE(intercon),2198 .use_pmdown_time = 1,2199 .endianness = 1,2200};2201 2202static int twl4030_codec_probe(struct platform_device *pdev)2203{2204 return devm_snd_soc_register_component(&pdev->dev,2205 &soc_component_dev_twl4030,2206 twl4030_dai, ARRAY_SIZE(twl4030_dai));2207}2208 2209MODULE_ALIAS("platform:twl4030-codec");2210 2211static struct platform_driver twl4030_codec_driver = {2212 .probe = twl4030_codec_probe,2213 .driver = {2214 .name = "twl4030-codec",2215 },2216};2217 2218module_platform_driver(twl4030_codec_driver);2219 2220MODULE_DESCRIPTION("ASoC TWL4030 codec driver");2221MODULE_AUTHOR("Steve Sakoman");2222MODULE_LICENSE("GPL");2223