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1// SPDX-License-Identifier: GPL-2.0-only2/*3 * uda1380.c - Philips UDA1380 ALSA SoC audio driver4 *5 * Copyright (c) 2007-2009 Philipp Zabel <philipp.zabel@gmail.com>6 *7 * Modified by Richard Purdie <richard@openedhand.com> to fit into SoC8 * codec model.9 *10 * Copyright (c) 2005 Giorgio Padrin <giorgio@mandarinlogiq.org>11 * Copyright 2005 Openedhand Ltd.12 */13 14#include <linux/module.h>15#include <linux/init.h>16#include <linux/types.h>17#include <linux/slab.h>18#include <linux/errno.h>19#include <linux/gpio.h>20#include <linux/delay.h>21#include <linux/i2c.h>22#include <linux/workqueue.h>23#include <sound/core.h>24#include <sound/control.h>25#include <sound/initval.h>26#include <sound/soc.h>27#include <sound/tlv.h>28#include <sound/uda1380.h>29 30#include "uda1380.h"31 32/* codec private data */33struct uda1380_priv {34 struct snd_soc_component *component;35 unsigned int dac_clk;36 struct work_struct work;37 struct i2c_client *i2c;38 u16 *reg_cache;39};40 41/*42 * uda1380 register cache43 */44static const u16 uda1380_reg[UDA1380_CACHEREGNUM] = {45 0x0502, 0x0000, 0x0000, 0x3f3f,46 0x0202, 0x0000, 0x0000, 0x0000,47 0x0000, 0x0000, 0x0000, 0x0000,48 0x0000, 0x0000, 0x0000, 0x0000,49 0x0000, 0xff00, 0x0000, 0x4800,50 0x0000, 0x0000, 0x0000, 0x0000,51 0x0000, 0x0000, 0x0000, 0x0000,52 0x0000, 0x0000, 0x0000, 0x0000,53 0x0000, 0x8000, 0x0002, 0x0000,54};55 56static unsigned long uda1380_cache_dirty;57 58/*59 * read uda1380 register cache60 */61static inline unsigned int uda1380_read_reg_cache(struct snd_soc_component *component,62 unsigned int reg)63{64 struct uda1380_priv *uda1380 = snd_soc_component_get_drvdata(component);65 u16 *cache = uda1380->reg_cache;66 67 if (reg == UDA1380_RESET)68 return 0;69 if (reg >= UDA1380_CACHEREGNUM)70 return -1;71 return cache[reg];72}73 74/*75 * write uda1380 register cache76 */77static inline void uda1380_write_reg_cache(struct snd_soc_component *component,78 u16 reg, unsigned int value)79{80 struct uda1380_priv *uda1380 = snd_soc_component_get_drvdata(component);81 u16 *cache = uda1380->reg_cache;82 83 if (reg >= UDA1380_CACHEREGNUM)84 return;85 if ((reg >= 0x10) && (cache[reg] != value))86 set_bit(reg - 0x10, &uda1380_cache_dirty);87 cache[reg] = value;88}89 90/*91 * write to the UDA1380 register space92 */93static int uda1380_write(struct snd_soc_component *component, unsigned int reg,94 unsigned int value)95{96 struct uda1380_priv *uda1380 = snd_soc_component_get_drvdata(component);97 u8 data[3];98 99 /* data is100 * data[0] is register offset101 * data[1] is MS byte102 * data[2] is LS byte103 */104 data[0] = reg;105 data[1] = (value & 0xff00) >> 8;106 data[2] = value & 0x00ff;107 108 uda1380_write_reg_cache(component, reg, value);109 110 /* the interpolator & decimator regs must only be written when the111 * codec DAI is active.112 */113 if (!snd_soc_component_active(component) && (reg >= UDA1380_MVOL))114 return 0;115 pr_debug("uda1380: hw write %x val %x\n", reg, value);116 if (i2c_master_send(uda1380->i2c, data, 3) == 3) {117 unsigned int val;118 i2c_master_send(uda1380->i2c, data, 1);119 i2c_master_recv(uda1380->i2c, data, 2);120 val = (data[0]<<8) | data[1];121 if (val != value) {122 pr_debug("uda1380: READ BACK VAL %x\n",123 (data[0]<<8) | data[1]);124 return -EIO;125 }126 if (reg >= 0x10)127 clear_bit(reg - 0x10, &uda1380_cache_dirty);128 return 0;129 } else130 return -EIO;131}132 133static void uda1380_sync_cache(struct snd_soc_component *component)134{135 struct uda1380_priv *uda1380 = snd_soc_component_get_drvdata(component);136 int reg;137 u8 data[3];138 u16 *cache = uda1380->reg_cache;139 140 /* Sync reg_cache with the hardware */141 for (reg = 0; reg < UDA1380_MVOL; reg++) {142 data[0] = reg;143 data[1] = (cache[reg] & 0xff00) >> 8;144 data[2] = cache[reg] & 0x00ff;145 if (i2c_master_send(uda1380->i2c, data, 3) != 3)146 dev_err(component->dev, "%s: write to reg 0x%x failed\n",147 __func__, reg);148 }149}150 151static int uda1380_reset(struct snd_soc_component *component)152{153 struct uda1380_platform_data *pdata = component->dev->platform_data;154 struct uda1380_priv *uda1380 = snd_soc_component_get_drvdata(component);155 156 if (gpio_is_valid(pdata->gpio_reset)) {157 gpio_set_value(pdata->gpio_reset, 1);158 mdelay(1);159 gpio_set_value(pdata->gpio_reset, 0);160 } else {161 u8 data[3];162 163 data[0] = UDA1380_RESET;164 data[1] = 0;165 data[2] = 0;166 167 if (i2c_master_send(uda1380->i2c, data, 3) != 3) {168 dev_err(component->dev, "%s: failed\n", __func__);169 return -EIO;170 }171 }172 173 return 0;174}175 176static void uda1380_flush_work(struct work_struct *work)177{178 struct uda1380_priv *uda1380 = container_of(work, struct uda1380_priv, work);179 struct snd_soc_component *uda1380_component = uda1380->component;180 int bit, reg;181 182 for_each_set_bit(bit, &uda1380_cache_dirty, UDA1380_CACHEREGNUM - 0x10) {183 reg = 0x10 + bit;184 pr_debug("uda1380: flush reg %x val %x:\n", reg,185 uda1380_read_reg_cache(uda1380_component, reg));186 uda1380_write(uda1380_component, reg,187 uda1380_read_reg_cache(uda1380_component, reg));188 clear_bit(bit, &uda1380_cache_dirty);189 }190 191}192 193/* declarations of ALSA reg_elem_REAL controls */194static const char *uda1380_deemp[] = {195 "None",196 "32kHz",197 "44.1kHz",198 "48kHz",199 "96kHz",200};201static const char *uda1380_input_sel[] = {202 "Line",203 "Mic + Line R",204 "Line L",205 "Mic",206};207static const char *uda1380_output_sel[] = {208 "DAC",209 "Analog Mixer",210};211static const char *uda1380_spf_mode[] = {212 "Flat",213 "Minimum1",214 "Minimum2",215 "Maximum"216};217static const char *uda1380_capture_sel[] = {218 "ADC",219 "Digital Mixer"220};221static const char *uda1380_sel_ns[] = {222 "3rd-order",223 "5th-order"224};225static const char *uda1380_mix_control[] = {226 "off",227 "PCM only",228 "before sound processing",229 "after sound processing"230};231static const char *uda1380_sdet_setting[] = {232 "3200",233 "4800",234 "9600",235 "19200"236};237static const char *uda1380_os_setting[] = {238 "single-speed",239 "double-speed (no mixing)",240 "quad-speed (no mixing)"241};242 243static const struct soc_enum uda1380_deemp_enum[] = {244 SOC_ENUM_SINGLE(UDA1380_DEEMP, 8, ARRAY_SIZE(uda1380_deemp),245 uda1380_deemp),246 SOC_ENUM_SINGLE(UDA1380_DEEMP, 0, ARRAY_SIZE(uda1380_deemp),247 uda1380_deemp),248};249static SOC_ENUM_SINGLE_DECL(uda1380_input_sel_enum,250 UDA1380_ADC, 2, uda1380_input_sel); /* SEL_MIC, SEL_LNA */251static SOC_ENUM_SINGLE_DECL(uda1380_output_sel_enum,252 UDA1380_PM, 7, uda1380_output_sel); /* R02_EN_AVC */253static SOC_ENUM_SINGLE_DECL(uda1380_spf_enum,254 UDA1380_MODE, 14, uda1380_spf_mode); /* M */255static SOC_ENUM_SINGLE_DECL(uda1380_capture_sel_enum,256 UDA1380_IFACE, 6, uda1380_capture_sel); /* SEL_SOURCE */257static SOC_ENUM_SINGLE_DECL(uda1380_sel_ns_enum,258 UDA1380_MIXER, 14, uda1380_sel_ns); /* SEL_NS */259static SOC_ENUM_SINGLE_DECL(uda1380_mix_enum,260 UDA1380_MIXER, 12, uda1380_mix_control); /* MIX, MIX_POS */261static SOC_ENUM_SINGLE_DECL(uda1380_sdet_enum,262 UDA1380_MIXER, 4, uda1380_sdet_setting); /* SD_VALUE */263static SOC_ENUM_SINGLE_DECL(uda1380_os_enum,264 UDA1380_MIXER, 0, uda1380_os_setting); /* OS */265 266/*267 * from -48 dB in 1.5 dB steps (mute instead of -49.5 dB)268 */269static DECLARE_TLV_DB_SCALE(amix_tlv, -4950, 150, 1);270 271/*272 * from -78 dB in 1 dB steps (3 dB steps, really. LSB are ignored),273 * from -66 dB in 0.5 dB steps (2 dB steps, really) and274 * from -52 dB in 0.25 dB steps275 */276static const DECLARE_TLV_DB_RANGE(mvol_tlv,277 0, 15, TLV_DB_SCALE_ITEM(-8200, 100, 1),278 16, 43, TLV_DB_SCALE_ITEM(-6600, 50, 0),279 44, 252, TLV_DB_SCALE_ITEM(-5200, 25, 0)280);281 282/*283 * from -72 dB in 1.5 dB steps (6 dB steps really),284 * from -66 dB in 0.75 dB steps (3 dB steps really),285 * from -60 dB in 0.5 dB steps (2 dB steps really) and286 * from -46 dB in 0.25 dB steps287 */288static const DECLARE_TLV_DB_RANGE(vc_tlv,289 0, 7, TLV_DB_SCALE_ITEM(-7800, 150, 1),290 8, 15, TLV_DB_SCALE_ITEM(-6600, 75, 0),291 16, 43, TLV_DB_SCALE_ITEM(-6000, 50, 0),292 44, 228, TLV_DB_SCALE_ITEM(-4600, 25, 0)293);294 295/* from 0 to 6 dB in 2 dB steps if SPF mode != flat */296static DECLARE_TLV_DB_SCALE(tr_tlv, 0, 200, 0);297 298/* from 0 to 24 dB in 2 dB steps, if SPF mode == maximum, otherwise cuts299 * off at 18 dB max) */300static DECLARE_TLV_DB_SCALE(bb_tlv, 0, 200, 0);301 302/* from -63 to 24 dB in 0.5 dB steps (-128...48) */303static DECLARE_TLV_DB_SCALE(dec_tlv, -6400, 50, 1);304 305/* from 0 to 24 dB in 3 dB steps */306static DECLARE_TLV_DB_SCALE(pga_tlv, 0, 300, 0);307 308/* from 0 to 30 dB in 2 dB steps */309static DECLARE_TLV_DB_SCALE(vga_tlv, 0, 200, 0);310 311static const struct snd_kcontrol_new uda1380_snd_controls[] = {312 SOC_DOUBLE_TLV("Analog Mixer Volume", UDA1380_AMIX, 0, 8, 44, 1, amix_tlv), /* AVCR, AVCL */313 SOC_DOUBLE_TLV("Master Playback Volume", UDA1380_MVOL, 0, 8, 252, 1, mvol_tlv), /* MVCL, MVCR */314 SOC_SINGLE_TLV("ADC Playback Volume", UDA1380_MIXVOL, 8, 228, 1, vc_tlv), /* VC2 */315 SOC_SINGLE_TLV("PCM Playback Volume", UDA1380_MIXVOL, 0, 228, 1, vc_tlv), /* VC1 */316 SOC_ENUM("Sound Processing Filter", uda1380_spf_enum), /* M */317 SOC_DOUBLE_TLV("Tone Control - Treble", UDA1380_MODE, 4, 12, 3, 0, tr_tlv), /* TRL, TRR */318 SOC_DOUBLE_TLV("Tone Control - Bass", UDA1380_MODE, 0, 8, 15, 0, bb_tlv), /* BBL, BBR */319/**/ SOC_SINGLE("Master Playback Switch", UDA1380_DEEMP, 14, 1, 1), /* MTM */320 SOC_SINGLE("ADC Playback Switch", UDA1380_DEEMP, 11, 1, 1), /* MT2 from decimation filter */321 SOC_ENUM("ADC Playback De-emphasis", uda1380_deemp_enum[0]), /* DE2 */322 SOC_SINGLE("PCM Playback Switch", UDA1380_DEEMP, 3, 1, 1), /* MT1, from digital data input */323 SOC_ENUM("PCM Playback De-emphasis", uda1380_deemp_enum[1]), /* DE1 */324 SOC_SINGLE("DAC Polarity inverting Switch", UDA1380_MIXER, 15, 1, 0), /* DA_POL_INV */325 SOC_ENUM("Noise Shaper", uda1380_sel_ns_enum), /* SEL_NS */326 SOC_ENUM("Digital Mixer Signal Control", uda1380_mix_enum), /* MIX_POS, MIX */327 SOC_SINGLE("Silence Detector Switch", UDA1380_MIXER, 6, 1, 0), /* SDET_ON */328 SOC_ENUM("Silence Detector Setting", uda1380_sdet_enum), /* SD_VALUE */329 SOC_ENUM("Oversampling Input", uda1380_os_enum), /* OS */330 SOC_DOUBLE_S8_TLV("ADC Capture Volume", UDA1380_DEC, -128, 48, dec_tlv), /* ML_DEC, MR_DEC */331/**/ SOC_SINGLE("ADC Capture Switch", UDA1380_PGA, 15, 1, 1), /* MT_ADC */332 SOC_DOUBLE_TLV("Line Capture Volume", UDA1380_PGA, 0, 8, 8, 0, pga_tlv), /* PGA_GAINCTRLL, PGA_GAINCTRLR */333 SOC_SINGLE("ADC Polarity inverting Switch", UDA1380_ADC, 12, 1, 0), /* ADCPOL_INV */334 SOC_SINGLE_TLV("Mic Capture Volume", UDA1380_ADC, 8, 15, 0, vga_tlv), /* VGA_CTRL */335 SOC_SINGLE("DC Filter Bypass Switch", UDA1380_ADC, 1, 1, 0), /* SKIP_DCFIL (before decimator) */336 SOC_SINGLE("DC Filter Enable Switch", UDA1380_ADC, 0, 1, 0), /* EN_DCFIL (at output of decimator) */337 SOC_SINGLE("AGC Timing", UDA1380_AGC, 8, 7, 0), /* TODO: enum, see table 62 */338 SOC_SINGLE("AGC Target level", UDA1380_AGC, 2, 3, 1), /* AGC_LEVEL */339 /* -5.5, -8, -11.5, -14 dBFS */340 SOC_SINGLE("AGC Switch", UDA1380_AGC, 0, 1, 0),341};342 343/* Input mux */344static const struct snd_kcontrol_new uda1380_input_mux_control =345 SOC_DAPM_ENUM("Route", uda1380_input_sel_enum);346 347/* Output mux */348static const struct snd_kcontrol_new uda1380_output_mux_control =349 SOC_DAPM_ENUM("Route", uda1380_output_sel_enum);350 351/* Capture mux */352static const struct snd_kcontrol_new uda1380_capture_mux_control =353 SOC_DAPM_ENUM("Route", uda1380_capture_sel_enum);354 355 356static const struct snd_soc_dapm_widget uda1380_dapm_widgets[] = {357 SND_SOC_DAPM_MUX("Input Mux", SND_SOC_NOPM, 0, 0,358 &uda1380_input_mux_control),359 SND_SOC_DAPM_MUX("Output Mux", SND_SOC_NOPM, 0, 0,360 &uda1380_output_mux_control),361 SND_SOC_DAPM_MUX("Capture Mux", SND_SOC_NOPM, 0, 0,362 &uda1380_capture_mux_control),363 SND_SOC_DAPM_PGA("Left PGA", UDA1380_PM, 3, 0, NULL, 0),364 SND_SOC_DAPM_PGA("Right PGA", UDA1380_PM, 1, 0, NULL, 0),365 SND_SOC_DAPM_PGA("Mic LNA", UDA1380_PM, 4, 0, NULL, 0),366 SND_SOC_DAPM_ADC("Left ADC", "Left Capture", UDA1380_PM, 2, 0),367 SND_SOC_DAPM_ADC("Right ADC", "Right Capture", UDA1380_PM, 0, 0),368 SND_SOC_DAPM_INPUT("VINM"),369 SND_SOC_DAPM_INPUT("VINL"),370 SND_SOC_DAPM_INPUT("VINR"),371 SND_SOC_DAPM_MIXER("Analog Mixer", UDA1380_PM, 6, 0, NULL, 0),372 SND_SOC_DAPM_OUTPUT("VOUTLHP"),373 SND_SOC_DAPM_OUTPUT("VOUTRHP"),374 SND_SOC_DAPM_OUTPUT("VOUTL"),375 SND_SOC_DAPM_OUTPUT("VOUTR"),376 SND_SOC_DAPM_DAC("DAC", "Playback", UDA1380_PM, 10, 0),377 SND_SOC_DAPM_PGA("HeadPhone Driver", UDA1380_PM, 13, 0, NULL, 0),378};379 380static const struct snd_soc_dapm_route uda1380_dapm_routes[] = {381 382 /* output mux */383 {"HeadPhone Driver", NULL, "Output Mux"},384 {"VOUTR", NULL, "Output Mux"},385 {"VOUTL", NULL, "Output Mux"},386 387 {"Analog Mixer", NULL, "VINR"},388 {"Analog Mixer", NULL, "VINL"},389 {"Analog Mixer", NULL, "DAC"},390 391 {"Output Mux", "DAC", "DAC"},392 {"Output Mux", "Analog Mixer", "Analog Mixer"},393 394 /* {"DAC", "Digital Mixer", "I2S" } */395 396 /* headphone driver */397 {"VOUTLHP", NULL, "HeadPhone Driver"},398 {"VOUTRHP", NULL, "HeadPhone Driver"},399 400 /* input mux */401 {"Left ADC", NULL, "Input Mux"},402 {"Input Mux", "Mic", "Mic LNA"},403 {"Input Mux", "Mic + Line R", "Mic LNA"},404 {"Input Mux", "Line L", "Left PGA"},405 {"Input Mux", "Line", "Left PGA"},406 407 /* right input */408 {"Right ADC", "Mic + Line R", "Right PGA"},409 {"Right ADC", "Line", "Right PGA"},410 411 /* inputs */412 {"Mic LNA", NULL, "VINM"},413 {"Left PGA", NULL, "VINL"},414 {"Right PGA", NULL, "VINR"},415};416 417static int uda1380_set_dai_fmt_both(struct snd_soc_dai *codec_dai,418 unsigned int fmt)419{420 struct snd_soc_component *component = codec_dai->component;421 int iface;422 423 /* set up DAI based upon fmt */424 iface = uda1380_read_reg_cache(component, UDA1380_IFACE);425 iface &= ~(R01_SFORI_MASK | R01_SIM | R01_SFORO_MASK);426 427 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {428 case SND_SOC_DAIFMT_I2S:429 iface |= R01_SFORI_I2S | R01_SFORO_I2S;430 break;431 case SND_SOC_DAIFMT_LSB:432 iface |= R01_SFORI_LSB16 | R01_SFORO_LSB16;433 break;434 case SND_SOC_DAIFMT_MSB:435 iface |= R01_SFORI_MSB | R01_SFORO_MSB;436 }437 438 /* DATAI is consumer only */439 if ((fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) != SND_SOC_DAIFMT_CBC_CFC)440 return -EINVAL;441 442 uda1380_write_reg_cache(component, UDA1380_IFACE, iface);443 444 return 0;445}446 447static int uda1380_set_dai_fmt_playback(struct snd_soc_dai *codec_dai,448 unsigned int fmt)449{450 struct snd_soc_component *component = codec_dai->component;451 int iface;452 453 /* set up DAI based upon fmt */454 iface = uda1380_read_reg_cache(component, UDA1380_IFACE);455 iface &= ~R01_SFORI_MASK;456 457 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {458 case SND_SOC_DAIFMT_I2S:459 iface |= R01_SFORI_I2S;460 break;461 case SND_SOC_DAIFMT_LSB:462 iface |= R01_SFORI_LSB16;463 break;464 case SND_SOC_DAIFMT_MSB:465 iface |= R01_SFORI_MSB;466 }467 468 /* DATAI is consumer only */469 if ((fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) != SND_SOC_DAIFMT_CBC_CFC)470 return -EINVAL;471 472 uda1380_write(component, UDA1380_IFACE, iface);473 474 return 0;475}476 477static int uda1380_set_dai_fmt_capture(struct snd_soc_dai *codec_dai,478 unsigned int fmt)479{480 struct snd_soc_component *component = codec_dai->component;481 int iface;482 483 /* set up DAI based upon fmt */484 iface = uda1380_read_reg_cache(component, UDA1380_IFACE);485 iface &= ~(R01_SIM | R01_SFORO_MASK);486 487 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {488 case SND_SOC_DAIFMT_I2S:489 iface |= R01_SFORO_I2S;490 break;491 case SND_SOC_DAIFMT_LSB:492 iface |= R01_SFORO_LSB16;493 break;494 case SND_SOC_DAIFMT_MSB:495 iface |= R01_SFORO_MSB;496 }497 498 if ((fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) == SND_SOC_DAIFMT_CBP_CFP)499 iface |= R01_SIM;500 501 uda1380_write(component, UDA1380_IFACE, iface);502 503 return 0;504}505 506static int uda1380_trigger(struct snd_pcm_substream *substream, int cmd,507 struct snd_soc_dai *dai)508{509 struct snd_soc_component *component = dai->component;510 struct uda1380_priv *uda1380 = snd_soc_component_get_drvdata(component);511 int mixer = uda1380_read_reg_cache(component, UDA1380_MIXER);512 513 switch (cmd) {514 case SNDRV_PCM_TRIGGER_START:515 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:516 uda1380_write_reg_cache(component, UDA1380_MIXER,517 mixer & ~R14_SILENCE);518 schedule_work(&uda1380->work);519 break;520 case SNDRV_PCM_TRIGGER_STOP:521 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:522 uda1380_write_reg_cache(component, UDA1380_MIXER,523 mixer | R14_SILENCE);524 schedule_work(&uda1380->work);525 break;526 }527 return 0;528}529 530static int uda1380_pcm_hw_params(struct snd_pcm_substream *substream,531 struct snd_pcm_hw_params *params,532 struct snd_soc_dai *dai)533{534 struct snd_soc_component *component = dai->component;535 u16 clk = uda1380_read_reg_cache(component, UDA1380_CLK);536 537 /* set WSPLL power and divider if running from this clock */538 if (clk & R00_DAC_CLK) {539 int rate = params_rate(params);540 u16 pm = uda1380_read_reg_cache(component, UDA1380_PM);541 clk &= ~0x3; /* clear SEL_LOOP_DIV */542 switch (rate) {543 case 6250 ... 12500:544 clk |= 0x0;545 break;546 case 12501 ... 25000:547 clk |= 0x1;548 break;549 case 25001 ... 50000:550 clk |= 0x2;551 break;552 case 50001 ... 100000:553 clk |= 0x3;554 break;555 }556 uda1380_write(component, UDA1380_PM, R02_PON_PLL | pm);557 }558 559 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)560 clk |= R00_EN_DAC | R00_EN_INT;561 else562 clk |= R00_EN_ADC | R00_EN_DEC;563 564 uda1380_write(component, UDA1380_CLK, clk);565 return 0;566}567 568static void uda1380_pcm_shutdown(struct snd_pcm_substream *substream,569 struct snd_soc_dai *dai)570{571 struct snd_soc_component *component = dai->component;572 u16 clk = uda1380_read_reg_cache(component, UDA1380_CLK);573 574 /* shut down WSPLL power if running from this clock */575 if (clk & R00_DAC_CLK) {576 u16 pm = uda1380_read_reg_cache(component, UDA1380_PM);577 uda1380_write(component, UDA1380_PM, ~R02_PON_PLL & pm);578 }579 580 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)581 clk &= ~(R00_EN_DAC | R00_EN_INT);582 else583 clk &= ~(R00_EN_ADC | R00_EN_DEC);584 585 uda1380_write(component, UDA1380_CLK, clk);586}587 588static int uda1380_set_bias_level(struct snd_soc_component *component,589 enum snd_soc_bias_level level)590{591 int pm = uda1380_read_reg_cache(component, UDA1380_PM);592 int reg;593 struct uda1380_platform_data *pdata = component->dev->platform_data;594 595 switch (level) {596 case SND_SOC_BIAS_ON:597 case SND_SOC_BIAS_PREPARE:598 /* ADC, DAC on */599 uda1380_write(component, UDA1380_PM, R02_PON_BIAS | pm);600 break;601 case SND_SOC_BIAS_STANDBY:602 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {603 if (gpio_is_valid(pdata->gpio_power)) {604 gpio_set_value(pdata->gpio_power, 1);605 mdelay(1);606 uda1380_reset(component);607 }608 609 uda1380_sync_cache(component);610 }611 uda1380_write(component, UDA1380_PM, 0x0);612 break;613 case SND_SOC_BIAS_OFF:614 if (!gpio_is_valid(pdata->gpio_power))615 break;616 617 gpio_set_value(pdata->gpio_power, 0);618 619 /* Mark mixer regs cache dirty to sync them with620 * codec regs on power on.621 */622 for (reg = UDA1380_MVOL; reg < UDA1380_CACHEREGNUM; reg++)623 set_bit(reg - 0x10, &uda1380_cache_dirty);624 }625 return 0;626}627 628#define UDA1380_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |\629 SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 |\630 SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000)631 632static const struct snd_soc_dai_ops uda1380_dai_ops = {633 .hw_params = uda1380_pcm_hw_params,634 .shutdown = uda1380_pcm_shutdown,635 .trigger = uda1380_trigger,636 .set_fmt = uda1380_set_dai_fmt_both,637};638 639static const struct snd_soc_dai_ops uda1380_dai_ops_playback = {640 .hw_params = uda1380_pcm_hw_params,641 .shutdown = uda1380_pcm_shutdown,642 .trigger = uda1380_trigger,643 .set_fmt = uda1380_set_dai_fmt_playback,644};645 646static const struct snd_soc_dai_ops uda1380_dai_ops_capture = {647 .hw_params = uda1380_pcm_hw_params,648 .shutdown = uda1380_pcm_shutdown,649 .trigger = uda1380_trigger,650 .set_fmt = uda1380_set_dai_fmt_capture,651};652 653static struct snd_soc_dai_driver uda1380_dai[] = {654{655 .name = "uda1380-hifi",656 .playback = {657 .stream_name = "Playback",658 .channels_min = 1,659 .channels_max = 2,660 .rates = UDA1380_RATES,661 .formats = SNDRV_PCM_FMTBIT_S16_LE,},662 .capture = {663 .stream_name = "Capture",664 .channels_min = 1,665 .channels_max = 2,666 .rates = UDA1380_RATES,667 .formats = SNDRV_PCM_FMTBIT_S16_LE,},668 .ops = &uda1380_dai_ops,669},670{ /* playback only - dual interface */671 .name = "uda1380-hifi-playback",672 .playback = {673 .stream_name = "Playback",674 .channels_min = 1,675 .channels_max = 2,676 .rates = UDA1380_RATES,677 .formats = SNDRV_PCM_FMTBIT_S16_LE,678 },679 .ops = &uda1380_dai_ops_playback,680},681{ /* capture only - dual interface*/682 .name = "uda1380-hifi-capture",683 .capture = {684 .stream_name = "Capture",685 .channels_min = 1,686 .channels_max = 2,687 .rates = UDA1380_RATES,688 .formats = SNDRV_PCM_FMTBIT_S16_LE,689 },690 .ops = &uda1380_dai_ops_capture,691},692};693 694static int uda1380_probe(struct snd_soc_component *component)695{696 struct uda1380_platform_data *pdata =component->dev->platform_data;697 struct uda1380_priv *uda1380 = snd_soc_component_get_drvdata(component);698 int ret;699 700 uda1380->component = component;701 702 if (!gpio_is_valid(pdata->gpio_power)) {703 ret = uda1380_reset(component);704 if (ret)705 return ret;706 }707 708 INIT_WORK(&uda1380->work, uda1380_flush_work);709 710 /* set clock input */711 switch (pdata->dac_clk) {712 case UDA1380_DAC_CLK_SYSCLK:713 uda1380_write_reg_cache(component, UDA1380_CLK, 0);714 break;715 case UDA1380_DAC_CLK_WSPLL:716 uda1380_write_reg_cache(component, UDA1380_CLK,717 R00_DAC_CLK);718 break;719 }720 721 return 0;722}723 724static const struct snd_soc_component_driver soc_component_dev_uda1380 = {725 .probe = uda1380_probe,726 .read = uda1380_read_reg_cache,727 .write = uda1380_write,728 .set_bias_level = uda1380_set_bias_level,729 .controls = uda1380_snd_controls,730 .num_controls = ARRAY_SIZE(uda1380_snd_controls),731 .dapm_widgets = uda1380_dapm_widgets,732 .num_dapm_widgets = ARRAY_SIZE(uda1380_dapm_widgets),733 .dapm_routes = uda1380_dapm_routes,734 .num_dapm_routes = ARRAY_SIZE(uda1380_dapm_routes),735 .suspend_bias_off = 1,736 .idle_bias_on = 1,737 .use_pmdown_time = 1,738 .endianness = 1,739};740 741static int uda1380_i2c_probe(struct i2c_client *i2c)742{743 struct uda1380_platform_data *pdata = i2c->dev.platform_data;744 struct uda1380_priv *uda1380;745 int ret;746 747 if (!pdata)748 return -EINVAL;749 750 uda1380 = devm_kzalloc(&i2c->dev, sizeof(struct uda1380_priv),751 GFP_KERNEL);752 if (uda1380 == NULL)753 return -ENOMEM;754 755 if (gpio_is_valid(pdata->gpio_reset)) {756 ret = devm_gpio_request_one(&i2c->dev, pdata->gpio_reset,757 GPIOF_OUT_INIT_LOW, "uda1380 reset");758 if (ret)759 return ret;760 }761 762 if (gpio_is_valid(pdata->gpio_power)) {763 ret = devm_gpio_request_one(&i2c->dev, pdata->gpio_power,764 GPIOF_OUT_INIT_LOW, "uda1380 power");765 if (ret)766 return ret;767 }768 769 uda1380->reg_cache = devm_kmemdup(&i2c->dev,770 uda1380_reg,771 ARRAY_SIZE(uda1380_reg) * sizeof(u16),772 GFP_KERNEL);773 if (!uda1380->reg_cache)774 return -ENOMEM;775 776 i2c_set_clientdata(i2c, uda1380);777 uda1380->i2c = i2c;778 779 ret = devm_snd_soc_register_component(&i2c->dev,780 &soc_component_dev_uda1380, uda1380_dai, ARRAY_SIZE(uda1380_dai));781 return ret;782}783 784static const struct i2c_device_id uda1380_i2c_id[] = {785 { "uda1380" },786 { }787};788MODULE_DEVICE_TABLE(i2c, uda1380_i2c_id);789 790static const struct of_device_id uda1380_of_match[] = {791 { .compatible = "nxp,uda1380", },792 { }793};794MODULE_DEVICE_TABLE(of, uda1380_of_match);795 796static struct i2c_driver uda1380_i2c_driver = {797 .driver = {798 .name = "uda1380-codec",799 .of_match_table = uda1380_of_match,800 },801 .probe = uda1380_i2c_probe,802 .id_table = uda1380_i2c_id,803};804 805module_i2c_driver(uda1380_i2c_driver);806 807MODULE_AUTHOR("Giorgio Padrin");808MODULE_DESCRIPTION("Audio support for codec Philips UDA1380");809MODULE_LICENSE("GPL");810