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1/* SPDX-License-Identifier: GPL-2.0-only2 * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.3 */4 5#ifndef _WCD937X_REGISTERS_H6#define _WCD937X_REGISTERS_H7 8#include <linux/soundwire/sdw.h>9#include <linux/soundwire/sdw_type.h>10 11#define WCD937X_BASE_ADDRESS 0x300012#define WCD937X_ANA_BIAS 0x300113#define WCD937X_ANA_RX_SUPPLIES 0x300814#define WCD937X_ANA_HPH 0x300915#define WCD937X_ANA_EAR 0x300A16#define WCD937X_ANA_EAR_COMPANDER_CTL 0x300B17#define WCD937X_EAR_GAIN_MASK GENMASK(6, 2)18#define WCD937X_ANA_TX_CH1 0x300E19#define WCD937X_ANA_TX_CH2 0x300F20#define WCD937X_ANA_TX_CH3 0x301021#define WCD937X_ANA_TX_CH3_HPF 0x301122#define WCD937X_ANA_MICB1_MICB2_DSP_EN_LOGIC 0x301223#define WCD937X_ANA_MICB3_DSP_EN_LOGIC 0x301324#define WCD937X_ANA_MBHC_MECH 0x301425#define WCD937X_MBHC_L_DET_EN_MASK BIT(7)26#define WCD937X_MBHC_L_DET_EN BIT(7)27#define WCD937X_MBHC_GND_DET_EN_MASK BIT(6)28#define WCD937X_MBHC_MECH_DETECT_TYPE_MASK BIT(5)29#define WCD937X_MBHC_MECH_DETECT_TYPE_INS 130#define WCD937X_MBHC_HPHL_PLUG_TYPE_MASK BIT(4)31#define WCD937X_MBHC_HPHL_PLUG_TYPE_NO 132#define WCD937X_MBHC_GND_PLUG_TYPE_MASK BIT(3)33#define WCD937X_MBHC_GND_PLUG_TYPE_NO 134#define WCD937X_MBHC_HSL_PULLUP_COMP_EN BIT(2)35#define WCD937X_MBHC_HSG_PULLUP_COMP_EN BIT(1)36#define WCD937X_MBHC_HPHL_100K_TO_GND_EN BIT(0)37#define WCD937X_ANA_MBHC_ELECT 0x301538#define WCD937X_ANA_MBHC_BD_ISRC_CTL_MASK GENMASK(6, 4)39#define WCD937X_ANA_MBHC_BD_ISRC_100UA GENMASK(5, 4)40#define WCD937X_ANA_MBHC_BD_ISRC_OFF 041#define WCD937X_ANA_MBHC_BIAS_EN_MASK BIT(0)42#define WCD937X_ANA_MBHC_BIAS_EN BIT(0)43#define WCD937X_ANA_MBHC_ZDET 0x301644#define WCD937X_ANA_MBHC_RESULT_1 0x301745#define WCD937X_ANA_MBHC_RESULT_2 0x301846#define WCD937X_ANA_MBHC_RESULT_3 0x301947#define WCD937X_MBHC_BTN_RESULT_MASK GENMASK(2, 0)48#define WCD937X_ANA_MBHC_BTN0 0x301A49#define WCD937X_MBHC_BTN_VTH_MASK GENMASK(7, 2)50#define WCD937X_ANA_MBHC_BTN1 0x301B51#define WCD937X_ANA_MBHC_BTN2 0x301C52#define WCD937X_ANA_MBHC_BTN3 0x301D53#define WCD937X_ANA_MBHC_BTN4 0x301E54#define WCD937X_ANA_MBHC_BTN5 0x301F55#define WCD937X_VTH_MASK GENMASK(7, 2)56#define WCD937X_ANA_MBHC_BTN6 0x302057#define WCD937X_ANA_MBHC_BTN7 0x302158#define WCD937X_ANA_MICB1 0x302259#define WCD937X_MICB_VOUT_MASK GENMASK(5, 0)60#define WCD937X_MICB_EN_MASK GENMASK(7, 6)61#define WCD937X_MICB_DISABLE 062#define WCD937X_MICB_ENABLE 163#define WCD937X_MICB_PULL_UP 264#define WCD937X_MICB_PULL_DOWN 365#define WCD937X_ANA_MICB2 0x302366#define WCD937X_ANA_MICB2_ENABLE BIT(6)67#define WCD937X_ANA_MICB2_ENABLE_MASK GENMASK(7, 6)68#define WCD937X_ANA_MICB2_VOUT_MASK GENMASK(5, 0)69#define WCD937X_ANA_MICB2_RAMP 0x302470#define WCD937X_RAMP_EN_MASK BIT(7)71#define WCD937X_RAMP_SHIFT_CTRL_MASK GENMASK(4, 2)72#define WCD937X_ANA_MICB3 0x302573#define WCD937X_ANA_MICB_EN GENMASK(7, 6)74#define WCD937X_MICB_DISABLE 075#define WCD937X_MICB_ENABLE 176#define WCD937X_MICB_PULL_UP 277#define WCD937X_ANA_MICB_VOUT GENMASK(5, 0)78#define WCD937X_BIAS_CTL 0x302879#define WCD937X_BIAS_VBG_FINE_ADJ 0x302980#define WCD937X_LDOL_VDDCX_ADJUST 0x304081#define WCD937X_LDOL_DISABLE_LDOL 0x304182#define WCD937X_MBHC_CTL_CLK 0x305683#define WCD937X_MBHC_CTL_ANA 0x305784#define WCD937X_MBHC_CTL_SPARE_1 0x305885#define WCD937X_MBHC_CTL_SPARE_2 0x305986#define WCD937X_MBHC_CTL_BCS 0x305A87#define WCD937X_MBHC_MOISTURE_DET_FSM_STATUS 0x305B88#define WCD937X_MBHC_TEST_CTL 0x305C89#define WCD937X_LDOH_MODE 0x306790#define WCD937X_LDOH_BIAS 0x306891#define WCD937X_LDOH_STB_LOADS 0x306992#define WCD937X_LDOH_SLOWRAMP 0x306A93#define WCD937X_MICB1_TEST_CTL_1 0x306B94#define WCD937X_MICB1_TEST_CTL_2 0x306C95#define WCD937X_MICB1_TEST_CTL_3 0x306D96#define WCD937X_MICB2_TEST_CTL_1 0x306E97#define WCD937X_MICB2_TEST_CTL_2 0x306F98#define WCD937X_MICB2_TEST_CTL_3 0x307099#define WCD937X_MICB3_TEST_CTL_1 0x3071100#define WCD937X_MICB3_TEST_CTL_2 0x3072101#define WCD937X_MICB3_TEST_CTL_3 0x3073102#define WCD937X_TX_COM_ADC_VCM 0x3077103#define WCD937X_TX_COM_BIAS_ATEST 0x3078104#define WCD937X_TX_COM_ADC_INT1_IB 0x3079105#define WCD937X_TX_COM_ADC_INT2_IB 0x307A106#define WCD937X_TX_COM_TXFE_DIV_CTL 0x307B107#define WCD937X_TX_COM_TXFE_DIV_START 0x307C108#define WCD937X_TX_COM_TXFE_DIV_STOP_9P6M 0x307D109#define WCD937X_TX_COM_TXFE_DIV_STOP_12P288M 0x307E110#define WCD937X_TX_1_2_TEST_EN 0x307F111#define WCD937X_TX_1_2_ADC_IB 0x3080112#define WCD937X_TX_1_2_ATEST_REFCTL 0x3081113#define WCD937X_TX_1_2_TEST_CTL 0x3082114#define WCD937X_TX_1_2_TEST_BLK_EN 0x3083115#define WCD937X_TX_1_2_TXFE_CLKDIV 0x3084116#define WCD937X_TX_1_2_SAR2_ERR 0x3085117#define WCD937X_TX_1_2_SAR1_ERR 0x3086118#define WCD937X_TX_3_TEST_EN 0x3087119#define WCD937X_TX_3_ADC_IB 0x3088120#define WCD937X_TX_3_ATEST_REFCTL 0x3089121#define WCD937X_TX_3_TEST_CTL 0x308A122#define WCD937X_TX_3_TEST_BLK_EN 0x308B123#define WCD937X_TX_3_TXFE_CLKDIV 0x308C124#define WCD937X_TX_3_SPARE_MONO 0x308D125#define WCD937X_TX_3_SAR1_ERR 0x308E126#define WCD937X_CLASSH_MODE_1 0x3097127#define WCD937X_CLASSH_MODE_2 0x3098128#define WCD937X_CLASSH_MODE_3 0x3099129#define WCD937X_CLASSH_CTRL_VCL_1 0x309A130#define WCD937X_CLASSH_CTRL_VCL_2 0x309B131#define WCD937X_CLASSH_CTRL_CCL_1 0x309C132#define WCD937X_CLASSH_CTRL_CCL_2 0x309D133#define WCD937X_CLASSH_CTRL_CCL_3 0x309E134#define WCD937X_CLASSH_CTRL_CCL_4 0x309F135#define WCD937X_CLASSH_CTRL_CCL_5 0x30A0136#define WCD937X_CLASSH_BUCK_TMUX_A_D 0x30A1137#define WCD937X_CLASSH_BUCK_SW_DRV_CNTL 0x30A2138#define WCD937X_CLASSH_SPARE 0x30A3139#define WCD937X_FLYBACK_EN 0x30A4140#define WCD937X_FLYBACK_VNEG_CTRL_1 0x30A5141#define WCD937X_FLYBACK_VNEG_CTRL_2 0x30A6142#define WCD937X_FLYBACK_VNEG_CTRL_3 0x30A7143#define WCD937X_FLYBACK_VNEG_CTRL_4 0x30A8144#define WCD937X_FLYBACK_VNEG_CTRL_5 0x30A9145#define WCD937X_FLYBACK_VNEG_CTRL_6 0x30AA146#define WCD937X_FLYBACK_VNEG_CTRL_7 0x30AB147#define WCD937X_FLYBACK_VNEG_CTRL_8 0x30AC148#define WCD937X_FLYBACK_VNEG_CTRL_9 0x30AD149#define WCD937X_FLYBACK_VNEGDAC_CTRL_1 0x30AE150#define WCD937X_FLYBACK_VNEGDAC_CTRL_2 0x30AF151#define WCD937X_FLYBACK_VNEGDAC_CTRL_3 0x30B0152#define WCD937X_FLYBACK_CTRL_1 0x30B1153#define WCD937X_FLYBACK_TEST_CTL 0x30B2154#define WCD937X_RX_AUX_SW_CTL 0x30B3155#define WCD937X_RX_PA_AUX_IN_CONN 0x30B4156#define WCD937X_RX_TIMER_DIV 0x30B5157#define WCD937X_RX_OCP_CTL 0x30B6158#define WCD937X_RX_OCP_COUNT 0x30B7159#define WCD937X_RX_BIAS_EAR_DAC 0x30B8160#define WCD937X_RX_BIAS_EAR_AMP 0x30B9161#define WCD937X_RX_BIAS_HPH_LDO 0x30BA162#define WCD937X_RX_BIAS_HPH_PA 0x30BB163#define WCD937X_RX_BIAS_HPH_RDACBUFF_CNP2 0x30BC164#define WCD937X_RX_BIAS_HPH_RDAC_LDO 0x30BD165#define WCD937X_RX_BIAS_HPH_CNP1 0x30BE166#define WCD937X_RX_BIAS_HPH_LOWPOWER 0x30BF167#define WCD937X_RX_BIAS_AUX_DAC 0x30C0168#define WCD937X_RX_BIAS_AUX_AMP 0x30C1169#define WCD937X_RX_BIAS_VNEGDAC_BLEEDER 0x30C2170#define WCD937X_RX_BIAS_MISC 0x30C3171#define WCD937X_RX_BIAS_BUCK_RST 0x30C4172#define WCD937X_RX_BIAS_BUCK_VREF_ERRAMP 0x30C5173#define WCD937X_RX_BIAS_FLYB_ERRAMP 0x30C6174#define WCD937X_RX_BIAS_FLYB_BUFF 0x30C7175#define WCD937X_RX_BIAS_FLYB_MID_RST 0x30C8176#define WCD937X_HPH_L_STATUS 0x30C9177#define WCD937X_HPH_R_STATUS 0x30CA178#define WCD937X_HPH_CNP_EN 0x30CB179#define WCD937X_HPH_CNP_WG_CTL 0x30CC180#define WCD937X_HPH_CNP_WG_TIME 0x30CD181#define WCD937X_HPH_OCP_CTL 0x30CE182#define WCD937X_HPH_AUTO_CHOP 0x30CF183#define WCD937X_HPH_CHOP_CTL 0x30D0184#define WCD937X_HPH_PA_CTL1 0x30D1185#define WCD937X_HPH_PA_CTL2 0x30D2186#define WCD937X_HPHPA_GND_R_MASK BIT(6)187#define WCD937X_HPHPA_GND_L_MASK BIT(4)188#define WCD937X_HPH_L_EN 0x30D3189#define WCD937X_HPH_L_TEST 0x30D4190#define WCD937X_HPH_L_ATEST 0x30D5191#define WCD937X_HPH_R_EN 0x30D6192#define WCD937X_GAIN_SRC_SEL_MASK BIT(5)193#define WCD937X_GAIN_SRC_SEL_REGISTER 1194#define WCD937X_HPH_R_TEST 0x30D7195#define WCD937X_HPH_R_ATEST 0x30D8196#define WCD937X_HPH_RDAC_CLK_CTL1 0x30D9197#define WCD937X_HPHPA_GND_OVR_MASK BIT(1)198#define WCD937X_CHOP_CLK_EN_MASK BIT(7)199#define WCD937X_HPH_RDAC_CLK_CTL2 0x30DA200#define WCD937X_HPH_RDAC_LDO_CTL 0x30DB201#define WCD937X_HPH_RDAC_CHOP_CLK_LP_CTL 0x30DC202#define WCD937X_HPH_REFBUFF_UHQA_CTL 0x30DD203#define WCD937X_HPH_REFBUFF_LP_CTL 0x30DE204#define WCD937X_PREREF_FLIT_BYPASS_MASK BIT(0)205#define WCD937X_HPH_L_DAC_CTL 0x30DF206#define WCD937X_HPH_R_DAC_CTL 0x30E0207#define WCD937X_HPH_SURGE_HPHLR_SURGE_COMP_SEL 0x30E1208#define WCD937X_HPH_SURGE_HPHLR_SURGE_EN 0x30E2209#define WCD937X_HPH_SURGE_HPHLR_SURGE_MISC1 0x30E3210#define WCD937X_HPH_SURGE_HPHLR_SURGE_STATUS 0x30E4211#define WCD937X_EAR_EAR_EN_REG 0x30E9212#define WCD937X_EAR_EAR_PA_CON 0x30EA213#define WCD937X_EAR_EAR_SP_CON 0x30EB214#define WCD937X_EAR_EAR_DAC_CON 0x30EC215#define WCD937X_EAR_EAR_CNP_FSM_CON 0x30ED216#define WCD937X_EAR_TEST_CTL 0x30EE217#define WCD937X_EAR_STATUS_REG_1 0x30EF218#define WCD937X_EAR_STATUS_REG_2 0x30F0219#define WCD937X_ANA_NEW_PAGE_REGISTER 0x3100220#define WCD937X_HPH_NEW_ANA_HPH2 0x3101221#define WCD937X_HPH_NEW_ANA_HPH3 0x3102222#define WCD937X_SLEEP_CTL 0x3103223#define WCD937X_SLEEP_WATCHDOG_CTL 0x3104224#define WCD937X_MBHC_NEW_ELECT_REM_CLAMP_CTL 0x311F225#define WCD937X_MBHC_NEW_CTL_1 0x3120226#define WCD937X_MBHC_CTL_RCO_EN_MASK BIT(7)227#define WCD937X_MBHC_CTL_RCO_EN BIT(7)228#define WCD937X_MBHC_BTN_DBNC_MASK GENMASK(1, 0)229#define WCD937X_MBHC_BTN_DBNC_T_16_MS 0x2230#define WCD937X_MBHC_NEW_CTL_2 0x3121231#define WCD937X_MBHC_NEW_PLUG_DETECT_CTL 0x3122232#define WCD937X_MBHC_NEW_ZDET_ANA_CTL 0x3123233#define WCD937X_M_RTH_CTL_MASK GENMASK(3, 2)234#define WCD937X_MBHC_HS_VREF_CTL_MASK GENMASK(1, 0)235#define WCD937X_MBHC_HS_VREF_1P5_V 0x1236#define WCD937X_MBHC_DBNC_TIMER_INSREM_DBNC_T_96_MS 0x6237#define WCD937X_ZDET_RANGE_CTL_MASK GENMASK(3, 0)238#define WCD937X_ZDET_MAXV_CTL_MASK GENMASK(6, 4)239#define WCD937X_MBHC_NEW_ZDET_RAMP_CTL 0x3124240#define WCD937X_MBHC_NEW_FSM_STATUS 0x3125241#define WCD937X_MBHC_NEW_ADC_RESULT 0x3126242#define WCD937X_TX_NEW_TX_CH2_SEL 0x3127243#define WCD937X_AUX_AUXPA 0x3128244#define WCD937X_AUXPA_CLK_EN_MASK BIT(4)245#define WCD937X_AUXPA_CLK_EN_MASK BIT(4)246#define WCD937X_LDORXTX_MODE 0x3129247#define WCD937X_LDORXTX_CONFIG 0x312A248#define WCD937X_DIE_CRACK_DIE_CRK_DET_EN 0x312C249#define WCD937X_DIE_CRACK_DIE_CRK_DET_OUT 0x312D250#define WCD937X_HPH_NEW_INT_RDAC_GAIN_CTL 0x3132251#define WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_L 0x3133252#define WCD937X_HPH_NEW_INT_RDAC_VREF_CTL 0x3134253#define WCD937X_HPH_NEW_INT_RDAC_OVERRIDE_CTL 0x3135254#define WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_R 0x3136255#define WCD937X_HPH_NEW_INT_PA_MISC1 0x3137256#define WCD937X_HPH_NEW_INT_PA_MISC2 0x3138257#define WCD937X_HPH_NEW_INT_PA_RDAC_MISC 0x3139258#define WCD937X_HPH_NEW_INT_HPH_TIMER1 0x313A259#define WCD937X_HPH_NEW_INT_HPH_TIMER2 0x313B260#define WCD937X_HPH_NEW_INT_HPH_TIMER3 0x313C261#define WCD937X_HPH_NEW_INT_HPH_TIMER4 0x313D262#define WCD937X_HPH_NEW_INT_PA_RDAC_MISC2 0x313E263#define WCD937X_HPH_NEW_INT_PA_RDAC_MISC3 0x313F264#define WCD937X_RX_NEW_INT_HPH_RDAC_BIAS_LOHIFI 0x3145265#define WCD937X_RX_NEW_INT_HPH_RDAC_BIAS_ULP 0x3146266#define WCD937X_RX_NEW_INT_HPH_RDAC_LDO_LP 0x3147267#define WCD937X_MBHC_NEW_INT_MOISTURE_DET_DC_CTRL 0x31AF268#define WCD937X_MBHC_NEW_INT_MOISTURE_DET_POLLING_CTRL 0x31B0269#define WCD937X_MOISTURE_EN_POLLING_MASK BIT(2)270#define WCD937X_HSDET_PULLUP_C_MASK GENMASK(4, 0)271#define WCD937X_MBHC_NEW_INT_MECH_DET_CURRENT 0x31B1272#define WCD937X_MBHC_NEW_INT_SPARE_2 0x31B2273#define WCD937X_EAR_INT_NEW_EAR_CHOPPER_CON 0x31B7274#define WCD937X_EAR_INT_NEW_CNP_VCM_CON1 0x31B8275#define WCD937X_EAR_INT_NEW_CNP_VCM_CON2 0x31B9276#define WCD937X_EAR_INT_NEW_EAR_DYNAMIC_BIAS 0x31BA277#define WCD937X_AUX_INT_EN_REG 0x31BD278#define WCD937X_AUX_INT_PA_CTRL 0x31BE279#define WCD937X_AUX_INT_SP_CTRL 0x31BF280#define WCD937X_AUX_INT_DAC_CTRL 0x31C0281#define WCD937X_AUX_INT_CLK_CTRL 0x31C1282#define WCD937X_AUX_INT_TEST_CTRL 0x31C2283#define WCD937X_AUX_INT_STATUS_REG 0x31C3284#define WCD937X_AUX_INT_MISC 0x31C4285#define WCD937X_LDORXTX_INT_BIAS 0x31C5286#define WCD937X_LDORXTX_INT_STB_LOADS_DTEST 0x31C6287#define WCD937X_LDORXTX_INT_TEST0 0x31C7288#define WCD937X_LDORXTX_INT_STARTUP_TIMER 0x31C8289#define WCD937X_LDORXTX_INT_TEST1 0x31C9290#define WCD937X_LDORXTX_INT_STATUS 0x31CA291#define WCD937X_SLEEP_INT_WATCHDOG_CTL_1 0x31D0292#define WCD937X_SLEEP_INT_WATCHDOG_CTL_2 0x31D1293#define WCD937X_DIE_CRACK_INT_DIE_CRK_DET_INT1 0x31D3294#define WCD937X_DIE_CRACK_INT_DIE_CRK_DET_INT2 0x31D4295#define WCD937X_DIGITAL_PAGE_REGISTER 0x3400296#define WCD937X_DIGITAL_CHIP_ID0 0x3401297#define WCD937X_DIGITAL_CHIP_ID1 0x3402298#define WCD937X_DIGITAL_CHIP_ID2 0x3403299#define WCD937X_DIGITAL_CHIP_ID3 0x3404300#define WCD937X_DIGITAL_CDC_RST_CTL 0x3406301#define WCD937X_DIGITAL_TOP_CLK_CFG 0x3407302#define WCD937X_DIGITAL_CDC_ANA_CLK_CTL 0x3408303#define WCD937X_DIGITAL_CDC_DIG_CLK_CTL 0x3409304#define WCD937X_DIGITAL_SWR_RST_EN 0x340A305#define WCD937X_DIGITAL_CDC_PATH_MODE 0x340B306#define WCD937X_DIGITAL_CDC_RX_RST 0x340C307#define WCD937X_DIGITAL_CDC_RX0_CTL 0x340D308#define WCD937X_DIGITAL_CDC_RX1_CTL 0x340E309#define WCD937X_DIGITAL_CDC_RX2_CTL 0x340F310#define WCD937X_DIGITAL_DEM_BYPASS_DATA0 0x3410311#define WCD937X_DIGITAL_DEM_BYPASS_DATA1 0x3411312#define WCD937X_DIGITAL_DEM_BYPASS_DATA2 0x3412313#define WCD937X_DIGITAL_DEM_BYPASS_DATA3 0x3413314#define WCD937X_DIGITAL_CDC_COMP_CTL_0 0x3414315#define WCD937X_DIGITAL_CDC_RX_DELAY_CTL 0x3417316#define WCD937X_DIGITAL_CDC_HPH_DSM_A1_0 0x3418317#define WCD937X_DIGITAL_CDC_HPH_DSM_A1_1 0x3419318#define WCD937X_DIGITAL_CDC_HPH_DSM_A2_0 0x341A319#define WCD937X_DIGITAL_CDC_HPH_DSM_A2_1 0x341B320#define WCD937X_DIGITAL_CDC_HPH_DSM_A3_0 0x341C321#define WCD937X_DIGITAL_CDC_HPH_DSM_A3_1 0x341D322#define WCD937X_DIGITAL_CDC_HPH_DSM_A4_0 0x341E323#define WCD937X_DIGITAL_CDC_HPH_DSM_A4_1 0x341F324#define WCD937X_DIGITAL_CDC_HPH_DSM_A5_0 0x3420325#define WCD937X_DIGITAL_CDC_HPH_DSM_A5_1 0x3421326#define WCD937X_DIGITAL_CDC_HPH_DSM_A6_0 0x3422327#define WCD937X_DIGITAL_CDC_HPH_DSM_A7_0 0x3423328#define WCD937X_DIGITAL_CDC_HPH_DSM_C_0 0x3424329#define WCD937X_DIGITAL_CDC_HPH_DSM_C_1 0x3425330#define WCD937X_DIGITAL_CDC_HPH_DSM_C_2 0x3426331#define WCD937X_DIGITAL_CDC_HPH_DSM_C_3 0x3427332#define WCD937X_DIGITAL_CDC_HPH_DSM_R1 0x3428333#define WCD937X_DIGITAL_CDC_HPH_DSM_R2 0x3429334#define WCD937X_DIGITAL_CDC_HPH_DSM_R3 0x342A335#define WCD937X_DIGITAL_CDC_HPH_DSM_R4 0x342B336#define WCD937X_DIGITAL_CDC_HPH_DSM_R5 0x342C337#define WCD937X_DIGITAL_CDC_HPH_DSM_R6 0x342D338#define WCD937X_DIGITAL_CDC_HPH_DSM_R7 0x342E339#define WCD937X_DIGITAL_CDC_AUX_DSM_A1_0 0x342F340#define WCD937X_DIGITAL_CDC_AUX_DSM_A1_1 0x3430341#define WCD937X_DIGITAL_CDC_AUX_DSM_A2_0 0x3431342#define WCD937X_DIGITAL_CDC_AUX_DSM_A2_1 0x3432343#define WCD937X_DIGITAL_CDC_AUX_DSM_A3_0 0x3433344#define WCD937X_DIGITAL_CDC_AUX_DSM_A3_1 0x3434345#define WCD937X_DIGITAL_CDC_AUX_DSM_A4_0 0x3435346#define WCD937X_DIGITAL_CDC_AUX_DSM_A4_1 0x3436347#define WCD937X_DIGITAL_CDC_AUX_DSM_A5_0 0x3437348#define WCD937X_DIGITAL_CDC_AUX_DSM_A5_1 0x3438349#define WCD937X_DIGITAL_CDC_AUX_DSM_A6_0 0x3439350#define WCD937X_DIGITAL_CDC_AUX_DSM_A7_0 0x343A351#define WCD937X_DIGITAL_CDC_AUX_DSM_C_0 0x343B352#define WCD937X_DIGITAL_CDC_AUX_DSM_C_1 0x343C353#define WCD937X_DIGITAL_CDC_AUX_DSM_C_2 0x343D354#define WCD937X_DIGITAL_CDC_AUX_DSM_C_3 0x343E355#define WCD937X_DIGITAL_CDC_AUX_DSM_R1 0x343F356#define WCD937X_DIGITAL_CDC_AUX_DSM_R2 0x3440357#define WCD937X_DIGITAL_CDC_AUX_DSM_R3 0x3441358#define WCD937X_DIGITAL_CDC_AUX_DSM_R4 0x3442359#define WCD937X_DIGITAL_CDC_AUX_DSM_R5 0x3443360#define WCD937X_DIGITAL_CDC_AUX_DSM_R6 0x3444361#define WCD937X_DIGITAL_CDC_AUX_DSM_R7 0x3445362#define WCD937X_DIGITAL_CDC_HPH_GAIN_RX_0 0x3446363#define WCD937X_DIGITAL_CDC_HPH_GAIN_RX_1 0x3447364#define WCD937X_DIGITAL_CDC_HPH_GAIN_DSD_0 0x3448365#define WCD937X_DIGITAL_CDC_HPH_GAIN_DSD_1 0x3449366#define WCD937X_DIGITAL_CDC_HPH_GAIN_DSD_2 0x344A367#define WCD937X_DIGITAL_CDC_AUX_GAIN_DSD_0 0x344B368#define WCD937X_DIGITAL_CDC_AUX_GAIN_DSD_1 0x344C369#define WCD937X_DIGITAL_CDC_AUX_GAIN_DSD_2 0x344D370#define WCD937X_DIGITAL_CDC_HPH_GAIN_CTL 0x344E371#define WCD937X_DIGITAL_CDC_AUX_GAIN_CTL 0x344F372#define WCD937X_DIGITAL_CDC_EAR_PATH_CTL 0x3450373#define WCD937X_DIGITAL_CDC_SWR_CLH 0x3451374#define WCD937X_DIGITAL_SWR_CLH_BYP 0x3452375#define WCD937X_DIGITAL_CDC_TX0_CTL 0x3453376#define WCD937X_DIGITAL_CDC_TX1_CTL 0x3454377#define WCD937X_DIGITAL_CDC_TX2_CTL 0x3455378#define WCD937X_DIGITAL_CDC_TX_RST 0x3456379#define WCD937X_DIGITAL_CDC_REQ_CTL 0x3457380#define WCD937X_DIGITAL_CDC_AMIC_CTL 0x345A381#define WCD937X_DIGITAL_CDC_DMIC_CTL 0x345B382#define WCD937X_DIGITAL_CDC_DMIC1_CTL 0x345C383#define WCD937X_DIGITAL_CDC_DMIC2_CTL 0x345D384#define WCD937X_DIGITAL_CDC_DMIC3_CTL 0x345E385#define WCD937X_DIGITAL_EFUSE_CTL 0x345F386#define WCD937X_DIGITAL_EFUSE_PRG_CTL 0x3460387#define WCD937X_DIGITAL_EFUSE_TEST_CTL_0 0x3461388#define WCD937X_DIGITAL_EFUSE_TEST_CTL_1 0x3462389#define WCD937X_DIGITAL_EFUSE_T_DATA_0 0x3463390#define WCD937X_DIGITAL_EFUSE_T_DATA_1 0x3464391#define WCD937X_DIGITAL_PDM_WD_CTL0 0x3465392#define WCD937X_DIGITAL_PDM_WD_CTL1 0x3466393#define WCD937X_DIGITAL_PDM_WD_CTL2 0x3467394#define WCD937X_DIGITAL_PDM_WD_CTL2_HOLD_OFF BIT(2)395#define WCD937X_DIGITAL_PDM_WD_CTL2_TIMEOUT_SEL BIT(1)396#define WCD937X_DIGITAL_PDM_WD_CTL2_EN BIT(0)397#define WCD937X_DIGITAL_PDM_WD_CTL2_MASK GENMASK(2, 0)398#define WCD937X_DIGITAL_INTR_MODE 0x346A399#define WCD937X_DIGITAL_INTR_MASK_0 0x346B400#define WCD937X_DIGITAL_INTR_MASK_1 0x346C401#define WCD937X_DIGITAL_INTR_MASK_2 0x346D402#define WCD937X_DIGITAL_INTR_STATUS_0 0x346E403#define WCD937X_DIGITAL_INTR_STATUS_1 0x346F404#define WCD937X_DIGITAL_INTR_STATUS_2 0x3470405#define WCD937X_DIGITAL_INTR_CLEAR_0 0x3471406#define WCD937X_DIGITAL_INTR_CLEAR_1 0x3472407#define WCD937X_DIGITAL_INTR_CLEAR_2 0x3473408#define WCD937X_DIGITAL_INTR_LEVEL_0 0x3474409#define WCD937X_DIGITAL_INTR_LEVEL_1 0x3475410#define WCD937X_DIGITAL_INTR_LEVEL_2 0x3476411#define WCD937X_DIGITAL_INTR_SET_0 0x3477412#define WCD937X_DIGITAL_INTR_SET_1 0x3478413#define WCD937X_DIGITAL_INTR_SET_2 0x3479414#define WCD937X_DIGITAL_INTR_TEST_0 0x347A415#define WCD937X_DIGITAL_INTR_TEST_1 0x347B416#define WCD937X_DIGITAL_INTR_TEST_2 0x347C417#define WCD937X_DIGITAL_CDC_CONN_RX0_CTL 0x347F418#define WCD937X_DIGITAL_CDC_CONN_RX1_CTL 0x3480419#define WCD937X_DIGITAL_CDC_CONN_RX2_CTL 0x3481420#define WCD937X_DIGITAL_CDC_CONN_TX_CTL 0x3482421#define WCD937X_DIGITAL_LOOP_BACK_MODE 0x3483422#define WCD937X_DIGITAL_SWR_DAC_TEST 0x3484423#define WCD937X_DIGITAL_SWR_HM_TEST_RX_0 0x3485424#define WCD937X_DIGITAL_SWR_HM_TEST_TX_0 0x3491425#define WCD937X_DIGITAL_SWR_HM_TEST_RX_1 0x3492426#define WCD937X_DIGITAL_SWR_HM_TEST_TX_1 0x3493427#define WCD937X_DIGITAL_SWR_HM_TEST 0x3494428#define WCD937X_DIGITAL_PAD_CTL_PDM_RX0 0x3495429#define WCD937X_DIGITAL_PAD_CTL_PDM_RX1 0x3496430#define WCD937X_DIGITAL_PAD_CTL_PDM_TX0 0x3497431#define WCD937X_DIGITAL_PAD_CTL_PDM_TX1 0x3498432#define WCD937X_DIGITAL_PAD_INP_DIS_0 0x3499433#define WCD937X_DIGITAL_PAD_INP_DIS_1 0x349A434#define WCD937X_DIGITAL_DRIVE_STRENGTH_0 0x349B435#define WCD937X_DIGITAL_DRIVE_STRENGTH_1 0x349C436#define WCD937X_DIGITAL_DRIVE_STRENGTH_2 0x349D437#define WCD937X_DIGITAL_RX_DATA_EDGE_CTL 0x349E438#define WCD937X_DIGITAL_TX_DATA_EDGE_CTL 0x349F439#define WCD937X_DIGITAL_GPIO_MODE 0x34A0440#define WCD937X_DIGITAL_PIN_CTL_OE 0x34A1441#define WCD937X_DIGITAL_PIN_CTL_DATA_0 0x34A2442#define WCD937X_DIGITAL_PIN_CTL_DATA_1 0x34A3443#define WCD937X_DIGITAL_PIN_STATUS_0 0x34A4444#define WCD937X_DIGITAL_PIN_STATUS_1 0x34A5445#define WCD937X_DIGITAL_DIG_DEBUG_CTL 0x34A6446#define WCD937X_DIGITAL_DIG_DEBUG_EN 0x34A7447#define WCD937X_DIGITAL_ANA_CSR_DBG_ADD 0x34A8448#define WCD937X_DIGITAL_ANA_CSR_DBG_CTL 0x34A9449#define WCD937X_DIGITAL_SSP_DBG 0x34AA450#define WCD937X_DIGITAL_MODE_STATUS_0 0x34AB451#define WCD937X_DIGITAL_MODE_STATUS_1 0x34AC452#define WCD937X_DIGITAL_SPARE_0 0x34AD453#define WCD937X_DIGITAL_SPARE_1 0x34AE454#define WCD937X_DIGITAL_SPARE_2 0x34AF455#define WCD937X_DIGITAL_EFUSE_REG_0 0x34B0456#define WCD937X_DIGITAL_EFUSE_REG_1 0x34B1457#define WCD937X_DIGITAL_EFUSE_REG_2 0x34B2458#define WCD937X_DIGITAL_EFUSE_REG_3 0x34B3459#define WCD937X_DIGITAL_EFUSE_REG_4 0x34B4460#define WCD937X_DIGITAL_EFUSE_REG_5 0x34B5461#define WCD937X_DIGITAL_EFUSE_REG_6 0x34B6462#define WCD937X_DIGITAL_EFUSE_REG_7 0x34B7463#define WCD937X_DIGITAL_EFUSE_REG_8 0x34B8464#define WCD937X_DIGITAL_EFUSE_REG_9 0x34B9465#define WCD937X_DIGITAL_EFUSE_REG_10 0x34BA466#define WCD937X_DIGITAL_EFUSE_REG_11 0x34BB467#define WCD937X_DIGITAL_EFUSE_REG_12 0x34BC468#define WCD937X_DIGITAL_EFUSE_REG_13 0x34BD469#define WCD937X_DIGITAL_EFUSE_REG_14 0x34BE470#define WCD937X_DIGITAL_EFUSE_REG_15 0x34BF471#define WCD937X_DIGITAL_EFUSE_REG_16 0x34C0472#define WCD937X_DIGITAL_EFUSE_REG_17 0x34C1473#define WCD937X_DIGITAL_EFUSE_REG_18 0x34C2474#define WCD937X_DIGITAL_EFUSE_REG_19 0x34C3475#define WCD937X_DIGITAL_EFUSE_REG_20 0x34C4476#define WCD937X_DIGITAL_EFUSE_REG_21 0x34C5477#define WCD937X_DIGITAL_EFUSE_REG_22 0x34C6478#define WCD937X_DIGITAL_EFUSE_REG_23 0x34C7479#define WCD937X_DIGITAL_EFUSE_REG_24 0x34C8480#define WCD937X_DIGITAL_EFUSE_REG_25 0x34C9481#define WCD937X_DIGITAL_EFUSE_REG_26 0x34CA482#define WCD937X_DIGITAL_EFUSE_REG_27 0x34CB483#define WCD937X_DIGITAL_EFUSE_REG_28 0x34CC484#define WCD937X_DIGITAL_EFUSE_REG_29 0x34CD485#define WCD937X_DIGITAL_EFUSE_REG_30 0x34CE486#define WCD937X_DIGITAL_EFUSE_REG_31 0x34CF487#define WCD937X_MAX_REGISTER (WCD937X_DIGITAL_EFUSE_REG_31)488 489#define WCD937X_MAX_MICBIAS 3490#define WCD937X_MAX_BULK_SUPPLY 4491#define WCD937X_MAX_SWR_CH_IDS 15492 493enum wcd937x_tx_sdw_ports {494 WCD937X_ADC_1_PORT = 1,495 WCD937X_ADC_2_3_PORT,496 WCD937X_DMIC_0_3_MBHC_PORT,497 WCD937X_DMIC_4_6_PORT,498 WCD937X_MAX_TX_SWR_PORTS = WCD937X_DMIC_4_6_PORT,499};500 501enum wcd937x_rx_sdw_ports {502 WCD937X_HPH_PORT = 1,503 WCD937X_CLSH_PORT,504 WCD937X_COMP_PORT,505 WCD937X_LO_PORT,506 WCD937X_DSD_PORT,507 WCD937X_MAX_SWR_PORTS = WCD937X_DSD_PORT,508};509 510struct wcd937x_sdw_ch_info {511 int port_num;512 unsigned int ch_mask;513};514 515#define WCD_SDW_CH(id, pn, cmask) \516 [id] = { \517 .port_num = pn, \518 .ch_mask = cmask, \519 }520 521struct wcd937x_priv;522struct wcd937x_sdw_priv {523 struct sdw_slave *sdev;524 struct sdw_stream_config sconfig;525 struct sdw_stream_runtime *sruntime;526 struct sdw_port_config port_config[WCD937X_MAX_SWR_PORTS];527 const struct wcd937x_sdw_ch_info *ch_info;528 bool port_enable[WCD937X_MAX_SWR_CH_IDS];529 int active_ports;530 bool is_tx;531 struct wcd937x_priv *wcd937x;532 struct irq_domain *slave_irq;533 struct regmap *regmap;534};535 536#if IS_ENABLED(CONFIG_SND_SOC_WCD937X_SDW)537int wcd937x_sdw_free(struct wcd937x_sdw_priv *wcd,538 struct snd_pcm_substream *substream,539 struct snd_soc_dai *dai);540int wcd937x_sdw_set_sdw_stream(struct wcd937x_sdw_priv *wcd,541 struct snd_soc_dai *dai,542 void *stream, int direction);543int wcd937x_sdw_hw_params(struct wcd937x_sdw_priv *wcd,544 struct snd_pcm_substream *substream,545 struct snd_pcm_hw_params *params,546 struct snd_soc_dai *dai);547 548struct device *wcd937x_sdw_device_get(struct device_node *np);549 550#else551int wcd937x_sdw_free(struct wcd937x_sdw_priv *wcd,552 struct snd_pcm_substream *substream,553 struct snd_soc_dai *dai)554{555 return -EOPNOTSUPP;556}557 558int wcd937x_sdw_set_sdw_stream(struct wcd937x_sdw_priv *wcd,559 struct snd_soc_dai *dai,560 void *stream, int direction)561{562 return -EOPNOTSUPP;563}564 565int wcd937x_sdw_hw_params(struct wcd937x_sdw_priv *wcd,566 struct snd_pcm_substream *substream,567 struct snd_pcm_hw_params *params,568 struct snd_soc_dai *dai)569{570 return -EOPNOTSUPP;571}572#endif573 574enum {575 /* INTR_CTRL_INT_MASK_0 */576 WCD937X_IRQ_MBHC_BUTTON_PRESS_DET = 0,577 WCD937X_IRQ_MBHC_BUTTON_RELEASE_DET,578 WCD937X_IRQ_MBHC_ELECT_INS_REM_DET,579 WCD937X_IRQ_MBHC_ELECT_INS_REM_LEG_DET,580 WCD937X_IRQ_MBHC_SW_DET,581 WCD937X_IRQ_HPHR_OCP_INT,582 WCD937X_IRQ_HPHR_CNP_INT,583 WCD937X_IRQ_HPHL_OCP_INT,584 585 /* INTR_CTRL_INT_MASK_1 */586 WCD937X_IRQ_HPHL_CNP_INT,587 WCD937X_IRQ_EAR_CNP_INT,588 WCD937X_IRQ_EAR_SCD_INT,589 WCD937X_IRQ_AUX_CNP_INT,590 WCD937X_IRQ_AUX_SCD_INT,591 WCD937X_IRQ_HPHL_PDM_WD_INT,592 WCD937X_IRQ_HPHR_PDM_WD_INT,593 WCD937X_IRQ_AUX_PDM_WD_INT,594 595 /* INTR_CTRL_INT_MASK_2 */596 WCD937X_IRQ_LDORT_SCD_INT,597 WCD937X_IRQ_MBHC_MOISTURE_INT,598 WCD937X_IRQ_HPHL_SURGE_DET_INT,599 WCD937X_IRQ_HPHR_SURGE_DET_INT,600 WCD937X_NUM_IRQS,601};602 603enum wcd937x_tx_sdw_channels {604 WCD937X_ADC1,605 WCD937X_ADC2,606 WCD937X_ADC3,607 WCD937X_DMIC0,608 WCD937X_DMIC1,609 WCD937X_MBHC,610 WCD937X_DMIC2,611 WCD937X_DMIC3,612 WCD937X_DMIC4,613 WCD937X_DMIC5,614 WCD937X_DMIC6,615};616 617enum wcd937x_rx_sdw_channels {618 WCD937X_HPH_L,619 WCD937X_HPH_R,620 WCD937X_CLSH,621 WCD937X_COMP_L,622 WCD937X_COMP_R,623 WCD937X_LO,624 WCD937X_DSD_R,625 WCD937X_DSD_L,626};627 628#endif629