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1/* SPDX-License-Identifier: GPL-2.0-only */2/*3 * Copyright (c) 2018-2021, The Linux Foundation. All rights reserved.4 * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.5 */6 7#ifndef __WCD939X_H__8#define __WCD939X_H__9#include <linux/soundwire/sdw.h>10#include <linux/soundwire/sdw_type.h>11 12#define WCD939X_BASE (0x3000)13#define WCD939X_ANA_PAGE (0x3000)14#define WCD939X_ANA_BIAS (0x3001)15#define WCD939X_BIAS_ANALOG_BIAS_EN BIT(7)16#define WCD939X_BIAS_PRECHRG_EN BIT(6)17#define WCD939X_BIAS_PRECHRG_CTL_MODE BIT(5)18#define WCD939X_ANA_RX_SUPPLIES (0x3008)19#define WCD939X_RX_SUPPLIES_VPOS_EN BIT(7)20#define WCD939X_RX_SUPPLIES_VNEG_EN BIT(6)21#define WCD939X_RX_SUPPLIES_VPOS_PWR_LVL BIT(3)22#define WCD939X_RX_SUPPLIES_VNEG_PWR_LVL BIT(2)23#define WCD939X_RX_SUPPLIES_REGULATOR_MODE BIT(1)24#define WCD939X_RX_SUPPLIES_RX_BIAS_ENABLE BIT(0)25#define WCD939X_ANA_HPH (0x3009)26#define WCD939X_HPH_HPHL_ENABLE BIT(7)27#define WCD939X_HPH_HPHR_ENABLE BIT(6)28#define WCD939X_HPH_HPHL_REF_ENABLE BIT(5)29#define WCD939X_HPH_HPHR_REF_ENABLE BIT(4)30#define WCD939X_HPH_PWR_LEVEL GENMASK(3, 2)31#define WCD939X_ANA_EAR (0x300a)32#define WCD939X_ANA_EAR_COMPANDER_CTL (0x300b)33#define WCD939X_EAR_COMPANDER_CTL_GAIN_OVRD_REG BIT(7)34#define WCD939X_EAR_COMPANDER_CTL_EAR_GAIN GENMASK(6, 2)35#define WCD939X_EAR_COMPANDER_CTL_COMP_DFF_BYP BIT(1)36#define WCD939X_EAR_COMPANDER_CTL_COMP_DFF_CLK_EDGE BIT(0)37#define WCD939X_ANA_TX_CH1 (0x300e)38#define WCD939X_ANA_TX_CH2 (0x300f)39#define WCD939X_TX_CH2_ENABLE BIT(7)40#define WCD939X_TX_CH2_HPF1_INIT BIT(6)41#define WCD939X_TX_CH2_HPF2_INIT BIT(5)42#define WCD939X_TX_CH2_GAIN GENMASK(4, 0)43#define WCD939X_ANA_TX_CH3 (0x3010)44#define WCD939X_ANA_TX_CH4 (0x3011)45#define WCD939X_TX_CH4_ENABLE BIT(7)46#define WCD939X_TX_CH4_HPF3_INIT BIT(6)47#define WCD939X_TX_CH4_HPF4_INIT BIT(5)48#define WCD939X_TX_CH4_GAIN GENMASK(4, 0)49#define WCD939X_ANA_MICB1_MICB2_DSP_EN_LOGIC (0x3012)50#define WCD939X_ANA_MICB3_DSP_EN_LOGIC (0x3013)51#define WCD939X_ANA_MBHC_MECH (0x3014)52#define WCD939X_MBHC_MECH_L_DET_EN BIT(7)53#define WCD939X_MBHC_MECH_GND_DET_EN BIT(6)54#define WCD939X_MBHC_MECH_MECH_DETECT_TYPE BIT(5)55#define WCD939X_MBHC_MECH_HPHL_PLUG_TYPE BIT(4)56#define WCD939X_MBHC_MECH_GND_PLUG_TYPE BIT(3)57#define WCD939X_MBHC_MECH_MECH_HS_L_PULLUP_COMP_EN BIT(2)58#define WCD939X_MBHC_MECH_MECH_HS_G_PULLUP_COMP_EN BIT(1)59#define WCD939X_MBHC_MECH_SW_HPH_L_P_100K_TO_GND BIT(0)60#define WCD939X_ANA_MBHC_ELECT (0x3015)61#define WCD939X_MBHC_ELECT_FSM_EN BIT(7)62#define WCD939X_MBHC_ELECT_BTNDET_ISRC_CTL GENMASK(6, 4)63#define WCD939X_MBHC_ELECT_ELECT_DET_TYPE BIT(3)64#define WCD939X_MBHC_ELECT_ELECT_SCHMT_ISRC_CTL GENMASK(2, 1)65#define WCD939X_MBHC_ELECT_BIAS_EN BIT(0)66#define WCD939X_ANA_MBHC_ZDET (0x3016)67#define WCD939X_MBHC_ZDET_ZDET_L_MEAS_EN BIT(7)68#define WCD939X_MBHC_ZDET_ZDET_R_MEAS_EN BIT(6)69#define WCD939X_MBHC_ZDET_ZDET_CHG_EN BIT(5)70#define WCD939X_MBHC_ZDET_ZDET_ILEAK_COMP_EN BIT(4)71#define WCD939X_MBHC_ZDET_ELECT_ISRC_EN BIT(1)72#define WCD939X_ANA_MBHC_RESULT_1 (0x3017)73#define WCD939X_MBHC_RESULT_1_Z_RESULT_LSB GENMASK(7, 0)74#define WCD939X_ANA_MBHC_RESULT_2 (0x3018)75#define WCD939X_MBHC_RESULT_2_Z_RESULT_MSB GENMASK(7, 0)76#define WCD939X_ANA_MBHC_RESULT_3 (0x3019)77#define WCD939X_ANA_MBHC_BTN0 (0x301a)78#define WCD939X_MBHC_BTN0_VTH GENMASK(7, 2)79#define WCD939X_ANA_MBHC_BTN1 (0x301b)80#define WCD939X_MBHC_BTN1_VTH GENMASK(7, 2)81#define WCD939X_ANA_MBHC_BTN2 (0x301c)82#define WCD939X_MBHC_BTN2_VTH GENMASK(7, 2)83#define WCD939X_ANA_MBHC_BTN3 (0x301d)84#define WCD939X_MBHC_BTN3_VTH GENMASK(7, 2)85#define WCD939X_ANA_MBHC_BTN4 (0x301e)86#define WCD939X_MBHC_BTN4_VTH GENMASK(7, 2)87#define WCD939X_ANA_MBHC_BTN5 (0x301f)88#define WCD939X_MBHC_BTN5_VTH GENMASK(7, 2)89#define WCD939X_ANA_MBHC_BTN6 (0x3020)90#define WCD939X_MBHC_BTN6_VTH GENMASK(7, 2)91#define WCD939X_ANA_MBHC_BTN7 (0x3021)92#define WCD939X_MBHC_BTN7_VTH GENMASK(7, 2)93#define WCD939X_ANA_MICB1 (0x3022)94#define WCD939X_MICB_ENABLE GENMASK(7, 6)95#define WCD939X_MICB_VOUT_CTL GENMASK(5, 0)96#define WCD939X_ANA_MICB2 (0x3023)97#define WCD939X_ANA_MICB2_RAMP (0x3024)98#define WCD939X_MICB2_RAMP_RAMP_ENABLE BIT(7)99#define WCD939X_MICB2_RAMP_MB2_IN2P_SHORT_ENABLE BIT(6)100#define WCD939X_MICB2_RAMP_ALLSW_OVRD_ENABLE BIT(5)101#define WCD939X_MICB2_RAMP_SHIFT_CTL GENMASK(4, 2)102#define WCD939X_MICB2_RAMP_USB_MGDET_MICB2_RAMP GENMASK(1, 0)103#define WCD939X_ANA_MICB3 (0x3025)104#define WCD939X_ANA_MICB4 (0x3026)105#define WCD939X_BIAS_CTL (0x3028)106#define WCD939X_BIAS_VBG_FINE_ADJ (0x3029)107#define WCD939X_LDOL_VDDCX_ADJUST (0x3040)108#define WCD939X_LDOL_DISABLE_LDOL (0x3041)109#define WCD939X_MBHC_CTL_CLK (0x3056)110#define WCD939X_MBHC_CTL_ANA (0x3057)111#define WCD939X_MBHC_ZDET_VNEG_CTL (0x3058)112#define WCD939X_MBHC_ZDET_BIAS_CTL (0x3059)113#define WCD939X_MBHC_CTL_BCS (0x305a)114#define WCD939X_MBHC_MOISTURE_DET_FSM_STATUS (0x305b)115#define WCD939X_MBHC_TEST_CTL (0x305c)116#define WCD939X_LDOH_MODE (0x3067)117#define WCD939X_MODE_LDOH_EN BIT(7)118#define WCD939X_MODE_PWRDN_STATE BIT(6)119#define WCD939X_MODE_SLOWRAMP_EN BIT(5)120#define WCD939X_MODE_VOUT_ADJUST GENMASK(4, 3)121#define WCD939X_MODE_VOUT_COARSE_ADJ GENMASK(2, 0)122#define WCD939X_LDOH_BIAS (0x3068)123#define WCD939X_LDOH_STB_LOADS (0x3069)124#define WCD939X_LDOH_SLOWRAMP (0x306a)125#define WCD939X_MICB1_TEST_CTL_1 (0x306b)126#define WCD939X_TEST_CTL_1_NOISE_FILT_RES_VAL GENMASK(7, 5)127#define WCD939X_TEST_CTL_1_EN_VREFGEN BIT(4)128#define WCD939X_TEST_CTL_1_EN_LDO BIT(3)129#define WCD939X_TEST_CTL_1_LDO_BLEEDER_I_CTRL GENMASK(2, 0)130#define WCD939X_MICB1_TEST_CTL_2 (0x306c)131#define WCD939X_TEST_CTL_2_IBIAS_VREFGEN GENMASK(7, 6)132#define WCD939X_TEST_CTL_2_INRUSH_CURRENT_FIX_DIS BIT(5)133#define WCD939X_TEST_CTL_2_IBIAS_LDO_DRIVER GENMASK(2, 0)134#define WCD939X_MICB1_TEST_CTL_3 (0x306d)135#define WCD939X_TEST_CTL_3_CFILT_REF_EN BIT(7)136#define WCD939X_TEST_CTL_3_RZ_LDO_VAL GENMASK(6, 4)137#define WCD939X_TEST_CTL_3_IBIAS_LDO_STG3 GENMASK(3, 2)138#define WCD939X_TEST_CTL_3_ATEST_CTRL GENMASK(1, 0)139#define WCD939X_MICB2_TEST_CTL_1 (0x306e)140#define WCD939X_MICB2_TEST_CTL_2 (0x306f)141#define WCD939X_MICB2_TEST_CTL_3 (0x3070)142#define WCD939X_MICB3_TEST_CTL_1 (0x3071)143#define WCD939X_MICB3_TEST_CTL_2 (0x3072)144#define WCD939X_MICB3_TEST_CTL_3 (0x3073)145#define WCD939X_MICB4_TEST_CTL_1 (0x3074)146#define WCD939X_MICB4_TEST_CTL_2 (0x3075)147#define WCD939X_MICB4_TEST_CTL_3 (0x3076)148#define WCD939X_TX_COM_ADC_VCM (0x3077)149#define WCD939X_TX_COM_BIAS_ATEST (0x3078)150#define WCD939X_TX_COM_SPARE1 (0x3079)151#define WCD939X_TX_COM_SPARE2 (0x307a)152#define WCD939X_TX_COM_TXFE_DIV_CTL (0x307b)153#define WCD939X_TX_COM_TXFE_DIV_START (0x307c)154#define WCD939X_TX_COM_SPARE3 (0x307d)155#define WCD939X_TX_COM_SPARE4 (0x307e)156#define WCD939X_TX_1_2_TEST_EN (0x307f)157#define WCD939X_TX_1_2_ADC_IB (0x3080)158#define WCD939X_TX_1_2_ATEST_REFCTL (0x3081)159#define WCD939X_TX_1_2_TEST_CTL (0x3082)160#define WCD939X_TX_1_2_TEST_BLK_EN1 (0x3083)161#define WCD939X_TX_1_2_TXFE1_CLKDIV (0x3084)162#define WCD939X_TX_1_2_SAR2_ERR (0x3085)163#define WCD939X_TX_1_2_SAR1_ERR (0x3086)164#define WCD939X_TX_3_4_TEST_EN (0x3087)165#define WCD939X_TX_3_4_ADC_IB (0x3088)166#define WCD939X_TX_3_4_ATEST_REFCTL (0x3089)167#define WCD939X_TX_3_4_TEST_CTL (0x308a)168#define WCD939X_TX_3_4_TEST_BLK_EN3 (0x308b)169#define WCD939X_TX_3_4_TXFE3_CLKDIV (0x308c)170#define WCD939X_TX_3_4_SAR4_ERR (0x308d)171#define WCD939X_TX_3_4_SAR3_ERR (0x308e)172#define WCD939X_TX_3_4_TEST_BLK_EN2 (0x308f)173#define WCD939X_TEST_BLK_EN2_ADC2_INT1_EN BIT(7)174#define WCD939X_TEST_BLK_EN2_ADC2_INT2_EN BIT(6)175#define WCD939X_TEST_BLK_EN2_ADC2_SAR_EN BIT(5)176#define WCD939X_TEST_BLK_EN2_ADC2_CMGEN_EN BIT(4)177#define WCD939X_TEST_BLK_EN2_ADC2_CLKGEN_EN BIT(3)178#define WCD939X_TEST_BLK_EN2_ADC12_VREF_NONL2 GENMASK(2, 1)179#define WCD939X_TEST_BLK_EN2_TXFE2_MBHC_CLKRST_EN BIT(0)180#define WCD939X_TX_3_4_TXFE2_CLKDIV (0x3090)181#define WCD939X_TX_3_4_SPARE1 (0x3091)182#define WCD939X_TX_3_4_TEST_BLK_EN4 (0x3092)183#define WCD939X_TX_3_4_TXFE4_CLKDIV (0x3093)184#define WCD939X_TX_3_4_SPARE2 (0x3094)185#define WCD939X_CLASSH_MODE_1 (0x3097)186#define WCD939X_CLASSH_MODE_2 (0x3098)187#define WCD939X_CLASSH_MODE_3 (0x3099)188#define WCD939X_CLASSH_CTRL_VCL_1 (0x309a)189#define WCD939X_CLASSH_CTRL_VCL_2 (0x309b)190#define WCD939X_CLASSH_CTRL_CCL_1 (0x309c)191#define WCD939X_CLASSH_CTRL_CCL_2 (0x309d)192#define WCD939X_CLASSH_CTRL_CCL_3 (0x309e)193#define WCD939X_CLASSH_CTRL_CCL_4 (0x309f)194#define WCD939X_CLASSH_CTRL_CCL_5 (0x30a0)195#define WCD939X_CLASSH_BUCK_TMUX_A_D (0x30a1)196#define WCD939X_CLASSH_BUCK_SW_DRV_CNTL (0x30a2)197#define WCD939X_CLASSH_SPARE (0x30a3)198#define WCD939X_FLYBACK_EN (0x30a4)199#define WCD939X_FLYBACK_VNEG_CTRL_1 (0x30a5)200#define WCD939X_FLYBACK_VNEG_CTRL_2 (0x30a6)201#define WCD939X_FLYBACK_VNEG_CTRL_3 (0x30a7)202#define WCD939X_FLYBACK_VNEG_CTRL_4 (0x30a8)203#define WCD939X_VNEG_CTRL_4_ILIM_SEL GENMASK(7, 4)204#define WCD939X_VNEG_CTRL_4_PW_BUF_POS GENMASK(3, 2)205#define WCD939X_VNEG_CTRL_4_PW_BUF_NEG GENMASK(1, 0)206#define WCD939X_FLYBACK_VNEG_CTRL_5 (0x30a9)207#define WCD939X_FLYBACK_VNEG_CTRL_6 (0x30aa)208#define WCD939X_FLYBACK_VNEG_CTRL_7 (0x30ab)209#define WCD939X_FLYBACK_VNEG_CTRL_8 (0x30ac)210#define WCD939X_FLYBACK_VNEG_CTRL_9 (0x30ad)211#define WCD939X_FLYBACK_VNEGDAC_CTRL_1 (0x30ae)212#define WCD939X_FLYBACK_VNEGDAC_CTRL_2 (0x30af)213#define WCD939X_FLYBACK_VNEGDAC_CTRL_3 (0x30b0)214#define WCD939X_FLYBACK_CTRL_1 (0x30b1)215#define WCD939X_FLYBACK_TEST_CTL (0x30b2)216#define WCD939X_RX_AUX_SW_CTL (0x30b3)217#define WCD939X_RX_PA_AUX_IN_CONN (0x30b4)218#define WCD939X_RX_TIMER_DIV (0x30b5)219#define WCD939X_RX_OCP_CTL (0x30b6)220#define WCD939X_RX_OCP_COUNT (0x30b7)221#define WCD939X_RX_BIAS_EAR_DAC (0x30b8)222#define WCD939X_RX_BIAS_EAR_AMP (0x30b9)223#define WCD939X_RX_BIAS_HPH_LDO (0x30ba)224#define WCD939X_RX_BIAS_HPH_PA (0x30bb)225#define WCD939X_RX_BIAS_HPH_RDACBUFF_CNP2 (0x30bc)226#define WCD939X_RX_BIAS_HPH_RDAC_LDO (0x30bd)227#define WCD939X_RX_BIAS_HPH_CNP1 (0x30be)228#define WCD939X_RX_BIAS_HPH_LOWPOWER (0x30bf)229#define WCD939X_RX_BIAS_AUX_DAC (0x30c0)230#define WCD939X_RX_BIAS_AUX_AMP (0x30c1)231#define WCD939X_RX_BIAS_VNEGDAC_BLEEDER (0x30c2)232#define WCD939X_RX_BIAS_MISC (0x30c3)233#define WCD939X_RX_BIAS_BUCK_RST (0x30c4)234#define WCD939X_RX_BIAS_BUCK_VREF_ERRAMP (0x30c5)235#define WCD939X_RX_BIAS_FLYB_ERRAMP (0x30c6)236#define WCD939X_RX_BIAS_FLYB_BUFF (0x30c7)237#define WCD939X_RX_BIAS_FLYB_MID_RST (0x30c8)238#define WCD939X_HPH_L_STATUS (0x30c9)239#define WCD939X_HPH_R_STATUS (0x30ca)240#define WCD939X_HPH_CNP_EN (0x30cb)241#define WCD939X_HPH_CNP_WG_CTL (0x30cc)242#define WCD939X_HPH_CNP_WG_TIME (0x30cd)243#define WCD939X_HPH_OCP_CTL (0x30ce)244#define WCD939X_OCP_CTL_OCP_CURR_LIMIT GENMASK(7, 5)245#define WCD939X_OCP_CTL_OCP_FSM_EN BIT(4)246#define WCD939X_OCP_CTL_SPARE_BITS BIT(3)247#define WCD939X_OCP_CTL_SCD_OP_EN BIT(1)248#define WCD939X_HPH_AUTO_CHOP (0x30cf)249#define WCD939X_HPH_CHOP_CTL (0x30d0)250#define WCD939X_HPH_PA_CTL1 (0x30d1)251#define WCD939X_HPH_PA_CTL2 (0x30d2)252#define WCD939X_PA_CTL2_HPHPA_GND_R BIT(6)253#define WCD939X_PA_CTL2_HPHPA_GND_L BIT(4)254#define WCD939X_PA_CTL2_GM3_CASCODE_CTL_NORMAL GENMASK(1, 0)255#define WCD939X_HPH_L_EN (0x30d3)256#define WCD939X_L_EN_CONST_SEL_L GENMASK(7, 6)257#define WCD939X_L_EN_GAIN_SOURCE_SEL BIT(5)258#define WCD939X_L_EN_SPARE_BITS GENMASK(4, 0)259#define WCD939X_HPH_L_TEST (0x30d4)260#define WCD939X_HPH_L_ATEST (0x30d5)261#define WCD939X_HPH_R_EN (0x30d6)262#define WCD939X_R_EN_CONST_SEL_R GENMASK(7, 6)263#define WCD939X_R_EN_GAIN_SOURCE_SEL BIT(5)264#define WCD939X_R_EN_SPARE_BITS GENMASK(4, 0)265#define WCD939X_HPH_R_TEST (0x30d7)266#define WCD939X_HPH_R_ATEST (0x30d8)267#define WCD939X_R_ATEST_DACR_REF_ATEST1_CONN BIT(7)268#define WCD939X_R_ATEST_LDO1_R_ATEST2_CONN BIT(6)269#define WCD939X_R_ATEST_LDO_R_ATEST2_CAL BIT(5)270#define WCD939X_R_ATEST_LDO2_R_ATEST2_CONN BIT(4)271#define WCD939X_R_ATEST_LDO_1P65V_ATEST1_CONN BIT(3)272#define WCD939X_R_ATEST_HPH_GND_OVR BIT(1)273#define WCD939X_HPH_RDAC_CLK_CTL1 (0x30d9)274#define WCD939X_RDAC_CLK_CTL1_OPAMP_CHOP_CLK_EN BIT(7)275#define WCD939X_RDAC_CLK_CTL1_OPAMP_CHOP_CLK_DIV_CTRL GENMASK(6, 4)276#define WCD939X_RDAC_CLK_CTL1_SPARE_BITS GENMASK(3, 0)277#define WCD939X_HPH_RDAC_CLK_CTL2 (0x30da)278#define WCD939X_HPH_RDAC_LDO_CTL (0x30db)279#define WCD939X_HPH_RDAC_CHOP_CLK_LP_CTL (0x30dc)280#define WCD939X_HPH_REFBUFF_UHQA_CTL (0x30dd)281#define WCD939X_REFBUFF_UHQA_CTL_SPARE_BITS GENMASK(7, 6)282#define WCD939X_REFBUFF_UHQA_CTL_HPH_VNEGREG2_COMP_CTL_OV BIT(5)283#define WCD939X_REFBUFF_UHQA_CTL_REFBUFN_RBIAS_ADJUST BIT(4)284#define WCD939X_REFBUFF_UHQA_CTL_REFBUFP_IOUT_CTL GENMASK(3, 2)285#define WCD939X_REFBUFF_UHQA_CTL_REFBUFN_IOUT_CTL GENMASK(1, 0)286#define WCD939X_HPH_REFBUFF_LP_CTL (0x30de)287#define WCD939X_REFBUFF_LP_CTL_HPH_VNEGREG2_CURR_COMP GENMASK(7, 6)288#define WCD939X_REFBUFF_LP_CTL_SPARE_BITS GENMASK(5, 4)289#define WCD939X_REFBUFF_LP_CTL_EN_PREREF_FILT_STARTUP_CLKDIV BIT(3)290#define WCD939X_REFBUFF_LP_CTL_PREREF_FILT_STARTUP_CLKDIV_CTL GENMASK(2, 1)291#define WCD939X_REFBUFF_LP_CTL_PREREF_FILT_BYPASS BIT(0)292#define WCD939X_HPH_L_DAC_CTL (0x30df)293#define WCD939X_HPH_R_DAC_CTL (0x30e0)294#define WCD939X_HPH_SURGE_COMP_SEL (0x30e1)295#define WCD939X_HPH_SURGE_EN (0x30e2)296#define WCD939X_EN_EN_SURGE_PROTECTION_HPHL BIT(7)297#define WCD939X_EN_EN_SURGE_PROTECTION_HPHR BIT(6)298#define WCD939X_EN_SEL_SURGE_COMP_IQ GENMASK(5, 4)299#define WCD939X_EN_SURGE_VOLT_MODE_SHUTOFF_EN BIT(3)300#define WCD939X_EN_LATCH_INTR_OP_STG_HIZ_EN BIT(2)301#define WCD939X_EN_SURGE_LATCH_REG_RESET BIT(1)302#define WCD939X_EN_SWTICH_VN_VNDAC_NSURGE_EN BIT(0)303#define WCD939X_HPH_SURGE_MISC1 (0x30e3)304#define WCD939X_HPH_SURGE_STATUS (0x30e4)305#define WCD939X_EAR_EN (0x30e9)306#define WCD939X_EAR_PA_CON (0x30ea)307#define WCD939X_EAR_SP_CON (0x30eb)308#define WCD939X_EAR_DAC_CON (0x30ec)309#define WCD939X_DAC_CON_DAC_SAMPLE_EDGE_SEL BIT(7)310#define WCD939X_DAC_CON_REF_DBG_EN BIT(6)311#define WCD939X_DAC_CON_REF_DBG_GAIN GENMASK(5, 3)312#define WCD939X_DAC_CON_GAIN_DAC GENMASK(2, 1)313#define WCD939X_DAC_CON_INV_DATA BIT(0)314#define WCD939X_EAR_CNP_FSM_CON (0x30ed)315#define WCD939X_EAR_TEST_CTL (0x30ee)316#define WCD939X_EAR_STATUS_REG_1 (0x30ef)317#define WCD939X_EAR_STATUS_REG_2 (0x30f0)318#define WCD939X_FLYBACK_NEW_CTRL_2 (0x30f6)319#define WCD939X_FLYBACK_NEW_CTRL_3 (0x30f7)320#define WCD939X_FLYBACK_NEW_CTRL_4 (0x30f8)321#define WCD939X_ANA_NEW_PAGE (0x3100)322#define WCD939X_HPH_NEW_ANA_HPH2 (0x3101)323#define WCD939X_HPH_NEW_ANA_HPH3 (0x3102)324#define WCD939X_SLEEP_CTL (0x3103)325#define WCD939X_SLEEP_WATCHDOG_CTL (0x3104)326#define WCD939X_MBHC_NEW_ELECT_REM_CLAMP_CTL (0x311f)327#define WCD939X_MBHC_NEW_CTL_1 (0x3120)328#define WCD939X_CTL_1_RCO_EN BIT(7)329#define WCD939X_CTL_1_ADC_MODE BIT(4)330#define WCD939X_CTL_1_ADC_ENABLE BIT(3)331#define WCD939X_CTL_1_DETECTION_DONE BIT(2)332#define WCD939X_CTL_1_BTN_DBNC_CTL GENMASK(1, 0)333#define WCD939X_MBHC_NEW_CTL_2 (0x3121)334#define WCD939X_CTL_2_MUX_CTL GENMASK(6, 4)335#define WCD939X_CTL_2_M_RTH_CTL GENMASK(3, 2)336#define WCD939X_CTL_2_HS_VREF_CTL GENMASK(1, 0)337#define WCD939X_MBHC_NEW_PLUG_DETECT_CTL (0x3122)338#define WCD939X_MBHC_NEW_ZDET_ANA_CTL (0x3123)339#define WCD939X_ZDET_ANA_CTL_AVERAGING_EN BIT(7)340#define WCD939X_ZDET_ANA_CTL_MAXV_CTL GENMASK(6, 4)341#define WCD939X_ZDET_ANA_CTL_RANGE_CTL GENMASK(3, 0)342#define WCD939X_MBHC_NEW_ZDET_RAMP_CTL (0x3124)343#define WCD939X_ZDET_RAMP_CTL_ACC1_MIN_CTL GENMASK(6, 4)344#define WCD939X_ZDET_RAMP_CTL_TIME_CTL GENMASK(3, 0)345#define WCD939X_MBHC_NEW_FSM_STATUS (0x3125)346#define WCD939X_FSM_STATUS_ADC_TIMEOUT BIT(7)347#define WCD939X_FSM_STATUS_ADC_COMPLETE BIT(6)348#define WCD939X_FSM_STATUS_HS_M_COMP_STATUS BIT(5)349#define WCD939X_FSM_STATUS_FAST_PRESS_FLAG_STATUS BIT(4)350#define WCD939X_FSM_STATUS_FAST_REMOVAL_FLAG_STATUS BIT(3)351#define WCD939X_FSM_STATUS_REMOVAL_FLAG_STATUS BIT(2)352#define WCD939X_FSM_STATUS_ELECT_REM_RT_STATUS BIT(1)353#define WCD939X_FSM_STATUS_BTN_STATUS BIT(0)354#define WCD939X_MBHC_NEW_ADC_RESULT (0x3126)355#define WCD939X_ADC_RESULT_VALUE GENMASK(7, 0)356#define WCD939X_TX_NEW_CH12_MUX (0x3127)357#define WCD939X_TX_NEW_CH34_MUX (0x3128)358#define WCD939X_DIE_CRACK_DET_EN (0x312c)359#define WCD939X_DIE_CRACK_DET_OUT (0x312d)360#define WCD939X_HPH_NEW_INT_RDAC_GAIN_CTL (0x3132)361#define WCD939X_HPH_NEW_INT_PA_GAIN_CTL_L (0x3133)362#define WCD939X_PA_GAIN_CTL_L_EN_HPHPA_2VPK BIT(7)363#define WCD939X_PA_GAIN_CTL_L_RX_SUPPLY_LEVEL BIT(6)364#define WCD939X_PA_GAIN_CTL_L_DAC_DR_BOOST BIT(5)365#define WCD939X_PA_GAIN_CTL_L_VALUE GENMASK(4, 0)366#define WCD939X_HPH_NEW_INT_RDAC_VREF_CTL (0x3134)367#define WCD939X_HPH_NEW_INT_RDAC_OVERRIDE_CTL (0x3135)368#define WCD939X_HPH_NEW_INT_PA_GAIN_CTL_R (0x3136)369#define WCD939X_PA_GAIN_CTL_R_D_RCO_CLK_EN BIT(7)370#define WCD939X_PA_GAIN_CTL_R_SPARE_BITS GENMASK(6, 5)371#define WCD939X_PA_GAIN_CTL_R_VALUE GENMASK(4, 0)372#define WCD939X_HPH_NEW_INT_PA_MISC1 (0x3137)373#define WCD939X_HPH_NEW_INT_PA_MISC2 (0x3138)374#define WCD939X_HPH_NEW_INT_PA_RDAC_MISC (0x3139)375#define WCD939X_HPH_NEW_INT_TIMER1 (0x313a)376#define WCD939X_TIMER1_CURR_IDIV_CTL_CMPDR_OFF GENMASK(7, 5)377#define WCD939X_TIMER1_CURR_IDIV_CTL_AUTOCHOP GENMASK(4, 2)378#define WCD939X_TIMER1_AUTOCHOP_TIMER_CTL_EN BIT(1)379#define WCD939X_HPH_NEW_INT_TIMER2 (0x313b)380#define WCD939X_HPH_NEW_INT_TIMER3 (0x313c)381#define WCD939X_HPH_NEW_INT_TIMER4 (0x313d)382#define WCD939X_HPH_NEW_INT_PA_RDAC_MISC2 (0x313e)383#define WCD939X_HPH_NEW_INT_PA_RDAC_MISC3 (0x313f)384#define WCD939X_HPH_NEW_INT_RDAC_HD2_CTL_L (0x3140)385#define WCD939X_RDAC_HD2_CTL_L_EN_HD2_RES_DIV_L BIT(7)386#define WCD939X_RDAC_HD2_CTL_L_HD2_RES_DIV_PULLGND_L BIT(6)387#define WCD939X_RDAC_HD2_CTL_L_HD2_RES_DIV_CTL_L GENMASK(5, 0)388#define WCD939X_HPH_NEW_INT_RDAC_HD2_CTL_R (0x3141)389#define WCD939X_RDAC_HD2_CTL_R_EN_HD2_RES_DIV_R BIT(7)390#define WCD939X_RDAC_HD2_CTL_R_HD2_RES_DIV_PULLGND_L BIT(6)391#define WCD939X_RDAC_HD2_CTL_R_HD2_RES_DIV_CTL_R GENMASK(5, 0)392#define WCD939X_RX_NEW_INT_HPH_RDAC_BIAS_LOHIFI (0x3145)393#define WCD939X_RX_NEW_INT_HPH_RDAC_BIAS_ULP (0x3146)394#define WCD939X_RX_NEW_INT_HPH_RDAC_LDO_LP (0x3147)395#define WCD939X_MBHC_NEW_INT_MOISTURE_DET_DC_CTRL (0x31af)396#define WCD939X_MOISTURE_DET_DC_CTRL_ONCOUNT GENMASK(6, 5)397#define WCD939X_MOISTURE_DET_DC_CTRL_OFFCOUNT GENMASK(4, 0)398#define WCD939X_MBHC_NEW_INT_MOISTURE_DET_POLLING_CTRL (0x31b0)399#define WCD939X_MOISTURE_DET_POLLING_CTRL_HPHL_PA_EN BIT(6)400#define WCD939X_MOISTURE_DET_POLLING_CTRL_DTEST_EN GENMASK(5, 4)401#define WCD939X_MOISTURE_DET_POLLING_CTRL_MOIST_OVRD_POLLING BIT(3)402#define WCD939X_MOISTURE_DET_POLLING_CTRL_MOIST_EN_POLLING BIT(2)403#define WCD939X_MOISTURE_DET_POLLING_CTRL_MOIST_DBNC_TIME GENMASK(1, 0)404#define WCD939X_MBHC_NEW_INT_MECH_DET_CURRENT (0x31b1)405#define WCD939X_MECH_DET_CURRENT_HSDET_PULLUP_CTL GENMASK(4, 0)406#define WCD939X_MBHC_NEW_INT_ZDET_CLK_AND_MOISTURE_CTL_NEW (0x31b2)407#define WCD939X_EAR_INT_NEW_CHOPPER_CON (0x31b7)408#define WCD939X_EAR_INT_NEW_CNP_VCM_CON1 (0x31b8)409#define WCD939X_EAR_INT_NEW_CNP_VCM_CON2 (0x31b9)410#define WCD939X_EAR_INT_NEW_DYNAMIC_BIAS (0x31ba)411#define WCD939X_SLEEP_INT_WATCHDOG_CTL_1 (0x31d0)412#define WCD939X_SLEEP_INT_WATCHDOG_CTL_2 (0x31d1)413#define WCD939X_DIE_CRACK_INT_DET_INT1 (0x31d3)414#define WCD939X_DIE_CRACK_INT_DET_INT2 (0x31d4)415#define WCD939X_TX_COM_NEW_INT_FE_DIVSTOP_L2 (0x31d5)416#define WCD939X_TX_COM_NEW_INT_FE_DIVSTOP_L1 (0x31d6)417#define WCD939X_TX_COM_NEW_INT_FE_DIVSTOP_L0 (0x31d7)418#define WCD939X_TX_COM_NEW_INT_FE_DIVSTOP_ULP1P2M (0x31d8)419#define WCD939X_TX_COM_NEW_INT_FE_DIVSTOP_ULP0P6M (0x31d9)420#define WCD939X_TX_COM_NEW_INT_FE_ICTRL_STG1_L2L1 (0x31da)421#define WCD939X_TX_COM_NEW_INT_FE_ICTRL_STG1_L0 (0x31db)422#define WCD939X_TX_COM_NEW_INT_FE_ICTRL_STG1_ULP (0x31dc)423#define WCD939X_TX_COM_NEW_INT_FE_ICTRL_STG2MAIN_L2L1 (0x31dd)424#define WCD939X_TX_COM_NEW_INT_FE_ICTRL_STG2MAIN_L0 (0x31de)425#define WCD939X_TX_COM_NEW_INT_FE_ICTRL_STG2MAIN_ULP (0x31df)426#define WCD939X_FE_ICTRL_STG2MAIN_ULP_VALUE GENMASK(4, 0)427#define WCD939X_TX_COM_NEW_INT_FE_ICTRL_STG2CASC_L2L1L0 (0x31e0)428#define WCD939X_TX_COM_NEW_INT_FE_ICTRL_STG2CASC_ULP (0x31e1)429#define WCD939X_FE_ICTRL_STG2CASC_ULP_ICTRL_SCBIAS_ULP0P6M GENMASK(7, 4)430#define WCD939X_FE_ICTRL_STG2CASC_ULP_VALUE GENMASK(3, 0)431#define WCD939X_TX_COM_NEW_INT_ADC_SCBIAS_L2L1 (0x31e2)432#define WCD939X_TX_COM_NEW_INT_ADC_SCBIAS_L0ULP (0x31e3)433#define WCD939X_TX_COM_NEW_INT_ADC_INT_L2 (0x31e4)434#define WCD939X_TX_COM_NEW_INT_ADC_INT_L1 (0x31e5)435#define WCD939X_TX_COM_NEW_INT_ADC_INT_L0 (0x31e6)436#define WCD939X_TX_COM_NEW_INT_ADC_INT_ULP (0x31e7)437#define WCD939X_DIGITAL_PAGE (0x3400)438#define WCD939X_DIGITAL_CHIP_ID0 (0x3401)439#define WCD939X_DIGITAL_CHIP_ID1 (0x3402)440#define WCD939X_DIGITAL_CHIP_ID2 (0x3403)441#define WCD939X_DIGITAL_CHIP_ID3 (0x3404)442#define WCD939X_DIGITAL_SWR_TX_CLK_RATE (0x3405)443#define WCD939X_DIGITAL_CDC_RST_CTL (0x3406)444#define WCD939X_DIGITAL_TOP_CLK_CFG (0x3407)445#define WCD939X_DIGITAL_CDC_ANA_CLK_CTL (0x3408)446#define WCD939X_CDC_ANA_CLK_CTL_ANA_TX_DIV4_CLK_EN BIT(5)447#define WCD939X_CDC_ANA_CLK_CTL_ANA_TX_DIV2_CLK_EN BIT(4)448#define WCD939X_CDC_ANA_CLK_CTL_ANA_TX_CLK_EN BIT(3)449#define WCD939X_CDC_ANA_CLK_CTL_ANA_RX_DIV4_CLK_EN BIT(2)450#define WCD939X_CDC_ANA_CLK_CTL_ANA_RX_DIV2_CLK_EN BIT(1)451#define WCD939X_CDC_ANA_CLK_CTL_ANA_RX_CLK_EN BIT(0)452#define WCD939X_CDC_ANA_CLK_CTL_ANA_TX_DIV2_CLK_EN BIT(4)453#define WCD939X_DIGITAL_CDC_DIG_CLK_CTL (0x3409)454#define WCD939X_CDC_DIG_CLK_CTL_TXD3_CLK_EN BIT(7)455#define WCD939X_CDC_DIG_CLK_CTL_TXD2_CLK_EN BIT(6)456#define WCD939X_CDC_DIG_CLK_CTL_TXD1_CLK_EN BIT(5)457#define WCD939X_CDC_DIG_CLK_CTL_TXD0_CLK_EN BIT(4)458#define WCD939X_CDC_DIG_CLK_CTL_RXD2_CLK_EN BIT(2)459#define WCD939X_CDC_DIG_CLK_CTL_RXD1_CLK_EN BIT(1)460#define WCD939X_CDC_DIG_CLK_CTL_RXD0_CLK_EN BIT(0)461#define WCD939X_DIGITAL_SWR_RST_EN (0x340a)462#define WCD939X_DIGITAL_CDC_PATH_MODE (0x340b)463#define WCD939X_DIGITAL_CDC_RX_RST (0x340c)464#define WCD939X_DIGITAL_CDC_RX0_CTL (0x340d)465#define WCD939X_DIGITAL_CDC_RX1_CTL (0x340e)466#define WCD939X_DIGITAL_CDC_RX2_CTL (0x340f)467#define WCD939X_DIGITAL_CDC_TX_ANA_MODE_0_1 (0x3410)468#define WCD939X_CDC_TX_ANA_MODE_0_1_TXD1_MODE GENMASK(7, 4)469#define WCD939X_CDC_TX_ANA_MODE_0_1_TXD0_MODE GENMASK(3, 0)470#define WCD939X_DIGITAL_CDC_TX_ANA_MODE_2_3 (0x3411)471#define WCD939X_CDC_TX_ANA_MODE_2_3_TXD3_MODE GENMASK(7, 4)472#define WCD939X_CDC_TX_ANA_MODE_2_3_TXD2_MODE GENMASK(3, 0)473#define WCD939X_DIGITAL_CDC_COMP_CTL_0 (0x3414)474#define WCD939X_CDC_COMP_CTL_0_HPHL_COMP_EN BIT(1)475#define WCD939X_CDC_COMP_CTL_0_HPHR_COMP_EN BIT(0)476#define WCD939X_DIGITAL_CDC_ANA_TX_CLK_CTL (0x3417)477#define WCD939X_CDC_ANA_TX_CLK_CTL_ANA_MBHC_1P2M_CLK_EN BIT(5)478#define WCD939X_CDC_ANA_TX_CLK_CTL_ANA_TX3_ADC_CLK_EN BIT(4)479#define WCD939X_CDC_ANA_TX_CLK_CTL_ANA_TX2_ADC_CLK_EN BIT(3)480#define WCD939X_CDC_ANA_TX_CLK_CTL_ANA_TX1_ADC_CLK_EN BIT(2)481#define WCD939X_CDC_ANA_TX_CLK_CTL_ANA_TX0_ADC_CLK_EN BIT(1)482#define WCD939X_CDC_ANA_TX_CLK_CTL_ANA_TXSCBIAS_CLK_EN BIT(0)483#define WCD939X_DIGITAL_CDC_HPH_DSM_A1_0 (0x3418)484#define WCD939X_DIGITAL_CDC_HPH_DSM_A1_1 (0x3419)485#define WCD939X_DIGITAL_CDC_HPH_DSM_A2_0 (0x341a)486#define WCD939X_DIGITAL_CDC_HPH_DSM_A2_1 (0x341b)487#define WCD939X_DIGITAL_CDC_HPH_DSM_A3_0 (0x341c)488#define WCD939X_DIGITAL_CDC_HPH_DSM_A3_1 (0x341d)489#define WCD939X_DIGITAL_CDC_HPH_DSM_A4_0 (0x341e)490#define WCD939X_DIGITAL_CDC_HPH_DSM_A4_1 (0x341f)491#define WCD939X_DIGITAL_CDC_HPH_DSM_A5_0 (0x3420)492#define WCD939X_DIGITAL_CDC_HPH_DSM_A5_1 (0x3421)493#define WCD939X_DIGITAL_CDC_HPH_DSM_A6_0 (0x3422)494#define WCD939X_DIGITAL_CDC_HPH_DSM_A7_0 (0x3423)495#define WCD939X_DIGITAL_CDC_HPH_DSM_C_0 (0x3424)496#define WCD939X_DIGITAL_CDC_HPH_DSM_C_1 (0x3425)497#define WCD939X_DIGITAL_CDC_HPH_DSM_C_2 (0x3426)498#define WCD939X_DIGITAL_CDC_HPH_DSM_C_3 (0x3427)499#define WCD939X_DIGITAL_CDC_HPH_DSM_R1 (0x3428)500#define WCD939X_DIGITAL_CDC_HPH_DSM_R2 (0x3429)501#define WCD939X_DIGITAL_CDC_HPH_DSM_R3 (0x342a)502#define WCD939X_DIGITAL_CDC_HPH_DSM_R4 (0x342b)503#define WCD939X_DIGITAL_CDC_HPH_DSM_R5 (0x342c)504#define WCD939X_DIGITAL_CDC_HPH_DSM_R6 (0x342d)505#define WCD939X_DIGITAL_CDC_HPH_DSM_R7 (0x342e)506#define WCD939X_DIGITAL_CDC_EAR_DSM_A1_0 (0x342f)507#define WCD939X_DIGITAL_CDC_EAR_DSM_A1_1 (0x3430)508#define WCD939X_DIGITAL_CDC_EAR_DSM_A2_0 (0x3431)509#define WCD939X_DIGITAL_CDC_EAR_DSM_A2_1 (0x3432)510#define WCD939X_DIGITAL_CDC_EAR_DSM_A3_0 (0x3433)511#define WCD939X_DIGITAL_CDC_EAR_DSM_A3_1 (0x3434)512#define WCD939X_DIGITAL_CDC_EAR_DSM_A4_0 (0x3435)513#define WCD939X_DIGITAL_CDC_EAR_DSM_A4_1 (0x3436)514#define WCD939X_DIGITAL_CDC_EAR_DSM_A5_0 (0x3437)515#define WCD939X_DIGITAL_CDC_EAR_DSM_A5_1 (0x3438)516#define WCD939X_DIGITAL_CDC_EAR_DSM_A6_0 (0x3439)517#define WCD939X_DIGITAL_CDC_EAR_DSM_A7_0 (0x343a)518#define WCD939X_DIGITAL_CDC_EAR_DSM_C_0 (0x343b)519#define WCD939X_DIGITAL_CDC_EAR_DSM_C_1 (0x343c)520#define WCD939X_DIGITAL_CDC_EAR_DSM_C_2 (0x343d)521#define WCD939X_DIGITAL_CDC_EAR_DSM_C_3 (0x343e)522#define WCD939X_DIGITAL_CDC_EAR_DSM_R1 (0x343f)523#define WCD939X_DIGITAL_CDC_EAR_DSM_R2 (0x3440)524#define WCD939X_DIGITAL_CDC_EAR_DSM_R3 (0x3441)525#define WCD939X_DIGITAL_CDC_EAR_DSM_R4 (0x3442)526#define WCD939X_DIGITAL_CDC_EAR_DSM_R5 (0x3443)527#define WCD939X_DIGITAL_CDC_EAR_DSM_R6 (0x3444)528#define WCD939X_DIGITAL_CDC_EAR_DSM_R7 (0x3445)529#define WCD939X_DIGITAL_CDC_HPH_GAIN_RX_0 (0x3446)530#define WCD939X_DIGITAL_CDC_HPH_GAIN_RX_1 (0x3447)531#define WCD939X_DIGITAL_CDC_HPH_GAIN_DSD_0 (0x3448)532#define WCD939X_DIGITAL_CDC_HPH_GAIN_DSD_1 (0x3449)533#define WCD939X_DIGITAL_CDC_HPH_GAIN_DSD_2 (0x344a)534#define WCD939X_DIGITAL_CDC_EAR_GAIN_DSD_0 (0x344b)535#define WCD939X_DIGITAL_CDC_EAR_GAIN_DSD_1 (0x344c)536#define WCD939X_DIGITAL_CDC_EAR_GAIN_DSD_2 (0x344d)537#define WCD939X_DIGITAL_CDC_HPH_GAIN_CTL (0x344e)538#define WCD939X_CDC_HPH_GAIN_CTL_HPH_STEREO_EN BIT(4)539#define WCD939X_CDC_HPH_GAIN_CTL_HPHR_RX_EN BIT(3)540#define WCD939X_CDC_HPH_GAIN_CTL_HPHL_RX_EN BIT(2)541#define WCD939X_CDC_HPH_GAIN_CTL_HPHR_DSD_EN BIT(1)542#define WCD939X_CDC_HPH_GAIN_CTL_HPHL_DSD_EN BIT(0)543#define WCD939X_DIGITAL_CDC_EAR_GAIN_CTL (0x344f)544#define WCD939X_CDC_EAR_GAIN_CTL_EAR_EN BIT(0)545#define WCD939X_DIGITAL_CDC_EAR_PATH_CTL (0x3450)546#define WCD939X_DIGITAL_CDC_SWR_CLH (0x3451)547#define WCD939X_CDC_SWR_CLH_CLH_CTL GENMASK(7, 0)548#define WCD939X_DIGITAL_SWR_CLH_BYP (0x3452)549#define WCD939X_DIGITAL_CDC_TX0_CTL (0x3453)550#define WCD939X_DIGITAL_CDC_TX1_CTL (0x3454)551#define WCD939X_DIGITAL_CDC_TX2_CTL (0x3455)552#define WCD939X_DIGITAL_CDC_TX_RST (0x3456)553#define WCD939X_DIGITAL_CDC_REQ_CTL (0x3457)554#define WCD939X_CDC_REQ_CTL_TX3_WIDE_BAND BIT(5)555#define WCD939X_CDC_REQ_CTL_TX2_WIDE_BAND BIT(4)556#define WCD939X_CDC_REQ_CTL_TX1_WIDE_BAND BIT(3)557#define WCD939X_CDC_REQ_CTL_TX0_WIDE_BAND BIT(2)558#define WCD939X_CDC_REQ_CTL_FS_RATE_4P8 BIT(1)559#define WCD939X_CDC_REQ_CTL_NO_NOTCH BIT(0)560#define WCD939X_DIGITAL_CDC_RST (0x3458)561#define WCD939X_DIGITAL_CDC_AMIC_CTL (0x345a)562#define WCD939X_CDC_AMIC_CTL_AMIC5_IN_SEL BIT(3)563#define WCD939X_CDC_AMIC_CTL_AMIC4_IN_SEL BIT(2)564#define WCD939X_CDC_AMIC_CTL_AMIC3_IN_SEL BIT(1)565#define WCD939X_CDC_AMIC_CTL_AMIC1_IN_SEL BIT(0)566#define WCD939X_DIGITAL_CDC_DMIC_CTL (0x345b)567#define WCD939X_CDC_DMIC_CTL_DMIC_LEGACY_SW_MODE BIT(3)568#define WCD939X_CDC_DMIC_CTL_DMIC_DIV_BAK_EN BIT(2)569#define WCD939X_CDC_DMIC_CTL_CLK_SCALE_EN BIT(1)570#define WCD939X_CDC_DMIC_CTL_SOFT_RESET BIT(0)571#define WCD939X_DIGITAL_CDC_DMIC1_CTL (0x345c)572#define WCD939X_CDC_DMIC1_CTL_DMIC_CLK_SCALE_SEL GENMASK(6, 4)573#define WCD939X_CDC_DMIC1_CTL_DMIC_CLK_EN BIT(3)574#define WCD939X_CDC_DMIC1_CTL_DMIC_CLK_SEL GENMASK(2, 0)575#define WCD939X_DIGITAL_CDC_DMIC2_CTL (0x345d)576#define WCD939X_CDC_DMIC2_CTL_DMIC_LEFT_EN BIT(7)577#define WCD939X_CDC_DMIC2_CTL_DMIC_CLK_SCALE_SEL GENMASK(6, 4)578#define WCD939X_CDC_DMIC2_CTL_DMIC_CLK_EN BIT(3)579#define WCD939X_CDC_DMIC2_CTL_DMIC_CLK_SEL GENMASK(2, 0)580#define WCD939X_DIGITAL_CDC_DMIC3_CTL (0x345e)581#define WCD939X_CDC_DMIC3_CTL_DMIC_CLK_SCALE_SEL GENMASK(6, 4)582#define WCD939X_CDC_DMIC3_CTL_DMIC_CLK_EN BIT(3)583#define WCD939X_CDC_DMIC3_CTL_DMIC_CLK_SEL GENMASK(2, 0)584#define WCD939X_DIGITAL_CDC_DMIC4_CTL (0x345f)585#define WCD939X_CDC_DMIC4_CTL_DMIC_CLK_SCALE_SEL GENMASK(6, 4)586#define WCD939X_CDC_DMIC4_CTL_DMIC_CLK_EN BIT(3)587#define WCD939X_CDC_DMIC4_CTL_DMIC_CLK_SEL GENMASK(2, 0)588#define WCD939X_DIGITAL_EFUSE_PRG_CTL (0x3460)589#define WCD939X_DIGITAL_EFUSE_CTL (0x3461)590#define WCD939X_DIGITAL_CDC_DMIC_RATE_1_2 (0x3462)591#define WCD939X_CDC_DMIC_RATE_1_2_DMIC2_RATE GENMASK(7, 4)592#define WCD939X_CDC_DMIC_RATE_1_2_DMIC1_RATE GENMASK(3, 0)593#define WCD939X_DIGITAL_CDC_DMIC_RATE_3_4 (0x3463)594#define WCD939X_CDC_DMIC_RATE_3_4_DMIC4_RATE GENMASK(7, 4)595#define WCD939X_CDC_DMIC_RATE_3_4_DMIC3_RATE GENMASK(3, 0)596#define WCD939X_DIGITAL_PDM_WD_CTL0 (0x3465)597#define WCD939X_PDM_WD_CTL0_HOLD_OFF BIT(4)598#define WCD939X_PDM_WD_CTL0_TIME_OUT_SEL BIT(3)599#define WCD939X_PDM_WD_CTL0_PDM_WD_EN GENMASK(2, 0)600#define WCD939X_DIGITAL_PDM_WD_CTL1 (0x3466)601#define WCD939X_PDM_WD_CTL1_HOLD_OFF BIT(4)602#define WCD939X_PDM_WD_CTL1_TIME_OUT_SEL BIT(3)603#define WCD939X_PDM_WD_CTL1_PDM_WD_EN GENMASK(2, 0)604#define WCD939X_DIGITAL_PDM_WD_CTL2 (0x3467)605#define WCD939X_DIGITAL_INTR_MODE (0x346a)606#define WCD939X_DIGITAL_INTR_MASK_0 (0x346b)607#define WCD939X_DIGITAL_INTR_MASK_1 (0x346c)608#define WCD939X_DIGITAL_INTR_MASK_2 (0x346d)609#define WCD939X_DIGITAL_INTR_STATUS_0 (0x346e)610#define WCD939X_DIGITAL_INTR_STATUS_1 (0x346f)611#define WCD939X_DIGITAL_INTR_STATUS_2 (0x3470)612#define WCD939X_DIGITAL_INTR_CLEAR_0 (0x3471)613#define WCD939X_DIGITAL_INTR_CLEAR_1 (0x3472)614#define WCD939X_DIGITAL_INTR_CLEAR_2 (0x3473)615#define WCD939X_DIGITAL_INTR_LEVEL_0 (0x3474)616#define WCD939X_DIGITAL_INTR_LEVEL_1 (0x3475)617#define WCD939X_DIGITAL_INTR_LEVEL_2 (0x3476)618#define WCD939X_DIGITAL_INTR_SET_0 (0x3477)619#define WCD939X_DIGITAL_INTR_SET_1 (0x3478)620#define WCD939X_DIGITAL_INTR_SET_2 (0x3479)621#define WCD939X_DIGITAL_INTR_TEST_0 (0x347a)622#define WCD939X_DIGITAL_INTR_TEST_1 (0x347b)623#define WCD939X_DIGITAL_INTR_TEST_2 (0x347c)624#define WCD939X_DIGITAL_TX_MODE_DBG_EN (0x347f)625#define WCD939X_DIGITAL_TX_MODE_DBG_0_1 (0x3480)626#define WCD939X_DIGITAL_TX_MODE_DBG_2_3 (0x3481)627#define WCD939X_DIGITAL_LB_IN_SEL_CTL (0x3482)628#define WCD939X_DIGITAL_LOOP_BACK_MODE (0x3483)629#define WCD939X_DIGITAL_SWR_DAC_TEST (0x3484)630#define WCD939X_DIGITAL_SWR_HM_TEST_RX_0 (0x3485)631#define WCD939X_DIGITAL_SWR_HM_TEST_TX_0 (0x3486)632#define WCD939X_DIGITAL_SWR_HM_TEST_RX_1 (0x3487)633#define WCD939X_DIGITAL_SWR_HM_TEST_TX_1 (0x3488)634#define WCD939X_DIGITAL_SWR_HM_TEST_TX_2 (0x3489)635#define WCD939X_DIGITAL_SWR_HM_TEST_0 (0x348a)636#define WCD939X_DIGITAL_SWR_HM_TEST_1 (0x348b)637#define WCD939X_DIGITAL_PAD_CTL_SWR_0 (0x348c)638#define WCD939X_DIGITAL_PAD_CTL_SWR_1 (0x348d)639#define WCD939X_DIGITAL_I2C_CTL (0x348e)640#define WCD939X_DIGITAL_CDC_TX_TANGGU_SW_MODE (0x348f)641#define WCD939X_DIGITAL_EFUSE_TEST_CTL_0 (0x3490)642#define WCD939X_DIGITAL_EFUSE_TEST_CTL_1 (0x3491)643#define WCD939X_DIGITAL_EFUSE_T_DATA_0 (0x3492)644#define WCD939X_DIGITAL_EFUSE_T_DATA_1 (0x3493)645#define WCD939X_DIGITAL_PAD_CTL_PDM_RX0 (0x3494)646#define WCD939X_DIGITAL_PAD_CTL_PDM_RX1 (0x3495)647#define WCD939X_DIGITAL_PAD_CTL_PDM_TX0 (0x3496)648#define WCD939X_DIGITAL_PAD_CTL_PDM_TX1 (0x3497)649#define WCD939X_DIGITAL_PAD_CTL_PDM_TX2 (0x3498)650#define WCD939X_DIGITAL_PAD_INP_DIS_0 (0x3499)651#define WCD939X_DIGITAL_PAD_INP_DIS_1 (0x349a)652#define WCD939X_DIGITAL_DRIVE_STRENGTH_0 (0x349b)653#define WCD939X_DIGITAL_DRIVE_STRENGTH_1 (0x349c)654#define WCD939X_DIGITAL_DRIVE_STRENGTH_2 (0x349d)655#define WCD939X_DIGITAL_RX_DATA_EDGE_CTL (0x349e)656#define WCD939X_DIGITAL_TX_DATA_EDGE_CTL (0x349f)657#define WCD939X_DIGITAL_GPIO_MODE (0x34a0)658#define WCD939X_DIGITAL_PIN_CTL_OE (0x34a1)659#define WCD939X_DIGITAL_PIN_CTL_DATA_0 (0x34a2)660#define WCD939X_DIGITAL_PIN_CTL_DATA_1 (0x34a3)661#define WCD939X_DIGITAL_PIN_STATUS_0 (0x34a4)662#define WCD939X_DIGITAL_PIN_STATUS_1 (0x34a5)663#define WCD939X_DIGITAL_DIG_DEBUG_CTL (0x34a6)664#define WCD939X_DIGITAL_DIG_DEBUG_EN (0x34a7)665#define WCD939X_DIGITAL_ANA_CSR_DBG_ADD (0x34a8)666#define WCD939X_DIGITAL_ANA_CSR_DBG_CTL (0x34a9)667#define WCD939X_DIGITAL_SSP_DBG (0x34aa)668#define WCD939X_DIGITAL_MODE_STATUS_0 (0x34ab)669#define WCD939X_DIGITAL_MODE_STATUS_1 (0x34ac)670#define WCD939X_DIGITAL_SPARE_0 (0x34ad)671#define WCD939X_DIGITAL_SPARE_1 (0x34ae)672#define WCD939X_DIGITAL_SPARE_2 (0x34af)673#define WCD939X_DIGITAL_EFUSE_REG_0 (0x34b0)674#define WCD939X_EFUSE_REG_0_WCD939X_ID GENMASK(4, 1)675#define WCD939X_EFUSE_REG_0_EFUSE_BLOWN BIT(0)676#define WCD939X_DIGITAL_EFUSE_REG_1 (0x34b1)677#define WCD939X_DIGITAL_EFUSE_REG_2 (0x34b2)678#define WCD939X_DIGITAL_EFUSE_REG_3 (0x34b3)679#define WCD939X_DIGITAL_EFUSE_REG_4 (0x34b4)680#define WCD939X_DIGITAL_EFUSE_REG_5 (0x34b5)681#define WCD939X_DIGITAL_EFUSE_REG_6 (0x34b6)682#define WCD939X_DIGITAL_EFUSE_REG_7 (0x34b7)683#define WCD939X_DIGITAL_EFUSE_REG_8 (0x34b8)684#define WCD939X_DIGITAL_EFUSE_REG_9 (0x34b9)685#define WCD939X_DIGITAL_EFUSE_REG_10 (0x34ba)686#define WCD939X_DIGITAL_EFUSE_REG_11 (0x34bb)687#define WCD939X_DIGITAL_EFUSE_REG_12 (0x34bc)688#define WCD939X_DIGITAL_EFUSE_REG_13 (0x34bd)689#define WCD939X_DIGITAL_EFUSE_REG_14 (0x34be)690#define WCD939X_DIGITAL_EFUSE_REG_15 (0x34bf)691#define WCD939X_DIGITAL_EFUSE_REG_16 (0x34c0)692#define WCD939X_DIGITAL_EFUSE_REG_17 (0x34c1)693#define WCD939X_DIGITAL_EFUSE_REG_18 (0x34c2)694#define WCD939X_DIGITAL_EFUSE_REG_19 (0x34c3)695#define WCD939X_DIGITAL_EFUSE_REG_20 (0x34c4)696#define WCD939X_DIGITAL_EFUSE_REG_21 (0x34c5)697#define WCD939X_DIGITAL_EFUSE_REG_22 (0x34c6)698#define WCD939X_DIGITAL_EFUSE_REG_23 (0x34c7)699#define WCD939X_DIGITAL_EFUSE_REG_24 (0x34c8)700#define WCD939X_DIGITAL_EFUSE_REG_25 (0x34c9)701#define WCD939X_DIGITAL_EFUSE_REG_26 (0x34ca)702#define WCD939X_DIGITAL_EFUSE_REG_27 (0x34cb)703#define WCD939X_DIGITAL_EFUSE_REG_28 (0x34cc)704#define WCD939X_DIGITAL_EFUSE_REG_29 (0x34cd)705#define WCD939X_DIGITAL_EFUSE_REG_30 (0x34ce)706#define WCD939X_DIGITAL_EFUSE_REG_31 (0x34cf)707#define WCD939X_DIGITAL_TX_REQ_FB_CTL_0 (0x34d0)708#define WCD939X_DIGITAL_TX_REQ_FB_CTL_1 (0x34d1)709#define WCD939X_DIGITAL_TX_REQ_FB_CTL_2 (0x34d2)710#define WCD939X_DIGITAL_TX_REQ_FB_CTL_3 (0x34d3)711#define WCD939X_DIGITAL_TX_REQ_FB_CTL_4 (0x34d4)712#define WCD939X_DIGITAL_DEM_BYPASS_DATA0 (0x34d5)713#define WCD939X_DIGITAL_DEM_BYPASS_DATA1 (0x34d6)714#define WCD939X_DIGITAL_DEM_BYPASS_DATA2 (0x34d7)715#define WCD939X_DIGITAL_DEM_BYPASS_DATA3 (0x34d8)716#define WCD939X_DIGITAL_DEM_SECOND_ORDER (0x34d9)717#define WCD939X_DIGITAL_DSM_CTRL (0x34da)718#define WCD939X_DIGITAL_DSM_0_STATIC_DATA_0 (0x34db)719#define WCD939X_DIGITAL_DSM_0_STATIC_DATA_1 (0x34dc)720#define WCD939X_DIGITAL_DSM_0_STATIC_DATA_2 (0x34dd)721#define WCD939X_DIGITAL_DSM_0_STATIC_DATA_3 (0x34de)722#define WCD939X_DIGITAL_DSM_1_STATIC_DATA_0 (0x34df)723#define WCD939X_DIGITAL_DSM_1_STATIC_DATA_1 (0x34e0)724#define WCD939X_DIGITAL_DSM_1_STATIC_DATA_2 (0x34e1)725#define WCD939X_DIGITAL_DSM_1_STATIC_DATA_3 (0x34e2)726#define WCD939X_RX_TOP_PAGE (0x3500)727#define WCD939X_RX_TOP_TOP_CFG0 (0x3501)728#define WCD939X_TOP_CFG0_HPH_DAC_RATE_SEL BIT(1)729#define WCD939X_TOP_CFG0_PGA_UPDATE BIT(0)730#define WCD939X_RX_TOP_HPHL_COMP_WR_LSB (0x3502)731#define WCD939X_RX_TOP_HPHL_COMP_WR_MSB (0x3503)732#define WCD939X_RX_TOP_HPHL_COMP_LUT (0x3504)733#define WCD939X_RX_TOP_HPHL_COMP_RD_LSB (0x3505)734#define WCD939X_RX_TOP_HPHL_COMP_RD_MSB (0x3506)735#define WCD939X_RX_TOP_HPHR_COMP_WR_LSB (0x3507)736#define WCD939X_RX_TOP_HPHR_COMP_WR_MSB (0x3508)737#define WCD939X_RX_TOP_HPHR_COMP_LUT (0x3509)738#define WCD939X_RX_TOP_HPHR_COMP_RD_LSB (0x350a)739#define WCD939X_RX_TOP_HPHR_COMP_RD_MSB (0x350b)740#define WCD939X_RX_TOP_DSD0_DEBUG_CFG1 (0x350c)741#define WCD939X_RX_TOP_DSD0_DEBUG_CFG2 (0x350d)742#define WCD939X_RX_TOP_DSD0_DEBUG_CFG3 (0x350e)743#define WCD939X_RX_TOP_DSD0_DEBUG_CFG4 (0x350f)744#define WCD939X_RX_TOP_DSD0_DEBUG_CFG5 (0x3510)745#define WCD939X_RX_TOP_DSD0_DEBUG_CFG6 (0x3511)746#define WCD939X_RX_TOP_DSD1_DEBUG_CFG1 (0x3512)747#define WCD939X_RX_TOP_DSD1_DEBUG_CFG2 (0x3513)748#define WCD939X_RX_TOP_DSD1_DEBUG_CFG3 (0x3514)749#define WCD939X_RX_TOP_DSD1_DEBUG_CFG4 (0x3515)750#define WCD939X_RX_TOP_DSD1_DEBUG_CFG5 (0x3516)751#define WCD939X_RX_TOP_DSD1_DEBUG_CFG6 (0x3517)752#define WCD939X_RX_TOP_HPHL_PATH_CFG0 (0x351c)753#define WCD939X_HPHL_PATH_CFG0_INT_EN BIT(1)754#define WCD939X_HPHL_PATH_CFG0_DLY_ZN_EN BIT(0)755#define WCD939X_RX_TOP_HPHL_PATH_CFG1 (0x351d)756#define WCD939X_HPHL_PATH_CFG1_DSM_SOFT_RST BIT(5)757#define WCD939X_HPHL_PATH_CFG1_INT_SOFT_RST BIT(4)758#define WCD939X_HPHL_PATH_CFG1_FMT_CONV BIT(3)759#define WCD939X_HPHL_PATH_CFG1_IDLE_OVRD_EN BIT(2)760#define WCD939X_HPHL_PATH_CFG1_RX_DC_DROOP_COEFF_SEL GENMASK(1, 0)761#define WCD939X_RX_TOP_HPHR_PATH_CFG0 (0x351e)762#define WCD939X_HPHR_PATH_CFG0_INT_EN BIT(2)763#define WCD939X_HPHR_PATH_CFG0_DLY_ZN_EN BIT(1)764#define WCD939X_RX_TOP_HPHR_PATH_CFG1 (0x351f)765#define WCD939X_HPHR_PATH_CFG1_DSM_SOFT_RST BIT(5)766#define WCD939X_HPHR_PATH_CFG1_INT_SOFT_RST BIT(4)767#define WCD939X_HPHR_PATH_CFG1_FMT_CONV BIT(3)768#define WCD939X_HPHR_PATH_CFG1_IDLE_OVRD_EN BIT(2)769#define WCD939X_HPHR_PATH_CFG1_RX_DC_DROOP_COEFF_SEL GENMASK(1, 0)770#define WCD939X_RX_TOP_PATH_CFG2 (0x3520)771#define WCD939X_RX_TOP_HPHL_PATH_SEC0 (0x3521)772#define WCD939X_RX_TOP_HPHL_PATH_SEC1 (0x3522)773#define WCD939X_RX_TOP_HPHL_PATH_SEC2 (0x3523)774#define WCD939X_RX_TOP_HPHL_PATH_SEC3 (0x3524)775#define WCD939X_RX_TOP_HPHR_PATH_SEC0 (0x3525)776#define WCD939X_RX_TOP_HPHR_PATH_SEC1 (0x3526)777#define WCD939X_RX_TOP_HPHR_PATH_SEC2 (0x3527)778#define WCD939X_RX_TOP_HPHR_PATH_SEC3 (0x3528)779#define WCD939X_RX_TOP_PATH_SEC4 (0x3529)780#define WCD939X_RX_TOP_PATH_SEC5 (0x352a)781#define WCD939X_COMPANDER_HPHL_CTL0 (0x3540)782#define WCD939X_COMPANDER_HPHL_CTL1 (0x3541)783#define WCD939X_COMPANDER_HPHL_CTL2 (0x3542)784#define WCD939X_COMPANDER_HPHL_CTL3 (0x3543)785#define WCD939X_COMPANDER_HPHL_CTL4 (0x3544)786#define WCD939X_COMPANDER_HPHL_CTL5 (0x3545)787#define WCD939X_COMPANDER_HPHL_CTL6 (0x3546)788#define WCD939X_COMPANDER_HPHL_CTL7 (0x3547)789#define WCD939X_COMPANDER_HPHL_CTL8 (0x3548)790#define WCD939X_COMPANDER_HPHL_CTL9 (0x3549)791#define WCD939X_COMPANDER_HPHL_CTL10 (0x354a)792#define WCD939X_COMPANDER_HPHL_CTL11 (0x354b)793#define WCD939X_COMPANDER_HPHL_CTL12 (0x354c)794#define WCD939X_COMPANDER_HPHL_CTL13 (0x354d)795#define WCD939X_COMPANDER_HPHL_CTL14 (0x354e)796#define WCD939X_COMPANDER_HPHL_CTL15 (0x354f)797#define WCD939X_COMPANDER_HPHL_CTL16 (0x3550)798#define WCD939X_COMPANDER_HPHL_CTL17 (0x3551)799#define WCD939X_COMPANDER_HPHL_CTL18 (0x3552)800#define WCD939X_COMPANDER_HPHL_CTL19 (0x3553)801#define WCD939X_R_CTL0 (0x3560)802#define WCD939X_R_CTL1 (0x3561)803#define WCD939X_R_CTL2 (0x3562)804#define WCD939X_R_CTL3 (0x3563)805#define WCD939X_R_CTL4 (0x3564)806#define WCD939X_R_CTL5 (0x3565)807#define WCD939X_R_CTL6 (0x3566)808#define WCD939X_R_CTL7 (0x3567)809#define WCD939X_R_CTL8 (0x3568)810#define WCD939X_R_CTL9 (0x3569)811#define WCD939X_R_CTL10 (0x356a)812#define WCD939X_R_CTL11 (0x356b)813#define WCD939X_R_CTL12 (0x356c)814#define WCD939X_R_CTL13 (0x356d)815#define WCD939X_R_CTL14 (0x356e)816#define WCD939X_R_CTL15 (0x356f)817#define WCD939X_R_CTL16 (0x3570)818#define WCD939X_R_CTL17 (0x3571)819#define WCD939X_R_CTL18 (0x3572)820#define WCD939X_R_CTL19 (0x3573)821#define WCD939X_E_PATH_CTL (0x3580)822#define WCD939X_E_CFG0 (0x3581)823#define WCD939X_CFG0_AUTO_DISABLE_ANC BIT(2)824#define WCD939X_CFG0_AUTO_DISABLE_DSD BIT(1)825#define WCD939X_CFG0_IDLE_STEREO BIT(0)826#define WCD939X_E_CFG1 (0x3582)827#define WCD939X_E_CFG2 (0x3583)828#define WCD939X_E_CFG3 (0x3584)829#define WCD939X_DSD_HPHL_PATH_CTL (0x3590)830#define WCD939X_DSD_HPHL_CFG0 (0x3591)831#define WCD939X_DSD_HPHL_CFG1 (0x3592)832#define WCD939X_DSD_HPHL_CFG2 (0x3593)833#define WCD939X_DSD_HPHL_CFG3 (0x3594)834#define WCD939X_DSD_HPHL_CFG4 (0x3595)835#define WCD939X_DSD_HPHL_CFG5 (0x3596)836#define WCD939X_DSD_HPHR_PATH_CTL (0x35a0)837#define WCD939X_DSD_HPHR_CFG0 (0x35a1)838#define WCD939X_DSD_HPHR_CFG1 (0x35a2)839#define WCD939X_DSD_HPHR_CFG2 (0x35a3)840#define WCD939X_DSD_HPHR_CFG3 (0x35a4)841#define WCD939X_DSD_HPHR_CFG4 (0x35a5)842#define WCD939X_DSD_HPHR_CFG5 (0x35a6)843#define WCD939X_MAX_REGISTER (WCD939X_DSD_HPHR_CFG5)844 845#define WCD939X_MAX_SWR_CH_IDS (15)846 847struct wcd939x_sdw_ch_info {848 int port_num;849 unsigned int ch_mask;850};851 852#define WCD_SDW_CH(id, pn, cmask) \853 [id] = { \854 .port_num = pn, \855 .ch_mask = cmask, \856 }857 858enum wcd939x_tx_sdw_ports {859 WCD939X_ADC_1_4_PORT = 1,860 WCD939X_ADC_DMIC_1_2_PORT,861 WCD939X_DMIC_0_3_MBHC_PORT,862 WCD939X_DMIC_3_7_PORT,863 WCD939X_MAX_TX_SWR_PORTS = WCD939X_DMIC_3_7_PORT,864};865 866enum wcd939x_tx_sdw_channels {867 WCD939X_ADC1,868 WCD939X_ADC2,869 WCD939X_ADC3,870 WCD939X_ADC4,871 WCD939X_DMIC0,872 WCD939X_DMIC1,873 WCD939X_MBHC,874 WCD939X_DMIC2,875 WCD939X_DMIC3,876 WCD939X_DMIC4,877 WCD939X_DMIC5,878 WCD939X_DMIC6,879 WCD939X_DMIC7,880};881 882enum wcd939x_rx_sdw_ports {883 WCD939X_HPH_PORT = 1,884 WCD939X_CLSH_PORT,885 WCD939X_COMP_PORT,886 WCD939X_LO_PORT,887 WCD939X_DSD_PORT,888 WCD939X_HIFI_PCM_PORT,889 WCD939X_MAX_RX_SWR_PORTS = WCD939X_HIFI_PCM_PORT,890 WCD939X_MAX_SWR_PORTS = WCD939X_MAX_RX_SWR_PORTS,891};892 893enum wcd939x_rx_sdw_channels {894 WCD939X_HPH_L,895 WCD939X_HPH_R,896 WCD939X_CLSH,897 WCD939X_COMP_L,898 WCD939X_COMP_R,899 WCD939X_LO,900 WCD939X_DSD_L,901 WCD939X_DSD_R,902 WCD939X_HIFI_PCM_L,903 WCD939X_HIFI_PCM_R,904};905 906struct wcd939x_priv;907struct wcd939x_sdw_priv {908 struct sdw_slave *sdev;909 struct sdw_stream_config sconfig;910 struct sdw_stream_runtime *sruntime;911 struct sdw_port_config port_config[WCD939X_MAX_SWR_PORTS];912 const struct wcd939x_sdw_ch_info *ch_info;913 bool port_enable[WCD939X_MAX_SWR_CH_IDS];914 int active_ports;915 bool is_tx;916 struct wcd939x_priv *wcd939x;917 struct irq_domain *slave_irq;918 struct regmap *regmap;919};920 921#if IS_ENABLED(CONFIG_SND_SOC_WCD939X_SDW)922int wcd939x_sdw_free(struct wcd939x_sdw_priv *wcd,923 struct snd_pcm_substream *substream,924 struct snd_soc_dai *dai);925int wcd939x_sdw_set_sdw_stream(struct wcd939x_sdw_priv *wcd,926 struct snd_soc_dai *dai,927 void *stream, int direction);928int wcd939x_sdw_hw_params(struct wcd939x_sdw_priv *wcd,929 struct snd_pcm_substream *substream,930 struct snd_pcm_hw_params *params,931 struct snd_soc_dai *dai);932 933struct device *wcd939x_sdw_device_get(struct device_node *np);934unsigned int wcd939x_swr_get_current_bank(struct sdw_slave *sdev);935 936struct regmap *wcd939x_swr_get_regmap(struct wcd939x_sdw_priv *wcd);937#else938 939static inline int wcd939x_sdw_free(struct wcd939x_sdw_priv *wcd,940 struct snd_pcm_substream *substream,941 struct snd_soc_dai *dai)942{943 return -EOPNOTSUPP;944}945 946static inline int wcd939x_sdw_set_sdw_stream(struct wcd939x_sdw_priv *wcd,947 struct snd_soc_dai *dai,948 void *stream, int direction)949{950 return -EOPNOTSUPP;951}952 953static inline int wcd939x_sdw_hw_params(struct wcd939x_sdw_priv *wcd,954 struct snd_pcm_substream *substream,955 struct snd_pcm_hw_params *params,956 struct snd_soc_dai *dai)957{958 return -EOPNOTSUPP;959}960 961static inline struct device *wcd939x_sdw_device_get(struct device_node *np)962{963 return NULL;964}965 966static inline unsigned int wcd939x_swr_get_current_bank(struct sdw_slave *sdev)967{968 return 0;969}970 971struct regmap *wcd939x_swr_get_regmap(struct wcd939x_sdw_priv *wcd)972{973 return PTR_ERR(-EINVAL);974}975#endif /* CONFIG_SND_SOC_WCD939X_SDW */976 977#endif /* __WCD939X_H__ */978