1638 lines · c
1// SPDX-License-Identifier: GPL-2.0-only2/*3 * wm8350.c -- WM8350 ALSA SoC audio driver4 *5 * Copyright (C) 2007-12 Wolfson Microelectronics PLC.6 *7 * Author: Liam Girdwood <lrg@slimlogic.co.uk>8 */9 10#include <linux/module.h>11#include <linux/moduleparam.h>12#include <linux/init.h>13#include <linux/slab.h>14#include <linux/delay.h>15#include <linux/pm.h>16#include <linux/platform_device.h>17#include <linux/mfd/wm8350/audio.h>18#include <linux/mfd/wm8350/core.h>19#include <linux/regulator/consumer.h>20#include <sound/core.h>21#include <sound/pcm.h>22#include <sound/pcm_params.h>23#include <sound/soc.h>24#include <sound/initval.h>25#include <sound/tlv.h>26#include <trace/events/asoc.h>27 28#include "wm8350.h"29 30#define WM8350_OUTn_0dB 0x3931 32#define WM8350_RAMP_NONE 033#define WM8350_RAMP_UP 134#define WM8350_RAMP_DOWN 235 36/* We only include the analogue supplies here; the digital supplies37 * need to be available well before this driver can be probed.38 */39static const char *supply_names[] = {40 "AVDD",41 "HPVDD",42};43 44struct wm8350_output {45 u16 active;46 u16 left_vol;47 u16 right_vol;48 u16 ramp;49 u16 mute;50};51 52struct wm8350_jack_data {53 struct snd_soc_jack *jack;54 struct delayed_work work;55 int report;56 int short_report;57};58 59struct wm8350_data {60 struct wm8350 *wm8350;61 struct wm8350_output out1;62 struct wm8350_output out2;63 struct wm8350_jack_data hpl;64 struct wm8350_jack_data hpr;65 struct wm8350_jack_data mic;66 struct regulator_bulk_data supplies[ARRAY_SIZE(supply_names)];67 int fll_freq_out;68 int fll_freq_in;69 struct delayed_work pga_work;70};71 72/*73 * Ramp OUT1 PGA volume to minimise pops at stream startup and shutdown.74 */75static inline int wm8350_out1_ramp_step(struct wm8350_data *wm8350_data)76{77 struct wm8350_output *out1 = &wm8350_data->out1;78 struct wm8350 *wm8350 = wm8350_data->wm8350;79 int left_complete = 0, right_complete = 0;80 u16 reg, val;81 82 /* left channel */83 reg = wm8350_reg_read(wm8350, WM8350_LOUT1_VOLUME);84 val = (reg & WM8350_OUT1L_VOL_MASK) >> WM8350_OUT1L_VOL_SHIFT;85 86 if (out1->ramp == WM8350_RAMP_UP) {87 /* ramp step up */88 if (val < out1->left_vol) {89 val++;90 reg &= ~WM8350_OUT1L_VOL_MASK;91 wm8350_reg_write(wm8350, WM8350_LOUT1_VOLUME,92 reg | (val << WM8350_OUT1L_VOL_SHIFT));93 } else94 left_complete = 1;95 } else if (out1->ramp == WM8350_RAMP_DOWN) {96 /* ramp step down */97 if (val > 0) {98 val--;99 reg &= ~WM8350_OUT1L_VOL_MASK;100 wm8350_reg_write(wm8350, WM8350_LOUT1_VOLUME,101 reg | (val << WM8350_OUT1L_VOL_SHIFT));102 } else103 left_complete = 1;104 } else105 return 1;106 107 /* right channel */108 reg = wm8350_reg_read(wm8350, WM8350_ROUT1_VOLUME);109 val = (reg & WM8350_OUT1R_VOL_MASK) >> WM8350_OUT1R_VOL_SHIFT;110 if (out1->ramp == WM8350_RAMP_UP) {111 /* ramp step up */112 if (val < out1->right_vol) {113 val++;114 reg &= ~WM8350_OUT1R_VOL_MASK;115 wm8350_reg_write(wm8350, WM8350_ROUT1_VOLUME,116 reg | (val << WM8350_OUT1R_VOL_SHIFT));117 } else118 right_complete = 1;119 } else if (out1->ramp == WM8350_RAMP_DOWN) {120 /* ramp step down */121 if (val > 0) {122 val--;123 reg &= ~WM8350_OUT1R_VOL_MASK;124 wm8350_reg_write(wm8350, WM8350_ROUT1_VOLUME,125 reg | (val << WM8350_OUT1R_VOL_SHIFT));126 } else127 right_complete = 1;128 }129 130 /* only hit the update bit if either volume has changed this step */131 if (!left_complete || !right_complete)132 wm8350_set_bits(wm8350, WM8350_LOUT1_VOLUME, WM8350_OUT1_VU);133 134 return left_complete & right_complete;135}136 137/*138 * Ramp OUT2 PGA volume to minimise pops at stream startup and shutdown.139 */140static inline int wm8350_out2_ramp_step(struct wm8350_data *wm8350_data)141{142 struct wm8350_output *out2 = &wm8350_data->out2;143 struct wm8350 *wm8350 = wm8350_data->wm8350;144 int left_complete = 0, right_complete = 0;145 u16 reg, val;146 147 /* left channel */148 reg = wm8350_reg_read(wm8350, WM8350_LOUT2_VOLUME);149 val = (reg & WM8350_OUT2L_VOL_MASK) >> WM8350_OUT1L_VOL_SHIFT;150 if (out2->ramp == WM8350_RAMP_UP) {151 /* ramp step up */152 if (val < out2->left_vol) {153 val++;154 reg &= ~WM8350_OUT2L_VOL_MASK;155 wm8350_reg_write(wm8350, WM8350_LOUT2_VOLUME,156 reg | (val << WM8350_OUT1L_VOL_SHIFT));157 } else158 left_complete = 1;159 } else if (out2->ramp == WM8350_RAMP_DOWN) {160 /* ramp step down */161 if (val > 0) {162 val--;163 reg &= ~WM8350_OUT2L_VOL_MASK;164 wm8350_reg_write(wm8350, WM8350_LOUT2_VOLUME,165 reg | (val << WM8350_OUT1L_VOL_SHIFT));166 } else167 left_complete = 1;168 } else169 return 1;170 171 /* right channel */172 reg = wm8350_reg_read(wm8350, WM8350_ROUT2_VOLUME);173 val = (reg & WM8350_OUT2R_VOL_MASK) >> WM8350_OUT1R_VOL_SHIFT;174 if (out2->ramp == WM8350_RAMP_UP) {175 /* ramp step up */176 if (val < out2->right_vol) {177 val++;178 reg &= ~WM8350_OUT2R_VOL_MASK;179 wm8350_reg_write(wm8350, WM8350_ROUT2_VOLUME,180 reg | (val << WM8350_OUT1R_VOL_SHIFT));181 } else182 right_complete = 1;183 } else if (out2->ramp == WM8350_RAMP_DOWN) {184 /* ramp step down */185 if (val > 0) {186 val--;187 reg &= ~WM8350_OUT2R_VOL_MASK;188 wm8350_reg_write(wm8350, WM8350_ROUT2_VOLUME,189 reg | (val << WM8350_OUT1R_VOL_SHIFT));190 } else191 right_complete = 1;192 }193 194 /* only hit the update bit if either volume has changed this step */195 if (!left_complete || !right_complete)196 wm8350_set_bits(wm8350, WM8350_LOUT2_VOLUME, WM8350_OUT2_VU);197 198 return left_complete & right_complete;199}200 201/*202 * This work ramps both output PGAs at stream start/stop time to203 * minimise pop associated with DAPM power switching.204 * It's best to enable Zero Cross when ramping occurs to minimise any205 * zipper noises.206 */207static void wm8350_pga_work(struct work_struct *work)208{209 struct wm8350_data *wm8350_data =210 container_of(work, struct wm8350_data, pga_work.work);211 struct wm8350_output *out1 = &wm8350_data->out1,212 *out2 = &wm8350_data->out2;213 int i, out1_complete, out2_complete;214 215 /* do we need to ramp at all ? */216 if (out1->ramp == WM8350_RAMP_NONE && out2->ramp == WM8350_RAMP_NONE)217 return;218 219 /* PGA volumes have 6 bits of resolution to ramp */220 for (i = 0; i <= 63; i++) {221 out1_complete = 1;222 out2_complete = 1;223 if (out1->ramp != WM8350_RAMP_NONE)224 out1_complete = wm8350_out1_ramp_step(wm8350_data);225 if (out2->ramp != WM8350_RAMP_NONE)226 out2_complete = wm8350_out2_ramp_step(wm8350_data);227 228 /* ramp finished ? */229 if (out1_complete && out2_complete)230 break;231 232 /* we need to delay longer on the up ramp */233 if (out1->ramp == WM8350_RAMP_UP ||234 out2->ramp == WM8350_RAMP_UP) {235 /* delay is longer over 0dB as increases are larger */236 if (i >= WM8350_OUTn_0dB)237 schedule_timeout_interruptible(msecs_to_jiffies238 (2));239 else240 schedule_timeout_interruptible(msecs_to_jiffies241 (1));242 } else243 udelay(50); /* doesn't matter if we delay longer */244 }245 246 out1->ramp = WM8350_RAMP_NONE;247 out2->ramp = WM8350_RAMP_NONE;248}249 250/*251 * WM8350 Controls252 */253 254static int pga_event(struct snd_soc_dapm_widget *w,255 struct snd_kcontrol *kcontrol, int event)256{257 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);258 struct wm8350_data *wm8350_data = snd_soc_component_get_drvdata(component);259 struct wm8350_output *out;260 261 switch (w->shift) {262 case 0:263 case 1:264 out = &wm8350_data->out1;265 break;266 case 2:267 case 3:268 out = &wm8350_data->out2;269 break;270 271 default:272 WARN(1, "Invalid shift %d\n", w->shift);273 return -1;274 }275 276 switch (event) {277 case SND_SOC_DAPM_POST_PMU:278 out->ramp = WM8350_RAMP_UP;279 out->active = 1;280 281 schedule_delayed_work(&wm8350_data->pga_work,282 msecs_to_jiffies(1));283 break;284 285 case SND_SOC_DAPM_PRE_PMD:286 out->ramp = WM8350_RAMP_DOWN;287 out->active = 0;288 289 schedule_delayed_work(&wm8350_data->pga_work,290 msecs_to_jiffies(1));291 break;292 }293 294 return 0;295}296 297static int wm8350_put_volsw_2r_vu(struct snd_kcontrol *kcontrol,298 struct snd_ctl_elem_value *ucontrol)299{300 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);301 struct wm8350_data *wm8350_priv = snd_soc_component_get_drvdata(component);302 struct wm8350_output *out = NULL;303 struct soc_mixer_control *mc =304 (struct soc_mixer_control *)kcontrol->private_value;305 int ret;306 unsigned int reg = mc->reg;307 u16 val;308 309 /* For OUT1 and OUT2 we shadow the values and only actually write310 * them out when active in order to ensure the amplifier comes on311 * as quietly as possible. */312 switch (reg) {313 case WM8350_LOUT1_VOLUME:314 out = &wm8350_priv->out1;315 break;316 case WM8350_LOUT2_VOLUME:317 out = &wm8350_priv->out2;318 break;319 default:320 break;321 }322 323 if (out) {324 out->left_vol = ucontrol->value.integer.value[0];325 out->right_vol = ucontrol->value.integer.value[1];326 if (!out->active)327 return 1;328 }329 330 ret = snd_soc_put_volsw(kcontrol, ucontrol);331 if (ret < 0)332 return ret;333 334 /* now hit the volume update bits (always bit 8) */335 val = snd_soc_component_read(component, reg);336 snd_soc_component_write(component, reg, val | WM8350_OUT1_VU);337 return 1;338}339 340static int wm8350_get_volsw_2r(struct snd_kcontrol *kcontrol,341 struct snd_ctl_elem_value *ucontrol)342{343 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);344 struct wm8350_data *wm8350_priv = snd_soc_component_get_drvdata(component);345 struct wm8350_output *out1 = &wm8350_priv->out1;346 struct wm8350_output *out2 = &wm8350_priv->out2;347 struct soc_mixer_control *mc =348 (struct soc_mixer_control *)kcontrol->private_value;349 unsigned int reg = mc->reg;350 351 /* If these are cached registers use the cache */352 switch (reg) {353 case WM8350_LOUT1_VOLUME:354 ucontrol->value.integer.value[0] = out1->left_vol;355 ucontrol->value.integer.value[1] = out1->right_vol;356 return 0;357 358 case WM8350_LOUT2_VOLUME:359 ucontrol->value.integer.value[0] = out2->left_vol;360 ucontrol->value.integer.value[1] = out2->right_vol;361 return 0;362 363 default:364 break;365 }366 367 return snd_soc_get_volsw(kcontrol, ucontrol);368}369 370static const char *wm8350_deemp[] = { "None", "32kHz", "44.1kHz", "48kHz" };371static const char *wm8350_pol[] = { "Normal", "Inv R", "Inv L", "Inv L & R" };372static const char *wm8350_dacmutem[] = { "Normal", "Soft" };373static const char *wm8350_dacmutes[] = { "Fast", "Slow" };374static const char *wm8350_adcfilter[] = { "None", "High Pass" };375static const char *wm8350_adchp[] = { "44.1kHz", "8kHz", "16kHz", "32kHz" };376static const char *wm8350_lr[] = { "Left", "Right" };377 378static const struct soc_enum wm8350_enum[] = {379 SOC_ENUM_SINGLE(WM8350_DAC_CONTROL, 4, 4, wm8350_deemp),380 SOC_ENUM_SINGLE(WM8350_DAC_CONTROL, 0, 4, wm8350_pol),381 SOC_ENUM_SINGLE(WM8350_DAC_MUTE_VOLUME, 14, 2, wm8350_dacmutem),382 SOC_ENUM_SINGLE(WM8350_DAC_MUTE_VOLUME, 13, 2, wm8350_dacmutes),383 SOC_ENUM_SINGLE(WM8350_ADC_CONTROL, 15, 2, wm8350_adcfilter),384 SOC_ENUM_SINGLE(WM8350_ADC_CONTROL, 8, 4, wm8350_adchp),385 SOC_ENUM_SINGLE(WM8350_ADC_CONTROL, 0, 4, wm8350_pol),386 SOC_ENUM_SINGLE(WM8350_INPUT_MIXER_VOLUME, 15, 2, wm8350_lr),387};388 389static DECLARE_TLV_DB_SCALE(pre_amp_tlv, -1200, 3525, 0);390static DECLARE_TLV_DB_SCALE(out_pga_tlv, -5700, 600, 0);391static DECLARE_TLV_DB_SCALE(dac_pcm_tlv, -7163, 36, 1);392static DECLARE_TLV_DB_SCALE(adc_pcm_tlv, -12700, 50, 1);393static DECLARE_TLV_DB_SCALE(out_mix_tlv, -1500, 300, 1);394 395static const DECLARE_TLV_DB_RANGE(capture_sd_tlv,396 0, 12, TLV_DB_SCALE_ITEM(-3600, 300, 1),397 13, 15, TLV_DB_SCALE_ITEM(0, 0, 0)398);399 400static const struct snd_kcontrol_new wm8350_snd_controls[] = {401 SOC_ENUM("Playback Deemphasis", wm8350_enum[0]),402 SOC_ENUM("Playback DAC Inversion", wm8350_enum[1]),403 SOC_DOUBLE_R_EXT_TLV("Playback PCM Volume",404 WM8350_DAC_DIGITAL_VOLUME_L,405 WM8350_DAC_DIGITAL_VOLUME_R,406 0, 255, 0, wm8350_get_volsw_2r,407 wm8350_put_volsw_2r_vu, dac_pcm_tlv),408 SOC_ENUM("Playback PCM Mute Function", wm8350_enum[2]),409 SOC_ENUM("Playback PCM Mute Speed", wm8350_enum[3]),410 SOC_ENUM("Capture PCM Filter", wm8350_enum[4]),411 SOC_ENUM("Capture PCM HP Filter", wm8350_enum[5]),412 SOC_ENUM("Capture ADC Inversion", wm8350_enum[6]),413 SOC_DOUBLE_R_EXT_TLV("Capture PCM Volume",414 WM8350_ADC_DIGITAL_VOLUME_L,415 WM8350_ADC_DIGITAL_VOLUME_R,416 0, 255, 0, wm8350_get_volsw_2r,417 wm8350_put_volsw_2r_vu, adc_pcm_tlv),418 SOC_DOUBLE_TLV("Capture Sidetone Volume",419 WM8350_ADC_DIVIDER,420 8, 4, 15, 1, capture_sd_tlv),421 SOC_DOUBLE_R_EXT_TLV("Capture Volume",422 WM8350_LEFT_INPUT_VOLUME,423 WM8350_RIGHT_INPUT_VOLUME,424 2, 63, 0, wm8350_get_volsw_2r,425 wm8350_put_volsw_2r_vu, pre_amp_tlv),426 SOC_DOUBLE_R("Capture ZC Switch",427 WM8350_LEFT_INPUT_VOLUME,428 WM8350_RIGHT_INPUT_VOLUME, 13, 1, 0),429 SOC_SINGLE_TLV("Left Input Left Sidetone Volume",430 WM8350_OUTPUT_LEFT_MIXER_VOLUME, 1, 7, 0, out_mix_tlv),431 SOC_SINGLE_TLV("Left Input Right Sidetone Volume",432 WM8350_OUTPUT_LEFT_MIXER_VOLUME,433 5, 7, 0, out_mix_tlv),434 SOC_SINGLE_TLV("Left Input Bypass Volume",435 WM8350_OUTPUT_LEFT_MIXER_VOLUME,436 9, 7, 0, out_mix_tlv),437 SOC_SINGLE_TLV("Right Input Left Sidetone Volume",438 WM8350_OUTPUT_RIGHT_MIXER_VOLUME,439 1, 7, 0, out_mix_tlv),440 SOC_SINGLE_TLV("Right Input Right Sidetone Volume",441 WM8350_OUTPUT_RIGHT_MIXER_VOLUME,442 5, 7, 0, out_mix_tlv),443 SOC_SINGLE_TLV("Right Input Bypass Volume",444 WM8350_OUTPUT_RIGHT_MIXER_VOLUME,445 13, 7, 0, out_mix_tlv),446 SOC_SINGLE("Left Input Mixer +20dB Switch",447 WM8350_INPUT_MIXER_VOLUME_L, 0, 1, 0),448 SOC_SINGLE("Right Input Mixer +20dB Switch",449 WM8350_INPUT_MIXER_VOLUME_R, 0, 1, 0),450 SOC_SINGLE_TLV("Out4 Capture Volume",451 WM8350_INPUT_MIXER_VOLUME,452 1, 7, 0, out_mix_tlv),453 SOC_DOUBLE_R_EXT_TLV("Out1 Playback Volume",454 WM8350_LOUT1_VOLUME,455 WM8350_ROUT1_VOLUME,456 2, 63, 0, wm8350_get_volsw_2r,457 wm8350_put_volsw_2r_vu, out_pga_tlv),458 SOC_DOUBLE_R("Out1 Playback ZC Switch",459 WM8350_LOUT1_VOLUME,460 WM8350_ROUT1_VOLUME, 13, 1, 0),461 SOC_DOUBLE_R_EXT_TLV("Out2 Playback Volume",462 WM8350_LOUT2_VOLUME,463 WM8350_ROUT2_VOLUME,464 2, 63, 0, wm8350_get_volsw_2r,465 wm8350_put_volsw_2r_vu, out_pga_tlv),466 SOC_DOUBLE_R("Out2 Playback ZC Switch", WM8350_LOUT2_VOLUME,467 WM8350_ROUT2_VOLUME, 13, 1, 0),468 SOC_SINGLE("Out2 Right Invert Switch", WM8350_ROUT2_VOLUME, 10, 1, 0),469 SOC_SINGLE_TLV("Out2 Beep Volume", WM8350_BEEP_VOLUME,470 5, 7, 0, out_mix_tlv),471 472 SOC_DOUBLE_R("Out1 Playback Switch",473 WM8350_LOUT1_VOLUME,474 WM8350_ROUT1_VOLUME,475 14, 1, 1),476 SOC_DOUBLE_R("Out2 Playback Switch",477 WM8350_LOUT2_VOLUME,478 WM8350_ROUT2_VOLUME,479 14, 1, 1),480};481 482/*483 * DAPM Controls484 */485 486/* Left Playback Mixer */487static const struct snd_kcontrol_new wm8350_left_play_mixer_controls[] = {488 SOC_DAPM_SINGLE("Playback Switch",489 WM8350_LEFT_MIXER_CONTROL, 11, 1, 0),490 SOC_DAPM_SINGLE("Left Bypass Switch",491 WM8350_LEFT_MIXER_CONTROL, 2, 1, 0),492 SOC_DAPM_SINGLE("Right Playback Switch",493 WM8350_LEFT_MIXER_CONTROL, 12, 1, 0),494 SOC_DAPM_SINGLE("Left Sidetone Switch",495 WM8350_LEFT_MIXER_CONTROL, 0, 1, 0),496 SOC_DAPM_SINGLE("Right Sidetone Switch",497 WM8350_LEFT_MIXER_CONTROL, 1, 1, 0),498};499 500/* Right Playback Mixer */501static const struct snd_kcontrol_new wm8350_right_play_mixer_controls[] = {502 SOC_DAPM_SINGLE("Playback Switch",503 WM8350_RIGHT_MIXER_CONTROL, 12, 1, 0),504 SOC_DAPM_SINGLE("Right Bypass Switch",505 WM8350_RIGHT_MIXER_CONTROL, 3, 1, 0),506 SOC_DAPM_SINGLE("Left Playback Switch",507 WM8350_RIGHT_MIXER_CONTROL, 11, 1, 0),508 SOC_DAPM_SINGLE("Left Sidetone Switch",509 WM8350_RIGHT_MIXER_CONTROL, 0, 1, 0),510 SOC_DAPM_SINGLE("Right Sidetone Switch",511 WM8350_RIGHT_MIXER_CONTROL, 1, 1, 0),512};513 514/* Out4 Mixer */515static const struct snd_kcontrol_new wm8350_out4_mixer_controls[] = {516 SOC_DAPM_SINGLE("Right Playback Switch",517 WM8350_OUT4_MIXER_CONTROL, 12, 1, 0),518 SOC_DAPM_SINGLE("Left Playback Switch",519 WM8350_OUT4_MIXER_CONTROL, 11, 1, 0),520 SOC_DAPM_SINGLE("Right Capture Switch",521 WM8350_OUT4_MIXER_CONTROL, 9, 1, 0),522 SOC_DAPM_SINGLE("Out3 Playback Switch",523 WM8350_OUT4_MIXER_CONTROL, 2, 1, 0),524 SOC_DAPM_SINGLE("Right Mixer Switch",525 WM8350_OUT4_MIXER_CONTROL, 1, 1, 0),526 SOC_DAPM_SINGLE("Left Mixer Switch",527 WM8350_OUT4_MIXER_CONTROL, 0, 1, 0),528};529 530/* Out3 Mixer */531static const struct snd_kcontrol_new wm8350_out3_mixer_controls[] = {532 SOC_DAPM_SINGLE("Left Playback Switch",533 WM8350_OUT3_MIXER_CONTROL, 11, 1, 0),534 SOC_DAPM_SINGLE("Left Capture Switch",535 WM8350_OUT3_MIXER_CONTROL, 8, 1, 0),536 SOC_DAPM_SINGLE("Out4 Playback Switch",537 WM8350_OUT3_MIXER_CONTROL, 3, 1, 0),538 SOC_DAPM_SINGLE("Left Mixer Switch",539 WM8350_OUT3_MIXER_CONTROL, 0, 1, 0),540};541 542/* Left Input Mixer */543static const struct snd_kcontrol_new wm8350_left_capt_mixer_controls[] = {544 SOC_DAPM_SINGLE_TLV("L2 Capture Volume",545 WM8350_INPUT_MIXER_VOLUME_L, 1, 7, 0, out_mix_tlv),546 SOC_DAPM_SINGLE_TLV("L3 Capture Volume",547 WM8350_INPUT_MIXER_VOLUME_L, 9, 7, 0, out_mix_tlv),548 SOC_DAPM_SINGLE("PGA Capture Switch",549 WM8350_LEFT_INPUT_VOLUME, 14, 1, 1),550};551 552/* Right Input Mixer */553static const struct snd_kcontrol_new wm8350_right_capt_mixer_controls[] = {554 SOC_DAPM_SINGLE_TLV("L2 Capture Volume",555 WM8350_INPUT_MIXER_VOLUME_R, 5, 7, 0, out_mix_tlv),556 SOC_DAPM_SINGLE_TLV("L3 Capture Volume",557 WM8350_INPUT_MIXER_VOLUME_R, 13, 7, 0, out_mix_tlv),558 SOC_DAPM_SINGLE("PGA Capture Switch",559 WM8350_RIGHT_INPUT_VOLUME, 14, 1, 1),560};561 562/* Left Mic Mixer */563static const struct snd_kcontrol_new wm8350_left_mic_mixer_controls[] = {564 SOC_DAPM_SINGLE("INN Capture Switch", WM8350_INPUT_CONTROL, 1, 1, 0),565 SOC_DAPM_SINGLE("INP Capture Switch", WM8350_INPUT_CONTROL, 0, 1, 0),566 SOC_DAPM_SINGLE("IN2 Capture Switch", WM8350_INPUT_CONTROL, 2, 1, 0),567};568 569/* Right Mic Mixer */570static const struct snd_kcontrol_new wm8350_right_mic_mixer_controls[] = {571 SOC_DAPM_SINGLE("INN Capture Switch", WM8350_INPUT_CONTROL, 9, 1, 0),572 SOC_DAPM_SINGLE("INP Capture Switch", WM8350_INPUT_CONTROL, 8, 1, 0),573 SOC_DAPM_SINGLE("IN2 Capture Switch", WM8350_INPUT_CONTROL, 10, 1, 0),574};575 576/* Beep Switch */577static const struct snd_kcontrol_new wm8350_beep_switch_controls =578SOC_DAPM_SINGLE("Switch", WM8350_BEEP_VOLUME, 15, 1, 1);579 580/* Out4 Capture Mux */581static const struct snd_kcontrol_new wm8350_out4_capture_controls =582SOC_DAPM_ENUM("Route", wm8350_enum[7]);583 584static const struct snd_soc_dapm_widget wm8350_dapm_widgets[] = {585 586 SND_SOC_DAPM_PGA("IN3R PGA", WM8350_POWER_MGMT_2, 11, 0, NULL, 0),587 SND_SOC_DAPM_PGA("IN3L PGA", WM8350_POWER_MGMT_2, 10, 0, NULL, 0),588 SND_SOC_DAPM_PGA_E("Right Out2 PGA", WM8350_POWER_MGMT_3, 3, 0, NULL,589 0, pga_event,590 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),591 SND_SOC_DAPM_PGA_E("Left Out2 PGA", WM8350_POWER_MGMT_3, 2, 0, NULL, 0,592 pga_event,593 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),594 SND_SOC_DAPM_PGA_E("Right Out1 PGA", WM8350_POWER_MGMT_3, 1, 0, NULL,595 0, pga_event,596 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),597 SND_SOC_DAPM_PGA_E("Left Out1 PGA", WM8350_POWER_MGMT_3, 0, 0, NULL, 0,598 pga_event,599 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),600 601 SND_SOC_DAPM_MIXER("Right Capture Mixer", WM8350_POWER_MGMT_2,602 7, 0, &wm8350_right_capt_mixer_controls[0],603 ARRAY_SIZE(wm8350_right_capt_mixer_controls)),604 605 SND_SOC_DAPM_MIXER("Left Capture Mixer", WM8350_POWER_MGMT_2,606 6, 0, &wm8350_left_capt_mixer_controls[0],607 ARRAY_SIZE(wm8350_left_capt_mixer_controls)),608 609 SND_SOC_DAPM_MIXER("Out4 Mixer", WM8350_POWER_MGMT_2, 5, 0,610 &wm8350_out4_mixer_controls[0],611 ARRAY_SIZE(wm8350_out4_mixer_controls)),612 613 SND_SOC_DAPM_MIXER("Out3 Mixer", WM8350_POWER_MGMT_2, 4, 0,614 &wm8350_out3_mixer_controls[0],615 ARRAY_SIZE(wm8350_out3_mixer_controls)),616 617 SND_SOC_DAPM_MIXER("Right Playback Mixer", WM8350_POWER_MGMT_2, 1, 0,618 &wm8350_right_play_mixer_controls[0],619 ARRAY_SIZE(wm8350_right_play_mixer_controls)),620 621 SND_SOC_DAPM_MIXER("Left Playback Mixer", WM8350_POWER_MGMT_2, 0, 0,622 &wm8350_left_play_mixer_controls[0],623 ARRAY_SIZE(wm8350_left_play_mixer_controls)),624 625 SND_SOC_DAPM_MIXER("Left Mic Mixer", WM8350_POWER_MGMT_2, 8, 0,626 &wm8350_left_mic_mixer_controls[0],627 ARRAY_SIZE(wm8350_left_mic_mixer_controls)),628 629 SND_SOC_DAPM_MIXER("Right Mic Mixer", WM8350_POWER_MGMT_2, 9, 0,630 &wm8350_right_mic_mixer_controls[0],631 ARRAY_SIZE(wm8350_right_mic_mixer_controls)),632 633 /* virtual mixer for Beep and Out2R */634 SND_SOC_DAPM_MIXER("Out2 Mixer", SND_SOC_NOPM, 0, 0, NULL, 0),635 636 SND_SOC_DAPM_SWITCH("Beep", WM8350_POWER_MGMT_3, 7, 0,637 &wm8350_beep_switch_controls),638 639 SND_SOC_DAPM_ADC("Right ADC", "Right Capture",640 WM8350_POWER_MGMT_4, 3, 0),641 SND_SOC_DAPM_ADC("Left ADC", "Left Capture",642 WM8350_POWER_MGMT_4, 2, 0),643 SND_SOC_DAPM_DAC("Right DAC", "Right Playback",644 WM8350_POWER_MGMT_4, 5, 0),645 SND_SOC_DAPM_DAC("Left DAC", "Left Playback",646 WM8350_POWER_MGMT_4, 4, 0),647 648 SND_SOC_DAPM_MICBIAS("Mic Bias", WM8350_POWER_MGMT_1, 4, 0),649 650 SND_SOC_DAPM_MUX("Out4 Capture Channel", SND_SOC_NOPM, 0, 0,651 &wm8350_out4_capture_controls),652 653 SND_SOC_DAPM_OUTPUT("OUT1R"),654 SND_SOC_DAPM_OUTPUT("OUT1L"),655 SND_SOC_DAPM_OUTPUT("OUT2R"),656 SND_SOC_DAPM_OUTPUT("OUT2L"),657 SND_SOC_DAPM_OUTPUT("OUT3"),658 SND_SOC_DAPM_OUTPUT("OUT4"),659 660 SND_SOC_DAPM_INPUT("IN1RN"),661 SND_SOC_DAPM_INPUT("IN1RP"),662 SND_SOC_DAPM_INPUT("IN2R"),663 SND_SOC_DAPM_INPUT("IN1LP"),664 SND_SOC_DAPM_INPUT("IN1LN"),665 SND_SOC_DAPM_INPUT("IN2L"),666 SND_SOC_DAPM_INPUT("IN3R"),667 SND_SOC_DAPM_INPUT("IN3L"),668};669 670static const struct snd_soc_dapm_route wm8350_dapm_routes[] = {671 672 /* left playback mixer */673 {"Left Playback Mixer", "Playback Switch", "Left DAC"},674 {"Left Playback Mixer", "Left Bypass Switch", "IN3L PGA"},675 {"Left Playback Mixer", "Right Playback Switch", "Right DAC"},676 {"Left Playback Mixer", "Left Sidetone Switch", "Left Mic Mixer"},677 {"Left Playback Mixer", "Right Sidetone Switch", "Right Mic Mixer"},678 679 /* right playback mixer */680 {"Right Playback Mixer", "Playback Switch", "Right DAC"},681 {"Right Playback Mixer", "Right Bypass Switch", "IN3R PGA"},682 {"Right Playback Mixer", "Left Playback Switch", "Left DAC"},683 {"Right Playback Mixer", "Left Sidetone Switch", "Left Mic Mixer"},684 {"Right Playback Mixer", "Right Sidetone Switch", "Right Mic Mixer"},685 686 /* out4 playback mixer */687 {"Out4 Mixer", "Right Playback Switch", "Right DAC"},688 {"Out4 Mixer", "Left Playback Switch", "Left DAC"},689 {"Out4 Mixer", "Right Capture Switch", "Right Capture Mixer"},690 {"Out4 Mixer", "Out3 Playback Switch", "Out3 Mixer"},691 {"Out4 Mixer", "Right Mixer Switch", "Right Playback Mixer"},692 {"Out4 Mixer", "Left Mixer Switch", "Left Playback Mixer"},693 {"OUT4", NULL, "Out4 Mixer"},694 695 /* out3 playback mixer */696 {"Out3 Mixer", "Left Playback Switch", "Left DAC"},697 {"Out3 Mixer", "Left Capture Switch", "Left Capture Mixer"},698 {"Out3 Mixer", "Left Mixer Switch", "Left Playback Mixer"},699 {"Out3 Mixer", "Out4 Playback Switch", "Out4 Mixer"},700 {"OUT3", NULL, "Out3 Mixer"},701 702 /* out2 */703 {"Right Out2 PGA", NULL, "Right Playback Mixer"},704 {"Left Out2 PGA", NULL, "Left Playback Mixer"},705 {"OUT2L", NULL, "Left Out2 PGA"},706 {"OUT2R", NULL, "Right Out2 PGA"},707 708 /* out1 */709 {"Right Out1 PGA", NULL, "Right Playback Mixer"},710 {"Left Out1 PGA", NULL, "Left Playback Mixer"},711 {"OUT1L", NULL, "Left Out1 PGA"},712 {"OUT1R", NULL, "Right Out1 PGA"},713 714 /* ADCs */715 {"Left ADC", NULL, "Left Capture Mixer"},716 {"Right ADC", NULL, "Right Capture Mixer"},717 718 /* Left capture mixer */719 {"Left Capture Mixer", "L2 Capture Volume", "IN2L"},720 {"Left Capture Mixer", "L3 Capture Volume", "IN3L PGA"},721 {"Left Capture Mixer", "PGA Capture Switch", "Left Mic Mixer"},722 {"Left Capture Mixer", NULL, "Out4 Capture Channel"},723 724 /* Right capture mixer */725 {"Right Capture Mixer", "L2 Capture Volume", "IN2R"},726 {"Right Capture Mixer", "L3 Capture Volume", "IN3R PGA"},727 {"Right Capture Mixer", "PGA Capture Switch", "Right Mic Mixer"},728 {"Right Capture Mixer", NULL, "Out4 Capture Channel"},729 730 /* L3 Inputs */731 {"IN3L PGA", NULL, "IN3L"},732 {"IN3R PGA", NULL, "IN3R"},733 734 /* Left Mic mixer */735 {"Left Mic Mixer", "INN Capture Switch", "IN1LN"},736 {"Left Mic Mixer", "INP Capture Switch", "IN1LP"},737 {"Left Mic Mixer", "IN2 Capture Switch", "IN2L"},738 739 /* Right Mic mixer */740 {"Right Mic Mixer", "INN Capture Switch", "IN1RN"},741 {"Right Mic Mixer", "INP Capture Switch", "IN1RP"},742 {"Right Mic Mixer", "IN2 Capture Switch", "IN2R"},743 744 /* out 4 capture */745 {"Out4 Capture Channel", NULL, "Out4 Mixer"},746 747 /* Beep */748 {"Beep", NULL, "IN3R PGA"},749};750 751static int wm8350_set_dai_sysclk(struct snd_soc_dai *codec_dai,752 int clk_id, unsigned int freq, int dir)753{754 struct snd_soc_component *component = codec_dai->component;755 struct wm8350_data *wm8350_data = snd_soc_component_get_drvdata(component);756 struct wm8350 *wm8350 = wm8350_data->wm8350;757 u16 fll_4;758 759 switch (clk_id) {760 case WM8350_MCLK_SEL_MCLK:761 wm8350_clear_bits(wm8350, WM8350_CLOCK_CONTROL_1,762 WM8350_MCLK_SEL);763 break;764 case WM8350_MCLK_SEL_PLL_MCLK:765 case WM8350_MCLK_SEL_PLL_DAC:766 case WM8350_MCLK_SEL_PLL_ADC:767 case WM8350_MCLK_SEL_PLL_32K:768 wm8350_set_bits(wm8350, WM8350_CLOCK_CONTROL_1,769 WM8350_MCLK_SEL);770 fll_4 = snd_soc_component_read(component, WM8350_FLL_CONTROL_4) &771 ~WM8350_FLL_CLK_SRC_MASK;772 snd_soc_component_write(component, WM8350_FLL_CONTROL_4, fll_4 | clk_id);773 break;774 }775 776 /* MCLK direction */777 if (dir == SND_SOC_CLOCK_OUT)778 wm8350_set_bits(wm8350, WM8350_CLOCK_CONTROL_2,779 WM8350_MCLK_DIR);780 else781 wm8350_clear_bits(wm8350, WM8350_CLOCK_CONTROL_2,782 WM8350_MCLK_DIR);783 784 return 0;785}786 787static int wm8350_set_clkdiv(struct snd_soc_dai *codec_dai, int div_id, int div)788{789 struct snd_soc_component *component = codec_dai->component;790 u16 val;791 792 switch (div_id) {793 case WM8350_ADC_CLKDIV:794 val = snd_soc_component_read(component, WM8350_ADC_DIVIDER) &795 ~WM8350_ADC_CLKDIV_MASK;796 snd_soc_component_write(component, WM8350_ADC_DIVIDER, val | div);797 break;798 case WM8350_DAC_CLKDIV:799 val = snd_soc_component_read(component, WM8350_DAC_CLOCK_CONTROL) &800 ~WM8350_DAC_CLKDIV_MASK;801 snd_soc_component_write(component, WM8350_DAC_CLOCK_CONTROL, val | div);802 break;803 case WM8350_BCLK_CLKDIV:804 val = snd_soc_component_read(component, WM8350_CLOCK_CONTROL_1) &805 ~WM8350_BCLK_DIV_MASK;806 snd_soc_component_write(component, WM8350_CLOCK_CONTROL_1, val | div);807 break;808 case WM8350_OPCLK_CLKDIV:809 val = snd_soc_component_read(component, WM8350_CLOCK_CONTROL_1) &810 ~WM8350_OPCLK_DIV_MASK;811 snd_soc_component_write(component, WM8350_CLOCK_CONTROL_1, val | div);812 break;813 case WM8350_SYS_CLKDIV:814 val = snd_soc_component_read(component, WM8350_CLOCK_CONTROL_1) &815 ~WM8350_MCLK_DIV_MASK;816 snd_soc_component_write(component, WM8350_CLOCK_CONTROL_1, val | div);817 break;818 case WM8350_DACLR_CLKDIV:819 val = snd_soc_component_read(component, WM8350_DAC_LR_RATE) &820 ~WM8350_DACLRC_RATE_MASK;821 snd_soc_component_write(component, WM8350_DAC_LR_RATE, val | div);822 break;823 case WM8350_ADCLR_CLKDIV:824 val = snd_soc_component_read(component, WM8350_ADC_LR_RATE) &825 ~WM8350_ADCLRC_RATE_MASK;826 snd_soc_component_write(component, WM8350_ADC_LR_RATE, val | div);827 break;828 default:829 return -EINVAL;830 }831 832 return 0;833}834 835static int wm8350_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)836{837 struct snd_soc_component *component = codec_dai->component;838 u16 iface = snd_soc_component_read(component, WM8350_AI_FORMATING) &839 ~(WM8350_AIF_BCLK_INV | WM8350_AIF_LRCLK_INV | WM8350_AIF_FMT_MASK);840 u16 master = snd_soc_component_read(component, WM8350_AI_DAC_CONTROL) &841 ~WM8350_BCLK_MSTR;842 u16 dac_lrc = snd_soc_component_read(component, WM8350_DAC_LR_RATE) &843 ~WM8350_DACLRC_ENA;844 u16 adc_lrc = snd_soc_component_read(component, WM8350_ADC_LR_RATE) &845 ~WM8350_ADCLRC_ENA;846 847 /* set master/slave audio interface */848 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {849 case SND_SOC_DAIFMT_CBM_CFM:850 master |= WM8350_BCLK_MSTR;851 dac_lrc |= WM8350_DACLRC_ENA;852 adc_lrc |= WM8350_ADCLRC_ENA;853 break;854 case SND_SOC_DAIFMT_CBS_CFS:855 break;856 default:857 return -EINVAL;858 }859 860 /* interface format */861 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {862 case SND_SOC_DAIFMT_I2S:863 iface |= 0x2 << 8;864 break;865 case SND_SOC_DAIFMT_RIGHT_J:866 break;867 case SND_SOC_DAIFMT_LEFT_J:868 iface |= 0x1 << 8;869 break;870 case SND_SOC_DAIFMT_DSP_A:871 iface |= 0x3 << 8;872 break;873 case SND_SOC_DAIFMT_DSP_B:874 iface |= 0x3 << 8 | WM8350_AIF_LRCLK_INV;875 break;876 default:877 return -EINVAL;878 }879 880 /* clock inversion */881 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {882 case SND_SOC_DAIFMT_NB_NF:883 break;884 case SND_SOC_DAIFMT_IB_IF:885 iface |= WM8350_AIF_LRCLK_INV | WM8350_AIF_BCLK_INV;886 break;887 case SND_SOC_DAIFMT_IB_NF:888 iface |= WM8350_AIF_BCLK_INV;889 break;890 case SND_SOC_DAIFMT_NB_IF:891 iface |= WM8350_AIF_LRCLK_INV;892 break;893 default:894 return -EINVAL;895 }896 897 snd_soc_component_write(component, WM8350_AI_FORMATING, iface);898 snd_soc_component_write(component, WM8350_AI_DAC_CONTROL, master);899 snd_soc_component_write(component, WM8350_DAC_LR_RATE, dac_lrc);900 snd_soc_component_write(component, WM8350_ADC_LR_RATE, adc_lrc);901 return 0;902}903 904static int wm8350_pcm_hw_params(struct snd_pcm_substream *substream,905 struct snd_pcm_hw_params *params,906 struct snd_soc_dai *codec_dai)907{908 struct snd_soc_component *component = codec_dai->component;909 struct wm8350_data *wm8350_data = snd_soc_component_get_drvdata(component);910 struct wm8350 *wm8350 = wm8350_data->wm8350;911 u16 iface = snd_soc_component_read(component, WM8350_AI_FORMATING) &912 ~WM8350_AIF_WL_MASK;913 914 /* bit size */915 switch (params_width(params)) {916 case 16:917 break;918 case 20:919 iface |= 0x1 << 10;920 break;921 case 24:922 iface |= 0x2 << 10;923 break;924 case 32:925 iface |= 0x3 << 10;926 break;927 }928 929 snd_soc_component_write(component, WM8350_AI_FORMATING, iface);930 931 /* The sloping stopband filter is recommended for use with932 * lower sample rates to improve performance.933 */934 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {935 if (params_rate(params) < 24000)936 wm8350_set_bits(wm8350, WM8350_DAC_MUTE_VOLUME,937 WM8350_DAC_SB_FILT);938 else939 wm8350_clear_bits(wm8350, WM8350_DAC_MUTE_VOLUME,940 WM8350_DAC_SB_FILT);941 }942 943 return 0;944}945 946static int wm8350_mute(struct snd_soc_dai *dai, int mute, int direction)947{948 struct snd_soc_component *component = dai->component;949 unsigned int val;950 951 if (mute)952 val = WM8350_DAC_MUTE_ENA;953 else954 val = 0;955 956 snd_soc_component_update_bits(component, WM8350_DAC_MUTE, WM8350_DAC_MUTE_ENA, val);957 958 return 0;959}960 961/* FLL divisors */962struct _fll_div {963 int div; /* FLL_OUTDIV */964 int n;965 int k;966 int ratio; /* FLL_FRATIO */967};968 969/* The size in bits of the fll divide multiplied by 10970 * to allow rounding later */971#define FIXED_FLL_SIZE ((1 << 16) * 10)972 973static inline int fll_factors(struct _fll_div *fll_div, unsigned int input,974 unsigned int output)975{976 u64 Kpart;977 unsigned int t1, t2, K, Nmod;978 979 if (output >= 2815250 && output <= 3125000)980 fll_div->div = 0x4;981 else if (output >= 5625000 && output <= 6250000)982 fll_div->div = 0x3;983 else if (output >= 11250000 && output <= 12500000)984 fll_div->div = 0x2;985 else if (output >= 22500000 && output <= 25000000)986 fll_div->div = 0x1;987 else {988 printk(KERN_ERR "wm8350: fll freq %d out of range\n", output);989 return -EINVAL;990 }991 992 if (input > 48000)993 fll_div->ratio = 1;994 else995 fll_div->ratio = 8;996 997 t1 = output * (1 << (fll_div->div + 1));998 t2 = input * fll_div->ratio;999 1000 fll_div->n = t1 / t2;1001 Nmod = t1 % t2;1002 1003 if (Nmod) {1004 Kpart = FIXED_FLL_SIZE * (long long)Nmod;1005 do_div(Kpart, t2);1006 K = Kpart & 0xFFFFFFFF;1007 1008 /* Check if we need to round */1009 if ((K % 10) >= 5)1010 K += 5;1011 1012 /* Move down to proper range now rounding is done */1013 K /= 10;1014 fll_div->k = K;1015 } else1016 fll_div->k = 0;1017 1018 return 0;1019}1020 1021static int wm8350_set_fll(struct snd_soc_dai *codec_dai,1022 int pll_id, int source, unsigned int freq_in,1023 unsigned int freq_out)1024{1025 struct snd_soc_component *component = codec_dai->component;1026 struct wm8350_data *priv = snd_soc_component_get_drvdata(component);1027 struct wm8350 *wm8350 = priv->wm8350;1028 struct _fll_div fll_div;1029 int ret = 0;1030 u16 fll_1, fll_4;1031 1032 if (freq_in == priv->fll_freq_in && freq_out == priv->fll_freq_out)1033 return 0;1034 1035 /* power down FLL - we need to do this for reconfiguration */1036 wm8350_clear_bits(wm8350, WM8350_POWER_MGMT_4,1037 WM8350_FLL_ENA | WM8350_FLL_OSC_ENA);1038 1039 if (freq_out == 0 || freq_in == 0)1040 return ret;1041 1042 ret = fll_factors(&fll_div, freq_in, freq_out);1043 if (ret < 0)1044 return ret;1045 dev_dbg(wm8350->dev,1046 "FLL in %u FLL out %u N 0x%x K 0x%x div %d ratio %d",1047 freq_in, freq_out, fll_div.n, fll_div.k, fll_div.div,1048 fll_div.ratio);1049 1050 /* set up N.K & dividers */1051 fll_1 = snd_soc_component_read(component, WM8350_FLL_CONTROL_1) &1052 ~(WM8350_FLL_OUTDIV_MASK | WM8350_FLL_RSP_RATE_MASK | 0xc000);1053 snd_soc_component_write(component, WM8350_FLL_CONTROL_1,1054 fll_1 | (fll_div.div << 8) | 0x50);1055 snd_soc_component_write(component, WM8350_FLL_CONTROL_2,1056 (fll_div.ratio << 11) | (fll_div.1057 n & WM8350_FLL_N_MASK));1058 snd_soc_component_write(component, WM8350_FLL_CONTROL_3, fll_div.k);1059 fll_4 = snd_soc_component_read(component, WM8350_FLL_CONTROL_4) &1060 ~(WM8350_FLL_FRAC | WM8350_FLL_SLOW_LOCK_REF);1061 snd_soc_component_write(component, WM8350_FLL_CONTROL_4,1062 fll_4 | (fll_div.k ? WM8350_FLL_FRAC : 0) |1063 (fll_div.ratio == 8 ? WM8350_FLL_SLOW_LOCK_REF : 0));1064 1065 /* power FLL on */1066 wm8350_set_bits(wm8350, WM8350_POWER_MGMT_4, WM8350_FLL_OSC_ENA);1067 wm8350_set_bits(wm8350, WM8350_POWER_MGMT_4, WM8350_FLL_ENA);1068 1069 priv->fll_freq_out = freq_out;1070 priv->fll_freq_in = freq_in;1071 1072 return 0;1073}1074 1075static int wm8350_set_bias_level(struct snd_soc_component *component,1076 enum snd_soc_bias_level level)1077{1078 struct wm8350_data *priv = snd_soc_component_get_drvdata(component);1079 struct wm8350 *wm8350 = priv->wm8350;1080 struct wm8350_audio_platform_data *platform =1081 wm8350->codec.platform_data;1082 u16 pm1;1083 int ret;1084 1085 switch (level) {1086 case SND_SOC_BIAS_ON:1087 pm1 = wm8350_reg_read(wm8350, WM8350_POWER_MGMT_1) &1088 ~(WM8350_VMID_MASK | WM8350_CODEC_ISEL_MASK);1089 wm8350_reg_write(wm8350, WM8350_POWER_MGMT_1,1090 pm1 | WM8350_VMID_50K |1091 platform->codec_current_on << 14);1092 break;1093 1094 case SND_SOC_BIAS_PREPARE:1095 pm1 = wm8350_reg_read(wm8350, WM8350_POWER_MGMT_1);1096 pm1 &= ~WM8350_VMID_MASK;1097 wm8350_reg_write(wm8350, WM8350_POWER_MGMT_1,1098 pm1 | WM8350_VMID_50K);1099 break;1100 1101 case SND_SOC_BIAS_STANDBY:1102 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {1103 ret = regulator_bulk_enable(ARRAY_SIZE(priv->supplies),1104 priv->supplies);1105 if (ret != 0)1106 return ret;1107 1108 /* Enable the system clock */1109 wm8350_set_bits(wm8350, WM8350_POWER_MGMT_4,1110 WM8350_SYSCLK_ENA);1111 1112 /* mute DAC & outputs */1113 wm8350_set_bits(wm8350, WM8350_DAC_MUTE,1114 WM8350_DAC_MUTE_ENA);1115 1116 /* discharge cap memory */1117 wm8350_reg_write(wm8350, WM8350_ANTI_POP_CONTROL,1118 platform->dis_out1 |1119 (platform->dis_out2 << 2) |1120 (platform->dis_out3 << 4) |1121 (platform->dis_out4 << 6));1122 1123 /* wait for discharge */1124 schedule_timeout_interruptible(msecs_to_jiffies1125 (platform->1126 cap_discharge_msecs));1127 1128 /* enable antipop */1129 wm8350_reg_write(wm8350, WM8350_ANTI_POP_CONTROL,1130 (platform->vmid_s_curve << 8));1131 1132 /* ramp up vmid */1133 wm8350_reg_write(wm8350, WM8350_POWER_MGMT_1,1134 (platform->1135 codec_current_charge << 14) |1136 WM8350_VMID_5K | WM8350_VMIDEN |1137 WM8350_VBUFEN);1138 1139 /* wait for vmid */1140 schedule_timeout_interruptible(msecs_to_jiffies1141 (platform->1142 vmid_charge_msecs));1143 1144 /* turn on vmid 300k */1145 pm1 = wm8350_reg_read(wm8350, WM8350_POWER_MGMT_1) &1146 ~(WM8350_VMID_MASK | WM8350_CODEC_ISEL_MASK);1147 pm1 |= WM8350_VMID_300K |1148 (platform->codec_current_standby << 14);1149 wm8350_reg_write(wm8350, WM8350_POWER_MGMT_1,1150 pm1);1151 1152 1153 /* enable analogue bias */1154 pm1 |= WM8350_BIASEN;1155 wm8350_reg_write(wm8350, WM8350_POWER_MGMT_1, pm1);1156 1157 /* disable antipop */1158 wm8350_reg_write(wm8350, WM8350_ANTI_POP_CONTROL, 0);1159 1160 } else {1161 /* turn on vmid 300k and reduce current */1162 pm1 = wm8350_reg_read(wm8350, WM8350_POWER_MGMT_1) &1163 ~(WM8350_VMID_MASK | WM8350_CODEC_ISEL_MASK);1164 wm8350_reg_write(wm8350, WM8350_POWER_MGMT_1,1165 pm1 | WM8350_VMID_300K |1166 (platform->1167 codec_current_standby << 14));1168 1169 }1170 break;1171 1172 case SND_SOC_BIAS_OFF:1173 1174 /* mute DAC & enable outputs */1175 wm8350_set_bits(wm8350, WM8350_DAC_MUTE, WM8350_DAC_MUTE_ENA);1176 1177 wm8350_set_bits(wm8350, WM8350_POWER_MGMT_3,1178 WM8350_OUT1L_ENA | WM8350_OUT1R_ENA |1179 WM8350_OUT2L_ENA | WM8350_OUT2R_ENA);1180 1181 /* enable anti pop S curve */1182 wm8350_reg_write(wm8350, WM8350_ANTI_POP_CONTROL,1183 (platform->vmid_s_curve << 8));1184 1185 /* turn off vmid */1186 pm1 = wm8350_reg_read(wm8350, WM8350_POWER_MGMT_1) &1187 ~WM8350_VMIDEN;1188 wm8350_reg_write(wm8350, WM8350_POWER_MGMT_1, pm1);1189 1190 /* wait */1191 schedule_timeout_interruptible(msecs_to_jiffies1192 (platform->1193 vmid_discharge_msecs));1194 1195 wm8350_reg_write(wm8350, WM8350_ANTI_POP_CONTROL,1196 (platform->vmid_s_curve << 8) |1197 platform->dis_out1 |1198 (platform->dis_out2 << 2) |1199 (platform->dis_out3 << 4) |1200 (platform->dis_out4 << 6));1201 1202 /* turn off VBuf and drain */1203 pm1 = wm8350_reg_read(wm8350, WM8350_POWER_MGMT_1) &1204 ~(WM8350_VBUFEN | WM8350_VMID_MASK);1205 wm8350_reg_write(wm8350, WM8350_POWER_MGMT_1,1206 pm1 | WM8350_OUTPUT_DRAIN_EN);1207 1208 /* wait */1209 schedule_timeout_interruptible(msecs_to_jiffies1210 (platform->drain_msecs));1211 1212 pm1 &= ~WM8350_BIASEN;1213 wm8350_reg_write(wm8350, WM8350_POWER_MGMT_1, pm1);1214 1215 /* disable anti-pop */1216 wm8350_reg_write(wm8350, WM8350_ANTI_POP_CONTROL, 0);1217 1218 wm8350_clear_bits(wm8350, WM8350_LOUT1_VOLUME,1219 WM8350_OUT1L_ENA);1220 wm8350_clear_bits(wm8350, WM8350_ROUT1_VOLUME,1221 WM8350_OUT1R_ENA);1222 wm8350_clear_bits(wm8350, WM8350_LOUT2_VOLUME,1223 WM8350_OUT2L_ENA);1224 wm8350_clear_bits(wm8350, WM8350_ROUT2_VOLUME,1225 WM8350_OUT2R_ENA);1226 1227 /* disable clock gen */1228 wm8350_clear_bits(wm8350, WM8350_POWER_MGMT_4,1229 WM8350_SYSCLK_ENA);1230 1231 regulator_bulk_disable(ARRAY_SIZE(priv->supplies),1232 priv->supplies);1233 break;1234 }1235 return 0;1236}1237 1238static void wm8350_hp_work(struct wm8350_data *priv,1239 struct wm8350_jack_data *jack,1240 u16 mask)1241{1242 struct wm8350 *wm8350 = priv->wm8350;1243 u16 reg;1244 int report;1245 1246 reg = wm8350_reg_read(wm8350, WM8350_JACK_PIN_STATUS);1247 if (reg & mask)1248 report = jack->report;1249 else1250 report = 0;1251 1252 snd_soc_jack_report(jack->jack, report, jack->report);1253 1254}1255 1256static void wm8350_hpl_work(struct work_struct *work)1257{1258 struct wm8350_data *priv =1259 container_of(work, struct wm8350_data, hpl.work.work);1260 1261 wm8350_hp_work(priv, &priv->hpl, WM8350_JACK_L_LVL);1262}1263 1264static void wm8350_hpr_work(struct work_struct *work)1265{1266 struct wm8350_data *priv =1267 container_of(work, struct wm8350_data, hpr.work.work);1268 1269 wm8350_hp_work(priv, &priv->hpr, WM8350_JACK_R_LVL);1270}1271 1272static irqreturn_t wm8350_hpl_jack_handler(int irq, void *data)1273{1274 struct wm8350_data *priv = data;1275 struct wm8350 *wm8350 = priv->wm8350;1276 1277#ifndef CONFIG_SND_SOC_WM8350_MODULE1278 trace_snd_soc_jack_irq("WM8350 HPL");1279#endif1280 1281 if (device_may_wakeup(wm8350->dev))1282 pm_wakeup_event(wm8350->dev, 250);1283 1284 queue_delayed_work(system_power_efficient_wq,1285 &priv->hpl.work, msecs_to_jiffies(200));1286 1287 return IRQ_HANDLED;1288}1289 1290static irqreturn_t wm8350_hpr_jack_handler(int irq, void *data)1291{1292 struct wm8350_data *priv = data;1293 struct wm8350 *wm8350 = priv->wm8350;1294 1295#ifndef CONFIG_SND_SOC_WM8350_MODULE1296 trace_snd_soc_jack_irq("WM8350 HPR");1297#endif1298 1299 if (device_may_wakeup(wm8350->dev))1300 pm_wakeup_event(wm8350->dev, 250);1301 1302 queue_delayed_work(system_power_efficient_wq,1303 &priv->hpr.work, msecs_to_jiffies(200));1304 1305 return IRQ_HANDLED;1306}1307 1308/**1309 * wm8350_hp_jack_detect - Enable headphone jack detection.1310 *1311 * @component: WM8350 component1312 * @which: left or right jack detect signal1313 * @jack: jack to report detection events on1314 * @report: value to report1315 *1316 * Enables the headphone jack detection of the WM8350. If no report1317 * is specified then detection is disabled.1318 */1319int wm8350_hp_jack_detect(struct snd_soc_component *component, enum wm8350_jack which,1320 struct snd_soc_jack *jack, int report)1321{1322 struct wm8350_data *priv = snd_soc_component_get_drvdata(component);1323 struct wm8350 *wm8350 = priv->wm8350;1324 int ena;1325 1326 switch (which) {1327 case WM8350_JDL:1328 priv->hpl.jack = jack;1329 priv->hpl.report = report;1330 ena = WM8350_JDL_ENA;1331 break;1332 1333 case WM8350_JDR:1334 priv->hpr.jack = jack;1335 priv->hpr.report = report;1336 ena = WM8350_JDR_ENA;1337 break;1338 1339 default:1340 return -EINVAL;1341 }1342 1343 if (report) {1344 wm8350_set_bits(wm8350, WM8350_POWER_MGMT_4, WM8350_TOCLK_ENA);1345 wm8350_set_bits(wm8350, WM8350_JACK_DETECT, ena);1346 } else {1347 wm8350_clear_bits(wm8350, WM8350_JACK_DETECT, ena);1348 }1349 1350 /* Sync status */1351 switch (which) {1352 case WM8350_JDL:1353 wm8350_hpl_jack_handler(0, priv);1354 break;1355 case WM8350_JDR:1356 wm8350_hpr_jack_handler(0, priv);1357 break;1358 }1359 1360 return 0;1361}1362EXPORT_SYMBOL_GPL(wm8350_hp_jack_detect);1363 1364static irqreturn_t wm8350_mic_handler(int irq, void *data)1365{1366 struct wm8350_data *priv = data;1367 struct wm8350 *wm8350 = priv->wm8350;1368 u16 reg;1369 int report = 0;1370 1371#ifndef CONFIG_SND_SOC_WM8350_MODULE1372 trace_snd_soc_jack_irq("WM8350 mic");1373#endif1374 1375 reg = wm8350_reg_read(wm8350, WM8350_JACK_PIN_STATUS);1376 if (reg & WM8350_JACK_MICSCD_LVL)1377 report |= priv->mic.short_report;1378 if (reg & WM8350_JACK_MICSD_LVL)1379 report |= priv->mic.report;1380 1381 snd_soc_jack_report(priv->mic.jack, report,1382 priv->mic.report | priv->mic.short_report);1383 1384 return IRQ_HANDLED;1385}1386 1387/**1388 * wm8350_mic_jack_detect - Enable microphone jack detection.1389 *1390 * @component: WM8350 component1391 * @jack: jack to report detection events on1392 * @detect_report: value to report when presence detected1393 * @short_report: value to report when microphone short detected1394 *1395 * Enables the microphone jack detection of the WM8350. If both reports1396 * are specified as zero then detection is disabled.1397 */1398int wm8350_mic_jack_detect(struct snd_soc_component *component,1399 struct snd_soc_jack *jack,1400 int detect_report, int short_report)1401{1402 struct wm8350_data *priv = snd_soc_component_get_drvdata(component);1403 struct wm8350 *wm8350 = priv->wm8350;1404 1405 priv->mic.jack = jack;1406 priv->mic.report = detect_report;1407 priv->mic.short_report = short_report;1408 1409 if (detect_report || short_report) {1410 wm8350_set_bits(wm8350, WM8350_POWER_MGMT_4, WM8350_TOCLK_ENA);1411 wm8350_set_bits(wm8350, WM8350_POWER_MGMT_1,1412 WM8350_MIC_DET_ENA);1413 } else {1414 wm8350_clear_bits(wm8350, WM8350_POWER_MGMT_1,1415 WM8350_MIC_DET_ENA);1416 }1417 1418 return 0;1419}1420EXPORT_SYMBOL_GPL(wm8350_mic_jack_detect);1421 1422#define WM8350_RATES (SNDRV_PCM_RATE_8000_96000)1423 1424#define WM8350_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\1425 SNDRV_PCM_FMTBIT_S20_3LE |\1426 SNDRV_PCM_FMTBIT_S24_LE)1427 1428static const struct snd_soc_dai_ops wm8350_dai_ops = {1429 .hw_params = wm8350_pcm_hw_params,1430 .mute_stream = wm8350_mute,1431 .set_fmt = wm8350_set_dai_fmt,1432 .set_sysclk = wm8350_set_dai_sysclk,1433 .set_pll = wm8350_set_fll,1434 .set_clkdiv = wm8350_set_clkdiv,1435 .no_capture_mute = 1,1436};1437 1438static struct snd_soc_dai_driver wm8350_dai = {1439 .name = "wm8350-hifi",1440 .playback = {1441 .stream_name = "Playback",1442 .channels_min = 1,1443 .channels_max = 2,1444 .rates = WM8350_RATES,1445 .formats = WM8350_FORMATS,1446 },1447 .capture = {1448 .stream_name = "Capture",1449 .channels_min = 1,1450 .channels_max = 2,1451 .rates = WM8350_RATES,1452 .formats = WM8350_FORMATS,1453 },1454 .ops = &wm8350_dai_ops,1455};1456 1457static int wm8350_component_probe(struct snd_soc_component *component)1458{1459 struct wm8350 *wm8350 = dev_get_platdata(component->dev);1460 struct wm8350_data *priv;1461 struct wm8350_output *out1;1462 struct wm8350_output *out2;1463 int ret, i;1464 1465 if (wm8350->codec.platform_data == NULL) {1466 dev_err(component->dev, "No audio platform data supplied\n");1467 return -EINVAL;1468 }1469 1470 priv = devm_kzalloc(component->dev, sizeof(struct wm8350_data),1471 GFP_KERNEL);1472 if (priv == NULL)1473 return -ENOMEM;1474 1475 snd_soc_component_init_regmap(component, wm8350->regmap);1476 snd_soc_component_set_drvdata(component, priv);1477 1478 priv->wm8350 = wm8350;1479 1480 for (i = 0; i < ARRAY_SIZE(supply_names); i++)1481 priv->supplies[i].supply = supply_names[i];1482 1483 ret = devm_regulator_bulk_get(wm8350->dev, ARRAY_SIZE(priv->supplies),1484 priv->supplies);1485 if (ret != 0)1486 return ret;1487 1488 /* Put the codec into reset if it wasn't already */1489 wm8350_clear_bits(wm8350, WM8350_POWER_MGMT_5, WM8350_CODEC_ENA);1490 1491 INIT_DELAYED_WORK(&priv->pga_work, wm8350_pga_work);1492 INIT_DELAYED_WORK(&priv->hpl.work, wm8350_hpl_work);1493 INIT_DELAYED_WORK(&priv->hpr.work, wm8350_hpr_work);1494 1495 /* Enable the codec */1496 wm8350_set_bits(wm8350, WM8350_POWER_MGMT_5, WM8350_CODEC_ENA);1497 1498 /* Enable robust clocking mode in ADC */1499 snd_soc_component_write(component, WM8350_SECURITY, 0xa7);1500 snd_soc_component_write(component, 0xde, 0x13);1501 snd_soc_component_write(component, WM8350_SECURITY, 0);1502 1503 /* read OUT1 & OUT2 volumes */1504 out1 = &priv->out1;1505 out2 = &priv->out2;1506 out1->left_vol = (wm8350_reg_read(wm8350, WM8350_LOUT1_VOLUME) &1507 WM8350_OUT1L_VOL_MASK) >> WM8350_OUT1L_VOL_SHIFT;1508 out1->right_vol = (wm8350_reg_read(wm8350, WM8350_ROUT1_VOLUME) &1509 WM8350_OUT1R_VOL_MASK) >> WM8350_OUT1R_VOL_SHIFT;1510 out2->left_vol = (wm8350_reg_read(wm8350, WM8350_LOUT2_VOLUME) &1511 WM8350_OUT2L_VOL_MASK) >> WM8350_OUT1L_VOL_SHIFT;1512 out2->right_vol = (wm8350_reg_read(wm8350, WM8350_ROUT2_VOLUME) &1513 WM8350_OUT2R_VOL_MASK) >> WM8350_OUT1R_VOL_SHIFT;1514 wm8350_reg_write(wm8350, WM8350_LOUT1_VOLUME, 0);1515 wm8350_reg_write(wm8350, WM8350_ROUT1_VOLUME, 0);1516 wm8350_reg_write(wm8350, WM8350_LOUT2_VOLUME, 0);1517 wm8350_reg_write(wm8350, WM8350_ROUT2_VOLUME, 0);1518 1519 /* Latch VU bits & mute */1520 wm8350_set_bits(wm8350, WM8350_LOUT1_VOLUME,1521 WM8350_OUT1_VU | WM8350_OUT1L_MUTE);1522 wm8350_set_bits(wm8350, WM8350_LOUT2_VOLUME,1523 WM8350_OUT2_VU | WM8350_OUT2L_MUTE);1524 wm8350_set_bits(wm8350, WM8350_ROUT1_VOLUME,1525 WM8350_OUT1_VU | WM8350_OUT1R_MUTE);1526 wm8350_set_bits(wm8350, WM8350_ROUT2_VOLUME,1527 WM8350_OUT2_VU | WM8350_OUT2R_MUTE);1528 1529 /* Make sure AIF tristating is disabled by default */1530 wm8350_clear_bits(wm8350, WM8350_AI_FORMATING, WM8350_AIF_TRI);1531 1532 /* Make sure we've got a sane companding setup too */1533 wm8350_clear_bits(wm8350, WM8350_ADC_DAC_COMP,1534 WM8350_DAC_COMP | WM8350_LOOPBACK);1535 1536 /* Make sure jack detect is disabled to start off with */1537 wm8350_clear_bits(wm8350, WM8350_JACK_DETECT,1538 WM8350_JDL_ENA | WM8350_JDR_ENA);1539 1540 ret = wm8350_register_irq(wm8350, WM8350_IRQ_CODEC_JCK_DET_L,1541 wm8350_hpl_jack_handler, 0, "Left jack detect",1542 priv);1543 if (ret != 0)1544 goto err;1545 1546 ret = wm8350_register_irq(wm8350, WM8350_IRQ_CODEC_JCK_DET_R,1547 wm8350_hpr_jack_handler, 0, "Right jack detect",1548 priv);1549 if (ret != 0)1550 goto free_jck_det_l;1551 1552 ret = wm8350_register_irq(wm8350, WM8350_IRQ_CODEC_MICSCD,1553 wm8350_mic_handler, 0, "Microphone short", priv);1554 if (ret != 0)1555 goto free_jck_det_r;1556 1557 ret = wm8350_register_irq(wm8350, WM8350_IRQ_CODEC_MICD,1558 wm8350_mic_handler, 0, "Microphone detect", priv);1559 if (ret != 0)1560 goto free_micscd;1561 1562 return 0;1563 1564free_micscd:1565 wm8350_free_irq(wm8350, WM8350_IRQ_CODEC_MICSCD, priv);1566free_jck_det_r:1567 wm8350_free_irq(wm8350, WM8350_IRQ_CODEC_JCK_DET_R, priv);1568free_jck_det_l:1569 wm8350_free_irq(wm8350, WM8350_IRQ_CODEC_JCK_DET_L, priv);1570err:1571 return ret;1572}1573 1574static void wm8350_component_remove(struct snd_soc_component *component)1575{1576 struct wm8350_data *priv = snd_soc_component_get_drvdata(component);1577 struct wm8350 *wm8350 = dev_get_platdata(component->dev);1578 1579 wm8350_clear_bits(wm8350, WM8350_JACK_DETECT,1580 WM8350_JDL_ENA | WM8350_JDR_ENA);1581 wm8350_clear_bits(wm8350, WM8350_POWER_MGMT_4, WM8350_TOCLK_ENA);1582 1583 wm8350_free_irq(wm8350, WM8350_IRQ_CODEC_MICD, priv);1584 wm8350_free_irq(wm8350, WM8350_IRQ_CODEC_MICSCD, priv);1585 wm8350_free_irq(wm8350, WM8350_IRQ_CODEC_JCK_DET_L, priv);1586 wm8350_free_irq(wm8350, WM8350_IRQ_CODEC_JCK_DET_R, priv);1587 1588 priv->hpl.jack = NULL;1589 priv->hpr.jack = NULL;1590 priv->mic.jack = NULL;1591 1592 cancel_delayed_work_sync(&priv->hpl.work);1593 cancel_delayed_work_sync(&priv->hpr.work);1594 1595 /* if there was any work waiting then we run it now and1596 * wait for its completion */1597 flush_delayed_work(&priv->pga_work);1598 1599 wm8350_clear_bits(wm8350, WM8350_POWER_MGMT_5, WM8350_CODEC_ENA);1600}1601 1602static const struct snd_soc_component_driver soc_component_dev_wm8350 = {1603 .probe = wm8350_component_probe,1604 .remove = wm8350_component_remove,1605 .set_bias_level = wm8350_set_bias_level,1606 .controls = wm8350_snd_controls,1607 .num_controls = ARRAY_SIZE(wm8350_snd_controls),1608 .dapm_widgets = wm8350_dapm_widgets,1609 .num_dapm_widgets = ARRAY_SIZE(wm8350_dapm_widgets),1610 .dapm_routes = wm8350_dapm_routes,1611 .num_dapm_routes = ARRAY_SIZE(wm8350_dapm_routes),1612 .suspend_bias_off = 1,1613 .idle_bias_on = 1,1614 .use_pmdown_time = 1,1615 .endianness = 1,1616};1617 1618static int wm8350_probe(struct platform_device *pdev)1619{1620 return devm_snd_soc_register_component(&pdev->dev,1621 &soc_component_dev_wm8350,1622 &wm8350_dai, 1);1623}1624 1625static struct platform_driver wm8350_codec_driver = {1626 .driver = {1627 .name = "wm8350-codec",1628 },1629 .probe = wm8350_probe,1630};1631 1632module_platform_driver(wm8350_codec_driver);1633 1634MODULE_DESCRIPTION("ASoC WM8350 driver");1635MODULE_AUTHOR("Liam Girdwood");1636MODULE_LICENSE("GPL");1637MODULE_ALIAS("platform:wm8350-codec");1638