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1/* SPDX-License-Identifier: GPL-2.0-or-later */2/*3 * wm8753.h -- audio driver for WM87534 *5 * Copyright 2003 Wolfson Microelectronics PLC.6 * Author: Liam Girdwood <lrg@slimlogic.co.uk>7 */8 9#ifndef _WM8753_H10#define _WM8753_H11 12/* WM8753 register space */13 14#define WM8753_DAC 0x0115#define WM8753_ADC 0x0216#define WM8753_PCM 0x0317#define WM8753_HIFI 0x0418#define WM8753_IOCTL 0x0519#define WM8753_SRATE1 0x0620#define WM8753_SRATE2 0x0721#define WM8753_LDAC 0x0822#define WM8753_RDAC 0x0923#define WM8753_BASS 0x0a24#define WM8753_TREBLE 0x0b25#define WM8753_ALC1 0x0c26#define WM8753_ALC2 0x0d27#define WM8753_ALC3 0x0e28#define WM8753_NGATE 0x0f29#define WM8753_LADC 0x1030#define WM8753_RADC 0x1131#define WM8753_ADCTL1 0x1232#define WM8753_3D 0x1333#define WM8753_PWR1 0x1434#define WM8753_PWR2 0x1535#define WM8753_PWR3 0x1636#define WM8753_PWR4 0x1737#define WM8753_ID 0x1838#define WM8753_INTPOL 0x1939#define WM8753_INTEN 0x1a40#define WM8753_GPIO1 0x1b41#define WM8753_GPIO2 0x1c42#define WM8753_RESET 0x1f43#define WM8753_RECMIX1 0x2044#define WM8753_RECMIX2 0x2145#define WM8753_LOUTM1 0x2246#define WM8753_LOUTM2 0x2347#define WM8753_ROUTM1 0x2448#define WM8753_ROUTM2 0x2549#define WM8753_MOUTM1 0x2650#define WM8753_MOUTM2 0x2751#define WM8753_LOUT1V 0x2852#define WM8753_ROUT1V 0x2953#define WM8753_LOUT2V 0x2a54#define WM8753_ROUT2V 0x2b55#define WM8753_MOUTV 0x2c56#define WM8753_OUTCTL 0x2d57#define WM8753_ADCIN 0x2e58#define WM8753_INCTL1 0x2f59#define WM8753_INCTL2 0x3060#define WM8753_LINVOL 0x3161#define WM8753_RINVOL 0x3262#define WM8753_MICBIAS 0x3363#define WM8753_CLOCK 0x3464#define WM8753_PLL1CTL1 0x3565#define WM8753_PLL1CTL2 0x3666#define WM8753_PLL1CTL3 0x3767#define WM8753_PLL1CTL4 0x3868#define WM8753_PLL2CTL1 0x3969#define WM8753_PLL2CTL2 0x3a70#define WM8753_PLL2CTL3 0x3b71#define WM8753_PLL2CTL4 0x3c72#define WM8753_BIASCTL 0x3d73#define WM8753_ADCTL2 0x3f74 75#define WM8753_PLL1 076#define WM8753_PLL2 177 78/* clock inputs */79#define WM8753_MCLK 080#define WM8753_PCMCLK 181 82/* clock divider id's */83#define WM8753_PCMDIV 084#define WM8753_BCLKDIV 185#define WM8753_VXCLKDIV 286 87/* PCM clock dividers */88#define WM8753_PCM_DIV_1 (0 << 6)89#define WM8753_PCM_DIV_3 (2 << 6)90#define WM8753_PCM_DIV_5_5 (3 << 6)91#define WM8753_PCM_DIV_2 (4 << 6)92#define WM8753_PCM_DIV_4 (5 << 6)93#define WM8753_PCM_DIV_6 (6 << 6)94#define WM8753_PCM_DIV_8 (7 << 6)95 96/* BCLK clock dividers */97#define WM8753_BCLK_DIV_1 (0 << 3)98#define WM8753_BCLK_DIV_2 (1 << 3)99#define WM8753_BCLK_DIV_4 (2 << 3)100#define WM8753_BCLK_DIV_8 (3 << 3)101#define WM8753_BCLK_DIV_16 (4 << 3)102 103/* VXCLK clock dividers */104#define WM8753_VXCLK_DIV_1 (0 << 6)105#define WM8753_VXCLK_DIV_2 (1 << 6)106#define WM8753_VXCLK_DIV_4 (2 << 6)107#define WM8753_VXCLK_DIV_8 (3 << 6)108#define WM8753_VXCLK_DIV_16 (4 << 6)109 110#endif111