2222 lines · c
1// SPDX-License-Identifier: GPL-2.0-only2/*3 * wm8903.c -- WM8903 ALSA SoC Audio driver4 *5 * Copyright 2008-12 Wolfson Microelectronics6 * Copyright 2011-2012 NVIDIA, Inc.7 *8 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>9 *10 * TODO:11 * - TDM mode configuration.12 */13 14#include <linux/module.h>15#include <linux/moduleparam.h>16#include <linux/init.h>17#include <linux/completion.h>18#include <linux/delay.h>19#include <linux/gpio/driver.h>20#include <linux/pm.h>21#include <linux/i2c.h>22#include <linux/regmap.h>23#include <linux/regulator/consumer.h>24#include <linux/slab.h>25#include <linux/irq.h>26#include <linux/mutex.h>27#include <sound/core.h>28#include <sound/jack.h>29#include <sound/pcm.h>30#include <sound/pcm_params.h>31#include <sound/tlv.h>32#include <sound/soc.h>33#include <sound/initval.h>34#include <sound/wm8903.h>35#include <trace/events/asoc.h>36 37#include "wm8903.h"38 39/* Register defaults at reset */40static const struct reg_default wm8903_reg_defaults[] = {41 { 4, 0x0018 }, /* R4 - Bias Control 0 */42 { 5, 0x0000 }, /* R5 - VMID Control 0 */43 { 6, 0x0000 }, /* R6 - Mic Bias Control 0 */44 { 8, 0x0001 }, /* R8 - Analogue DAC 0 */45 { 10, 0x0001 }, /* R10 - Analogue ADC 0 */46 { 12, 0x0000 }, /* R12 - Power Management 0 */47 { 13, 0x0000 }, /* R13 - Power Management 1 */48 { 14, 0x0000 }, /* R14 - Power Management 2 */49 { 15, 0x0000 }, /* R15 - Power Management 3 */50 { 16, 0x0000 }, /* R16 - Power Management 4 */51 { 17, 0x0000 }, /* R17 - Power Management 5 */52 { 18, 0x0000 }, /* R18 - Power Management 6 */53 { 20, 0x0400 }, /* R20 - Clock Rates 0 */54 { 21, 0x0D07 }, /* R21 - Clock Rates 1 */55 { 22, 0x0000 }, /* R22 - Clock Rates 2 */56 { 24, 0x0050 }, /* R24 - Audio Interface 0 */57 { 25, 0x0242 }, /* R25 - Audio Interface 1 */58 { 26, 0x0008 }, /* R26 - Audio Interface 2 */59 { 27, 0x0022 }, /* R27 - Audio Interface 3 */60 { 30, 0x00C0 }, /* R30 - DAC Digital Volume Left */61 { 31, 0x00C0 }, /* R31 - DAC Digital Volume Right */62 { 32, 0x0000 }, /* R32 - DAC Digital 0 */63 { 33, 0x0000 }, /* R33 - DAC Digital 1 */64 { 36, 0x00C0 }, /* R36 - ADC Digital Volume Left */65 { 37, 0x00C0 }, /* R37 - ADC Digital Volume Right */66 { 38, 0x0000 }, /* R38 - ADC Digital 0 */67 { 39, 0x0073 }, /* R39 - Digital Microphone 0 */68 { 40, 0x09BF }, /* R40 - DRC 0 */69 { 41, 0x3241 }, /* R41 - DRC 1 */70 { 42, 0x0020 }, /* R42 - DRC 2 */71 { 43, 0x0000 }, /* R43 - DRC 3 */72 { 44, 0x0085 }, /* R44 - Analogue Left Input 0 */73 { 45, 0x0085 }, /* R45 - Analogue Right Input 0 */74 { 46, 0x0044 }, /* R46 - Analogue Left Input 1 */75 { 47, 0x0044 }, /* R47 - Analogue Right Input 1 */76 { 50, 0x0008 }, /* R50 - Analogue Left Mix 0 */77 { 51, 0x0004 }, /* R51 - Analogue Right Mix 0 */78 { 52, 0x0000 }, /* R52 - Analogue Spk Mix Left 0 */79 { 53, 0x0000 }, /* R53 - Analogue Spk Mix Left 1 */80 { 54, 0x0000 }, /* R54 - Analogue Spk Mix Right 0 */81 { 55, 0x0000 }, /* R55 - Analogue Spk Mix Right 1 */82 { 57, 0x002D }, /* R57 - Analogue OUT1 Left */83 { 58, 0x002D }, /* R58 - Analogue OUT1 Right */84 { 59, 0x0039 }, /* R59 - Analogue OUT2 Left */85 { 60, 0x0039 }, /* R60 - Analogue OUT2 Right */86 { 62, 0x0139 }, /* R62 - Analogue OUT3 Left */87 { 63, 0x0139 }, /* R63 - Analogue OUT3 Right */88 { 64, 0x0000 }, /* R65 - Analogue SPK Output Control 0 */89 { 67, 0x0010 }, /* R67 - DC Servo 0 */90 { 69, 0x00A4 }, /* R69 - DC Servo 2 */91 { 90, 0x0000 }, /* R90 - Analogue HP 0 */92 { 94, 0x0000 }, /* R94 - Analogue Lineout 0 */93 { 98, 0x0000 }, /* R98 - Charge Pump 0 */94 { 104, 0x0000 }, /* R104 - Class W 0 */95 { 108, 0x0000 }, /* R108 - Write Sequencer 0 */96 { 109, 0x0000 }, /* R109 - Write Sequencer 1 */97 { 110, 0x0000 }, /* R110 - Write Sequencer 2 */98 { 111, 0x0000 }, /* R111 - Write Sequencer 3 */99 { 112, 0x0000 }, /* R112 - Write Sequencer 4 */100 { 114, 0x0000 }, /* R114 - Control Interface */101 { 116, 0x00A8 }, /* R116 - GPIO Control 1 */102 { 117, 0x00A8 }, /* R117 - GPIO Control 2 */103 { 118, 0x00A8 }, /* R118 - GPIO Control 3 */104 { 119, 0x0220 }, /* R119 - GPIO Control 4 */105 { 120, 0x01A0 }, /* R120 - GPIO Control 5 */106 { 122, 0xFFFF }, /* R122 - Interrupt Status 1 Mask */107 { 123, 0x0000 }, /* R123 - Interrupt Polarity 1 */108 { 126, 0x0000 }, /* R126 - Interrupt Control */109 { 129, 0x0000 }, /* R129 - Control Interface Test 1 */110 { 149, 0x6810 }, /* R149 - Charge Pump Test 1 */111 { 164, 0x0028 }, /* R164 - Clock Rate Test 4 */112 { 172, 0x0000 }, /* R172 - Analogue Output Bias 0 */113};114 115#define WM8903_NUM_SUPPLIES 4116static const char *wm8903_supply_names[WM8903_NUM_SUPPLIES] = {117 "AVDD",118 "CPVDD",119 "DBVDD",120 "DCVDD",121};122 123struct wm8903_priv {124 struct wm8903_platform_data *pdata;125 struct device *dev;126 struct regmap *regmap;127 struct regulator_bulk_data supplies[WM8903_NUM_SUPPLIES];128 129 int sysclk;130 int irq;131 132 struct mutex lock;133 int fs;134 int deemph;135 136 int dcs_pending;137 int dcs_cache[4];138 139 /* Reference count */140 int class_w_users;141 142 struct snd_soc_jack *mic_jack;143 int mic_det;144 int mic_short;145 int mic_last_report;146 int mic_delay;147 148#ifdef CONFIG_GPIOLIB149 struct gpio_chip gpio_chip;150#endif151};152 153static bool wm8903_readable_register(struct device *dev, unsigned int reg)154{155 switch (reg) {156 case WM8903_SW_RESET_AND_ID:157 case WM8903_REVISION_NUMBER:158 case WM8903_BIAS_CONTROL_0:159 case WM8903_VMID_CONTROL_0:160 case WM8903_MIC_BIAS_CONTROL_0:161 case WM8903_ANALOGUE_DAC_0:162 case WM8903_ANALOGUE_ADC_0:163 case WM8903_POWER_MANAGEMENT_0:164 case WM8903_POWER_MANAGEMENT_1:165 case WM8903_POWER_MANAGEMENT_2:166 case WM8903_POWER_MANAGEMENT_3:167 case WM8903_POWER_MANAGEMENT_4:168 case WM8903_POWER_MANAGEMENT_5:169 case WM8903_POWER_MANAGEMENT_6:170 case WM8903_CLOCK_RATES_0:171 case WM8903_CLOCK_RATES_1:172 case WM8903_CLOCK_RATES_2:173 case WM8903_AUDIO_INTERFACE_0:174 case WM8903_AUDIO_INTERFACE_1:175 case WM8903_AUDIO_INTERFACE_2:176 case WM8903_AUDIO_INTERFACE_3:177 case WM8903_DAC_DIGITAL_VOLUME_LEFT:178 case WM8903_DAC_DIGITAL_VOLUME_RIGHT:179 case WM8903_DAC_DIGITAL_0:180 case WM8903_DAC_DIGITAL_1:181 case WM8903_ADC_DIGITAL_VOLUME_LEFT:182 case WM8903_ADC_DIGITAL_VOLUME_RIGHT:183 case WM8903_ADC_DIGITAL_0:184 case WM8903_DIGITAL_MICROPHONE_0:185 case WM8903_DRC_0:186 case WM8903_DRC_1:187 case WM8903_DRC_2:188 case WM8903_DRC_3:189 case WM8903_ANALOGUE_LEFT_INPUT_0:190 case WM8903_ANALOGUE_RIGHT_INPUT_0:191 case WM8903_ANALOGUE_LEFT_INPUT_1:192 case WM8903_ANALOGUE_RIGHT_INPUT_1:193 case WM8903_ANALOGUE_LEFT_MIX_0:194 case WM8903_ANALOGUE_RIGHT_MIX_0:195 case WM8903_ANALOGUE_SPK_MIX_LEFT_0:196 case WM8903_ANALOGUE_SPK_MIX_LEFT_1:197 case WM8903_ANALOGUE_SPK_MIX_RIGHT_0:198 case WM8903_ANALOGUE_SPK_MIX_RIGHT_1:199 case WM8903_ANALOGUE_OUT1_LEFT:200 case WM8903_ANALOGUE_OUT1_RIGHT:201 case WM8903_ANALOGUE_OUT2_LEFT:202 case WM8903_ANALOGUE_OUT2_RIGHT:203 case WM8903_ANALOGUE_OUT3_LEFT:204 case WM8903_ANALOGUE_OUT3_RIGHT:205 case WM8903_ANALOGUE_SPK_OUTPUT_CONTROL_0:206 case WM8903_DC_SERVO_0:207 case WM8903_DC_SERVO_2:208 case WM8903_DC_SERVO_READBACK_1:209 case WM8903_DC_SERVO_READBACK_2:210 case WM8903_DC_SERVO_READBACK_3:211 case WM8903_DC_SERVO_READBACK_4:212 case WM8903_ANALOGUE_HP_0:213 case WM8903_ANALOGUE_LINEOUT_0:214 case WM8903_CHARGE_PUMP_0:215 case WM8903_CLASS_W_0:216 case WM8903_WRITE_SEQUENCER_0:217 case WM8903_WRITE_SEQUENCER_1:218 case WM8903_WRITE_SEQUENCER_2:219 case WM8903_WRITE_SEQUENCER_3:220 case WM8903_WRITE_SEQUENCER_4:221 case WM8903_CONTROL_INTERFACE:222 case WM8903_GPIO_CONTROL_1:223 case WM8903_GPIO_CONTROL_2:224 case WM8903_GPIO_CONTROL_3:225 case WM8903_GPIO_CONTROL_4:226 case WM8903_GPIO_CONTROL_5:227 case WM8903_INTERRUPT_STATUS_1:228 case WM8903_INTERRUPT_STATUS_1_MASK:229 case WM8903_INTERRUPT_POLARITY_1:230 case WM8903_INTERRUPT_CONTROL:231 case WM8903_CLOCK_RATE_TEST_4:232 case WM8903_ANALOGUE_OUTPUT_BIAS_0:233 return true;234 default:235 return false;236 }237}238 239static bool wm8903_volatile_register(struct device *dev, unsigned int reg)240{241 switch (reg) {242 case WM8903_SW_RESET_AND_ID:243 case WM8903_REVISION_NUMBER:244 case WM8903_INTERRUPT_STATUS_1:245 case WM8903_WRITE_SEQUENCER_4:246 case WM8903_DC_SERVO_READBACK_1:247 case WM8903_DC_SERVO_READBACK_2:248 case WM8903_DC_SERVO_READBACK_3:249 case WM8903_DC_SERVO_READBACK_4:250 return true;251 252 default:253 return false;254 }255}256 257static int wm8903_cp_event(struct snd_soc_dapm_widget *w,258 struct snd_kcontrol *kcontrol, int event)259{260 WARN_ON(event != SND_SOC_DAPM_POST_PMU);261 mdelay(4);262 263 return 0;264}265 266static int wm8903_dcs_event(struct snd_soc_dapm_widget *w,267 struct snd_kcontrol *kcontrol, int event)268{269 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);270 struct wm8903_priv *wm8903 = snd_soc_component_get_drvdata(component);271 272 switch (event) {273 case SND_SOC_DAPM_POST_PMU:274 wm8903->dcs_pending |= 1 << w->shift;275 break;276 case SND_SOC_DAPM_PRE_PMD:277 snd_soc_component_update_bits(component, WM8903_DC_SERVO_0,278 1 << w->shift, 0);279 break;280 }281 282 return 0;283}284 285#define WM8903_DCS_MODE_WRITE_STOP 0286#define WM8903_DCS_MODE_START_STOP 2287 288static void wm8903_seq_notifier(struct snd_soc_component *component,289 enum snd_soc_dapm_type event, int subseq)290{291 struct wm8903_priv *wm8903 = snd_soc_component_get_drvdata(component);292 int dcs_mode = WM8903_DCS_MODE_WRITE_STOP;293 int i, val;294 295 /* Complete any pending DC servo starts */296 if (wm8903->dcs_pending) {297 dev_dbg(component->dev, "Starting DC servo for %x\n",298 wm8903->dcs_pending);299 300 /* If we've no cached values then we need to do startup */301 for (i = 0; i < ARRAY_SIZE(wm8903->dcs_cache); i++) {302 if (!(wm8903->dcs_pending & (1 << i)))303 continue;304 305 if (wm8903->dcs_cache[i]) {306 dev_dbg(component->dev,307 "Restore DC servo %d value %x\n",308 3 - i, wm8903->dcs_cache[i]);309 310 snd_soc_component_write(component, WM8903_DC_SERVO_4 + i,311 wm8903->dcs_cache[i] & 0xff);312 } else {313 dev_dbg(component->dev,314 "Calibrate DC servo %d\n", 3 - i);315 dcs_mode = WM8903_DCS_MODE_START_STOP;316 }317 }318 319 /* Don't trust the cache for analogue */320 if (wm8903->class_w_users)321 dcs_mode = WM8903_DCS_MODE_START_STOP;322 323 snd_soc_component_update_bits(component, WM8903_DC_SERVO_2,324 WM8903_DCS_MODE_MASK, dcs_mode);325 326 snd_soc_component_update_bits(component, WM8903_DC_SERVO_0,327 WM8903_DCS_ENA_MASK, wm8903->dcs_pending);328 329 switch (dcs_mode) {330 case WM8903_DCS_MODE_WRITE_STOP:331 break;332 333 case WM8903_DCS_MODE_START_STOP:334 msleep(270);335 336 /* Cache the measured offsets for digital */337 if (wm8903->class_w_users)338 break;339 340 for (i = 0; i < ARRAY_SIZE(wm8903->dcs_cache); i++) {341 if (!(wm8903->dcs_pending & (1 << i)))342 continue;343 344 val = snd_soc_component_read(component,345 WM8903_DC_SERVO_READBACK_1 + i);346 dev_dbg(component->dev, "DC servo %d: %x\n",347 3 - i, val);348 wm8903->dcs_cache[i] = val;349 }350 break;351 352 default:353 pr_warn("DCS mode %d delay not set\n", dcs_mode);354 break;355 }356 357 wm8903->dcs_pending = 0;358 }359}360 361/*362 * When used with DAC outputs only the WM8903 charge pump supports363 * operation in class W mode, providing very low power consumption364 * when used with digital sources. Enable and disable this mode365 * automatically depending on the mixer configuration.366 *367 * All the relevant controls are simple switches.368 */369static int wm8903_class_w_put(struct snd_kcontrol *kcontrol,370 struct snd_ctl_elem_value *ucontrol)371{372 struct snd_soc_component *component = snd_soc_dapm_kcontrol_component(kcontrol);373 struct wm8903_priv *wm8903 = snd_soc_component_get_drvdata(component);374 u16 reg;375 int ret;376 377 reg = snd_soc_component_read(component, WM8903_CLASS_W_0);378 379 /* Turn it off if we're about to enable bypass */380 if (ucontrol->value.integer.value[0]) {381 if (wm8903->class_w_users == 0) {382 dev_dbg(component->dev, "Disabling Class W\n");383 snd_soc_component_write(component, WM8903_CLASS_W_0, reg &384 ~(WM8903_CP_DYN_FREQ | WM8903_CP_DYN_V));385 }386 wm8903->class_w_users++;387 }388 389 /* Implement the change */390 ret = snd_soc_dapm_put_volsw(kcontrol, ucontrol);391 392 /* If we've just disabled the last bypass path turn Class W on */393 if (!ucontrol->value.integer.value[0]) {394 if (wm8903->class_w_users == 1) {395 dev_dbg(component->dev, "Enabling Class W\n");396 snd_soc_component_write(component, WM8903_CLASS_W_0, reg |397 WM8903_CP_DYN_FREQ | WM8903_CP_DYN_V);398 }399 wm8903->class_w_users--;400 }401 402 dev_dbg(component->dev, "Bypass use count now %d\n",403 wm8903->class_w_users);404 405 return ret;406}407 408#define SOC_DAPM_SINGLE_W(xname, reg, shift, max, invert) \409 SOC_SINGLE_EXT(xname, reg, shift, max, invert, \410 snd_soc_dapm_get_volsw, wm8903_class_w_put)411 412 413static int wm8903_deemph[] = { 0, 32000, 44100, 48000 };414 415static int wm8903_set_deemph(struct snd_soc_component *component)416{417 struct wm8903_priv *wm8903 = snd_soc_component_get_drvdata(component);418 int val, i, best;419 420 /* If we're using deemphasis select the nearest available sample421 * rate.422 */423 if (wm8903->deemph) {424 best = 1;425 for (i = 2; i < ARRAY_SIZE(wm8903_deemph); i++) {426 if (abs(wm8903_deemph[i] - wm8903->fs) <427 abs(wm8903_deemph[best] - wm8903->fs))428 best = i;429 }430 431 val = best << WM8903_DEEMPH_SHIFT;432 } else {433 best = 0;434 val = 0;435 }436 437 dev_dbg(component->dev, "Set deemphasis %d (%dHz)\n",438 best, wm8903_deemph[best]);439 440 return snd_soc_component_update_bits(component, WM8903_DAC_DIGITAL_1,441 WM8903_DEEMPH_MASK, val);442}443 444static int wm8903_get_deemph(struct snd_kcontrol *kcontrol,445 struct snd_ctl_elem_value *ucontrol)446{447 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);448 struct wm8903_priv *wm8903 = snd_soc_component_get_drvdata(component);449 450 ucontrol->value.integer.value[0] = wm8903->deemph;451 452 return 0;453}454 455static int wm8903_put_deemph(struct snd_kcontrol *kcontrol,456 struct snd_ctl_elem_value *ucontrol)457{458 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);459 struct wm8903_priv *wm8903 = snd_soc_component_get_drvdata(component);460 unsigned int deemph = ucontrol->value.integer.value[0];461 int ret = 0;462 463 if (deemph > 1)464 return -EINVAL;465 466 mutex_lock(&wm8903->lock);467 if (wm8903->deemph != deemph) {468 wm8903->deemph = deemph;469 470 wm8903_set_deemph(component);471 472 ret = 1;473 }474 mutex_unlock(&wm8903->lock);475 476 return ret;477}478 479/* ALSA can only do steps of .01dB */480static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);481 482static const DECLARE_TLV_DB_SCALE(dac_boost_tlv, 0, 600, 0);483 484static const DECLARE_TLV_DB_SCALE(digital_sidetone_tlv, -3600, 300, 0);485static const DECLARE_TLV_DB_SCALE(out_tlv, -5700, 100, 0);486 487static const DECLARE_TLV_DB_SCALE(drc_tlv_thresh, 0, 75, 0);488static const DECLARE_TLV_DB_SCALE(drc_tlv_amp, -2250, 75, 0);489static const DECLARE_TLV_DB_SCALE(drc_tlv_min, 0, 600, 0);490static const DECLARE_TLV_DB_SCALE(drc_tlv_max, 1200, 600, 0);491static const DECLARE_TLV_DB_SCALE(drc_tlv_startup, -300, 50, 0);492 493static const char *hpf_mode_text[] = {494 "Hi-fi", "Voice 1", "Voice 2", "Voice 3"495};496 497static SOC_ENUM_SINGLE_DECL(hpf_mode,498 WM8903_ADC_DIGITAL_0, 5, hpf_mode_text);499 500static const char *osr_text[] = {501 "Low power", "High performance"502};503 504static SOC_ENUM_SINGLE_DECL(adc_osr,505 WM8903_ANALOGUE_ADC_0, 0, osr_text);506 507static SOC_ENUM_SINGLE_DECL(dac_osr,508 WM8903_DAC_DIGITAL_1, 0, osr_text);509 510static const char *drc_slope_text[] = {511 "1", "1/2", "1/4", "1/8", "1/16", "0"512};513 514static SOC_ENUM_SINGLE_DECL(drc_slope_r0,515 WM8903_DRC_2, 3, drc_slope_text);516 517static SOC_ENUM_SINGLE_DECL(drc_slope_r1,518 WM8903_DRC_2, 0, drc_slope_text);519 520static const char *drc_attack_text[] = {521 "instantaneous",522 "363us", "762us", "1.45ms", "2.9ms", "5.8ms", "11.6ms", "23.2ms",523 "46.4ms", "92.8ms", "185.6ms"524};525 526static SOC_ENUM_SINGLE_DECL(drc_attack,527 WM8903_DRC_1, 12, drc_attack_text);528 529static const char *drc_decay_text[] = {530 "186ms", "372ms", "743ms", "1.49s", "2.97s", "5.94s", "11.89s",531 "23.87s", "47.56s"532};533 534static SOC_ENUM_SINGLE_DECL(drc_decay,535 WM8903_DRC_1, 8, drc_decay_text);536 537static const char *drc_ff_delay_text[] = {538 "5 samples", "9 samples"539};540 541static SOC_ENUM_SINGLE_DECL(drc_ff_delay,542 WM8903_DRC_0, 5, drc_ff_delay_text);543 544static const char *drc_qr_decay_text[] = {545 "0.725ms", "1.45ms", "5.8ms"546};547 548static SOC_ENUM_SINGLE_DECL(drc_qr_decay,549 WM8903_DRC_1, 4, drc_qr_decay_text);550 551static const char *drc_smoothing_text[] = {552 "Low", "Medium", "High"553};554 555static SOC_ENUM_SINGLE_DECL(drc_smoothing,556 WM8903_DRC_0, 11, drc_smoothing_text);557 558static const char *soft_mute_text[] = {559 "Fast (fs/2)", "Slow (fs/32)"560};561 562static SOC_ENUM_SINGLE_DECL(soft_mute,563 WM8903_DAC_DIGITAL_1, 10, soft_mute_text);564 565static const char *mute_mode_text[] = {566 "Hard", "Soft"567};568 569static SOC_ENUM_SINGLE_DECL(mute_mode,570 WM8903_DAC_DIGITAL_1, 9, mute_mode_text);571 572static const char *companding_text[] = {573 "ulaw", "alaw"574};575 576static SOC_ENUM_SINGLE_DECL(dac_companding,577 WM8903_AUDIO_INTERFACE_0, 0, companding_text);578 579static SOC_ENUM_SINGLE_DECL(adc_companding,580 WM8903_AUDIO_INTERFACE_0, 2, companding_text);581 582static const char *input_mode_text[] = {583 "Single-Ended", "Differential Line", "Differential Mic"584};585 586static SOC_ENUM_SINGLE_DECL(linput_mode_enum,587 WM8903_ANALOGUE_LEFT_INPUT_1, 0, input_mode_text);588 589static SOC_ENUM_SINGLE_DECL(rinput_mode_enum,590 WM8903_ANALOGUE_RIGHT_INPUT_1, 0, input_mode_text);591 592static const char *linput_mux_text[] = {593 "IN1L", "IN2L", "IN3L"594};595 596static SOC_ENUM_SINGLE_DECL(linput_enum,597 WM8903_ANALOGUE_LEFT_INPUT_1, 2, linput_mux_text);598 599static SOC_ENUM_SINGLE_DECL(linput_inv_enum,600 WM8903_ANALOGUE_LEFT_INPUT_1, 4, linput_mux_text);601 602static const char *rinput_mux_text[] = {603 "IN1R", "IN2R", "IN3R"604};605 606static SOC_ENUM_SINGLE_DECL(rinput_enum,607 WM8903_ANALOGUE_RIGHT_INPUT_1, 2, rinput_mux_text);608 609static SOC_ENUM_SINGLE_DECL(rinput_inv_enum,610 WM8903_ANALOGUE_RIGHT_INPUT_1, 4, rinput_mux_text);611 612 613static const char *sidetone_text[] = {614 "None", "Left", "Right"615};616 617static SOC_ENUM_SINGLE_DECL(lsidetone_enum,618 WM8903_DAC_DIGITAL_0, 2, sidetone_text);619 620static SOC_ENUM_SINGLE_DECL(rsidetone_enum,621 WM8903_DAC_DIGITAL_0, 0, sidetone_text);622 623static const char *adcinput_text[] = {624 "ADC", "DMIC"625};626 627static SOC_ENUM_SINGLE_DECL(adcinput_enum,628 WM8903_CLOCK_RATE_TEST_4, 9, adcinput_text);629 630static const char *aif_text[] = {631 "Left", "Right"632};633 634static SOC_ENUM_SINGLE_DECL(lcapture_enum,635 WM8903_AUDIO_INTERFACE_0, 7, aif_text);636 637static SOC_ENUM_SINGLE_DECL(rcapture_enum,638 WM8903_AUDIO_INTERFACE_0, 6, aif_text);639 640static SOC_ENUM_SINGLE_DECL(lplay_enum,641 WM8903_AUDIO_INTERFACE_0, 5, aif_text);642 643static SOC_ENUM_SINGLE_DECL(rplay_enum,644 WM8903_AUDIO_INTERFACE_0, 4, aif_text);645 646static const struct snd_kcontrol_new wm8903_snd_controls[] = {647 648/* Input PGAs - No TLV since the scale depends on PGA mode */649SOC_SINGLE("Left Input PGA Switch", WM8903_ANALOGUE_LEFT_INPUT_0,650 7, 1, 1),651SOC_SINGLE("Left Input PGA Volume", WM8903_ANALOGUE_LEFT_INPUT_0,652 0, 31, 0),653SOC_SINGLE("Left Input PGA Common Mode Switch", WM8903_ANALOGUE_LEFT_INPUT_1,654 6, 1, 0),655 656SOC_SINGLE("Right Input PGA Switch", WM8903_ANALOGUE_RIGHT_INPUT_0,657 7, 1, 1),658SOC_SINGLE("Right Input PGA Volume", WM8903_ANALOGUE_RIGHT_INPUT_0,659 0, 31, 0),660SOC_SINGLE("Right Input PGA Common Mode Switch", WM8903_ANALOGUE_RIGHT_INPUT_1,661 6, 1, 0),662 663/* ADCs */664SOC_ENUM("ADC OSR", adc_osr),665SOC_SINGLE("HPF Switch", WM8903_ADC_DIGITAL_0, 4, 1, 0),666SOC_ENUM("HPF Mode", hpf_mode),667SOC_SINGLE("DRC Switch", WM8903_DRC_0, 15, 1, 0),668SOC_ENUM("DRC Compressor Slope R0", drc_slope_r0),669SOC_ENUM("DRC Compressor Slope R1", drc_slope_r1),670SOC_SINGLE_TLV("DRC Compressor Threshold Volume", WM8903_DRC_3, 5, 124, 1,671 drc_tlv_thresh),672SOC_SINGLE_TLV("DRC Volume", WM8903_DRC_3, 0, 30, 1, drc_tlv_amp),673SOC_SINGLE_TLV("DRC Minimum Gain Volume", WM8903_DRC_1, 2, 3, 1, drc_tlv_min),674SOC_SINGLE_TLV("DRC Maximum Gain Volume", WM8903_DRC_1, 0, 3, 0, drc_tlv_max),675SOC_ENUM("DRC Attack Rate", drc_attack),676SOC_ENUM("DRC Decay Rate", drc_decay),677SOC_ENUM("DRC FF Delay", drc_ff_delay),678SOC_SINGLE("DRC Anticlip Switch", WM8903_DRC_0, 1, 1, 0),679SOC_SINGLE("DRC QR Switch", WM8903_DRC_0, 2, 1, 0),680SOC_SINGLE_TLV("DRC QR Threshold Volume", WM8903_DRC_0, 6, 3, 0, drc_tlv_max),681SOC_ENUM("DRC QR Decay Rate", drc_qr_decay),682SOC_SINGLE("DRC Smoothing Switch", WM8903_DRC_0, 3, 1, 0),683SOC_SINGLE("DRC Smoothing Hysteresis Switch", WM8903_DRC_0, 0, 1, 0),684SOC_ENUM("DRC Smoothing Threshold", drc_smoothing),685SOC_SINGLE_TLV("DRC Startup Volume", WM8903_DRC_0, 6, 18, 0, drc_tlv_startup),686 687SOC_DOUBLE_R_TLV("Digital Capture Volume", WM8903_ADC_DIGITAL_VOLUME_LEFT,688 WM8903_ADC_DIGITAL_VOLUME_RIGHT, 1, 120, 0, digital_tlv),689SOC_ENUM("ADC Companding Mode", adc_companding),690SOC_SINGLE("ADC Companding Switch", WM8903_AUDIO_INTERFACE_0, 3, 1, 0),691 692SOC_DOUBLE_TLV("Digital Sidetone Volume", WM8903_DAC_DIGITAL_0, 4, 8,693 12, 0, digital_sidetone_tlv),694 695/* DAC */696SOC_ENUM("DAC OSR", dac_osr),697SOC_DOUBLE_R_TLV("Digital Playback Volume", WM8903_DAC_DIGITAL_VOLUME_LEFT,698 WM8903_DAC_DIGITAL_VOLUME_RIGHT, 1, 120, 0, digital_tlv),699SOC_ENUM("DAC Soft Mute Rate", soft_mute),700SOC_ENUM("DAC Mute Mode", mute_mode),701SOC_SINGLE("DAC Mono Switch", WM8903_DAC_DIGITAL_1, 12, 1, 0),702SOC_ENUM("DAC Companding Mode", dac_companding),703SOC_SINGLE("DAC Companding Switch", WM8903_AUDIO_INTERFACE_0, 1, 1, 0),704SOC_SINGLE_TLV("DAC Boost Volume", WM8903_AUDIO_INTERFACE_0, 9, 3, 0,705 dac_boost_tlv),706SOC_SINGLE_BOOL_EXT("Playback Deemphasis Switch", 0,707 wm8903_get_deemph, wm8903_put_deemph),708 709/* Headphones */710SOC_DOUBLE_R("Headphone Switch",711 WM8903_ANALOGUE_OUT1_LEFT, WM8903_ANALOGUE_OUT1_RIGHT,712 8, 1, 1),713SOC_DOUBLE_R("Headphone ZC Switch",714 WM8903_ANALOGUE_OUT1_LEFT, WM8903_ANALOGUE_OUT1_RIGHT,715 6, 1, 0),716SOC_DOUBLE_R_TLV("Headphone Volume",717 WM8903_ANALOGUE_OUT1_LEFT, WM8903_ANALOGUE_OUT1_RIGHT,718 0, 63, 0, out_tlv),719 720/* Line out */721SOC_DOUBLE_R("Line Out Switch",722 WM8903_ANALOGUE_OUT2_LEFT, WM8903_ANALOGUE_OUT2_RIGHT,723 8, 1, 1),724SOC_DOUBLE_R("Line Out ZC Switch",725 WM8903_ANALOGUE_OUT2_LEFT, WM8903_ANALOGUE_OUT2_RIGHT,726 6, 1, 0),727SOC_DOUBLE_R_TLV("Line Out Volume",728 WM8903_ANALOGUE_OUT2_LEFT, WM8903_ANALOGUE_OUT2_RIGHT,729 0, 63, 0, out_tlv),730 731/* Speaker */732SOC_DOUBLE_R("Speaker Switch",733 WM8903_ANALOGUE_OUT3_LEFT, WM8903_ANALOGUE_OUT3_RIGHT, 8, 1, 1),734SOC_DOUBLE_R("Speaker ZC Switch",735 WM8903_ANALOGUE_OUT3_LEFT, WM8903_ANALOGUE_OUT3_RIGHT, 6, 1, 0),736SOC_DOUBLE_R_TLV("Speaker Volume",737 WM8903_ANALOGUE_OUT3_LEFT, WM8903_ANALOGUE_OUT3_RIGHT,738 0, 63, 0, out_tlv),739};740 741static const struct snd_kcontrol_new linput_mode_mux =742 SOC_DAPM_ENUM("Left Input Mode Mux", linput_mode_enum);743 744static const struct snd_kcontrol_new rinput_mode_mux =745 SOC_DAPM_ENUM("Right Input Mode Mux", rinput_mode_enum);746 747static const struct snd_kcontrol_new linput_mux =748 SOC_DAPM_ENUM("Left Input Mux", linput_enum);749 750static const struct snd_kcontrol_new linput_inv_mux =751 SOC_DAPM_ENUM("Left Inverting Input Mux", linput_inv_enum);752 753static const struct snd_kcontrol_new rinput_mux =754 SOC_DAPM_ENUM("Right Input Mux", rinput_enum);755 756static const struct snd_kcontrol_new rinput_inv_mux =757 SOC_DAPM_ENUM("Right Inverting Input Mux", rinput_inv_enum);758 759static const struct snd_kcontrol_new lsidetone_mux =760 SOC_DAPM_ENUM("DACL Sidetone Mux", lsidetone_enum);761 762static const struct snd_kcontrol_new rsidetone_mux =763 SOC_DAPM_ENUM("DACR Sidetone Mux", rsidetone_enum);764 765static const struct snd_kcontrol_new adcinput_mux =766 SOC_DAPM_ENUM("ADC Input", adcinput_enum);767 768static const struct snd_kcontrol_new lcapture_mux =769 SOC_DAPM_ENUM("Left Capture Mux", lcapture_enum);770 771static const struct snd_kcontrol_new rcapture_mux =772 SOC_DAPM_ENUM("Right Capture Mux", rcapture_enum);773 774static const struct snd_kcontrol_new lplay_mux =775 SOC_DAPM_ENUM("Left Playback Mux", lplay_enum);776 777static const struct snd_kcontrol_new rplay_mux =778 SOC_DAPM_ENUM("Right Playback Mux", rplay_enum);779 780static const struct snd_kcontrol_new left_output_mixer[] = {781SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_LEFT_MIX_0, 3, 1, 0),782SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_LEFT_MIX_0, 2, 1, 0),783SOC_DAPM_SINGLE_W("Left Bypass Switch", WM8903_ANALOGUE_LEFT_MIX_0, 1, 1, 0),784SOC_DAPM_SINGLE_W("Right Bypass Switch", WM8903_ANALOGUE_LEFT_MIX_0, 0, 1, 0),785};786 787static const struct snd_kcontrol_new right_output_mixer[] = {788SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_RIGHT_MIX_0, 3, 1, 0),789SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_RIGHT_MIX_0, 2, 1, 0),790SOC_DAPM_SINGLE_W("Left Bypass Switch", WM8903_ANALOGUE_RIGHT_MIX_0, 1, 1, 0),791SOC_DAPM_SINGLE_W("Right Bypass Switch", WM8903_ANALOGUE_RIGHT_MIX_0, 0, 1, 0),792};793 794static const struct snd_kcontrol_new left_speaker_mixer[] = {795SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0, 3, 1, 0),796SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0, 2, 1, 0),797SOC_DAPM_SINGLE("Left Bypass Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0, 1, 1, 0),798SOC_DAPM_SINGLE("Right Bypass Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0,799 0, 1, 0),800};801 802static const struct snd_kcontrol_new right_speaker_mixer[] = {803SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0, 3, 1, 0),804SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0, 2, 1, 0),805SOC_DAPM_SINGLE("Left Bypass Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0,806 1, 1, 0),807SOC_DAPM_SINGLE("Right Bypass Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0,808 0, 1, 0),809};810 811static const struct snd_soc_dapm_widget wm8903_dapm_widgets[] = {812SND_SOC_DAPM_INPUT("IN1L"),813SND_SOC_DAPM_INPUT("IN1R"),814SND_SOC_DAPM_INPUT("IN2L"),815SND_SOC_DAPM_INPUT("IN2R"),816SND_SOC_DAPM_INPUT("IN3L"),817SND_SOC_DAPM_INPUT("IN3R"),818SND_SOC_DAPM_INPUT("DMICDAT"),819 820SND_SOC_DAPM_OUTPUT("HPOUTL"),821SND_SOC_DAPM_OUTPUT("HPOUTR"),822SND_SOC_DAPM_OUTPUT("LINEOUTL"),823SND_SOC_DAPM_OUTPUT("LINEOUTR"),824SND_SOC_DAPM_OUTPUT("LOP"),825SND_SOC_DAPM_OUTPUT("LON"),826SND_SOC_DAPM_OUTPUT("ROP"),827SND_SOC_DAPM_OUTPUT("RON"),828 829SND_SOC_DAPM_SUPPLY("MICBIAS", WM8903_MIC_BIAS_CONTROL_0, 0, 0, NULL, 0),830 831SND_SOC_DAPM_MUX("Left Input Mux", SND_SOC_NOPM, 0, 0, &linput_mux),832SND_SOC_DAPM_MUX("Left Input Inverting Mux", SND_SOC_NOPM, 0, 0,833 &linput_inv_mux),834SND_SOC_DAPM_MUX("Left Input Mode Mux", SND_SOC_NOPM, 0, 0, &linput_mode_mux),835 836SND_SOC_DAPM_MUX("Right Input Mux", SND_SOC_NOPM, 0, 0, &rinput_mux),837SND_SOC_DAPM_MUX("Right Input Inverting Mux", SND_SOC_NOPM, 0, 0,838 &rinput_inv_mux),839SND_SOC_DAPM_MUX("Right Input Mode Mux", SND_SOC_NOPM, 0, 0, &rinput_mode_mux),840 841SND_SOC_DAPM_PGA("Left Input PGA", WM8903_POWER_MANAGEMENT_0, 1, 0, NULL, 0),842SND_SOC_DAPM_PGA("Right Input PGA", WM8903_POWER_MANAGEMENT_0, 0, 0, NULL, 0),843 844SND_SOC_DAPM_MUX("Left ADC Input", SND_SOC_NOPM, 0, 0, &adcinput_mux),845SND_SOC_DAPM_MUX("Right ADC Input", SND_SOC_NOPM, 0, 0, &adcinput_mux),846 847SND_SOC_DAPM_ADC("ADCL", NULL, WM8903_POWER_MANAGEMENT_6, 1, 0),848SND_SOC_DAPM_ADC("ADCR", NULL, WM8903_POWER_MANAGEMENT_6, 0, 0),849 850SND_SOC_DAPM_MUX("Left Capture Mux", SND_SOC_NOPM, 0, 0, &lcapture_mux),851SND_SOC_DAPM_MUX("Right Capture Mux", SND_SOC_NOPM, 0, 0, &rcapture_mux),852 853SND_SOC_DAPM_AIF_OUT("AIFTXL", "Left HiFi Capture", 0, SND_SOC_NOPM, 0, 0),854SND_SOC_DAPM_AIF_OUT("AIFTXR", "Right HiFi Capture", 0, SND_SOC_NOPM, 0, 0),855 856SND_SOC_DAPM_MUX("DACL Sidetone", SND_SOC_NOPM, 0, 0, &lsidetone_mux),857SND_SOC_DAPM_MUX("DACR Sidetone", SND_SOC_NOPM, 0, 0, &rsidetone_mux),858 859SND_SOC_DAPM_AIF_IN("AIFRXL", "Left Playback", 0, SND_SOC_NOPM, 0, 0),860SND_SOC_DAPM_AIF_IN("AIFRXR", "Right Playback", 0, SND_SOC_NOPM, 0, 0),861 862SND_SOC_DAPM_MUX("Left Playback Mux", SND_SOC_NOPM, 0, 0, &lplay_mux),863SND_SOC_DAPM_MUX("Right Playback Mux", SND_SOC_NOPM, 0, 0, &rplay_mux),864 865SND_SOC_DAPM_DAC("DACL", NULL, WM8903_POWER_MANAGEMENT_6, 3, 0),866SND_SOC_DAPM_DAC("DACR", NULL, WM8903_POWER_MANAGEMENT_6, 2, 0),867 868SND_SOC_DAPM_MIXER("Left Output Mixer", WM8903_POWER_MANAGEMENT_1, 1, 0,869 left_output_mixer, ARRAY_SIZE(left_output_mixer)),870SND_SOC_DAPM_MIXER("Right Output Mixer", WM8903_POWER_MANAGEMENT_1, 0, 0,871 right_output_mixer, ARRAY_SIZE(right_output_mixer)),872 873SND_SOC_DAPM_MIXER("Left Speaker Mixer", WM8903_POWER_MANAGEMENT_4, 1, 0,874 left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer)),875SND_SOC_DAPM_MIXER("Right Speaker Mixer", WM8903_POWER_MANAGEMENT_4, 0, 0,876 right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer)),877 878SND_SOC_DAPM_PGA_S("Left Headphone Output PGA", 0, WM8903_POWER_MANAGEMENT_2,879 1, 0, NULL, 0),880SND_SOC_DAPM_PGA_S("Right Headphone Output PGA", 0, WM8903_POWER_MANAGEMENT_2,881 0, 0, NULL, 0),882 883SND_SOC_DAPM_PGA_S("Left Line Output PGA", 0, WM8903_POWER_MANAGEMENT_3, 1, 0,884 NULL, 0),885SND_SOC_DAPM_PGA_S("Right Line Output PGA", 0, WM8903_POWER_MANAGEMENT_3, 0, 0,886 NULL, 0),887 888SND_SOC_DAPM_PGA_S("HPL_RMV_SHORT", 4, WM8903_ANALOGUE_HP_0, 7, 0, NULL, 0),889SND_SOC_DAPM_PGA_S("HPL_ENA_OUTP", 3, WM8903_ANALOGUE_HP_0, 6, 0, NULL, 0),890SND_SOC_DAPM_PGA_S("HPL_ENA_DLY", 2, WM8903_ANALOGUE_HP_0, 5, 0, NULL, 0),891SND_SOC_DAPM_PGA_S("HPL_ENA", 1, WM8903_ANALOGUE_HP_0, 4, 0, NULL, 0),892SND_SOC_DAPM_PGA_S("HPR_RMV_SHORT", 4, WM8903_ANALOGUE_HP_0, 3, 0, NULL, 0),893SND_SOC_DAPM_PGA_S("HPR_ENA_OUTP", 3, WM8903_ANALOGUE_HP_0, 2, 0, NULL, 0),894SND_SOC_DAPM_PGA_S("HPR_ENA_DLY", 2, WM8903_ANALOGUE_HP_0, 1, 0, NULL, 0),895SND_SOC_DAPM_PGA_S("HPR_ENA", 1, WM8903_ANALOGUE_HP_0, 0, 0, NULL, 0),896 897SND_SOC_DAPM_PGA_S("LINEOUTL_RMV_SHORT", 4, WM8903_ANALOGUE_LINEOUT_0, 7, 0,898 NULL, 0),899SND_SOC_DAPM_PGA_S("LINEOUTL_ENA_OUTP", 3, WM8903_ANALOGUE_LINEOUT_0, 6, 0,900 NULL, 0),901SND_SOC_DAPM_PGA_S("LINEOUTL_ENA_DLY", 2, WM8903_ANALOGUE_LINEOUT_0, 5, 0,902 NULL, 0),903SND_SOC_DAPM_PGA_S("LINEOUTL_ENA", 1, WM8903_ANALOGUE_LINEOUT_0, 4, 0,904 NULL, 0),905SND_SOC_DAPM_PGA_S("LINEOUTR_RMV_SHORT", 4, WM8903_ANALOGUE_LINEOUT_0, 3, 0,906 NULL, 0),907SND_SOC_DAPM_PGA_S("LINEOUTR_ENA_OUTP", 3, WM8903_ANALOGUE_LINEOUT_0, 2, 0,908 NULL, 0),909SND_SOC_DAPM_PGA_S("LINEOUTR_ENA_DLY", 2, WM8903_ANALOGUE_LINEOUT_0, 1, 0,910 NULL, 0),911SND_SOC_DAPM_PGA_S("LINEOUTR_ENA", 1, WM8903_ANALOGUE_LINEOUT_0, 0, 0,912 NULL, 0),913 914SND_SOC_DAPM_SUPPLY("DCS Master", WM8903_DC_SERVO_0, 4, 0, NULL, 0),915SND_SOC_DAPM_PGA_S("HPL_DCS", 3, SND_SOC_NOPM, 3, 0, wm8903_dcs_event,916 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),917SND_SOC_DAPM_PGA_S("HPR_DCS", 3, SND_SOC_NOPM, 2, 0, wm8903_dcs_event,918 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),919SND_SOC_DAPM_PGA_S("LINEOUTL_DCS", 3, SND_SOC_NOPM, 1, 0, wm8903_dcs_event,920 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),921SND_SOC_DAPM_PGA_S("LINEOUTR_DCS", 3, SND_SOC_NOPM, 0, 0, wm8903_dcs_event,922 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),923 924SND_SOC_DAPM_PGA("Left Speaker PGA", WM8903_POWER_MANAGEMENT_5, 1, 0,925 NULL, 0),926SND_SOC_DAPM_PGA("Right Speaker PGA", WM8903_POWER_MANAGEMENT_5, 0, 0,927 NULL, 0),928 929SND_SOC_DAPM_SUPPLY("Charge Pump", WM8903_CHARGE_PUMP_0, 0, 0,930 wm8903_cp_event, SND_SOC_DAPM_POST_PMU),931SND_SOC_DAPM_SUPPLY("CLK_DSP", WM8903_CLOCK_RATES_2, 1, 0, NULL, 0),932SND_SOC_DAPM_SUPPLY("CLK_SYS", WM8903_CLOCK_RATES_2, 2, 0, NULL, 0),933};934 935static const struct snd_soc_dapm_route wm8903_intercon[] = {936 937 { "CLK_DSP", NULL, "CLK_SYS" },938 { "MICBIAS", NULL, "CLK_SYS" },939 { "HPL_DCS", NULL, "CLK_SYS" },940 { "HPR_DCS", NULL, "CLK_SYS" },941 { "LINEOUTL_DCS", NULL, "CLK_SYS" },942 { "LINEOUTR_DCS", NULL, "CLK_SYS" },943 944 { "Left Input Mux", "IN1L", "IN1L" },945 { "Left Input Mux", "IN2L", "IN2L" },946 { "Left Input Mux", "IN3L", "IN3L" },947 948 { "Left Input Inverting Mux", "IN1L", "IN1L" },949 { "Left Input Inverting Mux", "IN2L", "IN2L" },950 { "Left Input Inverting Mux", "IN3L", "IN3L" },951 952 { "Right Input Mux", "IN1R", "IN1R" },953 { "Right Input Mux", "IN2R", "IN2R" },954 { "Right Input Mux", "IN3R", "IN3R" },955 956 { "Right Input Inverting Mux", "IN1R", "IN1R" },957 { "Right Input Inverting Mux", "IN2R", "IN2R" },958 { "Right Input Inverting Mux", "IN3R", "IN3R" },959 960 { "Left Input Mode Mux", "Single-Ended", "Left Input Inverting Mux" },961 { "Left Input Mode Mux", "Differential Line",962 "Left Input Mux" },963 { "Left Input Mode Mux", "Differential Line",964 "Left Input Inverting Mux" },965 { "Left Input Mode Mux", "Differential Mic",966 "Left Input Mux" },967 { "Left Input Mode Mux", "Differential Mic",968 "Left Input Inverting Mux" },969 970 { "Right Input Mode Mux", "Single-Ended",971 "Right Input Inverting Mux" },972 { "Right Input Mode Mux", "Differential Line",973 "Right Input Mux" },974 { "Right Input Mode Mux", "Differential Line",975 "Right Input Inverting Mux" },976 { "Right Input Mode Mux", "Differential Mic",977 "Right Input Mux" },978 { "Right Input Mode Mux", "Differential Mic",979 "Right Input Inverting Mux" },980 981 { "Left Input PGA", NULL, "Left Input Mode Mux" },982 { "Right Input PGA", NULL, "Right Input Mode Mux" },983 984 { "Left ADC Input", "ADC", "Left Input PGA" },985 { "Left ADC Input", "DMIC", "DMICDAT" },986 { "Right ADC Input", "ADC", "Right Input PGA" },987 { "Right ADC Input", "DMIC", "DMICDAT" },988 989 { "Left Capture Mux", "Left", "ADCL" },990 { "Left Capture Mux", "Right", "ADCR" },991 992 { "Right Capture Mux", "Left", "ADCL" },993 { "Right Capture Mux", "Right", "ADCR" },994 995 { "AIFTXL", NULL, "Left Capture Mux" },996 { "AIFTXR", NULL, "Right Capture Mux" },997 998 { "ADCL", NULL, "Left ADC Input" },999 { "ADCL", NULL, "CLK_DSP" },1000 { "ADCR", NULL, "Right ADC Input" },1001 { "ADCR", NULL, "CLK_DSP" },1002 1003 { "Left Playback Mux", "Left", "AIFRXL" },1004 { "Left Playback Mux", "Right", "AIFRXR" },1005 1006 { "Right Playback Mux", "Left", "AIFRXL" },1007 { "Right Playback Mux", "Right", "AIFRXR" },1008 1009 { "DACL Sidetone", "Left", "ADCL" },1010 { "DACL Sidetone", "Right", "ADCR" },1011 { "DACR Sidetone", "Left", "ADCL" },1012 { "DACR Sidetone", "Right", "ADCR" },1013 1014 { "DACL", NULL, "Left Playback Mux" },1015 { "DACL", NULL, "DACL Sidetone" },1016 { "DACL", NULL, "CLK_DSP" },1017 1018 { "DACR", NULL, "Right Playback Mux" },1019 { "DACR", NULL, "DACR Sidetone" },1020 { "DACR", NULL, "CLK_DSP" },1021 1022 { "Left Output Mixer", "Left Bypass Switch", "Left Input PGA" },1023 { "Left Output Mixer", "Right Bypass Switch", "Right Input PGA" },1024 { "Left Output Mixer", "DACL Switch", "DACL" },1025 { "Left Output Mixer", "DACR Switch", "DACR" },1026 1027 { "Right Output Mixer", "Left Bypass Switch", "Left Input PGA" },1028 { "Right Output Mixer", "Right Bypass Switch", "Right Input PGA" },1029 { "Right Output Mixer", "DACL Switch", "DACL" },1030 { "Right Output Mixer", "DACR Switch", "DACR" },1031 1032 { "Left Speaker Mixer", "Left Bypass Switch", "Left Input PGA" },1033 { "Left Speaker Mixer", "Right Bypass Switch", "Right Input PGA" },1034 { "Left Speaker Mixer", "DACL Switch", "DACL" },1035 { "Left Speaker Mixer", "DACR Switch", "DACR" },1036 1037 { "Right Speaker Mixer", "Left Bypass Switch", "Left Input PGA" },1038 { "Right Speaker Mixer", "Right Bypass Switch", "Right Input PGA" },1039 { "Right Speaker Mixer", "DACL Switch", "DACL" },1040 { "Right Speaker Mixer", "DACR Switch", "DACR" },1041 1042 { "Left Line Output PGA", NULL, "Left Output Mixer" },1043 { "Right Line Output PGA", NULL, "Right Output Mixer" },1044 1045 { "Left Headphone Output PGA", NULL, "Left Output Mixer" },1046 { "Right Headphone Output PGA", NULL, "Right Output Mixer" },1047 1048 { "Left Speaker PGA", NULL, "Left Speaker Mixer" },1049 { "Right Speaker PGA", NULL, "Right Speaker Mixer" },1050 1051 { "HPL_ENA", NULL, "Left Headphone Output PGA" },1052 { "HPR_ENA", NULL, "Right Headphone Output PGA" },1053 { "HPL_ENA_DLY", NULL, "HPL_ENA" },1054 { "HPR_ENA_DLY", NULL, "HPR_ENA" },1055 { "LINEOUTL_ENA", NULL, "Left Line Output PGA" },1056 { "LINEOUTR_ENA", NULL, "Right Line Output PGA" },1057 { "LINEOUTL_ENA_DLY", NULL, "LINEOUTL_ENA" },1058 { "LINEOUTR_ENA_DLY", NULL, "LINEOUTR_ENA" },1059 1060 { "HPL_DCS", NULL, "DCS Master" },1061 { "HPR_DCS", NULL, "DCS Master" },1062 { "LINEOUTL_DCS", NULL, "DCS Master" },1063 { "LINEOUTR_DCS", NULL, "DCS Master" },1064 1065 { "HPL_DCS", NULL, "HPL_ENA_DLY" },1066 { "HPR_DCS", NULL, "HPR_ENA_DLY" },1067 { "LINEOUTL_DCS", NULL, "LINEOUTL_ENA_DLY" },1068 { "LINEOUTR_DCS", NULL, "LINEOUTR_ENA_DLY" },1069 1070 { "HPL_ENA_OUTP", NULL, "HPL_DCS" },1071 { "HPR_ENA_OUTP", NULL, "HPR_DCS" },1072 { "LINEOUTL_ENA_OUTP", NULL, "LINEOUTL_DCS" },1073 { "LINEOUTR_ENA_OUTP", NULL, "LINEOUTR_DCS" },1074 1075 { "HPL_RMV_SHORT", NULL, "HPL_ENA_OUTP" },1076 { "HPR_RMV_SHORT", NULL, "HPR_ENA_OUTP" },1077 { "LINEOUTL_RMV_SHORT", NULL, "LINEOUTL_ENA_OUTP" },1078 { "LINEOUTR_RMV_SHORT", NULL, "LINEOUTR_ENA_OUTP" },1079 1080 { "HPOUTL", NULL, "HPL_RMV_SHORT" },1081 { "HPOUTR", NULL, "HPR_RMV_SHORT" },1082 { "LINEOUTL", NULL, "LINEOUTL_RMV_SHORT" },1083 { "LINEOUTR", NULL, "LINEOUTR_RMV_SHORT" },1084 1085 { "LOP", NULL, "Left Speaker PGA" },1086 { "LON", NULL, "Left Speaker PGA" },1087 1088 { "ROP", NULL, "Right Speaker PGA" },1089 { "RON", NULL, "Right Speaker PGA" },1090 1091 { "Charge Pump", NULL, "CLK_DSP" },1092 1093 { "Left Headphone Output PGA", NULL, "Charge Pump" },1094 { "Right Headphone Output PGA", NULL, "Charge Pump" },1095 { "Left Line Output PGA", NULL, "Charge Pump" },1096 { "Right Line Output PGA", NULL, "Charge Pump" },1097};1098 1099static int wm8903_set_bias_level(struct snd_soc_component *component,1100 enum snd_soc_bias_level level)1101{1102 switch (level) {1103 case SND_SOC_BIAS_ON:1104 break;1105 1106 case SND_SOC_BIAS_PREPARE:1107 snd_soc_component_update_bits(component, WM8903_VMID_CONTROL_0,1108 WM8903_VMID_RES_MASK,1109 WM8903_VMID_RES_50K);1110 break;1111 1112 case SND_SOC_BIAS_STANDBY:1113 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {1114 snd_soc_component_update_bits(component, WM8903_BIAS_CONTROL_0,1115 WM8903_POBCTRL | WM8903_ISEL_MASK |1116 WM8903_STARTUP_BIAS_ENA |1117 WM8903_BIAS_ENA,1118 WM8903_POBCTRL |1119 (2 << WM8903_ISEL_SHIFT) |1120 WM8903_STARTUP_BIAS_ENA);1121 1122 snd_soc_component_update_bits(component,1123 WM8903_ANALOGUE_SPK_OUTPUT_CONTROL_0,1124 WM8903_SPK_DISCHARGE,1125 WM8903_SPK_DISCHARGE);1126 1127 msleep(33);1128 1129 snd_soc_component_update_bits(component, WM8903_POWER_MANAGEMENT_5,1130 WM8903_SPKL_ENA | WM8903_SPKR_ENA,1131 WM8903_SPKL_ENA | WM8903_SPKR_ENA);1132 1133 snd_soc_component_update_bits(component,1134 WM8903_ANALOGUE_SPK_OUTPUT_CONTROL_0,1135 WM8903_SPK_DISCHARGE, 0);1136 1137 snd_soc_component_update_bits(component, WM8903_VMID_CONTROL_0,1138 WM8903_VMID_TIE_ENA |1139 WM8903_BUFIO_ENA |1140 WM8903_VMID_IO_ENA |1141 WM8903_VMID_SOFT_MASK |1142 WM8903_VMID_RES_MASK |1143 WM8903_VMID_BUF_ENA,1144 WM8903_VMID_TIE_ENA |1145 WM8903_BUFIO_ENA |1146 WM8903_VMID_IO_ENA |1147 (2 << WM8903_VMID_SOFT_SHIFT) |1148 WM8903_VMID_RES_250K |1149 WM8903_VMID_BUF_ENA);1150 1151 msleep(129);1152 1153 snd_soc_component_update_bits(component, WM8903_POWER_MANAGEMENT_5,1154 WM8903_SPKL_ENA | WM8903_SPKR_ENA,1155 0);1156 1157 snd_soc_component_update_bits(component, WM8903_VMID_CONTROL_0,1158 WM8903_VMID_SOFT_MASK, 0);1159 1160 snd_soc_component_update_bits(component, WM8903_VMID_CONTROL_0,1161 WM8903_VMID_RES_MASK,1162 WM8903_VMID_RES_50K);1163 1164 snd_soc_component_update_bits(component, WM8903_BIAS_CONTROL_0,1165 WM8903_BIAS_ENA | WM8903_POBCTRL,1166 WM8903_BIAS_ENA);1167 1168 /* By default no bypass paths are enabled so1169 * enable Class W support.1170 */1171 dev_dbg(component->dev, "Enabling Class W\n");1172 snd_soc_component_update_bits(component, WM8903_CLASS_W_0,1173 WM8903_CP_DYN_FREQ |1174 WM8903_CP_DYN_V,1175 WM8903_CP_DYN_FREQ |1176 WM8903_CP_DYN_V);1177 }1178 1179 snd_soc_component_update_bits(component, WM8903_VMID_CONTROL_0,1180 WM8903_VMID_RES_MASK,1181 WM8903_VMID_RES_250K);1182 break;1183 1184 case SND_SOC_BIAS_OFF:1185 snd_soc_component_update_bits(component, WM8903_BIAS_CONTROL_0,1186 WM8903_BIAS_ENA, 0);1187 1188 snd_soc_component_update_bits(component, WM8903_VMID_CONTROL_0,1189 WM8903_VMID_SOFT_MASK,1190 2 << WM8903_VMID_SOFT_SHIFT);1191 1192 snd_soc_component_update_bits(component, WM8903_VMID_CONTROL_0,1193 WM8903_VMID_BUF_ENA, 0);1194 1195 msleep(290);1196 1197 snd_soc_component_update_bits(component, WM8903_VMID_CONTROL_0,1198 WM8903_VMID_TIE_ENA | WM8903_BUFIO_ENA |1199 WM8903_VMID_IO_ENA | WM8903_VMID_RES_MASK |1200 WM8903_VMID_SOFT_MASK |1201 WM8903_VMID_BUF_ENA, 0);1202 1203 snd_soc_component_update_bits(component, WM8903_BIAS_CONTROL_0,1204 WM8903_STARTUP_BIAS_ENA, 0);1205 break;1206 }1207 1208 return 0;1209}1210 1211static int wm8903_set_dai_sysclk(struct snd_soc_dai *codec_dai,1212 int clk_id, unsigned int freq, int dir)1213{1214 struct snd_soc_component *component = codec_dai->component;1215 struct wm8903_priv *wm8903 = snd_soc_component_get_drvdata(component);1216 1217 wm8903->sysclk = freq;1218 1219 return 0;1220}1221 1222static int wm8903_set_dai_fmt(struct snd_soc_dai *codec_dai,1223 unsigned int fmt)1224{1225 struct snd_soc_component *component = codec_dai->component;1226 u16 aif1 = snd_soc_component_read(component, WM8903_AUDIO_INTERFACE_1);1227 1228 aif1 &= ~(WM8903_LRCLK_DIR | WM8903_BCLK_DIR | WM8903_AIF_FMT_MASK |1229 WM8903_AIF_LRCLK_INV | WM8903_AIF_BCLK_INV);1230 1231 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {1232 case SND_SOC_DAIFMT_CBS_CFS:1233 break;1234 case SND_SOC_DAIFMT_CBS_CFM:1235 aif1 |= WM8903_LRCLK_DIR;1236 break;1237 case SND_SOC_DAIFMT_CBM_CFM:1238 aif1 |= WM8903_LRCLK_DIR | WM8903_BCLK_DIR;1239 break;1240 case SND_SOC_DAIFMT_CBM_CFS:1241 aif1 |= WM8903_BCLK_DIR;1242 break;1243 default:1244 return -EINVAL;1245 }1246 1247 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {1248 case SND_SOC_DAIFMT_DSP_A:1249 aif1 |= 0x3;1250 break;1251 case SND_SOC_DAIFMT_DSP_B:1252 aif1 |= 0x3 | WM8903_AIF_LRCLK_INV;1253 break;1254 case SND_SOC_DAIFMT_I2S:1255 aif1 |= 0x2;1256 break;1257 case SND_SOC_DAIFMT_RIGHT_J:1258 aif1 |= 0x1;1259 break;1260 case SND_SOC_DAIFMT_LEFT_J:1261 break;1262 default:1263 return -EINVAL;1264 }1265 1266 /* Clock inversion */1267 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {1268 case SND_SOC_DAIFMT_DSP_A:1269 case SND_SOC_DAIFMT_DSP_B:1270 /* frame inversion not valid for DSP modes */1271 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {1272 case SND_SOC_DAIFMT_NB_NF:1273 break;1274 case SND_SOC_DAIFMT_IB_NF:1275 aif1 |= WM8903_AIF_BCLK_INV;1276 break;1277 default:1278 return -EINVAL;1279 }1280 break;1281 case SND_SOC_DAIFMT_I2S:1282 case SND_SOC_DAIFMT_RIGHT_J:1283 case SND_SOC_DAIFMT_LEFT_J:1284 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {1285 case SND_SOC_DAIFMT_NB_NF:1286 break;1287 case SND_SOC_DAIFMT_IB_IF:1288 aif1 |= WM8903_AIF_BCLK_INV | WM8903_AIF_LRCLK_INV;1289 break;1290 case SND_SOC_DAIFMT_IB_NF:1291 aif1 |= WM8903_AIF_BCLK_INV;1292 break;1293 case SND_SOC_DAIFMT_NB_IF:1294 aif1 |= WM8903_AIF_LRCLK_INV;1295 break;1296 default:1297 return -EINVAL;1298 }1299 break;1300 default:1301 return -EINVAL;1302 }1303 1304 snd_soc_component_write(component, WM8903_AUDIO_INTERFACE_1, aif1);1305 1306 return 0;1307}1308 1309static int wm8903_mute(struct snd_soc_dai *codec_dai, int mute, int direction)1310{1311 struct snd_soc_component *component = codec_dai->component;1312 u16 reg;1313 1314 reg = snd_soc_component_read(component, WM8903_DAC_DIGITAL_1);1315 1316 if (mute)1317 reg |= WM8903_DAC_MUTE;1318 else1319 reg &= ~WM8903_DAC_MUTE;1320 1321 snd_soc_component_write(component, WM8903_DAC_DIGITAL_1, reg);1322 1323 return 0;1324}1325 1326/* Lookup table for CLK_SYS/fs ratio. 256fs or more is recommended1327 * for optimal performance so we list the lower rates first and match1328 * on the last match we find. */1329static struct {1330 int div;1331 int rate;1332 int mode;1333 int mclk_div;1334} clk_sys_ratios[] = {1335 { 64, 0x0, 0x0, 1 },1336 { 68, 0x0, 0x1, 1 },1337 { 125, 0x0, 0x2, 1 },1338 { 128, 0x1, 0x0, 1 },1339 { 136, 0x1, 0x1, 1 },1340 { 192, 0x2, 0x0, 1 },1341 { 204, 0x2, 0x1, 1 },1342 1343 { 64, 0x0, 0x0, 2 },1344 { 68, 0x0, 0x1, 2 },1345 { 125, 0x0, 0x2, 2 },1346 { 128, 0x1, 0x0, 2 },1347 { 136, 0x1, 0x1, 2 },1348 { 192, 0x2, 0x0, 2 },1349 { 204, 0x2, 0x1, 2 },1350 1351 { 250, 0x2, 0x2, 1 },1352 { 256, 0x3, 0x0, 1 },1353 { 272, 0x3, 0x1, 1 },1354 { 384, 0x4, 0x0, 1 },1355 { 408, 0x4, 0x1, 1 },1356 { 375, 0x4, 0x2, 1 },1357 { 512, 0x5, 0x0, 1 },1358 { 544, 0x5, 0x1, 1 },1359 { 500, 0x5, 0x2, 1 },1360 { 768, 0x6, 0x0, 1 },1361 { 816, 0x6, 0x1, 1 },1362 { 750, 0x6, 0x2, 1 },1363 { 1024, 0x7, 0x0, 1 },1364 { 1088, 0x7, 0x1, 1 },1365 { 1000, 0x7, 0x2, 1 },1366 { 1408, 0x8, 0x0, 1 },1367 { 1496, 0x8, 0x1, 1 },1368 { 1536, 0x9, 0x0, 1 },1369 { 1632, 0x9, 0x1, 1 },1370 { 1500, 0x9, 0x2, 1 },1371 1372 { 250, 0x2, 0x2, 2 },1373 { 256, 0x3, 0x0, 2 },1374 { 272, 0x3, 0x1, 2 },1375 { 384, 0x4, 0x0, 2 },1376 { 408, 0x4, 0x1, 2 },1377 { 375, 0x4, 0x2, 2 },1378 { 512, 0x5, 0x0, 2 },1379 { 544, 0x5, 0x1, 2 },1380 { 500, 0x5, 0x2, 2 },1381 { 768, 0x6, 0x0, 2 },1382 { 816, 0x6, 0x1, 2 },1383 { 750, 0x6, 0x2, 2 },1384 { 1024, 0x7, 0x0, 2 },1385 { 1088, 0x7, 0x1, 2 },1386 { 1000, 0x7, 0x2, 2 },1387 { 1408, 0x8, 0x0, 2 },1388 { 1496, 0x8, 0x1, 2 },1389 { 1536, 0x9, 0x0, 2 },1390 { 1632, 0x9, 0x1, 2 },1391 { 1500, 0x9, 0x2, 2 },1392};1393 1394/* CLK_SYS/BCLK ratios - multiplied by 10 due to .5s */1395static struct {1396 int ratio;1397 int div;1398} bclk_divs[] = {1399 { 10, 0 },1400 { 20, 2 },1401 { 30, 3 },1402 { 40, 4 },1403 { 50, 5 },1404 { 60, 7 },1405 { 80, 8 },1406 { 100, 9 },1407 { 120, 11 },1408 { 160, 12 },1409 { 200, 13 },1410 { 220, 14 },1411 { 240, 15 },1412 { 300, 17 },1413 { 320, 18 },1414 { 440, 19 },1415 { 480, 20 },1416};1417 1418/* Sample rates for DSP */1419static struct {1420 int rate;1421 int value;1422} sample_rates[] = {1423 { 8000, 0 },1424 { 11025, 1 },1425 { 12000, 2 },1426 { 16000, 3 },1427 { 22050, 4 },1428 { 24000, 5 },1429 { 32000, 6 },1430 { 44100, 7 },1431 { 48000, 8 },1432 { 88200, 9 },1433 { 96000, 10 },1434 { 0, 0 },1435};1436 1437static int wm8903_hw_params(struct snd_pcm_substream *substream,1438 struct snd_pcm_hw_params *params,1439 struct snd_soc_dai *dai)1440{1441 struct snd_soc_component *component = dai->component;1442 struct wm8903_priv *wm8903 = snd_soc_component_get_drvdata(component);1443 int fs = params_rate(params);1444 int bclk;1445 int bclk_div;1446 int i;1447 int dsp_config;1448 int clk_config;1449 int best_val;1450 int cur_val;1451 int clk_sys;1452 1453 u16 aif1 = snd_soc_component_read(component, WM8903_AUDIO_INTERFACE_1);1454 u16 aif2 = snd_soc_component_read(component, WM8903_AUDIO_INTERFACE_2);1455 u16 aif3 = snd_soc_component_read(component, WM8903_AUDIO_INTERFACE_3);1456 u16 clock0 = snd_soc_component_read(component, WM8903_CLOCK_RATES_0);1457 u16 clock1 = snd_soc_component_read(component, WM8903_CLOCK_RATES_1);1458 u16 dac_digital1 = snd_soc_component_read(component, WM8903_DAC_DIGITAL_1);1459 1460 /* Enable sloping stopband filter for low sample rates */1461 if (fs <= 24000)1462 dac_digital1 |= WM8903_DAC_SB_FILT;1463 else1464 dac_digital1 &= ~WM8903_DAC_SB_FILT;1465 1466 /* Configure sample rate logic for DSP - choose nearest rate */1467 dsp_config = 0;1468 best_val = abs(sample_rates[dsp_config].rate - fs);1469 for (i = 1; i < ARRAY_SIZE(sample_rates); i++) {1470 cur_val = abs(sample_rates[i].rate - fs);1471 if (cur_val <= best_val) {1472 dsp_config = i;1473 best_val = cur_val;1474 }1475 }1476 1477 dev_dbg(component->dev, "DSP fs = %dHz\n", sample_rates[dsp_config].rate);1478 clock1 &= ~WM8903_SAMPLE_RATE_MASK;1479 clock1 |= sample_rates[dsp_config].value;1480 1481 aif1 &= ~WM8903_AIF_WL_MASK;1482 bclk = 2 * fs;1483 switch (params_width(params)) {1484 case 16:1485 bclk *= 16;1486 break;1487 case 20:1488 bclk *= 20;1489 aif1 |= 0x4;1490 break;1491 case 24:1492 bclk *= 24;1493 aif1 |= 0x8;1494 break;1495 case 32:1496 bclk *= 32;1497 aif1 |= 0xc;1498 break;1499 default:1500 return -EINVAL;1501 }1502 1503 dev_dbg(component->dev, "MCLK = %dHz, target sample rate = %dHz\n",1504 wm8903->sysclk, fs);1505 1506 /* We may not have an MCLK which allows us to generate exactly1507 * the clock we want, particularly with USB derived inputs, so1508 * approximate.1509 */1510 clk_config = 0;1511 best_val = abs((wm8903->sysclk /1512 (clk_sys_ratios[0].mclk_div *1513 clk_sys_ratios[0].div)) - fs);1514 for (i = 1; i < ARRAY_SIZE(clk_sys_ratios); i++) {1515 cur_val = abs((wm8903->sysclk /1516 (clk_sys_ratios[i].mclk_div *1517 clk_sys_ratios[i].div)) - fs);1518 1519 if (cur_val <= best_val) {1520 clk_config = i;1521 best_val = cur_val;1522 }1523 }1524 1525 if (clk_sys_ratios[clk_config].mclk_div == 2) {1526 clock0 |= WM8903_MCLKDIV2;1527 clk_sys = wm8903->sysclk / 2;1528 } else {1529 clock0 &= ~WM8903_MCLKDIV2;1530 clk_sys = wm8903->sysclk;1531 }1532 1533 clock1 &= ~(WM8903_CLK_SYS_RATE_MASK |1534 WM8903_CLK_SYS_MODE_MASK);1535 clock1 |= clk_sys_ratios[clk_config].rate << WM8903_CLK_SYS_RATE_SHIFT;1536 clock1 |= clk_sys_ratios[clk_config].mode << WM8903_CLK_SYS_MODE_SHIFT;1537 1538 dev_dbg(component->dev, "CLK_SYS_RATE=%x, CLK_SYS_MODE=%x div=%d\n",1539 clk_sys_ratios[clk_config].rate,1540 clk_sys_ratios[clk_config].mode,1541 clk_sys_ratios[clk_config].div);1542 1543 dev_dbg(component->dev, "Actual CLK_SYS = %dHz\n", clk_sys);1544 1545 /* We may not get quite the right frequency if using1546 * approximate clocks so look for the closest match that is1547 * higher than the target (we need to ensure that there enough1548 * BCLKs to clock out the samples).1549 */1550 bclk_div = 0;1551 i = 1;1552 while (i < ARRAY_SIZE(bclk_divs)) {1553 cur_val = ((clk_sys * 10) / bclk_divs[i].ratio) - bclk;1554 if (cur_val < 0) /* BCLK table is sorted */1555 break;1556 bclk_div = i;1557 i++;1558 }1559 1560 aif2 &= ~WM8903_BCLK_DIV_MASK;1561 aif3 &= ~WM8903_LRCLK_RATE_MASK;1562 1563 dev_dbg(component->dev, "BCLK ratio %d for %dHz - actual BCLK = %dHz\n",1564 bclk_divs[bclk_div].ratio / 10, bclk,1565 (clk_sys * 10) / bclk_divs[bclk_div].ratio);1566 1567 aif2 |= bclk_divs[bclk_div].div;1568 aif3 |= bclk / fs;1569 1570 wm8903->fs = params_rate(params);1571 wm8903_set_deemph(component);1572 1573 snd_soc_component_write(component, WM8903_CLOCK_RATES_0, clock0);1574 snd_soc_component_write(component, WM8903_CLOCK_RATES_1, clock1);1575 snd_soc_component_write(component, WM8903_AUDIO_INTERFACE_1, aif1);1576 snd_soc_component_write(component, WM8903_AUDIO_INTERFACE_2, aif2);1577 snd_soc_component_write(component, WM8903_AUDIO_INTERFACE_3, aif3);1578 snd_soc_component_write(component, WM8903_DAC_DIGITAL_1, dac_digital1);1579 1580 return 0;1581}1582 1583/**1584 * wm8903_mic_detect - Enable microphone detection via the WM8903 IRQ1585 *1586 * @component: WM8903 component1587 * @jack: jack to report detection events on1588 * @det: value to report for presence detection1589 * @shrt: value to report for short detection1590 *1591 * Enable microphone detection via IRQ on the WM8903. If GPIOs are1592 * being used to bring out signals to the processor then only platform1593 * data configuration is needed for WM8903 and processor GPIOs should1594 * be configured using snd_soc_jack_add_gpios() instead.1595 *1596 * The current threasholds for detection should be configured using1597 * micdet_cfg in the platform data. Using this function will force on1598 * the microphone bias for the device.1599 */1600int wm8903_mic_detect(struct snd_soc_component *component, struct snd_soc_jack *jack,1601 int det, int shrt)1602{1603 struct wm8903_priv *wm8903 = snd_soc_component_get_drvdata(component);1604 int irq_mask = WM8903_MICDET_EINT | WM8903_MICSHRT_EINT;1605 1606 dev_dbg(component->dev, "Enabling microphone detection: %x %x\n",1607 det, shrt);1608 1609 /* Store the configuration */1610 wm8903->mic_jack = jack;1611 wm8903->mic_det = det;1612 wm8903->mic_short = shrt;1613 1614 /* Enable interrupts we've got a report configured for */1615 if (det)1616 irq_mask &= ~WM8903_MICDET_EINT;1617 if (shrt)1618 irq_mask &= ~WM8903_MICSHRT_EINT;1619 1620 snd_soc_component_update_bits(component, WM8903_INTERRUPT_STATUS_1_MASK,1621 WM8903_MICDET_EINT | WM8903_MICSHRT_EINT,1622 irq_mask);1623 1624 if (det || shrt) {1625 /* Enable mic detection, this may not have been set through1626 * platform data (eg, if the defaults are OK). */1627 snd_soc_component_update_bits(component, WM8903_WRITE_SEQUENCER_0,1628 WM8903_WSEQ_ENA, WM8903_WSEQ_ENA);1629 snd_soc_component_update_bits(component, WM8903_MIC_BIAS_CONTROL_0,1630 WM8903_MICDET_ENA, WM8903_MICDET_ENA);1631 } else {1632 snd_soc_component_update_bits(component, WM8903_MIC_BIAS_CONTROL_0,1633 WM8903_MICDET_ENA, 0);1634 }1635 1636 return 0;1637}1638EXPORT_SYMBOL_GPL(wm8903_mic_detect);1639 1640static irqreturn_t wm8903_irq(int irq, void *data)1641{1642 struct wm8903_priv *wm8903 = data;1643 int mic_report, ret;1644 unsigned int int_val, mask, int_pol;1645 1646 ret = regmap_read(wm8903->regmap, WM8903_INTERRUPT_STATUS_1_MASK,1647 &mask);1648 if (ret != 0) {1649 dev_err(wm8903->dev, "Failed to read IRQ mask: %d\n", ret);1650 return IRQ_NONE;1651 }1652 1653 ret = regmap_read(wm8903->regmap, WM8903_INTERRUPT_STATUS_1, &int_val);1654 if (ret != 0) {1655 dev_err(wm8903->dev, "Failed to read IRQ status: %d\n", ret);1656 return IRQ_NONE;1657 }1658 1659 int_val &= ~mask;1660 1661 if (int_val & WM8903_WSEQ_BUSY_EINT) {1662 dev_warn(wm8903->dev, "Write sequencer done\n");1663 }1664 1665 /*1666 * The rest is microphone jack detection. We need to manually1667 * invert the polarity of the interrupt after each event - to1668 * simplify the code keep track of the last state we reported1669 * and just invert the relevant bits in both the report and1670 * the polarity register.1671 */1672 mic_report = wm8903->mic_last_report;1673 ret = regmap_read(wm8903->regmap, WM8903_INTERRUPT_POLARITY_1,1674 &int_pol);1675 if (ret != 0) {1676 dev_err(wm8903->dev, "Failed to read interrupt polarity: %d\n",1677 ret);1678 return IRQ_HANDLED;1679 }1680 1681#ifndef CONFIG_SND_SOC_WM8903_MODULE1682 if (int_val & (WM8903_MICSHRT_EINT | WM8903_MICDET_EINT))1683 trace_snd_soc_jack_irq(dev_name(wm8903->dev));1684#endif1685 1686 if (int_val & WM8903_MICSHRT_EINT) {1687 dev_dbg(wm8903->dev, "Microphone short (pol=%x)\n", int_pol);1688 1689 mic_report ^= wm8903->mic_short;1690 int_pol ^= WM8903_MICSHRT_INV;1691 }1692 1693 if (int_val & WM8903_MICDET_EINT) {1694 dev_dbg(wm8903->dev, "Microphone detect (pol=%x)\n", int_pol);1695 1696 mic_report ^= wm8903->mic_det;1697 int_pol ^= WM8903_MICDET_INV;1698 1699 msleep(wm8903->mic_delay);1700 }1701 1702 regmap_update_bits(wm8903->regmap, WM8903_INTERRUPT_POLARITY_1,1703 WM8903_MICSHRT_INV | WM8903_MICDET_INV, int_pol);1704 1705 snd_soc_jack_report(wm8903->mic_jack, mic_report,1706 wm8903->mic_short | wm8903->mic_det);1707 1708 wm8903->mic_last_report = mic_report;1709 1710 return IRQ_HANDLED;1711}1712 1713#define WM8903_PLAYBACK_RATES (SNDRV_PCM_RATE_8000 |\1714 SNDRV_PCM_RATE_11025 | \1715 SNDRV_PCM_RATE_16000 | \1716 SNDRV_PCM_RATE_22050 | \1717 SNDRV_PCM_RATE_32000 | \1718 SNDRV_PCM_RATE_44100 | \1719 SNDRV_PCM_RATE_48000 | \1720 SNDRV_PCM_RATE_88200 | \1721 SNDRV_PCM_RATE_96000)1722 1723#define WM8903_CAPTURE_RATES (SNDRV_PCM_RATE_8000 |\1724 SNDRV_PCM_RATE_11025 | \1725 SNDRV_PCM_RATE_16000 | \1726 SNDRV_PCM_RATE_22050 | \1727 SNDRV_PCM_RATE_32000 | \1728 SNDRV_PCM_RATE_44100 | \1729 SNDRV_PCM_RATE_48000)1730 1731#define WM8903_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\1732 SNDRV_PCM_FMTBIT_S20_3LE |\1733 SNDRV_PCM_FMTBIT_S24_LE)1734 1735static const struct snd_soc_dai_ops wm8903_dai_ops = {1736 .hw_params = wm8903_hw_params,1737 .mute_stream = wm8903_mute,1738 .set_fmt = wm8903_set_dai_fmt,1739 .set_sysclk = wm8903_set_dai_sysclk,1740 .no_capture_mute = 1,1741};1742 1743static struct snd_soc_dai_driver wm8903_dai = {1744 .name = "wm8903-hifi",1745 .playback = {1746 .stream_name = "Playback",1747 .channels_min = 2,1748 .channels_max = 2,1749 .rates = WM8903_PLAYBACK_RATES,1750 .formats = WM8903_FORMATS,1751 },1752 .capture = {1753 .stream_name = "Capture",1754 .channels_min = 2,1755 .channels_max = 2,1756 .rates = WM8903_CAPTURE_RATES,1757 .formats = WM8903_FORMATS,1758 },1759 .ops = &wm8903_dai_ops,1760 .symmetric_rate = 1,1761};1762 1763static int wm8903_resume(struct snd_soc_component *component)1764{1765 struct wm8903_priv *wm8903 = snd_soc_component_get_drvdata(component);1766 1767 regcache_sync(wm8903->regmap);1768 1769 return 0;1770}1771 1772#ifdef CONFIG_GPIOLIB1773static int wm8903_gpio_request(struct gpio_chip *chip, unsigned offset)1774{1775 if (offset >= WM8903_NUM_GPIO)1776 return -EINVAL;1777 1778 return 0;1779}1780 1781static int wm8903_gpio_direction_in(struct gpio_chip *chip, unsigned offset)1782{1783 struct wm8903_priv *wm8903 = gpiochip_get_data(chip);1784 unsigned int mask, val;1785 int ret;1786 1787 mask = WM8903_GP1_FN_MASK | WM8903_GP1_DIR_MASK;1788 val = (WM8903_GPn_FN_GPIO_INPUT << WM8903_GP1_FN_SHIFT) |1789 WM8903_GP1_DIR;1790 1791 ret = regmap_update_bits(wm8903->regmap,1792 WM8903_GPIO_CONTROL_1 + offset, mask, val);1793 if (ret < 0)1794 return ret;1795 1796 return 0;1797}1798 1799static int wm8903_gpio_get(struct gpio_chip *chip, unsigned offset)1800{1801 struct wm8903_priv *wm8903 = gpiochip_get_data(chip);1802 unsigned int reg;1803 1804 regmap_read(wm8903->regmap, WM8903_GPIO_CONTROL_1 + offset, ®);1805 1806 return !!((reg & WM8903_GP1_LVL_MASK) >> WM8903_GP1_LVL_SHIFT);1807}1808 1809static int wm8903_gpio_direction_out(struct gpio_chip *chip,1810 unsigned offset, int value)1811{1812 struct wm8903_priv *wm8903 = gpiochip_get_data(chip);1813 unsigned int mask, val;1814 int ret;1815 1816 mask = WM8903_GP1_FN_MASK | WM8903_GP1_DIR_MASK | WM8903_GP1_LVL_MASK;1817 val = (WM8903_GPn_FN_GPIO_OUTPUT << WM8903_GP1_FN_SHIFT) |1818 (value << WM8903_GP2_LVL_SHIFT);1819 1820 ret = regmap_update_bits(wm8903->regmap,1821 WM8903_GPIO_CONTROL_1 + offset, mask, val);1822 if (ret < 0)1823 return ret;1824 1825 return 0;1826}1827 1828static void wm8903_gpio_set(struct gpio_chip *chip, unsigned offset, int value)1829{1830 struct wm8903_priv *wm8903 = gpiochip_get_data(chip);1831 1832 regmap_update_bits(wm8903->regmap, WM8903_GPIO_CONTROL_1 + offset,1833 WM8903_GP1_LVL_MASK,1834 !!value << WM8903_GP1_LVL_SHIFT);1835}1836 1837static const struct gpio_chip wm8903_template_chip = {1838 .label = "wm8903",1839 .owner = THIS_MODULE,1840 .request = wm8903_gpio_request,1841 .direction_input = wm8903_gpio_direction_in,1842 .get = wm8903_gpio_get,1843 .direction_output = wm8903_gpio_direction_out,1844 .set = wm8903_gpio_set,1845 .can_sleep = 1,1846};1847 1848static void wm8903_init_gpio(struct wm8903_priv *wm8903)1849{1850 struct wm8903_platform_data *pdata = wm8903->pdata;1851 int ret;1852 1853 wm8903->gpio_chip = wm8903_template_chip;1854 wm8903->gpio_chip.ngpio = WM8903_NUM_GPIO;1855 wm8903->gpio_chip.parent = wm8903->dev;1856 1857 if (pdata->gpio_base)1858 wm8903->gpio_chip.base = pdata->gpio_base;1859 else1860 wm8903->gpio_chip.base = -1;1861 1862 ret = gpiochip_add_data(&wm8903->gpio_chip, wm8903);1863 if (ret != 0)1864 dev_err(wm8903->dev, "Failed to add GPIOs: %d\n", ret);1865}1866 1867static void wm8903_free_gpio(struct wm8903_priv *wm8903)1868{1869 gpiochip_remove(&wm8903->gpio_chip);1870}1871#else1872static void wm8903_init_gpio(struct wm8903_priv *wm8903)1873{1874}1875 1876static void wm8903_free_gpio(struct wm8903_priv *wm8903)1877{1878}1879#endif1880 1881static const struct snd_soc_component_driver soc_component_dev_wm8903 = {1882 .resume = wm8903_resume,1883 .set_bias_level = wm8903_set_bias_level,1884 .seq_notifier = wm8903_seq_notifier,1885 .controls = wm8903_snd_controls,1886 .num_controls = ARRAY_SIZE(wm8903_snd_controls),1887 .dapm_widgets = wm8903_dapm_widgets,1888 .num_dapm_widgets = ARRAY_SIZE(wm8903_dapm_widgets),1889 .dapm_routes = wm8903_intercon,1890 .num_dapm_routes = ARRAY_SIZE(wm8903_intercon),1891 .suspend_bias_off = 1,1892 .idle_bias_on = 1,1893 .use_pmdown_time = 1,1894 .endianness = 1,1895};1896 1897static const struct regmap_config wm8903_regmap = {1898 .reg_bits = 8,1899 .val_bits = 16,1900 1901 .max_register = WM8903_MAX_REGISTER,1902 .volatile_reg = wm8903_volatile_register,1903 .readable_reg = wm8903_readable_register,1904 1905 .cache_type = REGCACHE_MAPLE,1906 .reg_defaults = wm8903_reg_defaults,1907 .num_reg_defaults = ARRAY_SIZE(wm8903_reg_defaults),1908};1909 1910static int wm8903_set_pdata_irq_trigger(struct i2c_client *i2c,1911 struct wm8903_platform_data *pdata)1912{1913 struct irq_data *irq_data = irq_get_irq_data(i2c->irq);1914 if (!irq_data) {1915 dev_err(&i2c->dev, "Invalid IRQ: %d\n",1916 i2c->irq);1917 return -EINVAL;1918 }1919 1920 switch (irqd_get_trigger_type(irq_data)) {1921 case IRQ_TYPE_NONE:1922 default:1923 /*1924 * We assume the controller imposes no restrictions,1925 * so we are able to select active-high1926 */1927 fallthrough;1928 case IRQ_TYPE_LEVEL_HIGH:1929 pdata->irq_active_low = false;1930 break;1931 case IRQ_TYPE_LEVEL_LOW:1932 pdata->irq_active_low = true;1933 break;1934 }1935 1936 return 0;1937}1938 1939static int wm8903_set_pdata_from_of(struct i2c_client *i2c,1940 struct wm8903_platform_data *pdata)1941{1942 const struct device_node *np = i2c->dev.of_node;1943 u32 val32;1944 int i;1945 1946 if (of_property_read_u32(np, "micdet-cfg", &val32) >= 0)1947 pdata->micdet_cfg = val32;1948 1949 if (of_property_read_u32(np, "micdet-delay", &val32) >= 0)1950 pdata->micdet_delay = val32;1951 1952 if (of_property_read_u32_array(np, "gpio-cfg", pdata->gpio_cfg,1953 ARRAY_SIZE(pdata->gpio_cfg)) >= 0) {1954 /*1955 * In device tree: 0 means "write 0",1956 * 0xffffffff means "don't touch".1957 *1958 * In platform data: 0 means "don't touch",1959 * 0x8000 means "write 0".1960 *1961 * Note: WM8903_GPIO_CONFIG_ZERO == 0x8000.1962 *1963 * Convert from DT to pdata representation here,1964 * so no other code needs to change.1965 */1966 for (i = 0; i < ARRAY_SIZE(pdata->gpio_cfg); i++) {1967 if (pdata->gpio_cfg[i] == 0) {1968 pdata->gpio_cfg[i] = WM8903_GPIO_CONFIG_ZERO;1969 } else if (pdata->gpio_cfg[i] == 0xffffffff) {1970 pdata->gpio_cfg[i] = 0;1971 } else if (pdata->gpio_cfg[i] > 0x7fff) {1972 dev_err(&i2c->dev, "Invalid gpio-cfg[%d] %x\n",1973 i, pdata->gpio_cfg[i]);1974 return -EINVAL;1975 }1976 }1977 }1978 1979 return 0;1980}1981 1982static int wm8903_i2c_probe(struct i2c_client *i2c)1983{1984 struct wm8903_platform_data *pdata = dev_get_platdata(&i2c->dev);1985 struct wm8903_priv *wm8903;1986 int trigger;1987 bool mic_gpio = false;1988 unsigned int val, irq_pol;1989 int ret, i;1990 1991 wm8903 = devm_kzalloc(&i2c->dev, sizeof(*wm8903), GFP_KERNEL);1992 if (wm8903 == NULL)1993 return -ENOMEM;1994 1995 mutex_init(&wm8903->lock);1996 wm8903->dev = &i2c->dev;1997 1998 wm8903->regmap = devm_regmap_init_i2c(i2c, &wm8903_regmap);1999 if (IS_ERR(wm8903->regmap)) {2000 ret = PTR_ERR(wm8903->regmap);2001 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",2002 ret);2003 return ret;2004 }2005 2006 i2c_set_clientdata(i2c, wm8903);2007 2008 /* If no platform data was supplied, create storage for defaults */2009 if (pdata) {2010 wm8903->pdata = pdata;2011 } else {2012 wm8903->pdata = devm_kzalloc(&i2c->dev, sizeof(*wm8903->pdata),2013 GFP_KERNEL);2014 if (!wm8903->pdata)2015 return -ENOMEM;2016 2017 if (i2c->irq) {2018 ret = wm8903_set_pdata_irq_trigger(i2c, wm8903->pdata);2019 if (ret != 0)2020 return ret;2021 }2022 2023 if (i2c->dev.of_node) {2024 ret = wm8903_set_pdata_from_of(i2c, wm8903->pdata);2025 if (ret != 0)2026 return ret;2027 }2028 }2029 2030 pdata = wm8903->pdata;2031 2032 for (i = 0; i < ARRAY_SIZE(wm8903->supplies); i++)2033 wm8903->supplies[i].supply = wm8903_supply_names[i];2034 2035 ret = devm_regulator_bulk_get(&i2c->dev, ARRAY_SIZE(wm8903->supplies),2036 wm8903->supplies);2037 if (ret != 0) {2038 dev_err(&i2c->dev, "Failed to request supplies: %d\n", ret);2039 return ret;2040 }2041 2042 ret = regulator_bulk_enable(ARRAY_SIZE(wm8903->supplies),2043 wm8903->supplies);2044 if (ret != 0) {2045 dev_err(&i2c->dev, "Failed to enable supplies: %d\n", ret);2046 return ret;2047 }2048 2049 ret = regmap_read(wm8903->regmap, WM8903_SW_RESET_AND_ID, &val);2050 if (ret != 0) {2051 dev_err(&i2c->dev, "Failed to read chip ID: %d\n", ret);2052 goto err;2053 }2054 if (val != 0x8903) {2055 dev_err(&i2c->dev, "Device with ID %x is not a WM8903\n", val);2056 ret = -ENODEV;2057 goto err;2058 }2059 2060 ret = regmap_read(wm8903->regmap, WM8903_REVISION_NUMBER, &val);2061 if (ret != 0) {2062 dev_err(&i2c->dev, "Failed to read chip revision: %d\n", ret);2063 goto err;2064 }2065 dev_info(&i2c->dev, "WM8903 revision %c\n",2066 (val & WM8903_CHIP_REV_MASK) + 'A');2067 2068 /* Reset the device */2069 regmap_write(wm8903->regmap, WM8903_SW_RESET_AND_ID, 0x8903);2070 2071 wm8903_init_gpio(wm8903);2072 2073 /* Set up GPIO pin state, detect if any are MIC detect outputs */2074 for (i = 0; i < ARRAY_SIZE(pdata->gpio_cfg); i++) {2075 if ((!pdata->gpio_cfg[i]) ||2076 (pdata->gpio_cfg[i] > WM8903_GPIO_CONFIG_ZERO))2077 continue;2078 2079 regmap_write(wm8903->regmap, WM8903_GPIO_CONTROL_1 + i,2080 pdata->gpio_cfg[i] & 0x7fff);2081 2082 val = (pdata->gpio_cfg[i] & WM8903_GP1_FN_MASK)2083 >> WM8903_GP1_FN_SHIFT;2084 2085 switch (val) {2086 case WM8903_GPn_FN_MICBIAS_CURRENT_DETECT:2087 case WM8903_GPn_FN_MICBIAS_SHORT_DETECT:2088 mic_gpio = true;2089 break;2090 default:2091 break;2092 }2093 }2094 2095 /* Set up microphone detection */2096 regmap_write(wm8903->regmap, WM8903_MIC_BIAS_CONTROL_0,2097 pdata->micdet_cfg);2098 2099 /* Microphone detection needs the WSEQ clock */2100 if (pdata->micdet_cfg)2101 regmap_update_bits(wm8903->regmap, WM8903_WRITE_SEQUENCER_0,2102 WM8903_WSEQ_ENA, WM8903_WSEQ_ENA);2103 2104 /* If microphone detection is enabled by pdata but2105 * detected via IRQ then interrupts can be lost before2106 * the machine driver has set up microphone detection2107 * IRQs as the IRQs are clear on read. The detection2108 * will be enabled when the machine driver configures.2109 */2110 WARN_ON(!mic_gpio && (pdata->micdet_cfg & WM8903_MICDET_ENA));2111 2112 wm8903->mic_delay = pdata->micdet_delay;2113 2114 if (i2c->irq) {2115 if (pdata->irq_active_low) {2116 trigger = IRQF_TRIGGER_LOW;2117 irq_pol = WM8903_IRQ_POL;2118 } else {2119 trigger = IRQF_TRIGGER_HIGH;2120 irq_pol = 0;2121 }2122 2123 regmap_update_bits(wm8903->regmap, WM8903_INTERRUPT_CONTROL,2124 WM8903_IRQ_POL, irq_pol);2125 2126 ret = request_threaded_irq(i2c->irq, NULL, wm8903_irq,2127 trigger | IRQF_ONESHOT,2128 "wm8903", wm8903);2129 if (ret != 0) {2130 dev_err(wm8903->dev, "Failed to request IRQ: %d\n",2131 ret);2132 goto err;2133 }2134 2135 /* Enable write sequencer interrupts */2136 regmap_update_bits(wm8903->regmap,2137 WM8903_INTERRUPT_STATUS_1_MASK,2138 WM8903_IM_WSEQ_BUSY_EINT, 0);2139 }2140 2141 /* Latch volume update bits */2142 regmap_update_bits(wm8903->regmap, WM8903_ADC_DIGITAL_VOLUME_LEFT,2143 WM8903_ADCVU, WM8903_ADCVU);2144 regmap_update_bits(wm8903->regmap, WM8903_ADC_DIGITAL_VOLUME_RIGHT,2145 WM8903_ADCVU, WM8903_ADCVU);2146 2147 regmap_update_bits(wm8903->regmap, WM8903_DAC_DIGITAL_VOLUME_LEFT,2148 WM8903_DACVU, WM8903_DACVU);2149 regmap_update_bits(wm8903->regmap, WM8903_DAC_DIGITAL_VOLUME_RIGHT,2150 WM8903_DACVU, WM8903_DACVU);2151 2152 regmap_update_bits(wm8903->regmap, WM8903_ANALOGUE_OUT1_LEFT,2153 WM8903_HPOUTVU, WM8903_HPOUTVU);2154 regmap_update_bits(wm8903->regmap, WM8903_ANALOGUE_OUT1_RIGHT,2155 WM8903_HPOUTVU, WM8903_HPOUTVU);2156 2157 regmap_update_bits(wm8903->regmap, WM8903_ANALOGUE_OUT2_LEFT,2158 WM8903_LINEOUTVU, WM8903_LINEOUTVU);2159 regmap_update_bits(wm8903->regmap, WM8903_ANALOGUE_OUT2_RIGHT,2160 WM8903_LINEOUTVU, WM8903_LINEOUTVU);2161 2162 regmap_update_bits(wm8903->regmap, WM8903_ANALOGUE_OUT3_LEFT,2163 WM8903_SPKVU, WM8903_SPKVU);2164 regmap_update_bits(wm8903->regmap, WM8903_ANALOGUE_OUT3_RIGHT,2165 WM8903_SPKVU, WM8903_SPKVU);2166 2167 /* Enable DAC soft mute by default */2168 regmap_update_bits(wm8903->regmap, WM8903_DAC_DIGITAL_1,2169 WM8903_DAC_MUTEMODE | WM8903_DAC_MUTE,2170 WM8903_DAC_MUTEMODE | WM8903_DAC_MUTE);2171 2172 ret = devm_snd_soc_register_component(&i2c->dev,2173 &soc_component_dev_wm8903, &wm8903_dai, 1);2174 if (ret != 0)2175 goto err;2176 2177 return 0;2178err:2179 regulator_bulk_disable(ARRAY_SIZE(wm8903->supplies),2180 wm8903->supplies);2181 return ret;2182}2183 2184static void wm8903_i2c_remove(struct i2c_client *client)2185{2186 struct wm8903_priv *wm8903 = i2c_get_clientdata(client);2187 2188 regulator_bulk_disable(ARRAY_SIZE(wm8903->supplies),2189 wm8903->supplies);2190 if (client->irq)2191 free_irq(client->irq, wm8903);2192 wm8903_free_gpio(wm8903);2193}2194 2195static const struct of_device_id wm8903_of_match[] = {2196 { .compatible = "wlf,wm8903", },2197 {},2198};2199MODULE_DEVICE_TABLE(of, wm8903_of_match);2200 2201static const struct i2c_device_id wm8903_i2c_id[] = {2202 { "wm8903" },2203 { }2204};2205MODULE_DEVICE_TABLE(i2c, wm8903_i2c_id);2206 2207static struct i2c_driver wm8903_i2c_driver = {2208 .driver = {2209 .name = "wm8903",2210 .of_match_table = wm8903_of_match,2211 },2212 .probe = wm8903_i2c_probe,2213 .remove = wm8903_i2c_remove,2214 .id_table = wm8903_i2c_id,2215};2216 2217module_i2c_driver(wm8903_i2c_driver);2218 2219MODULE_DESCRIPTION("ASoC WM8903 driver");2220MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.cm>");2221MODULE_LICENSE("GPL");2222