994 lines · c
1// SPDX-License-Identifier: GPL-2.0-only2/*3 * wm8961.c -- WM8961 ALSA SoC Audio driver4 *5 * Copyright 2009-10 Wolfson Microelectronics, plc6 *7 * Author: Mark Brown8 *9 * Currently unimplemented features:10 * - ALC11 */12 13#include <linux/module.h>14#include <linux/moduleparam.h>15#include <linux/init.h>16#include <linux/delay.h>17#include <linux/pm.h>18#include <linux/i2c.h>19#include <linux/regmap.h>20#include <linux/slab.h>21#include <sound/core.h>22#include <sound/pcm.h>23#include <sound/pcm_params.h>24#include <sound/soc.h>25#include <sound/initval.h>26#include <sound/tlv.h>27 28#include "wm8961.h"29 30#define WM8961_MAX_REGISTER 0xFC31 32static const struct reg_default wm8961_reg_defaults[] = {33 { 0, 0x009F }, /* R0 - Left Input volume */34 { 1, 0x009F }, /* R1 - Right Input volume */35 { 2, 0x0000 }, /* R2 - LOUT1 volume */36 { 3, 0x0000 }, /* R3 - ROUT1 volume */37 { 4, 0x0020 }, /* R4 - Clocking1 */38 { 5, 0x0008 }, /* R5 - ADC & DAC Control 1 */39 { 6, 0x0000 }, /* R6 - ADC & DAC Control 2 */40 { 7, 0x000A }, /* R7 - Audio Interface 0 */41 { 8, 0x01F4 }, /* R8 - Clocking2 */42 { 9, 0x0000 }, /* R9 - Audio Interface 1 */43 { 10, 0x00FF }, /* R10 - Left DAC volume */44 { 11, 0x00FF }, /* R11 - Right DAC volume */45 46 { 14, 0x0040 }, /* R14 - Audio Interface 2 */47 48 { 17, 0x007B }, /* R17 - ALC1 */49 { 18, 0x0000 }, /* R18 - ALC2 */50 { 19, 0x0032 }, /* R19 - ALC3 */51 { 20, 0x0000 }, /* R20 - Noise Gate */52 { 21, 0x00C0 }, /* R21 - Left ADC volume */53 { 22, 0x00C0 }, /* R22 - Right ADC volume */54 { 23, 0x0120 }, /* R23 - Additional control(1) */55 { 24, 0x0000 }, /* R24 - Additional control(2) */56 { 25, 0x0000 }, /* R25 - Pwr Mgmt (1) */57 { 26, 0x0000 }, /* R26 - Pwr Mgmt (2) */58 { 27, 0x0000 }, /* R27 - Additional Control (3) */59 { 28, 0x0000 }, /* R28 - Anti-pop */60 61 { 30, 0x005F }, /* R30 - Clocking 3 */62 63 { 32, 0x0000 }, /* R32 - ADCL signal path */64 { 33, 0x0000 }, /* R33 - ADCR signal path */65 66 { 40, 0x0000 }, /* R40 - LOUT2 volume */67 { 41, 0x0000 }, /* R41 - ROUT2 volume */68 69 { 47, 0x0000 }, /* R47 - Pwr Mgmt (3) */70 { 48, 0x0023 }, /* R48 - Additional Control (4) */71 { 49, 0x0000 }, /* R49 - Class D Control 1 */72 73 { 51, 0x0003 }, /* R51 - Class D Control 2 */74 75 { 56, 0x0106 }, /* R56 - Clocking 4 */76 { 57, 0x0000 }, /* R57 - DSP Sidetone 0 */77 { 58, 0x0000 }, /* R58 - DSP Sidetone 1 */78 79 { 60, 0x0000 }, /* R60 - DC Servo 0 */80 { 61, 0x0000 }, /* R61 - DC Servo 1 */81 82 { 63, 0x015E }, /* R63 - DC Servo 3 */83 84 { 65, 0x0010 }, /* R65 - DC Servo 5 */85 86 { 68, 0x0003 }, /* R68 - Analogue PGA Bias */87 { 69, 0x0000 }, /* R69 - Analogue HP 0 */88 89 { 71, 0x01FB }, /* R71 - Analogue HP 2 */90 { 72, 0x0000 }, /* R72 - Charge Pump 1 */91 92 { 82, 0x0000 }, /* R82 - Charge Pump B */93 94 { 87, 0x0000 }, /* R87 - Write Sequencer 1 */95 { 88, 0x0000 }, /* R88 - Write Sequencer 2 */96 { 89, 0x0000 }, /* R89 - Write Sequencer 3 */97 { 90, 0x0000 }, /* R90 - Write Sequencer 4 */98 { 91, 0x0000 }, /* R91 - Write Sequencer 5 */99 { 92, 0x0000 }, /* R92 - Write Sequencer 6 */100 { 93, 0x0000 }, /* R93 - Write Sequencer 7 */101 102 { 252, 0x0001 }, /* R252 - General test 1 */103};104 105struct wm8961_priv {106 struct regmap *regmap;107 int sysclk;108};109 110static bool wm8961_volatile(struct device *dev, unsigned int reg)111{112 switch (reg) {113 case WM8961_SOFTWARE_RESET:114 case WM8961_WRITE_SEQUENCER_7:115 case WM8961_DC_SERVO_1:116 return true;117 118 default:119 return false;120 }121}122 123static bool wm8961_readable(struct device *dev, unsigned int reg)124{125 switch (reg) {126 case WM8961_LEFT_INPUT_VOLUME:127 case WM8961_RIGHT_INPUT_VOLUME:128 case WM8961_LOUT1_VOLUME:129 case WM8961_ROUT1_VOLUME:130 case WM8961_CLOCKING1:131 case WM8961_ADC_DAC_CONTROL_1:132 case WM8961_ADC_DAC_CONTROL_2:133 case WM8961_AUDIO_INTERFACE_0:134 case WM8961_CLOCKING2:135 case WM8961_AUDIO_INTERFACE_1:136 case WM8961_LEFT_DAC_VOLUME:137 case WM8961_RIGHT_DAC_VOLUME:138 case WM8961_AUDIO_INTERFACE_2:139 case WM8961_SOFTWARE_RESET:140 case WM8961_ALC1:141 case WM8961_ALC2:142 case WM8961_ALC3:143 case WM8961_NOISE_GATE:144 case WM8961_LEFT_ADC_VOLUME:145 case WM8961_RIGHT_ADC_VOLUME:146 case WM8961_ADDITIONAL_CONTROL_1:147 case WM8961_ADDITIONAL_CONTROL_2:148 case WM8961_PWR_MGMT_1:149 case WM8961_PWR_MGMT_2:150 case WM8961_ADDITIONAL_CONTROL_3:151 case WM8961_ANTI_POP:152 case WM8961_CLOCKING_3:153 case WM8961_ADCL_SIGNAL_PATH:154 case WM8961_ADCR_SIGNAL_PATH:155 case WM8961_LOUT2_VOLUME:156 case WM8961_ROUT2_VOLUME:157 case WM8961_PWR_MGMT_3:158 case WM8961_ADDITIONAL_CONTROL_4:159 case WM8961_CLASS_D_CONTROL_1:160 case WM8961_CLASS_D_CONTROL_2:161 case WM8961_CLOCKING_4:162 case WM8961_DSP_SIDETONE_0:163 case WM8961_DSP_SIDETONE_1:164 case WM8961_DC_SERVO_0:165 case WM8961_DC_SERVO_1:166 case WM8961_DC_SERVO_3:167 case WM8961_DC_SERVO_5:168 case WM8961_ANALOGUE_PGA_BIAS:169 case WM8961_ANALOGUE_HP_0:170 case WM8961_ANALOGUE_HP_2:171 case WM8961_CHARGE_PUMP_1:172 case WM8961_CHARGE_PUMP_B:173 case WM8961_WRITE_SEQUENCER_1:174 case WM8961_WRITE_SEQUENCER_2:175 case WM8961_WRITE_SEQUENCER_3:176 case WM8961_WRITE_SEQUENCER_4:177 case WM8961_WRITE_SEQUENCER_5:178 case WM8961_WRITE_SEQUENCER_6:179 case WM8961_WRITE_SEQUENCER_7:180 case WM8961_GENERAL_TEST_1:181 return true;182 default:183 return false;184 }185}186 187/*188 * The headphone output supports special anti-pop sequences giving189 * silent power up and power down.190 */191static int wm8961_hp_event(struct snd_soc_dapm_widget *w,192 struct snd_kcontrol *kcontrol, int event)193{194 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);195 u16 hp_reg = snd_soc_component_read(component, WM8961_ANALOGUE_HP_0);196 u16 cp_reg = snd_soc_component_read(component, WM8961_CHARGE_PUMP_1);197 u16 pwr_reg = snd_soc_component_read(component, WM8961_PWR_MGMT_2);198 u16 dcs_reg = snd_soc_component_read(component, WM8961_DC_SERVO_1);199 int timeout = 500;200 201 if (event & SND_SOC_DAPM_POST_PMU) {202 /* Make sure the output is shorted */203 hp_reg &= ~(WM8961_HPR_RMV_SHORT | WM8961_HPL_RMV_SHORT);204 snd_soc_component_write(component, WM8961_ANALOGUE_HP_0, hp_reg);205 206 /* Enable the charge pump */207 cp_reg |= WM8961_CP_ENA;208 snd_soc_component_write(component, WM8961_CHARGE_PUMP_1, cp_reg);209 mdelay(5);210 211 /* Enable the PGA */212 pwr_reg |= WM8961_LOUT1_PGA | WM8961_ROUT1_PGA;213 snd_soc_component_write(component, WM8961_PWR_MGMT_2, pwr_reg);214 215 /* Enable the amplifier */216 hp_reg |= WM8961_HPR_ENA | WM8961_HPL_ENA;217 snd_soc_component_write(component, WM8961_ANALOGUE_HP_0, hp_reg);218 219 /* Second stage enable */220 hp_reg |= WM8961_HPR_ENA_DLY | WM8961_HPL_ENA_DLY;221 snd_soc_component_write(component, WM8961_ANALOGUE_HP_0, hp_reg);222 223 /* Enable the DC servo & trigger startup */224 dcs_reg |=225 WM8961_DCS_ENA_CHAN_HPR | WM8961_DCS_TRIG_STARTUP_HPR |226 WM8961_DCS_ENA_CHAN_HPL | WM8961_DCS_TRIG_STARTUP_HPL;227 dev_dbg(component->dev, "Enabling DC servo\n");228 229 snd_soc_component_write(component, WM8961_DC_SERVO_1, dcs_reg);230 do {231 msleep(1);232 dcs_reg = snd_soc_component_read(component, WM8961_DC_SERVO_1);233 } while (--timeout &&234 dcs_reg & (WM8961_DCS_TRIG_STARTUP_HPR |235 WM8961_DCS_TRIG_STARTUP_HPL));236 if (dcs_reg & (WM8961_DCS_TRIG_STARTUP_HPR |237 WM8961_DCS_TRIG_STARTUP_HPL))238 dev_err(component->dev, "DC servo timed out\n");239 else240 dev_dbg(component->dev, "DC servo startup complete\n");241 242 /* Enable the output stage */243 hp_reg |= WM8961_HPR_ENA_OUTP | WM8961_HPL_ENA_OUTP;244 snd_soc_component_write(component, WM8961_ANALOGUE_HP_0, hp_reg);245 246 /* Remove the short on the output stage */247 hp_reg |= WM8961_HPR_RMV_SHORT | WM8961_HPL_RMV_SHORT;248 snd_soc_component_write(component, WM8961_ANALOGUE_HP_0, hp_reg);249 }250 251 if (event & SND_SOC_DAPM_PRE_PMD) {252 /* Short the output */253 hp_reg &= ~(WM8961_HPR_RMV_SHORT | WM8961_HPL_RMV_SHORT);254 snd_soc_component_write(component, WM8961_ANALOGUE_HP_0, hp_reg);255 256 /* Disable the output stage */257 hp_reg &= ~(WM8961_HPR_ENA_OUTP | WM8961_HPL_ENA_OUTP);258 snd_soc_component_write(component, WM8961_ANALOGUE_HP_0, hp_reg);259 260 /* Disable DC offset cancellation */261 dcs_reg &= ~(WM8961_DCS_ENA_CHAN_HPR |262 WM8961_DCS_ENA_CHAN_HPL);263 snd_soc_component_write(component, WM8961_DC_SERVO_1, dcs_reg);264 265 /* Finish up */266 hp_reg &= ~(WM8961_HPR_ENA_DLY | WM8961_HPR_ENA |267 WM8961_HPL_ENA_DLY | WM8961_HPL_ENA);268 snd_soc_component_write(component, WM8961_ANALOGUE_HP_0, hp_reg);269 270 /* Disable the PGA */271 pwr_reg &= ~(WM8961_LOUT1_PGA | WM8961_ROUT1_PGA);272 snd_soc_component_write(component, WM8961_PWR_MGMT_2, pwr_reg);273 274 /* Disable the charge pump */275 dev_dbg(component->dev, "Disabling charge pump\n");276 snd_soc_component_write(component, WM8961_CHARGE_PUMP_1,277 cp_reg & ~WM8961_CP_ENA);278 }279 280 return 0;281}282 283static int wm8961_spk_event(struct snd_soc_dapm_widget *w,284 struct snd_kcontrol *kcontrol, int event)285{286 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);287 u16 pwr_reg = snd_soc_component_read(component, WM8961_PWR_MGMT_2);288 u16 spk_reg = snd_soc_component_read(component, WM8961_CLASS_D_CONTROL_1);289 290 if (event & SND_SOC_DAPM_POST_PMU) {291 /* Enable the PGA */292 pwr_reg |= WM8961_SPKL_PGA | WM8961_SPKR_PGA;293 snd_soc_component_write(component, WM8961_PWR_MGMT_2, pwr_reg);294 295 /* Enable the amplifier */296 spk_reg |= WM8961_SPKL_ENA | WM8961_SPKR_ENA;297 snd_soc_component_write(component, WM8961_CLASS_D_CONTROL_1, spk_reg);298 }299 300 if (event & SND_SOC_DAPM_PRE_PMD) {301 /* Disable the amplifier */302 spk_reg &= ~(WM8961_SPKL_ENA | WM8961_SPKR_ENA);303 snd_soc_component_write(component, WM8961_CLASS_D_CONTROL_1, spk_reg);304 305 /* Disable the PGA */306 pwr_reg &= ~(WM8961_SPKL_PGA | WM8961_SPKR_PGA);307 snd_soc_component_write(component, WM8961_PWR_MGMT_2, pwr_reg);308 }309 310 return 0;311}312 313static const char *adc_hpf_text[] = {314 "Hi-fi", "Voice 1", "Voice 2", "Voice 3",315};316 317static SOC_ENUM_SINGLE_DECL(adc_hpf,318 WM8961_ADC_DAC_CONTROL_2, 7, adc_hpf_text);319 320static const char *dac_deemph_text[] = {321 "None", "32kHz", "44.1kHz", "48kHz",322};323 324static SOC_ENUM_SINGLE_DECL(dac_deemph,325 WM8961_ADC_DAC_CONTROL_1, 1, dac_deemph_text);326 327static const DECLARE_TLV_DB_SCALE(out_tlv, -12100, 100, 1);328static const DECLARE_TLV_DB_SCALE(hp_sec_tlv, -700, 100, 0);329static const DECLARE_TLV_DB_SCALE(adc_tlv, -7200, 75, 1);330static const DECLARE_TLV_DB_SCALE(sidetone_tlv, -3600, 300, 0);331static const DECLARE_TLV_DB_RANGE(boost_tlv,332 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),333 1, 1, TLV_DB_SCALE_ITEM(13, 0, 0),334 2, 2, TLV_DB_SCALE_ITEM(20, 0, 0),335 3, 3, TLV_DB_SCALE_ITEM(29, 0, 0)336);337static const DECLARE_TLV_DB_SCALE(pga_tlv, -2325, 75, 0);338 339static const struct snd_kcontrol_new wm8961_snd_controls[] = {340SOC_DOUBLE_R_TLV("Headphone Volume", WM8961_LOUT1_VOLUME, WM8961_ROUT1_VOLUME,341 0, 127, 0, out_tlv),342SOC_DOUBLE_TLV("Headphone Secondary Volume", WM8961_ANALOGUE_HP_2,343 6, 3, 7, 0, hp_sec_tlv),344SOC_DOUBLE_R("Headphone ZC Switch", WM8961_LOUT1_VOLUME, WM8961_ROUT1_VOLUME,345 7, 1, 0),346 347SOC_DOUBLE_R_TLV("Speaker Volume", WM8961_LOUT2_VOLUME, WM8961_ROUT2_VOLUME,348 0, 127, 0, out_tlv),349SOC_DOUBLE_R("Speaker ZC Switch", WM8961_LOUT2_VOLUME, WM8961_ROUT2_VOLUME,350 7, 1, 0),351SOC_SINGLE("Speaker AC Gain", WM8961_CLASS_D_CONTROL_2, 0, 7, 0),352 353SOC_SINGLE("DAC x128 OSR Switch", WM8961_ADC_DAC_CONTROL_2, 0, 1, 0),354SOC_ENUM("DAC Deemphasis", dac_deemph),355SOC_SINGLE("DAC Soft Mute Switch", WM8961_ADC_DAC_CONTROL_2, 3, 1, 0),356 357SOC_DOUBLE_R_TLV("Sidetone Volume", WM8961_DSP_SIDETONE_0,358 WM8961_DSP_SIDETONE_1, 4, 12, 0, sidetone_tlv),359 360SOC_SINGLE("ADC High Pass Filter Switch", WM8961_ADC_DAC_CONTROL_1, 0, 1, 0),361SOC_ENUM("ADC High Pass Filter Mode", adc_hpf),362 363SOC_DOUBLE_R_TLV("Capture Volume",364 WM8961_LEFT_ADC_VOLUME, WM8961_RIGHT_ADC_VOLUME,365 1, 119, 0, adc_tlv),366SOC_DOUBLE_R_TLV("Capture Boost Volume",367 WM8961_ADCL_SIGNAL_PATH, WM8961_ADCR_SIGNAL_PATH,368 4, 3, 0, boost_tlv),369SOC_DOUBLE_R_TLV("Capture PGA Volume",370 WM8961_LEFT_INPUT_VOLUME, WM8961_RIGHT_INPUT_VOLUME,371 0, 62, 0, pga_tlv),372SOC_DOUBLE_R("Capture PGA ZC Switch",373 WM8961_LEFT_INPUT_VOLUME, WM8961_RIGHT_INPUT_VOLUME,374 6, 1, 1),375SOC_DOUBLE_R("Capture PGA Switch",376 WM8961_LEFT_INPUT_VOLUME, WM8961_RIGHT_INPUT_VOLUME,377 7, 1, 1),378};379 380static const char *sidetone_text[] = {381 "None", "Left", "Right"382};383 384static SOC_ENUM_SINGLE_DECL(dacl_sidetone,385 WM8961_DSP_SIDETONE_0, 2, sidetone_text);386 387static SOC_ENUM_SINGLE_DECL(dacr_sidetone,388 WM8961_DSP_SIDETONE_1, 2, sidetone_text);389 390static const struct snd_kcontrol_new dacl_mux =391 SOC_DAPM_ENUM("DACL Sidetone", dacl_sidetone);392 393static const struct snd_kcontrol_new dacr_mux =394 SOC_DAPM_ENUM("DACR Sidetone", dacr_sidetone);395 396static const struct snd_soc_dapm_widget wm8961_dapm_widgets[] = {397SND_SOC_DAPM_INPUT("LINPUT"),398SND_SOC_DAPM_INPUT("RINPUT"),399 400SND_SOC_DAPM_SUPPLY("CLK_DSP", WM8961_CLOCKING2, 4, 0, NULL, 0),401 402SND_SOC_DAPM_PGA("Left Input", WM8961_PWR_MGMT_1, 5, 0, NULL, 0),403SND_SOC_DAPM_PGA("Right Input", WM8961_PWR_MGMT_1, 4, 0, NULL, 0),404 405SND_SOC_DAPM_ADC("ADCL", "HiFi Capture", WM8961_PWR_MGMT_1, 3, 0),406SND_SOC_DAPM_ADC("ADCR", "HiFi Capture", WM8961_PWR_MGMT_1, 2, 0),407 408SND_SOC_DAPM_SUPPLY("MICBIAS", WM8961_PWR_MGMT_1, 1, 0, NULL, 0),409 410SND_SOC_DAPM_MUX("DACL Sidetone", SND_SOC_NOPM, 0, 0, &dacl_mux),411SND_SOC_DAPM_MUX("DACR Sidetone", SND_SOC_NOPM, 0, 0, &dacr_mux),412 413SND_SOC_DAPM_DAC("DACL", "HiFi Playback", WM8961_PWR_MGMT_2, 8, 0),414SND_SOC_DAPM_DAC("DACR", "HiFi Playback", WM8961_PWR_MGMT_2, 7, 0),415 416/* Handle as a mono path for DCS */417SND_SOC_DAPM_PGA_E("Headphone Output", SND_SOC_NOPM,418 4, 0, NULL, 0, wm8961_hp_event,419 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),420SND_SOC_DAPM_PGA_E("Speaker Output", SND_SOC_NOPM,421 4, 0, NULL, 0, wm8961_spk_event,422 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),423 424SND_SOC_DAPM_OUTPUT("HP_L"),425SND_SOC_DAPM_OUTPUT("HP_R"),426SND_SOC_DAPM_OUTPUT("SPK_LN"),427SND_SOC_DAPM_OUTPUT("SPK_LP"),428SND_SOC_DAPM_OUTPUT("SPK_RN"),429SND_SOC_DAPM_OUTPUT("SPK_RP"),430};431 432 433static const struct snd_soc_dapm_route audio_paths[] = {434 { "DACL", NULL, "CLK_DSP" },435 { "DACL", NULL, "DACL Sidetone" },436 { "DACR", NULL, "CLK_DSP" },437 { "DACR", NULL, "DACR Sidetone" },438 439 { "DACL Sidetone", "Left", "ADCL" },440 { "DACL Sidetone", "Right", "ADCR" },441 442 { "DACR Sidetone", "Left", "ADCL" },443 { "DACR Sidetone", "Right", "ADCR" },444 445 { "HP_L", NULL, "Headphone Output" },446 { "HP_R", NULL, "Headphone Output" },447 { "Headphone Output", NULL, "DACL" },448 { "Headphone Output", NULL, "DACR" },449 450 { "SPK_LN", NULL, "Speaker Output" },451 { "SPK_LP", NULL, "Speaker Output" },452 { "SPK_RN", NULL, "Speaker Output" },453 { "SPK_RP", NULL, "Speaker Output" },454 455 { "Speaker Output", NULL, "DACL" },456 { "Speaker Output", NULL, "DACR" },457 458 { "ADCL", NULL, "Left Input" },459 { "ADCL", NULL, "CLK_DSP" },460 { "ADCR", NULL, "Right Input" },461 { "ADCR", NULL, "CLK_DSP" },462 463 { "Left Input", NULL, "LINPUT" },464 { "Right Input", NULL, "RINPUT" },465 466};467 468/* Values for CLK_SYS_RATE */469static struct {470 int ratio;471 u16 val;472} wm8961_clk_sys_ratio[] = {473 { 64, 0 },474 { 128, 1 },475 { 192, 2 },476 { 256, 3 },477 { 384, 4 },478 { 512, 5 },479 { 768, 6 },480 { 1024, 7 },481 { 1408, 8 },482 { 1536, 9 },483};484 485/* Values for SAMPLE_RATE */486static struct {487 int rate;488 u16 val;489} wm8961_srate[] = {490 { 48000, 0 },491 { 44100, 0 },492 { 32000, 1 },493 { 22050, 2 },494 { 24000, 2 },495 { 16000, 3 },496 { 11250, 4 },497 { 12000, 4 },498 { 8000, 5 },499};500 501static int wm8961_hw_params(struct snd_pcm_substream *substream,502 struct snd_pcm_hw_params *params,503 struct snd_soc_dai *dai)504{505 struct snd_soc_component *component = dai->component;506 struct wm8961_priv *wm8961 = snd_soc_component_get_drvdata(component);507 int i, best, target, fs;508 u16 reg;509 510 fs = params_rate(params);511 512 if (!wm8961->sysclk) {513 dev_err(component->dev, "MCLK has not been specified\n");514 return -EINVAL;515 }516 517 /* Find the closest sample rate for the filters */518 best = 0;519 for (i = 0; i < ARRAY_SIZE(wm8961_srate); i++) {520 if (abs(wm8961_srate[i].rate - fs) <521 abs(wm8961_srate[best].rate - fs))522 best = i;523 }524 reg = snd_soc_component_read(component, WM8961_ADDITIONAL_CONTROL_3);525 reg &= ~WM8961_SAMPLE_RATE_MASK;526 reg |= wm8961_srate[best].val;527 snd_soc_component_write(component, WM8961_ADDITIONAL_CONTROL_3, reg);528 dev_dbg(component->dev, "Selected SRATE %dHz for %dHz\n",529 wm8961_srate[best].rate, fs);530 531 /* Select a CLK_SYS/fs ratio equal to or higher than required */532 target = wm8961->sysclk / fs;533 534 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK && target < 64) {535 dev_err(component->dev,536 "SYSCLK must be at least 64*fs for DAC\n");537 return -EINVAL;538 }539 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE && target < 256) {540 dev_err(component->dev,541 "SYSCLK must be at least 256*fs for ADC\n");542 return -EINVAL;543 }544 545 for (i = 0; i < ARRAY_SIZE(wm8961_clk_sys_ratio); i++) {546 if (wm8961_clk_sys_ratio[i].ratio >= target)547 break;548 }549 if (i == ARRAY_SIZE(wm8961_clk_sys_ratio)) {550 dev_err(component->dev, "Unable to generate CLK_SYS_RATE\n");551 return -EINVAL;552 }553 dev_dbg(component->dev, "Selected CLK_SYS_RATE of %d for %d/%d=%d\n",554 wm8961_clk_sys_ratio[i].ratio, wm8961->sysclk, fs,555 wm8961->sysclk / fs);556 557 reg = snd_soc_component_read(component, WM8961_CLOCKING_4);558 reg &= ~WM8961_CLK_SYS_RATE_MASK;559 reg |= wm8961_clk_sys_ratio[i].val << WM8961_CLK_SYS_RATE_SHIFT;560 snd_soc_component_write(component, WM8961_CLOCKING_4, reg);561 562 reg = snd_soc_component_read(component, WM8961_AUDIO_INTERFACE_0);563 reg &= ~WM8961_WL_MASK;564 switch (params_width(params)) {565 case 16:566 break;567 case 20:568 reg |= 1 << WM8961_WL_SHIFT;569 break;570 case 24:571 reg |= 2 << WM8961_WL_SHIFT;572 break;573 case 32:574 reg |= 3 << WM8961_WL_SHIFT;575 break;576 default:577 return -EINVAL;578 }579 snd_soc_component_write(component, WM8961_AUDIO_INTERFACE_0, reg);580 581 /* Sloping stop-band filter is recommended for <= 24kHz */582 reg = snd_soc_component_read(component, WM8961_ADC_DAC_CONTROL_2);583 if (fs <= 24000)584 reg |= WM8961_DACSLOPE;585 else586 reg &= ~WM8961_DACSLOPE;587 snd_soc_component_write(component, WM8961_ADC_DAC_CONTROL_2, reg);588 589 return 0;590}591 592static int wm8961_set_sysclk(struct snd_soc_dai *dai, int clk_id,593 unsigned int freq,594 int dir)595{596 struct snd_soc_component *component = dai->component;597 struct wm8961_priv *wm8961 = snd_soc_component_get_drvdata(component);598 u16 reg = snd_soc_component_read(component, WM8961_CLOCKING1);599 600 if (freq > 33000000) {601 dev_err(component->dev, "MCLK must be <33MHz\n");602 return -EINVAL;603 }604 605 if (freq > 16500000) {606 dev_dbg(component->dev, "Using MCLK/2 for %dHz MCLK\n", freq);607 reg |= WM8961_MCLKDIV;608 freq /= 2;609 } else {610 dev_dbg(component->dev, "Using MCLK/1 for %dHz MCLK\n", freq);611 reg &= ~WM8961_MCLKDIV;612 }613 614 snd_soc_component_write(component, WM8961_CLOCKING1, reg);615 616 wm8961->sysclk = freq;617 618 return 0;619}620 621static int wm8961_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)622{623 struct snd_soc_component *component = dai->component;624 u16 aif = snd_soc_component_read(component, WM8961_AUDIO_INTERFACE_0);625 626 aif &= ~(WM8961_BCLKINV | WM8961_LRP |627 WM8961_MS | WM8961_FORMAT_MASK);628 629 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {630 case SND_SOC_DAIFMT_CBM_CFM:631 aif |= WM8961_MS;632 break;633 case SND_SOC_DAIFMT_CBS_CFS:634 break;635 default:636 return -EINVAL;637 }638 639 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {640 case SND_SOC_DAIFMT_RIGHT_J:641 break;642 643 case SND_SOC_DAIFMT_LEFT_J:644 aif |= 1;645 break;646 647 case SND_SOC_DAIFMT_I2S:648 aif |= 2;649 break;650 651 case SND_SOC_DAIFMT_DSP_B:652 aif |= WM8961_LRP;653 fallthrough;654 case SND_SOC_DAIFMT_DSP_A:655 aif |= 3;656 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {657 case SND_SOC_DAIFMT_NB_NF:658 case SND_SOC_DAIFMT_IB_NF:659 break;660 default:661 return -EINVAL;662 }663 break;664 665 default:666 return -EINVAL;667 }668 669 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {670 case SND_SOC_DAIFMT_NB_NF:671 break;672 case SND_SOC_DAIFMT_NB_IF:673 aif |= WM8961_LRP;674 break;675 case SND_SOC_DAIFMT_IB_NF:676 aif |= WM8961_BCLKINV;677 break;678 case SND_SOC_DAIFMT_IB_IF:679 aif |= WM8961_BCLKINV | WM8961_LRP;680 break;681 default:682 return -EINVAL;683 }684 685 return snd_soc_component_write(component, WM8961_AUDIO_INTERFACE_0, aif);686}687 688static int wm8961_set_tristate(struct snd_soc_dai *dai, int tristate)689{690 struct snd_soc_component *component = dai->component;691 u16 reg = snd_soc_component_read(component, WM8961_ADDITIONAL_CONTROL_2);692 693 if (tristate)694 reg |= WM8961_TRIS;695 else696 reg &= ~WM8961_TRIS;697 698 return snd_soc_component_write(component, WM8961_ADDITIONAL_CONTROL_2, reg);699}700 701static int wm8961_mute(struct snd_soc_dai *dai, int mute, int direction)702{703 struct snd_soc_component *component = dai->component;704 u16 reg = snd_soc_component_read(component, WM8961_ADC_DAC_CONTROL_1);705 706 if (mute)707 reg |= WM8961_DACMU;708 else709 reg &= ~WM8961_DACMU;710 711 msleep(17);712 713 return snd_soc_component_write(component, WM8961_ADC_DAC_CONTROL_1, reg);714}715 716static int wm8961_set_clkdiv(struct snd_soc_dai *dai, int div_id, int div)717{718 struct snd_soc_component *component = dai->component;719 u16 reg;720 721 switch (div_id) {722 case WM8961_BCLK:723 reg = snd_soc_component_read(component, WM8961_CLOCKING2);724 reg &= ~WM8961_BCLKDIV_MASK;725 reg |= div;726 snd_soc_component_write(component, WM8961_CLOCKING2, reg);727 break;728 729 case WM8961_LRCLK:730 reg = snd_soc_component_read(component, WM8961_AUDIO_INTERFACE_2);731 reg &= ~WM8961_LRCLK_RATE_MASK;732 reg |= div;733 snd_soc_component_write(component, WM8961_AUDIO_INTERFACE_2, reg);734 break;735 736 default:737 return -EINVAL;738 }739 740 return 0;741}742 743static int wm8961_set_bias_level(struct snd_soc_component *component,744 enum snd_soc_bias_level level)745{746 u16 reg;747 748 /* This is all slightly unusual since we have no bypass paths749 * and the output amplifier structure means we can just slam750 * the biases straight up rather than having to ramp them751 * slowly.752 */753 switch (level) {754 case SND_SOC_BIAS_ON:755 break;756 757 case SND_SOC_BIAS_PREPARE:758 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_STANDBY) {759 /* Enable bias generation */760 reg = snd_soc_component_read(component, WM8961_ANTI_POP);761 reg |= WM8961_BUFIOEN | WM8961_BUFDCOPEN;762 snd_soc_component_write(component, WM8961_ANTI_POP, reg);763 764 /* VMID=2*50k, VREF */765 reg = snd_soc_component_read(component, WM8961_PWR_MGMT_1);766 reg &= ~WM8961_VMIDSEL_MASK;767 reg |= (1 << WM8961_VMIDSEL_SHIFT) | WM8961_VREF;768 snd_soc_component_write(component, WM8961_PWR_MGMT_1, reg);769 }770 break;771 772 case SND_SOC_BIAS_STANDBY:773 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_PREPARE) {774 /* VREF off */775 reg = snd_soc_component_read(component, WM8961_PWR_MGMT_1);776 reg &= ~WM8961_VREF;777 snd_soc_component_write(component, WM8961_PWR_MGMT_1, reg);778 779 /* Bias generation off */780 reg = snd_soc_component_read(component, WM8961_ANTI_POP);781 reg &= ~(WM8961_BUFIOEN | WM8961_BUFDCOPEN);782 snd_soc_component_write(component, WM8961_ANTI_POP, reg);783 784 /* VMID off */785 reg = snd_soc_component_read(component, WM8961_PWR_MGMT_1);786 reg &= ~WM8961_VMIDSEL_MASK;787 snd_soc_component_write(component, WM8961_PWR_MGMT_1, reg);788 }789 break;790 791 case SND_SOC_BIAS_OFF:792 break;793 }794 795 return 0;796}797 798 799#define WM8961_RATES SNDRV_PCM_RATE_8000_48000800 801#define WM8961_FORMATS \802 (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \803 SNDRV_PCM_FMTBIT_S24_LE)804 805static const struct snd_soc_dai_ops wm8961_dai_ops = {806 .hw_params = wm8961_hw_params,807 .set_sysclk = wm8961_set_sysclk,808 .set_fmt = wm8961_set_fmt,809 .mute_stream = wm8961_mute,810 .set_tristate = wm8961_set_tristate,811 .set_clkdiv = wm8961_set_clkdiv,812 .no_capture_mute = 1,813};814 815static struct snd_soc_dai_driver wm8961_dai = {816 .name = "wm8961-hifi",817 .playback = {818 .stream_name = "HiFi Playback",819 .channels_min = 1,820 .channels_max = 2,821 .rates = WM8961_RATES,822 .formats = WM8961_FORMATS,},823 .capture = {824 .stream_name = "HiFi Capture",825 .channels_min = 1,826 .channels_max = 2,827 .rates = WM8961_RATES,828 .formats = WM8961_FORMATS,},829 .ops = &wm8961_dai_ops,830};831 832static int wm8961_probe(struct snd_soc_component *component)833{834 u16 reg;835 836 /* Enable class W */837 reg = snd_soc_component_read(component, WM8961_CHARGE_PUMP_B);838 reg |= WM8961_CP_DYN_PWR_MASK;839 snd_soc_component_write(component, WM8961_CHARGE_PUMP_B, reg);840 841 /* Latch volume update bits (right channel only, we always842 * write both out) and default ZC on. */843 reg = snd_soc_component_read(component, WM8961_ROUT1_VOLUME);844 snd_soc_component_write(component, WM8961_ROUT1_VOLUME,845 reg | WM8961_LO1ZC | WM8961_OUT1VU);846 snd_soc_component_write(component, WM8961_LOUT1_VOLUME, reg | WM8961_LO1ZC);847 reg = snd_soc_component_read(component, WM8961_ROUT2_VOLUME);848 snd_soc_component_write(component, WM8961_ROUT2_VOLUME,849 reg | WM8961_SPKRZC | WM8961_SPKVU);850 snd_soc_component_write(component, WM8961_LOUT2_VOLUME, reg | WM8961_SPKLZC);851 852 reg = snd_soc_component_read(component, WM8961_RIGHT_ADC_VOLUME);853 snd_soc_component_write(component, WM8961_RIGHT_ADC_VOLUME, reg | WM8961_ADCVU);854 reg = snd_soc_component_read(component, WM8961_RIGHT_INPUT_VOLUME);855 snd_soc_component_write(component, WM8961_RIGHT_INPUT_VOLUME, reg | WM8961_IPVU);856 857 /* Use soft mute by default */858 reg = snd_soc_component_read(component, WM8961_ADC_DAC_CONTROL_2);859 reg |= WM8961_DACSMM;860 snd_soc_component_write(component, WM8961_ADC_DAC_CONTROL_2, reg);861 862 /* Use automatic clocking mode by default; for now this is all863 * we support.864 */865 reg = snd_soc_component_read(component, WM8961_CLOCKING_3);866 reg &= ~WM8961_MANUAL_MODE;867 snd_soc_component_write(component, WM8961_CLOCKING_3, reg);868 869 return 0;870}871 872#ifdef CONFIG_PM873 874static int wm8961_resume(struct snd_soc_component *component)875{876 snd_soc_component_cache_sync(component);877 878 return 0;879}880#else881#define wm8961_resume NULL882#endif883 884static const struct snd_soc_component_driver soc_component_dev_wm8961 = {885 .probe = wm8961_probe,886 .resume = wm8961_resume,887 .set_bias_level = wm8961_set_bias_level,888 .controls = wm8961_snd_controls,889 .num_controls = ARRAY_SIZE(wm8961_snd_controls),890 .dapm_widgets = wm8961_dapm_widgets,891 .num_dapm_widgets = ARRAY_SIZE(wm8961_dapm_widgets),892 .dapm_routes = audio_paths,893 .num_dapm_routes = ARRAY_SIZE(audio_paths),894 .suspend_bias_off = 1,895 .idle_bias_on = 1,896 .use_pmdown_time = 1,897 .endianness = 1,898};899 900static const struct regmap_config wm8961_regmap = {901 .reg_bits = 8,902 .val_bits = 16,903 .max_register = WM8961_MAX_REGISTER,904 905 .reg_defaults = wm8961_reg_defaults,906 .num_reg_defaults = ARRAY_SIZE(wm8961_reg_defaults),907 .cache_type = REGCACHE_MAPLE,908 909 .volatile_reg = wm8961_volatile,910 .readable_reg = wm8961_readable,911};912 913static int wm8961_i2c_probe(struct i2c_client *i2c)914{915 struct wm8961_priv *wm8961;916 unsigned int val;917 int ret;918 919 wm8961 = devm_kzalloc(&i2c->dev, sizeof(struct wm8961_priv),920 GFP_KERNEL);921 if (wm8961 == NULL)922 return -ENOMEM;923 924 wm8961->regmap = devm_regmap_init_i2c(i2c, &wm8961_regmap);925 if (IS_ERR(wm8961->regmap))926 return PTR_ERR(wm8961->regmap);927 928 ret = regmap_read(wm8961->regmap, WM8961_SOFTWARE_RESET, &val);929 if (ret != 0) {930 dev_err(&i2c->dev, "Failed to read chip ID: %d\n", ret);931 return ret;932 }933 934 if (val != 0x1801) {935 dev_err(&i2c->dev, "Device is not a WM8961: ID=0x%x\n", val);936 return -EINVAL;937 }938 939 /* This isn't volatile - readback doesn't correspond to write */940 regcache_cache_bypass(wm8961->regmap, true);941 ret = regmap_read(wm8961->regmap, WM8961_RIGHT_INPUT_VOLUME, &val);942 regcache_cache_bypass(wm8961->regmap, false);943 944 if (ret != 0) {945 dev_err(&i2c->dev, "Failed to read chip revision: %d\n", ret);946 return ret;947 }948 949 dev_info(&i2c->dev, "WM8961 family %d revision %c\n",950 (val & WM8961_DEVICE_ID_MASK) >> WM8961_DEVICE_ID_SHIFT,951 ((val & WM8961_CHIP_REV_MASK) >> WM8961_CHIP_REV_SHIFT)952 + 'A');953 954 ret = regmap_write(wm8961->regmap, WM8961_SOFTWARE_RESET, 0x1801);955 if (ret != 0) {956 dev_err(&i2c->dev, "Failed to issue reset: %d\n", ret);957 return ret;958 }959 960 i2c_set_clientdata(i2c, wm8961);961 962 ret = devm_snd_soc_register_component(&i2c->dev,963 &soc_component_dev_wm8961, &wm8961_dai, 1);964 965 return ret;966}967 968static const struct i2c_device_id wm8961_i2c_id[] = {969 { "wm8961" },970 { }971};972MODULE_DEVICE_TABLE(i2c, wm8961_i2c_id);973 974static const struct of_device_id wm8961_of_match[] __maybe_unused = {975 { .compatible = "wlf,wm8961", },976 { }977};978MODULE_DEVICE_TABLE(of, wm8961_of_match);979 980static struct i2c_driver wm8961_i2c_driver = {981 .driver = {982 .name = "wm8961",983 .of_match_table = of_match_ptr(wm8961_of_match),984 },985 .probe = wm8961_i2c_probe,986 .id_table = wm8961_i2c_id,987};988 989module_i2c_driver(wm8961_i2c_driver);990 991MODULE_DESCRIPTION("ASoC WM8961 driver");992MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");993MODULE_LICENSE("GPL");994