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1/* SPDX-License-Identifier: GPL-2.0-only */2/*3 * wm8974.h -- WM8974 Soc Audio driver4 */5 6#ifndef _WM8974_H7#define _WM8974_H8 9/* WM8974 register space */10 11#define WM8974_RESET 0x012#define WM8974_POWER1 0x113#define WM8974_POWER2 0x214#define WM8974_POWER3 0x315#define WM8974_IFACE 0x416#define WM8974_COMP 0x517#define WM8974_CLOCK 0x618#define WM8974_ADD 0x719#define WM8974_GPIO 0x820#define WM8974_DAC 0xa21#define WM8974_DACVOL 0xb22#define WM8974_ADC 0xe23#define WM8974_ADCVOL 0xf24#define WM8974_EQ1 0x1225#define WM8974_EQ2 0x1326#define WM8974_EQ3 0x1427#define WM8974_EQ4 0x1528#define WM8974_EQ5 0x1629#define WM8974_DACLIM1 0x1830#define WM8974_DACLIM2 0x1931#define WM8974_NOTCH1 0x1b32#define WM8974_NOTCH2 0x1c33#define WM8974_NOTCH3 0x1d34#define WM8974_NOTCH4 0x1e35#define WM8974_ALC1 0x2036#define WM8974_ALC2 0x2137#define WM8974_ALC3 0x2238#define WM8974_NGATE 0x2339#define WM8974_PLLN 0x2440#define WM8974_PLLK1 0x2541#define WM8974_PLLK2 0x2642#define WM8974_PLLK3 0x2743#define WM8974_ATTEN 0x2844#define WM8974_INPUT 0x2c45#define WM8974_INPPGA 0x2d46#define WM8974_ADCBOOST 0x2f47#define WM8974_OUTPUT 0x3148#define WM8974_SPKMIX 0x3249#define WM8974_SPKVOL 0x3650#define WM8974_MONOMIX 0x3851 52#define WM8974_CACHEREGNUM 5753 54/* Clock divider Id's */55#define WM8974_OPCLKDIV 056#define WM8974_MCLKDIV 157#define WM8974_BCLKDIV 258 59/* PLL Out dividers */60#define WM8974_OPCLKDIV_1 (0 << 4)61#define WM8974_OPCLKDIV_2 (1 << 4)62#define WM8974_OPCLKDIV_3 (2 << 4)63#define WM8974_OPCLKDIV_4 (3 << 4)64 65/* BCLK clock dividers */66#define WM8974_BCLKDIV_1 (0 << 2)67#define WM8974_BCLKDIV_2 (1 << 2)68#define WM8974_BCLKDIV_4 (2 << 2)69#define WM8974_BCLKDIV_8 (3 << 2)70#define WM8974_BCLKDIV_16 (4 << 2)71#define WM8974_BCLKDIV_32 (5 << 2)72 73/* MCLK clock dividers */74#define WM8974_MCLKDIV_1 (0 << 5)75#define WM8974_MCLKDIV_1_5 (1 << 5)76#define WM8974_MCLKDIV_2 (2 << 5)77#define WM8974_MCLKDIV_3 (3 << 5)78#define WM8974_MCLKDIV_4 (4 << 5)79#define WM8974_MCLKDIV_6 (5 << 5)80#define WM8974_MCLKDIV_8 (6 << 5)81#define WM8974_MCLKDIV_12 (7 << 5)82 83#endif84