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1/* SPDX-License-Identifier: GPL-2.0-or-later */2/*3 * wm8996.h - WM8996 audio codec interface4 *5 * Copyright 2011 Wolfson Microelectronics PLC.6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>7 */8 9#ifndef _WM8996_H10#define _WM8996_H11 12#define WM8996_SYSCLK_MCLK1 113#define WM8996_SYSCLK_MCLK2 214#define WM8996_SYSCLK_FLL 315 16#define WM8996_FLL_MCLK1 117#define WM8996_FLL_MCLK2 218#define WM8996_FLL_DACLRCLK1 319#define WM8996_FLL_BCLK1 420 21typedef void (*wm8996_polarity_fn)(struct snd_soc_component *component, int polarity);22 23int wm8996_detect(struct snd_soc_component *component, struct snd_soc_jack *jack,24 wm8996_polarity_fn polarity_cb);25 26/*27 * Register values.28 */29#define WM8996_SOFTWARE_RESET 0x0030#define WM8996_POWER_MANAGEMENT_1 0x0131#define WM8996_POWER_MANAGEMENT_2 0x0232#define WM8996_POWER_MANAGEMENT_3 0x0333#define WM8996_POWER_MANAGEMENT_4 0x0434#define WM8996_POWER_MANAGEMENT_5 0x0535#define WM8996_POWER_MANAGEMENT_6 0x0636#define WM8996_POWER_MANAGEMENT_7 0x0737#define WM8996_POWER_MANAGEMENT_8 0x0838#define WM8996_LEFT_LINE_INPUT_VOLUME 0x1039#define WM8996_RIGHT_LINE_INPUT_VOLUME 0x1140#define WM8996_LINE_INPUT_CONTROL 0x1241#define WM8996_DAC1_HPOUT1_VOLUME 0x1542#define WM8996_DAC2_HPOUT2_VOLUME 0x1643#define WM8996_DAC1_LEFT_VOLUME 0x1844#define WM8996_DAC1_RIGHT_VOLUME 0x1945#define WM8996_DAC2_LEFT_VOLUME 0x1A46#define WM8996_DAC2_RIGHT_VOLUME 0x1B47#define WM8996_OUTPUT1_LEFT_VOLUME 0x1C48#define WM8996_OUTPUT1_RIGHT_VOLUME 0x1D49#define WM8996_OUTPUT2_LEFT_VOLUME 0x1E50#define WM8996_OUTPUT2_RIGHT_VOLUME 0x1F51#define WM8996_MICBIAS_1 0x2052#define WM8996_MICBIAS_2 0x2153#define WM8996_LDO_1 0x2854#define WM8996_LDO_2 0x2955#define WM8996_ACCESSORY_DETECT_MODE_1 0x3056#define WM8996_ACCESSORY_DETECT_MODE_2 0x3157#define WM8996_HEADPHONE_DETECT_1 0x3458#define WM8996_HEADPHONE_DETECT_2 0x3559#define WM8996_MIC_DETECT_1 0x3860#define WM8996_MIC_DETECT_2 0x3961#define WM8996_MIC_DETECT_3 0x3A62#define WM8996_CHARGE_PUMP_1 0x4063#define WM8996_CHARGE_PUMP_2 0x4164#define WM8996_DC_SERVO_1 0x5065#define WM8996_DC_SERVO_2 0x5166#define WM8996_DC_SERVO_3 0x5267#define WM8996_DC_SERVO_5 0x5468#define WM8996_DC_SERVO_6 0x5569#define WM8996_DC_SERVO_7 0x5670#define WM8996_DC_SERVO_READBACK_0 0x5771#define WM8996_ANALOGUE_HP_1 0x6072#define WM8996_ANALOGUE_HP_2 0x6173#define WM8996_CHIP_REVISION 0x10074#define WM8996_CONTROL_INTERFACE_1 0x10175#define WM8996_WRITE_SEQUENCER_CTRL_1 0x11076#define WM8996_WRITE_SEQUENCER_CTRL_2 0x11177#define WM8996_AIF_CLOCKING_1 0x20078#define WM8996_AIF_CLOCKING_2 0x20179#define WM8996_CLOCKING_1 0x20880#define WM8996_CLOCKING_2 0x20981#define WM8996_AIF_RATE 0x21082#define WM8996_FLL_CONTROL_1 0x22083#define WM8996_FLL_CONTROL_2 0x22184#define WM8996_FLL_CONTROL_3 0x22285#define WM8996_FLL_CONTROL_4 0x22386#define WM8996_FLL_CONTROL_5 0x22487#define WM8996_FLL_CONTROL_6 0x22588#define WM8996_FLL_EFS_1 0x22689#define WM8996_FLL_EFS_2 0x22790#define WM8996_AIF1_CONTROL 0x30091#define WM8996_AIF1_BCLK 0x30192#define WM8996_AIF1_TX_LRCLK_1 0x30293#define WM8996_AIF1_TX_LRCLK_2 0x30394#define WM8996_AIF1_RX_LRCLK_1 0x30495#define WM8996_AIF1_RX_LRCLK_2 0x30596#define WM8996_AIF1TX_DATA_CONFIGURATION_1 0x30697#define WM8996_AIF1TX_DATA_CONFIGURATION_2 0x30798#define WM8996_AIF1RX_DATA_CONFIGURATION 0x30899#define WM8996_AIF1TX_CHANNEL_0_CONFIGURATION 0x309100#define WM8996_AIF1TX_CHANNEL_1_CONFIGURATION 0x30A101#define WM8996_AIF1TX_CHANNEL_2_CONFIGURATION 0x30B102#define WM8996_AIF1TX_CHANNEL_3_CONFIGURATION 0x30C103#define WM8996_AIF1TX_CHANNEL_4_CONFIGURATION 0x30D104#define WM8996_AIF1TX_CHANNEL_5_CONFIGURATION 0x30E105#define WM8996_AIF1RX_CHANNEL_0_CONFIGURATION 0x30F106#define WM8996_AIF1RX_CHANNEL_1_CONFIGURATION 0x310107#define WM8996_AIF1RX_CHANNEL_2_CONFIGURATION 0x311108#define WM8996_AIF1RX_CHANNEL_3_CONFIGURATION 0x312109#define WM8996_AIF1RX_CHANNEL_4_CONFIGURATION 0x313110#define WM8996_AIF1RX_CHANNEL_5_CONFIGURATION 0x314111#define WM8996_AIF1RX_MONO_CONFIGURATION 0x315112#define WM8996_AIF1TX_TEST 0x31A113#define WM8996_AIF2_CONTROL 0x320114#define WM8996_AIF2_BCLK 0x321115#define WM8996_AIF2_TX_LRCLK_1 0x322116#define WM8996_AIF2_TX_LRCLK_2 0x323117#define WM8996_AIF2_RX_LRCLK_1 0x324118#define WM8996_AIF2_RX_LRCLK_2 0x325119#define WM8996_AIF2TX_DATA_CONFIGURATION_1 0x326120#define WM8996_AIF2TX_DATA_CONFIGURATION_2 0x327121#define WM8996_AIF2RX_DATA_CONFIGURATION 0x328122#define WM8996_AIF2TX_CHANNEL_0_CONFIGURATION 0x329123#define WM8996_AIF2TX_CHANNEL_1_CONFIGURATION 0x32A124#define WM8996_AIF2RX_CHANNEL_0_CONFIGURATION 0x32B125#define WM8996_AIF2RX_CHANNEL_1_CONFIGURATION 0x32C126#define WM8996_AIF2RX_MONO_CONFIGURATION 0x32D127#define WM8996_AIF2TX_TEST 0x32F128#define WM8996_DSP1_TX_LEFT_VOLUME 0x400129#define WM8996_DSP1_TX_RIGHT_VOLUME 0x401130#define WM8996_DSP1_RX_LEFT_VOLUME 0x402131#define WM8996_DSP1_RX_RIGHT_VOLUME 0x403132#define WM8996_DSP1_TX_FILTERS 0x410133#define WM8996_DSP1_RX_FILTERS_1 0x420134#define WM8996_DSP1_RX_FILTERS_2 0x421135#define WM8996_DSP1_DRC_1 0x440136#define WM8996_DSP1_DRC_2 0x441137#define WM8996_DSP1_DRC_3 0x442138#define WM8996_DSP1_DRC_4 0x443139#define WM8996_DSP1_DRC_5 0x444140#define WM8996_DSP1_RX_EQ_GAINS_1 0x480141#define WM8996_DSP1_RX_EQ_GAINS_2 0x481142#define WM8996_DSP1_RX_EQ_BAND_1_A 0x482143#define WM8996_DSP1_RX_EQ_BAND_1_B 0x483144#define WM8996_DSP1_RX_EQ_BAND_1_PG 0x484145#define WM8996_DSP1_RX_EQ_BAND_2_A 0x485146#define WM8996_DSP1_RX_EQ_BAND_2_B 0x486147#define WM8996_DSP1_RX_EQ_BAND_2_C 0x487148#define WM8996_DSP1_RX_EQ_BAND_2_PG 0x488149#define WM8996_DSP1_RX_EQ_BAND_3_A 0x489150#define WM8996_DSP1_RX_EQ_BAND_3_B 0x48A151#define WM8996_DSP1_RX_EQ_BAND_3_C 0x48B152#define WM8996_DSP1_RX_EQ_BAND_3_PG 0x48C153#define WM8996_DSP1_RX_EQ_BAND_4_A 0x48D154#define WM8996_DSP1_RX_EQ_BAND_4_B 0x48E155#define WM8996_DSP1_RX_EQ_BAND_4_C 0x48F156#define WM8996_DSP1_RX_EQ_BAND_4_PG 0x490157#define WM8996_DSP1_RX_EQ_BAND_5_A 0x491158#define WM8996_DSP1_RX_EQ_BAND_5_B 0x492159#define WM8996_DSP1_RX_EQ_BAND_5_PG 0x493160#define WM8996_DSP2_TX_LEFT_VOLUME 0x500161#define WM8996_DSP2_TX_RIGHT_VOLUME 0x501162#define WM8996_DSP2_RX_LEFT_VOLUME 0x502163#define WM8996_DSP2_RX_RIGHT_VOLUME 0x503164#define WM8996_DSP2_TX_FILTERS 0x510165#define WM8996_DSP2_RX_FILTERS_1 0x520166#define WM8996_DSP2_RX_FILTERS_2 0x521167#define WM8996_DSP2_DRC_1 0x540168#define WM8996_DSP2_DRC_2 0x541169#define WM8996_DSP2_DRC_3 0x542170#define WM8996_DSP2_DRC_4 0x543171#define WM8996_DSP2_DRC_5 0x544172#define WM8996_DSP2_RX_EQ_GAINS_1 0x580173#define WM8996_DSP2_RX_EQ_GAINS_2 0x581174#define WM8996_DSP2_RX_EQ_BAND_1_A 0x582175#define WM8996_DSP2_RX_EQ_BAND_1_B 0x583176#define WM8996_DSP2_RX_EQ_BAND_1_PG 0x584177#define WM8996_DSP2_RX_EQ_BAND_2_A 0x585178#define WM8996_DSP2_RX_EQ_BAND_2_B 0x586179#define WM8996_DSP2_RX_EQ_BAND_2_C 0x587180#define WM8996_DSP2_RX_EQ_BAND_2_PG 0x588181#define WM8996_DSP2_RX_EQ_BAND_3_A 0x589182#define WM8996_DSP2_RX_EQ_BAND_3_B 0x58A183#define WM8996_DSP2_RX_EQ_BAND_3_C 0x58B184#define WM8996_DSP2_RX_EQ_BAND_3_PG 0x58C185#define WM8996_DSP2_RX_EQ_BAND_4_A 0x58D186#define WM8996_DSP2_RX_EQ_BAND_4_B 0x58E187#define WM8996_DSP2_RX_EQ_BAND_4_C 0x58F188#define WM8996_DSP2_RX_EQ_BAND_4_PG 0x590189#define WM8996_DSP2_RX_EQ_BAND_5_A 0x591190#define WM8996_DSP2_RX_EQ_BAND_5_B 0x592191#define WM8996_DSP2_RX_EQ_BAND_5_PG 0x593192#define WM8996_DAC1_MIXER_VOLUMES 0x600193#define WM8996_DAC1_LEFT_MIXER_ROUTING 0x601194#define WM8996_DAC1_RIGHT_MIXER_ROUTING 0x602195#define WM8996_DAC2_MIXER_VOLUMES 0x603196#define WM8996_DAC2_LEFT_MIXER_ROUTING 0x604197#define WM8996_DAC2_RIGHT_MIXER_ROUTING 0x605198#define WM8996_DSP1_TX_LEFT_MIXER_ROUTING 0x606199#define WM8996_DSP1_TX_RIGHT_MIXER_ROUTING 0x607200#define WM8996_DSP2_TX_LEFT_MIXER_ROUTING 0x608201#define WM8996_DSP2_TX_RIGHT_MIXER_ROUTING 0x609202#define WM8996_DSP_TX_MIXER_SELECT 0x60A203#define WM8996_DAC_SOFTMUTE 0x610204#define WM8996_OVERSAMPLING 0x620205#define WM8996_SIDETONE 0x621206#define WM8996_GPIO_1 0x700207#define WM8996_GPIO_2 0x701208#define WM8996_GPIO_3 0x702209#define WM8996_GPIO_4 0x703210#define WM8996_GPIO_5 0x704211#define WM8996_PULL_CONTROL_1 0x720212#define WM8996_PULL_CONTROL_2 0x721213#define WM8996_INTERRUPT_STATUS_1 0x730214#define WM8996_INTERRUPT_STATUS_2 0x731215#define WM8996_INTERRUPT_RAW_STATUS_2 0x732216#define WM8996_INTERRUPT_STATUS_1_MASK 0x738217#define WM8996_INTERRUPT_STATUS_2_MASK 0x739218#define WM8996_INTERRUPT_CONTROL 0x740219#define WM8996_LEFT_PDM_SPEAKER 0x800220#define WM8996_RIGHT_PDM_SPEAKER 0x801221#define WM8996_PDM_SPEAKER_MUTE_SEQUENCE 0x802222#define WM8996_PDM_SPEAKER_VOLUME 0x803223#define WM8996_WRITE_SEQUENCER_0 0x3000224#define WM8996_WRITE_SEQUENCER_1 0x3001225#define WM8996_WRITE_SEQUENCER_2 0x3002226#define WM8996_WRITE_SEQUENCER_3 0x3003227#define WM8996_WRITE_SEQUENCER_4 0x3004228#define WM8996_WRITE_SEQUENCER_5 0x3005229#define WM8996_WRITE_SEQUENCER_6 0x3006230#define WM8996_WRITE_SEQUENCER_7 0x3007231#define WM8996_WRITE_SEQUENCER_8 0x3008232#define WM8996_WRITE_SEQUENCER_9 0x3009233#define WM8996_WRITE_SEQUENCER_10 0x300A234#define WM8996_WRITE_SEQUENCER_11 0x300B235#define WM8996_WRITE_SEQUENCER_12 0x300C236#define WM8996_WRITE_SEQUENCER_13 0x300D237#define WM8996_WRITE_SEQUENCER_14 0x300E238#define WM8996_WRITE_SEQUENCER_15 0x300F239#define WM8996_WRITE_SEQUENCER_16 0x3010240#define WM8996_WRITE_SEQUENCER_17 0x3011241#define WM8996_WRITE_SEQUENCER_18 0x3012242#define WM8996_WRITE_SEQUENCER_19 0x3013243#define WM8996_WRITE_SEQUENCER_20 0x3014244#define WM8996_WRITE_SEQUENCER_21 0x3015245#define WM8996_WRITE_SEQUENCER_22 0x3016246#define WM8996_WRITE_SEQUENCER_23 0x3017247#define WM8996_WRITE_SEQUENCER_24 0x3018248#define WM8996_WRITE_SEQUENCER_25 0x3019249#define WM8996_WRITE_SEQUENCER_26 0x301A250#define WM8996_WRITE_SEQUENCER_27 0x301B251#define WM8996_WRITE_SEQUENCER_28 0x301C252#define WM8996_WRITE_SEQUENCER_29 0x301D253#define WM8996_WRITE_SEQUENCER_30 0x301E254#define WM8996_WRITE_SEQUENCER_31 0x301F255#define WM8996_WRITE_SEQUENCER_32 0x3020256#define WM8996_WRITE_SEQUENCER_33 0x3021257#define WM8996_WRITE_SEQUENCER_34 0x3022258#define WM8996_WRITE_SEQUENCER_35 0x3023259#define WM8996_WRITE_SEQUENCER_36 0x3024260#define WM8996_WRITE_SEQUENCER_37 0x3025261#define WM8996_WRITE_SEQUENCER_38 0x3026262#define WM8996_WRITE_SEQUENCER_39 0x3027263#define WM8996_WRITE_SEQUENCER_40 0x3028264#define WM8996_WRITE_SEQUENCER_41 0x3029265#define WM8996_WRITE_SEQUENCER_42 0x302A266#define WM8996_WRITE_SEQUENCER_43 0x302B267#define WM8996_WRITE_SEQUENCER_44 0x302C268#define WM8996_WRITE_SEQUENCER_45 0x302D269#define WM8996_WRITE_SEQUENCER_46 0x302E270#define WM8996_WRITE_SEQUENCER_47 0x302F271#define WM8996_WRITE_SEQUENCER_48 0x3030272#define WM8996_WRITE_SEQUENCER_49 0x3031273#define WM8996_WRITE_SEQUENCER_50 0x3032274#define WM8996_WRITE_SEQUENCER_51 0x3033275#define WM8996_WRITE_SEQUENCER_52 0x3034276#define WM8996_WRITE_SEQUENCER_53 0x3035277#define WM8996_WRITE_SEQUENCER_54 0x3036278#define WM8996_WRITE_SEQUENCER_55 0x3037279#define WM8996_WRITE_SEQUENCER_56 0x3038280#define WM8996_WRITE_SEQUENCER_57 0x3039281#define WM8996_WRITE_SEQUENCER_58 0x303A282#define WM8996_WRITE_SEQUENCER_59 0x303B283#define WM8996_WRITE_SEQUENCER_60 0x303C284#define WM8996_WRITE_SEQUENCER_61 0x303D285#define WM8996_WRITE_SEQUENCER_62 0x303E286#define WM8996_WRITE_SEQUENCER_63 0x303F287#define WM8996_WRITE_SEQUENCER_64 0x3040288#define WM8996_WRITE_SEQUENCER_65 0x3041289#define WM8996_WRITE_SEQUENCER_66 0x3042290#define WM8996_WRITE_SEQUENCER_67 0x3043291#define WM8996_WRITE_SEQUENCER_68 0x3044292#define WM8996_WRITE_SEQUENCER_69 0x3045293#define WM8996_WRITE_SEQUENCER_70 0x3046294#define WM8996_WRITE_SEQUENCER_71 0x3047295#define WM8996_WRITE_SEQUENCER_72 0x3048296#define WM8996_WRITE_SEQUENCER_73 0x3049297#define WM8996_WRITE_SEQUENCER_74 0x304A298#define WM8996_WRITE_SEQUENCER_75 0x304B299#define WM8996_WRITE_SEQUENCER_76 0x304C300#define WM8996_WRITE_SEQUENCER_77 0x304D301#define WM8996_WRITE_SEQUENCER_78 0x304E302#define WM8996_WRITE_SEQUENCER_79 0x304F303#define WM8996_WRITE_SEQUENCER_80 0x3050304#define WM8996_WRITE_SEQUENCER_81 0x3051305#define WM8996_WRITE_SEQUENCER_82 0x3052306#define WM8996_WRITE_SEQUENCER_83 0x3053307#define WM8996_WRITE_SEQUENCER_84 0x3054308#define WM8996_WRITE_SEQUENCER_85 0x3055309#define WM8996_WRITE_SEQUENCER_86 0x3056310#define WM8996_WRITE_SEQUENCER_87 0x3057311#define WM8996_WRITE_SEQUENCER_88 0x3058312#define WM8996_WRITE_SEQUENCER_89 0x3059313#define WM8996_WRITE_SEQUENCER_90 0x305A314#define WM8996_WRITE_SEQUENCER_91 0x305B315#define WM8996_WRITE_SEQUENCER_92 0x305C316#define WM8996_WRITE_SEQUENCER_93 0x305D317#define WM8996_WRITE_SEQUENCER_94 0x305E318#define WM8996_WRITE_SEQUENCER_95 0x305F319#define WM8996_WRITE_SEQUENCER_96 0x3060320#define WM8996_WRITE_SEQUENCER_97 0x3061321#define WM8996_WRITE_SEQUENCER_98 0x3062322#define WM8996_WRITE_SEQUENCER_99 0x3063323#define WM8996_WRITE_SEQUENCER_100 0x3064324#define WM8996_WRITE_SEQUENCER_101 0x3065325#define WM8996_WRITE_SEQUENCER_102 0x3066326#define WM8996_WRITE_SEQUENCER_103 0x3067327#define WM8996_WRITE_SEQUENCER_104 0x3068328#define WM8996_WRITE_SEQUENCER_105 0x3069329#define WM8996_WRITE_SEQUENCER_106 0x306A330#define WM8996_WRITE_SEQUENCER_107 0x306B331#define WM8996_WRITE_SEQUENCER_108 0x306C332#define WM8996_WRITE_SEQUENCER_109 0x306D333#define WM8996_WRITE_SEQUENCER_110 0x306E334#define WM8996_WRITE_SEQUENCER_111 0x306F335#define WM8996_WRITE_SEQUENCER_112 0x3070336#define WM8996_WRITE_SEQUENCER_113 0x3071337#define WM8996_WRITE_SEQUENCER_114 0x3072338#define WM8996_WRITE_SEQUENCER_115 0x3073339#define WM8996_WRITE_SEQUENCER_116 0x3074340#define WM8996_WRITE_SEQUENCER_117 0x3075341#define WM8996_WRITE_SEQUENCER_118 0x3076342#define WM8996_WRITE_SEQUENCER_119 0x3077343#define WM8996_WRITE_SEQUENCER_120 0x3078344#define WM8996_WRITE_SEQUENCER_121 0x3079345#define WM8996_WRITE_SEQUENCER_122 0x307A346#define WM8996_WRITE_SEQUENCER_123 0x307B347#define WM8996_WRITE_SEQUENCER_124 0x307C348#define WM8996_WRITE_SEQUENCER_125 0x307D349#define WM8996_WRITE_SEQUENCER_126 0x307E350#define WM8996_WRITE_SEQUENCER_127 0x307F351#define WM8996_WRITE_SEQUENCER_128 0x3080352#define WM8996_WRITE_SEQUENCER_129 0x3081353#define WM8996_WRITE_SEQUENCER_130 0x3082354#define WM8996_WRITE_SEQUENCER_131 0x3083355#define WM8996_WRITE_SEQUENCER_132 0x3084356#define WM8996_WRITE_SEQUENCER_133 0x3085357#define WM8996_WRITE_SEQUENCER_134 0x3086358#define WM8996_WRITE_SEQUENCER_135 0x3087359#define WM8996_WRITE_SEQUENCER_136 0x3088360#define WM8996_WRITE_SEQUENCER_137 0x3089361#define WM8996_WRITE_SEQUENCER_138 0x308A362#define WM8996_WRITE_SEQUENCER_139 0x308B363#define WM8996_WRITE_SEQUENCER_140 0x308C364#define WM8996_WRITE_SEQUENCER_141 0x308D365#define WM8996_WRITE_SEQUENCER_142 0x308E366#define WM8996_WRITE_SEQUENCER_143 0x308F367#define WM8996_WRITE_SEQUENCER_144 0x3090368#define WM8996_WRITE_SEQUENCER_145 0x3091369#define WM8996_WRITE_SEQUENCER_146 0x3092370#define WM8996_WRITE_SEQUENCER_147 0x3093371#define WM8996_WRITE_SEQUENCER_148 0x3094372#define WM8996_WRITE_SEQUENCER_149 0x3095373#define WM8996_WRITE_SEQUENCER_150 0x3096374#define WM8996_WRITE_SEQUENCER_151 0x3097375#define WM8996_WRITE_SEQUENCER_152 0x3098376#define WM8996_WRITE_SEQUENCER_153 0x3099377#define WM8996_WRITE_SEQUENCER_154 0x309A378#define WM8996_WRITE_SEQUENCER_155 0x309B379#define WM8996_WRITE_SEQUENCER_156 0x309C380#define WM8996_WRITE_SEQUENCER_157 0x309D381#define WM8996_WRITE_SEQUENCER_158 0x309E382#define WM8996_WRITE_SEQUENCER_159 0x309F383#define WM8996_WRITE_SEQUENCER_160 0x30A0384#define WM8996_WRITE_SEQUENCER_161 0x30A1385#define WM8996_WRITE_SEQUENCER_162 0x30A2386#define WM8996_WRITE_SEQUENCER_163 0x30A3387#define WM8996_WRITE_SEQUENCER_164 0x30A4388#define WM8996_WRITE_SEQUENCER_165 0x30A5389#define WM8996_WRITE_SEQUENCER_166 0x30A6390#define WM8996_WRITE_SEQUENCER_167 0x30A7391#define WM8996_WRITE_SEQUENCER_168 0x30A8392#define WM8996_WRITE_SEQUENCER_169 0x30A9393#define WM8996_WRITE_SEQUENCER_170 0x30AA394#define WM8996_WRITE_SEQUENCER_171 0x30AB395#define WM8996_WRITE_SEQUENCER_172 0x30AC396#define WM8996_WRITE_SEQUENCER_173 0x30AD397#define WM8996_WRITE_SEQUENCER_174 0x30AE398#define WM8996_WRITE_SEQUENCER_175 0x30AF399#define WM8996_WRITE_SEQUENCER_176 0x30B0400#define WM8996_WRITE_SEQUENCER_177 0x30B1401#define WM8996_WRITE_SEQUENCER_178 0x30B2402#define WM8996_WRITE_SEQUENCER_179 0x30B3403#define WM8996_WRITE_SEQUENCER_180 0x30B4404#define WM8996_WRITE_SEQUENCER_181 0x30B5405#define WM8996_WRITE_SEQUENCER_182 0x30B6406#define WM8996_WRITE_SEQUENCER_183 0x30B7407#define WM8996_WRITE_SEQUENCER_184 0x30B8408#define WM8996_WRITE_SEQUENCER_185 0x30B9409#define WM8996_WRITE_SEQUENCER_186 0x30BA410#define WM8996_WRITE_SEQUENCER_187 0x30BB411#define WM8996_WRITE_SEQUENCER_188 0x30BC412#define WM8996_WRITE_SEQUENCER_189 0x30BD413#define WM8996_WRITE_SEQUENCER_190 0x30BE414#define WM8996_WRITE_SEQUENCER_191 0x30BF415#define WM8996_WRITE_SEQUENCER_192 0x30C0416#define WM8996_WRITE_SEQUENCER_193 0x30C1417#define WM8996_WRITE_SEQUENCER_194 0x30C2418#define WM8996_WRITE_SEQUENCER_195 0x30C3419#define WM8996_WRITE_SEQUENCER_196 0x30C4420#define WM8996_WRITE_SEQUENCER_197 0x30C5421#define WM8996_WRITE_SEQUENCER_198 0x30C6422#define WM8996_WRITE_SEQUENCER_199 0x30C7423#define WM8996_WRITE_SEQUENCER_200 0x30C8424#define WM8996_WRITE_SEQUENCER_201 0x30C9425#define WM8996_WRITE_SEQUENCER_202 0x30CA426#define WM8996_WRITE_SEQUENCER_203 0x30CB427#define WM8996_WRITE_SEQUENCER_204 0x30CC428#define WM8996_WRITE_SEQUENCER_205 0x30CD429#define WM8996_WRITE_SEQUENCER_206 0x30CE430#define WM8996_WRITE_SEQUENCER_207 0x30CF431#define WM8996_WRITE_SEQUENCER_208 0x30D0432#define WM8996_WRITE_SEQUENCER_209 0x30D1433#define WM8996_WRITE_SEQUENCER_210 0x30D2434#define WM8996_WRITE_SEQUENCER_211 0x30D3435#define WM8996_WRITE_SEQUENCER_212 0x30D4436#define WM8996_WRITE_SEQUENCER_213 0x30D5437#define WM8996_WRITE_SEQUENCER_214 0x30D6438#define WM8996_WRITE_SEQUENCER_215 0x30D7439#define WM8996_WRITE_SEQUENCER_216 0x30D8440#define WM8996_WRITE_SEQUENCER_217 0x30D9441#define WM8996_WRITE_SEQUENCER_218 0x30DA442#define WM8996_WRITE_SEQUENCER_219 0x30DB443#define WM8996_WRITE_SEQUENCER_220 0x30DC444#define WM8996_WRITE_SEQUENCER_221 0x30DD445#define WM8996_WRITE_SEQUENCER_222 0x30DE446#define WM8996_WRITE_SEQUENCER_223 0x30DF447#define WM8996_WRITE_SEQUENCER_224 0x30E0448#define WM8996_WRITE_SEQUENCER_225 0x30E1449#define WM8996_WRITE_SEQUENCER_226 0x30E2450#define WM8996_WRITE_SEQUENCER_227 0x30E3451#define WM8996_WRITE_SEQUENCER_228 0x30E4452#define WM8996_WRITE_SEQUENCER_229 0x30E5453#define WM8996_WRITE_SEQUENCER_230 0x30E6454#define WM8996_WRITE_SEQUENCER_231 0x30E7455#define WM8996_WRITE_SEQUENCER_232 0x30E8456#define WM8996_WRITE_SEQUENCER_233 0x30E9457#define WM8996_WRITE_SEQUENCER_234 0x30EA458#define WM8996_WRITE_SEQUENCER_235 0x30EB459#define WM8996_WRITE_SEQUENCER_236 0x30EC460#define WM8996_WRITE_SEQUENCER_237 0x30ED461#define WM8996_WRITE_SEQUENCER_238 0x30EE462#define WM8996_WRITE_SEQUENCER_239 0x30EF463#define WM8996_WRITE_SEQUENCER_240 0x30F0464#define WM8996_WRITE_SEQUENCER_241 0x30F1465#define WM8996_WRITE_SEQUENCER_242 0x30F2466#define WM8996_WRITE_SEQUENCER_243 0x30F3467#define WM8996_WRITE_SEQUENCER_244 0x30F4468#define WM8996_WRITE_SEQUENCER_245 0x30F5469#define WM8996_WRITE_SEQUENCER_246 0x30F6470#define WM8996_WRITE_SEQUENCER_247 0x30F7471#define WM8996_WRITE_SEQUENCER_248 0x30F8472#define WM8996_WRITE_SEQUENCER_249 0x30F9473#define WM8996_WRITE_SEQUENCER_250 0x30FA474#define WM8996_WRITE_SEQUENCER_251 0x30FB475#define WM8996_WRITE_SEQUENCER_252 0x30FC476#define WM8996_WRITE_SEQUENCER_253 0x30FD477#define WM8996_WRITE_SEQUENCER_254 0x30FE478#define WM8996_WRITE_SEQUENCER_255 0x30FF479#define WM8996_WRITE_SEQUENCER_256 0x3100480#define WM8996_WRITE_SEQUENCER_257 0x3101481#define WM8996_WRITE_SEQUENCER_258 0x3102482#define WM8996_WRITE_SEQUENCER_259 0x3103483#define WM8996_WRITE_SEQUENCER_260 0x3104484#define WM8996_WRITE_SEQUENCER_261 0x3105485#define WM8996_WRITE_SEQUENCER_262 0x3106486#define WM8996_WRITE_SEQUENCER_263 0x3107487#define WM8996_WRITE_SEQUENCER_264 0x3108488#define WM8996_WRITE_SEQUENCER_265 0x3109489#define WM8996_WRITE_SEQUENCER_266 0x310A490#define WM8996_WRITE_SEQUENCER_267 0x310B491#define WM8996_WRITE_SEQUENCER_268 0x310C492#define WM8996_WRITE_SEQUENCER_269 0x310D493#define WM8996_WRITE_SEQUENCER_270 0x310E494#define WM8996_WRITE_SEQUENCER_271 0x310F495#define WM8996_WRITE_SEQUENCER_272 0x3110496#define WM8996_WRITE_SEQUENCER_273 0x3111497#define WM8996_WRITE_SEQUENCER_274 0x3112498#define WM8996_WRITE_SEQUENCER_275 0x3113499#define WM8996_WRITE_SEQUENCER_276 0x3114500#define WM8996_WRITE_SEQUENCER_277 0x3115501#define WM8996_WRITE_SEQUENCER_278 0x3116502#define WM8996_WRITE_SEQUENCER_279 0x3117503#define WM8996_WRITE_SEQUENCER_280 0x3118504#define WM8996_WRITE_SEQUENCER_281 0x3119505#define WM8996_WRITE_SEQUENCER_282 0x311A506#define WM8996_WRITE_SEQUENCER_283 0x311B507#define WM8996_WRITE_SEQUENCER_284 0x311C508#define WM8996_WRITE_SEQUENCER_285 0x311D509#define WM8996_WRITE_SEQUENCER_286 0x311E510#define WM8996_WRITE_SEQUENCER_287 0x311F511#define WM8996_WRITE_SEQUENCER_288 0x3120512#define WM8996_WRITE_SEQUENCER_289 0x3121513#define WM8996_WRITE_SEQUENCER_290 0x3122514#define WM8996_WRITE_SEQUENCER_291 0x3123515#define WM8996_WRITE_SEQUENCER_292 0x3124516#define WM8996_WRITE_SEQUENCER_293 0x3125517#define WM8996_WRITE_SEQUENCER_294 0x3126518#define WM8996_WRITE_SEQUENCER_295 0x3127519#define WM8996_WRITE_SEQUENCER_296 0x3128520#define WM8996_WRITE_SEQUENCER_297 0x3129521#define WM8996_WRITE_SEQUENCER_298 0x312A522#define WM8996_WRITE_SEQUENCER_299 0x312B523#define WM8996_WRITE_SEQUENCER_300 0x312C524#define WM8996_WRITE_SEQUENCER_301 0x312D525#define WM8996_WRITE_SEQUENCER_302 0x312E526#define WM8996_WRITE_SEQUENCER_303 0x312F527#define WM8996_WRITE_SEQUENCER_304 0x3130528#define WM8996_WRITE_SEQUENCER_305 0x3131529#define WM8996_WRITE_SEQUENCER_306 0x3132530#define WM8996_WRITE_SEQUENCER_307 0x3133531#define WM8996_WRITE_SEQUENCER_308 0x3134532#define WM8996_WRITE_SEQUENCER_309 0x3135533#define WM8996_WRITE_SEQUENCER_310 0x3136534#define WM8996_WRITE_SEQUENCER_311 0x3137535#define WM8996_WRITE_SEQUENCER_312 0x3138536#define WM8996_WRITE_SEQUENCER_313 0x3139537#define WM8996_WRITE_SEQUENCER_314 0x313A538#define WM8996_WRITE_SEQUENCER_315 0x313B539#define WM8996_WRITE_SEQUENCER_316 0x313C540#define WM8996_WRITE_SEQUENCER_317 0x313D541#define WM8996_WRITE_SEQUENCER_318 0x313E542#define WM8996_WRITE_SEQUENCER_319 0x313F543#define WM8996_WRITE_SEQUENCER_320 0x3140544#define WM8996_WRITE_SEQUENCER_321 0x3141545#define WM8996_WRITE_SEQUENCER_322 0x3142546#define WM8996_WRITE_SEQUENCER_323 0x3143547#define WM8996_WRITE_SEQUENCER_324 0x3144548#define WM8996_WRITE_SEQUENCER_325 0x3145549#define WM8996_WRITE_SEQUENCER_326 0x3146550#define WM8996_WRITE_SEQUENCER_327 0x3147551#define WM8996_WRITE_SEQUENCER_328 0x3148552#define WM8996_WRITE_SEQUENCER_329 0x3149553#define WM8996_WRITE_SEQUENCER_330 0x314A554#define WM8996_WRITE_SEQUENCER_331 0x314B555#define WM8996_WRITE_SEQUENCER_332 0x314C556#define WM8996_WRITE_SEQUENCER_333 0x314D557#define WM8996_WRITE_SEQUENCER_334 0x314E558#define WM8996_WRITE_SEQUENCER_335 0x314F559#define WM8996_WRITE_SEQUENCER_336 0x3150560#define WM8996_WRITE_SEQUENCER_337 0x3151561#define WM8996_WRITE_SEQUENCER_338 0x3152562#define WM8996_WRITE_SEQUENCER_339 0x3153563#define WM8996_WRITE_SEQUENCER_340 0x3154564#define WM8996_WRITE_SEQUENCER_341 0x3155565#define WM8996_WRITE_SEQUENCER_342 0x3156566#define WM8996_WRITE_SEQUENCER_343 0x3157567#define WM8996_WRITE_SEQUENCER_344 0x3158568#define WM8996_WRITE_SEQUENCER_345 0x3159569#define WM8996_WRITE_SEQUENCER_346 0x315A570#define WM8996_WRITE_SEQUENCER_347 0x315B571#define WM8996_WRITE_SEQUENCER_348 0x315C572#define WM8996_WRITE_SEQUENCER_349 0x315D573#define WM8996_WRITE_SEQUENCER_350 0x315E574#define WM8996_WRITE_SEQUENCER_351 0x315F575#define WM8996_WRITE_SEQUENCER_352 0x3160576#define WM8996_WRITE_SEQUENCER_353 0x3161577#define WM8996_WRITE_SEQUENCER_354 0x3162578#define WM8996_WRITE_SEQUENCER_355 0x3163579#define WM8996_WRITE_SEQUENCER_356 0x3164580#define WM8996_WRITE_SEQUENCER_357 0x3165581#define WM8996_WRITE_SEQUENCER_358 0x3166582#define WM8996_WRITE_SEQUENCER_359 0x3167583#define WM8996_WRITE_SEQUENCER_360 0x3168584#define WM8996_WRITE_SEQUENCER_361 0x3169585#define WM8996_WRITE_SEQUENCER_362 0x316A586#define WM8996_WRITE_SEQUENCER_363 0x316B587#define WM8996_WRITE_SEQUENCER_364 0x316C588#define WM8996_WRITE_SEQUENCER_365 0x316D589#define WM8996_WRITE_SEQUENCER_366 0x316E590#define WM8996_WRITE_SEQUENCER_367 0x316F591#define WM8996_WRITE_SEQUENCER_368 0x3170592#define WM8996_WRITE_SEQUENCER_369 0x3171593#define WM8996_WRITE_SEQUENCER_370 0x3172594#define WM8996_WRITE_SEQUENCER_371 0x3173595#define WM8996_WRITE_SEQUENCER_372 0x3174596#define WM8996_WRITE_SEQUENCER_373 0x3175597#define WM8996_WRITE_SEQUENCER_374 0x3176598#define WM8996_WRITE_SEQUENCER_375 0x3177599#define WM8996_WRITE_SEQUENCER_376 0x3178600#define WM8996_WRITE_SEQUENCER_377 0x3179601#define WM8996_WRITE_SEQUENCER_378 0x317A602#define WM8996_WRITE_SEQUENCER_379 0x317B603#define WM8996_WRITE_SEQUENCER_380 0x317C604#define WM8996_WRITE_SEQUENCER_381 0x317D605#define WM8996_WRITE_SEQUENCER_382 0x317E606#define WM8996_WRITE_SEQUENCER_383 0x317F607#define WM8996_WRITE_SEQUENCER_384 0x3180608#define WM8996_WRITE_SEQUENCER_385 0x3181609#define WM8996_WRITE_SEQUENCER_386 0x3182610#define WM8996_WRITE_SEQUENCER_387 0x3183611#define WM8996_WRITE_SEQUENCER_388 0x3184612#define WM8996_WRITE_SEQUENCER_389 0x3185613#define WM8996_WRITE_SEQUENCER_390 0x3186614#define WM8996_WRITE_SEQUENCER_391 0x3187615#define WM8996_WRITE_SEQUENCER_392 0x3188616#define WM8996_WRITE_SEQUENCER_393 0x3189617#define WM8996_WRITE_SEQUENCER_394 0x318A618#define WM8996_WRITE_SEQUENCER_395 0x318B619#define WM8996_WRITE_SEQUENCER_396 0x318C620#define WM8996_WRITE_SEQUENCER_397 0x318D621#define WM8996_WRITE_SEQUENCER_398 0x318E622#define WM8996_WRITE_SEQUENCER_399 0x318F623#define WM8996_WRITE_SEQUENCER_400 0x3190624#define WM8996_WRITE_SEQUENCER_401 0x3191625#define WM8996_WRITE_SEQUENCER_402 0x3192626#define WM8996_WRITE_SEQUENCER_403 0x3193627#define WM8996_WRITE_SEQUENCER_404 0x3194628#define WM8996_WRITE_SEQUENCER_405 0x3195629#define WM8996_WRITE_SEQUENCER_406 0x3196630#define WM8996_WRITE_SEQUENCER_407 0x3197631#define WM8996_WRITE_SEQUENCER_408 0x3198632#define WM8996_WRITE_SEQUENCER_409 0x3199633#define WM8996_WRITE_SEQUENCER_410 0x319A634#define WM8996_WRITE_SEQUENCER_411 0x319B635#define WM8996_WRITE_SEQUENCER_412 0x319C636#define WM8996_WRITE_SEQUENCER_413 0x319D637#define WM8996_WRITE_SEQUENCER_414 0x319E638#define WM8996_WRITE_SEQUENCER_415 0x319F639#define WM8996_WRITE_SEQUENCER_416 0x31A0640#define WM8996_WRITE_SEQUENCER_417 0x31A1641#define WM8996_WRITE_SEQUENCER_418 0x31A2642#define WM8996_WRITE_SEQUENCER_419 0x31A3643#define WM8996_WRITE_SEQUENCER_420 0x31A4644#define WM8996_WRITE_SEQUENCER_421 0x31A5645#define WM8996_WRITE_SEQUENCER_422 0x31A6646#define WM8996_WRITE_SEQUENCER_423 0x31A7647#define WM8996_WRITE_SEQUENCER_424 0x31A8648#define WM8996_WRITE_SEQUENCER_425 0x31A9649#define WM8996_WRITE_SEQUENCER_426 0x31AA650#define WM8996_WRITE_SEQUENCER_427 0x31AB651#define WM8996_WRITE_SEQUENCER_428 0x31AC652#define WM8996_WRITE_SEQUENCER_429 0x31AD653#define WM8996_WRITE_SEQUENCER_430 0x31AE654#define WM8996_WRITE_SEQUENCER_431 0x31AF655#define WM8996_WRITE_SEQUENCER_432 0x31B0656#define WM8996_WRITE_SEQUENCER_433 0x31B1657#define WM8996_WRITE_SEQUENCER_434 0x31B2658#define WM8996_WRITE_SEQUENCER_435 0x31B3659#define WM8996_WRITE_SEQUENCER_436 0x31B4660#define WM8996_WRITE_SEQUENCER_437 0x31B5661#define WM8996_WRITE_SEQUENCER_438 0x31B6662#define WM8996_WRITE_SEQUENCER_439 0x31B7663#define WM8996_WRITE_SEQUENCER_440 0x31B8664#define WM8996_WRITE_SEQUENCER_441 0x31B9665#define WM8996_WRITE_SEQUENCER_442 0x31BA666#define WM8996_WRITE_SEQUENCER_443 0x31BB667#define WM8996_WRITE_SEQUENCER_444 0x31BC668#define WM8996_WRITE_SEQUENCER_445 0x31BD669#define WM8996_WRITE_SEQUENCER_446 0x31BE670#define WM8996_WRITE_SEQUENCER_447 0x31BF671#define WM8996_WRITE_SEQUENCER_448 0x31C0672#define WM8996_WRITE_SEQUENCER_449 0x31C1673#define WM8996_WRITE_SEQUENCER_450 0x31C2674#define WM8996_WRITE_SEQUENCER_451 0x31C3675#define WM8996_WRITE_SEQUENCER_452 0x31C4676#define WM8996_WRITE_SEQUENCER_453 0x31C5677#define WM8996_WRITE_SEQUENCER_454 0x31C6678#define WM8996_WRITE_SEQUENCER_455 0x31C7679#define WM8996_WRITE_SEQUENCER_456 0x31C8680#define WM8996_WRITE_SEQUENCER_457 0x31C9681#define WM8996_WRITE_SEQUENCER_458 0x31CA682#define WM8996_WRITE_SEQUENCER_459 0x31CB683#define WM8996_WRITE_SEQUENCER_460 0x31CC684#define WM8996_WRITE_SEQUENCER_461 0x31CD685#define WM8996_WRITE_SEQUENCER_462 0x31CE686#define WM8996_WRITE_SEQUENCER_463 0x31CF687#define WM8996_WRITE_SEQUENCER_464 0x31D0688#define WM8996_WRITE_SEQUENCER_465 0x31D1689#define WM8996_WRITE_SEQUENCER_466 0x31D2690#define WM8996_WRITE_SEQUENCER_467 0x31D3691#define WM8996_WRITE_SEQUENCER_468 0x31D4692#define WM8996_WRITE_SEQUENCER_469 0x31D5693#define WM8996_WRITE_SEQUENCER_470 0x31D6694#define WM8996_WRITE_SEQUENCER_471 0x31D7695#define WM8996_WRITE_SEQUENCER_472 0x31D8696#define WM8996_WRITE_SEQUENCER_473 0x31D9697#define WM8996_WRITE_SEQUENCER_474 0x31DA698#define WM8996_WRITE_SEQUENCER_475 0x31DB699#define WM8996_WRITE_SEQUENCER_476 0x31DC700#define WM8996_WRITE_SEQUENCER_477 0x31DD701#define WM8996_WRITE_SEQUENCER_478 0x31DE702#define WM8996_WRITE_SEQUENCER_479 0x31DF703#define WM8996_WRITE_SEQUENCER_480 0x31E0704#define WM8996_WRITE_SEQUENCER_481 0x31E1705#define WM8996_WRITE_SEQUENCER_482 0x31E2706#define WM8996_WRITE_SEQUENCER_483 0x31E3707#define WM8996_WRITE_SEQUENCER_484 0x31E4708#define WM8996_WRITE_SEQUENCER_485 0x31E5709#define WM8996_WRITE_SEQUENCER_486 0x31E6710#define WM8996_WRITE_SEQUENCER_487 0x31E7711#define WM8996_WRITE_SEQUENCER_488 0x31E8712#define WM8996_WRITE_SEQUENCER_489 0x31E9713#define WM8996_WRITE_SEQUENCER_490 0x31EA714#define WM8996_WRITE_SEQUENCER_491 0x31EB715#define WM8996_WRITE_SEQUENCER_492 0x31EC716#define WM8996_WRITE_SEQUENCER_493 0x31ED717#define WM8996_WRITE_SEQUENCER_494 0x31EE718#define WM8996_WRITE_SEQUENCER_495 0x31EF719#define WM8996_WRITE_SEQUENCER_496 0x31F0720#define WM8996_WRITE_SEQUENCER_497 0x31F1721#define WM8996_WRITE_SEQUENCER_498 0x31F2722#define WM8996_WRITE_SEQUENCER_499 0x31F3723#define WM8996_WRITE_SEQUENCER_500 0x31F4724#define WM8996_WRITE_SEQUENCER_501 0x31F5725#define WM8996_WRITE_SEQUENCER_502 0x31F6726#define WM8996_WRITE_SEQUENCER_503 0x31F7727#define WM8996_WRITE_SEQUENCER_504 0x31F8728#define WM8996_WRITE_SEQUENCER_505 0x31F9729#define WM8996_WRITE_SEQUENCER_506 0x31FA730#define WM8996_WRITE_SEQUENCER_507 0x31FB731#define WM8996_WRITE_SEQUENCER_508 0x31FC732#define WM8996_WRITE_SEQUENCER_509 0x31FD733#define WM8996_WRITE_SEQUENCER_510 0x31FE734#define WM8996_WRITE_SEQUENCER_511 0x31FF735 736#define WM8996_REGISTER_COUNT 706737#define WM8996_MAX_REGISTER 0x31FF738 739/*740 * Field Definitions.741 */742 743/*744 * R0 (0x00) - Software Reset745 */746#define WM8996_SW_RESET_MASK 0xFFFF /* SW_RESET - [15:0] */747#define WM8996_SW_RESET_SHIFT 0 /* SW_RESET - [15:0] */748#define WM8996_SW_RESET_WIDTH 16 /* SW_RESET - [15:0] */749 750/*751 * R1 (0x01) - Power Management (1)752 */753#define WM8996_MICB2_ENA 0x0200 /* MICB2_ENA */754#define WM8996_MICB2_ENA_MASK 0x0200 /* MICB2_ENA */755#define WM8996_MICB2_ENA_SHIFT 9 /* MICB2_ENA */756#define WM8996_MICB2_ENA_WIDTH 1 /* MICB2_ENA */757#define WM8996_MICB1_ENA 0x0100 /* MICB1_ENA */758#define WM8996_MICB1_ENA_MASK 0x0100 /* MICB1_ENA */759#define WM8996_MICB1_ENA_SHIFT 8 /* MICB1_ENA */760#define WM8996_MICB1_ENA_WIDTH 1 /* MICB1_ENA */761#define WM8996_HPOUT2L_ENA 0x0080 /* HPOUT2L_ENA */762#define WM8996_HPOUT2L_ENA_MASK 0x0080 /* HPOUT2L_ENA */763#define WM8996_HPOUT2L_ENA_SHIFT 7 /* HPOUT2L_ENA */764#define WM8996_HPOUT2L_ENA_WIDTH 1 /* HPOUT2L_ENA */765#define WM8996_HPOUT2R_ENA 0x0040 /* HPOUT2R_ENA */766#define WM8996_HPOUT2R_ENA_MASK 0x0040 /* HPOUT2R_ENA */767#define WM8996_HPOUT2R_ENA_SHIFT 6 /* HPOUT2R_ENA */768#define WM8996_HPOUT2R_ENA_WIDTH 1 /* HPOUT2R_ENA */769#define WM8996_HPOUT1L_ENA 0x0020 /* HPOUT1L_ENA */770#define WM8996_HPOUT1L_ENA_MASK 0x0020 /* HPOUT1L_ENA */771#define WM8996_HPOUT1L_ENA_SHIFT 5 /* HPOUT1L_ENA */772#define WM8996_HPOUT1L_ENA_WIDTH 1 /* HPOUT1L_ENA */773#define WM8996_HPOUT1R_ENA 0x0010 /* HPOUT1R_ENA */774#define WM8996_HPOUT1R_ENA_MASK 0x0010 /* HPOUT1R_ENA */775#define WM8996_HPOUT1R_ENA_SHIFT 4 /* HPOUT1R_ENA */776#define WM8996_HPOUT1R_ENA_WIDTH 1 /* HPOUT1R_ENA */777#define WM8996_BG_ENA 0x0001 /* BG_ENA */778#define WM8996_BG_ENA_MASK 0x0001 /* BG_ENA */779#define WM8996_BG_ENA_SHIFT 0 /* BG_ENA */780#define WM8996_BG_ENA_WIDTH 1 /* BG_ENA */781 782/*783 * R2 (0x02) - Power Management (2)784 */785#define WM8996_OPCLK_ENA 0x0800 /* OPCLK_ENA */786#define WM8996_OPCLK_ENA_MASK 0x0800 /* OPCLK_ENA */787#define WM8996_OPCLK_ENA_SHIFT 11 /* OPCLK_ENA */788#define WM8996_OPCLK_ENA_WIDTH 1 /* OPCLK_ENA */789#define WM8996_INL_ENA 0x0020 /* INL_ENA */790#define WM8996_INL_ENA_MASK 0x0020 /* INL_ENA */791#define WM8996_INL_ENA_SHIFT 5 /* INL_ENA */792#define WM8996_INL_ENA_WIDTH 1 /* INL_ENA */793#define WM8996_INR_ENA 0x0010 /* INR_ENA */794#define WM8996_INR_ENA_MASK 0x0010 /* INR_ENA */795#define WM8996_INR_ENA_SHIFT 4 /* INR_ENA */796#define WM8996_INR_ENA_WIDTH 1 /* INR_ENA */797#define WM8996_LDO2_ENA 0x0002 /* LDO2_ENA */798#define WM8996_LDO2_ENA_MASK 0x0002 /* LDO2_ENA */799#define WM8996_LDO2_ENA_SHIFT 1 /* LDO2_ENA */800#define WM8996_LDO2_ENA_WIDTH 1 /* LDO2_ENA */801 802/*803 * R3 (0x03) - Power Management (3)804 */805#define WM8996_DSP2RXL_ENA 0x0800 /* DSP2RXL_ENA */806#define WM8996_DSP2RXL_ENA_MASK 0x0800 /* DSP2RXL_ENA */807#define WM8996_DSP2RXL_ENA_SHIFT 11 /* DSP2RXL_ENA */808#define WM8996_DSP2RXL_ENA_WIDTH 1 /* DSP2RXL_ENA */809#define WM8996_DSP2RXR_ENA 0x0400 /* DSP2RXR_ENA */810#define WM8996_DSP2RXR_ENA_MASK 0x0400 /* DSP2RXR_ENA */811#define WM8996_DSP2RXR_ENA_SHIFT 10 /* DSP2RXR_ENA */812#define WM8996_DSP2RXR_ENA_WIDTH 1 /* DSP2RXR_ENA */813#define WM8996_DSP1RXL_ENA 0x0200 /* DSP1RXL_ENA */814#define WM8996_DSP1RXL_ENA_MASK 0x0200 /* DSP1RXL_ENA */815#define WM8996_DSP1RXL_ENA_SHIFT 9 /* DSP1RXL_ENA */816#define WM8996_DSP1RXL_ENA_WIDTH 1 /* DSP1RXL_ENA */817#define WM8996_DSP1RXR_ENA 0x0100 /* DSP1RXR_ENA */818#define WM8996_DSP1RXR_ENA_MASK 0x0100 /* DSP1RXR_ENA */819#define WM8996_DSP1RXR_ENA_SHIFT 8 /* DSP1RXR_ENA */820#define WM8996_DSP1RXR_ENA_WIDTH 1 /* DSP1RXR_ENA */821#define WM8996_DMIC2L_ENA 0x0020 /* DMIC2L_ENA */822#define WM8996_DMIC2L_ENA_MASK 0x0020 /* DMIC2L_ENA */823#define WM8996_DMIC2L_ENA_SHIFT 5 /* DMIC2L_ENA */824#define WM8996_DMIC2L_ENA_WIDTH 1 /* DMIC2L_ENA */825#define WM8996_DMIC2R_ENA 0x0010 /* DMIC2R_ENA */826#define WM8996_DMIC2R_ENA_MASK 0x0010 /* DMIC2R_ENA */827#define WM8996_DMIC2R_ENA_SHIFT 4 /* DMIC2R_ENA */828#define WM8996_DMIC2R_ENA_WIDTH 1 /* DMIC2R_ENA */829#define WM8996_DMIC1L_ENA 0x0008 /* DMIC1L_ENA */830#define WM8996_DMIC1L_ENA_MASK 0x0008 /* DMIC1L_ENA */831#define WM8996_DMIC1L_ENA_SHIFT 3 /* DMIC1L_ENA */832#define WM8996_DMIC1L_ENA_WIDTH 1 /* DMIC1L_ENA */833#define WM8996_DMIC1R_ENA 0x0004 /* DMIC1R_ENA */834#define WM8996_DMIC1R_ENA_MASK 0x0004 /* DMIC1R_ENA */835#define WM8996_DMIC1R_ENA_SHIFT 2 /* DMIC1R_ENA */836#define WM8996_DMIC1R_ENA_WIDTH 1 /* DMIC1R_ENA */837#define WM8996_ADCL_ENA 0x0002 /* ADCL_ENA */838#define WM8996_ADCL_ENA_MASK 0x0002 /* ADCL_ENA */839#define WM8996_ADCL_ENA_SHIFT 1 /* ADCL_ENA */840#define WM8996_ADCL_ENA_WIDTH 1 /* ADCL_ENA */841#define WM8996_ADCR_ENA 0x0001 /* ADCR_ENA */842#define WM8996_ADCR_ENA_MASK 0x0001 /* ADCR_ENA */843#define WM8996_ADCR_ENA_SHIFT 0 /* ADCR_ENA */844#define WM8996_ADCR_ENA_WIDTH 1 /* ADCR_ENA */845 846/*847 * R4 (0x04) - Power Management (4)848 */849#define WM8996_AIF2RX_CHAN1_ENA 0x0200 /* AIF2RX_CHAN1_ENA */850#define WM8996_AIF2RX_CHAN1_ENA_MASK 0x0200 /* AIF2RX_CHAN1_ENA */851#define WM8996_AIF2RX_CHAN1_ENA_SHIFT 9 /* AIF2RX_CHAN1_ENA */852#define WM8996_AIF2RX_CHAN1_ENA_WIDTH 1 /* AIF2RX_CHAN1_ENA */853#define WM8996_AIF2RX_CHAN0_ENA 0x0100 /* AIF2RX_CHAN0_ENA */854#define WM8996_AIF2RX_CHAN0_ENA_MASK 0x0100 /* AIF2RX_CHAN0_ENA */855#define WM8996_AIF2RX_CHAN0_ENA_SHIFT 8 /* AIF2RX_CHAN0_ENA */856#define WM8996_AIF2RX_CHAN0_ENA_WIDTH 1 /* AIF2RX_CHAN0_ENA */857#define WM8996_AIF1RX_CHAN5_ENA 0x0020 /* AIF1RX_CHAN5_ENA */858#define WM8996_AIF1RX_CHAN5_ENA_MASK 0x0020 /* AIF1RX_CHAN5_ENA */859#define WM8996_AIF1RX_CHAN5_ENA_SHIFT 5 /* AIF1RX_CHAN5_ENA */860#define WM8996_AIF1RX_CHAN5_ENA_WIDTH 1 /* AIF1RX_CHAN5_ENA */861#define WM8996_AIF1RX_CHAN4_ENA 0x0010 /* AIF1RX_CHAN4_ENA */862#define WM8996_AIF1RX_CHAN4_ENA_MASK 0x0010 /* AIF1RX_CHAN4_ENA */863#define WM8996_AIF1RX_CHAN4_ENA_SHIFT 4 /* AIF1RX_CHAN4_ENA */864#define WM8996_AIF1RX_CHAN4_ENA_WIDTH 1 /* AIF1RX_CHAN4_ENA */865#define WM8996_AIF1RX_CHAN3_ENA 0x0008 /* AIF1RX_CHAN3_ENA */866#define WM8996_AIF1RX_CHAN3_ENA_MASK 0x0008 /* AIF1RX_CHAN3_ENA */867#define WM8996_AIF1RX_CHAN3_ENA_SHIFT 3 /* AIF1RX_CHAN3_ENA */868#define WM8996_AIF1RX_CHAN3_ENA_WIDTH 1 /* AIF1RX_CHAN3_ENA */869#define WM8996_AIF1RX_CHAN2_ENA 0x0004 /* AIF1RX_CHAN2_ENA */870#define WM8996_AIF1RX_CHAN2_ENA_MASK 0x0004 /* AIF1RX_CHAN2_ENA */871#define WM8996_AIF1RX_CHAN2_ENA_SHIFT 2 /* AIF1RX_CHAN2_ENA */872#define WM8996_AIF1RX_CHAN2_ENA_WIDTH 1 /* AIF1RX_CHAN2_ENA */873#define WM8996_AIF1RX_CHAN1_ENA 0x0002 /* AIF1RX_CHAN1_ENA */874#define WM8996_AIF1RX_CHAN1_ENA_MASK 0x0002 /* AIF1RX_CHAN1_ENA */875#define WM8996_AIF1RX_CHAN1_ENA_SHIFT 1 /* AIF1RX_CHAN1_ENA */876#define WM8996_AIF1RX_CHAN1_ENA_WIDTH 1 /* AIF1RX_CHAN1_ENA */877#define WM8996_AIF1RX_CHAN0_ENA 0x0001 /* AIF1RX_CHAN0_ENA */878#define WM8996_AIF1RX_CHAN0_ENA_MASK 0x0001 /* AIF1RX_CHAN0_ENA */879#define WM8996_AIF1RX_CHAN0_ENA_SHIFT 0 /* AIF1RX_CHAN0_ENA */880#define WM8996_AIF1RX_CHAN0_ENA_WIDTH 1 /* AIF1RX_CHAN0_ENA */881 882/*883 * R5 (0x05) - Power Management (5)884 */885#define WM8996_DSP2TXL_ENA 0x0800 /* DSP2TXL_ENA */886#define WM8996_DSP2TXL_ENA_MASK 0x0800 /* DSP2TXL_ENA */887#define WM8996_DSP2TXL_ENA_SHIFT 11 /* DSP2TXL_ENA */888#define WM8996_DSP2TXL_ENA_WIDTH 1 /* DSP2TXL_ENA */889#define WM8996_DSP2TXR_ENA 0x0400 /* DSP2TXR_ENA */890#define WM8996_DSP2TXR_ENA_MASK 0x0400 /* DSP2TXR_ENA */891#define WM8996_DSP2TXR_ENA_SHIFT 10 /* DSP2TXR_ENA */892#define WM8996_DSP2TXR_ENA_WIDTH 1 /* DSP2TXR_ENA */893#define WM8996_DSP1TXL_ENA 0x0200 /* DSP1TXL_ENA */894#define WM8996_DSP1TXL_ENA_MASK 0x0200 /* DSP1TXL_ENA */895#define WM8996_DSP1TXL_ENA_SHIFT 9 /* DSP1TXL_ENA */896#define WM8996_DSP1TXL_ENA_WIDTH 1 /* DSP1TXL_ENA */897#define WM8996_DSP1TXR_ENA 0x0100 /* DSP1TXR_ENA */898#define WM8996_DSP1TXR_ENA_MASK 0x0100 /* DSP1TXR_ENA */899#define WM8996_DSP1TXR_ENA_SHIFT 8 /* DSP1TXR_ENA */900#define WM8996_DSP1TXR_ENA_WIDTH 1 /* DSP1TXR_ENA */901#define WM8996_DAC2L_ENA 0x0008 /* DAC2L_ENA */902#define WM8996_DAC2L_ENA_MASK 0x0008 /* DAC2L_ENA */903#define WM8996_DAC2L_ENA_SHIFT 3 /* DAC2L_ENA */904#define WM8996_DAC2L_ENA_WIDTH 1 /* DAC2L_ENA */905#define WM8996_DAC2R_ENA 0x0004 /* DAC2R_ENA */906#define WM8996_DAC2R_ENA_MASK 0x0004 /* DAC2R_ENA */907#define WM8996_DAC2R_ENA_SHIFT 2 /* DAC2R_ENA */908#define WM8996_DAC2R_ENA_WIDTH 1 /* DAC2R_ENA */909#define WM8996_DAC1L_ENA 0x0002 /* DAC1L_ENA */910#define WM8996_DAC1L_ENA_MASK 0x0002 /* DAC1L_ENA */911#define WM8996_DAC1L_ENA_SHIFT 1 /* DAC1L_ENA */912#define WM8996_DAC1L_ENA_WIDTH 1 /* DAC1L_ENA */913#define WM8996_DAC1R_ENA 0x0001 /* DAC1R_ENA */914#define WM8996_DAC1R_ENA_MASK 0x0001 /* DAC1R_ENA */915#define WM8996_DAC1R_ENA_SHIFT 0 /* DAC1R_ENA */916#define WM8996_DAC1R_ENA_WIDTH 1 /* DAC1R_ENA */917 918/*919 * R6 (0x06) - Power Management (6)920 */921#define WM8996_AIF2TX_CHAN1_ENA 0x0200 /* AIF2TX_CHAN1_ENA */922#define WM8996_AIF2TX_CHAN1_ENA_MASK 0x0200 /* AIF2TX_CHAN1_ENA */923#define WM8996_AIF2TX_CHAN1_ENA_SHIFT 9 /* AIF2TX_CHAN1_ENA */924#define WM8996_AIF2TX_CHAN1_ENA_WIDTH 1 /* AIF2TX_CHAN1_ENA */925#define WM8996_AIF2TX_CHAN0_ENA 0x0100 /* AIF2TX_CHAN0_ENA */926#define WM8996_AIF2TX_CHAN0_ENA_MASK 0x0100 /* AIF2TX_CHAN0_ENA */927#define WM8996_AIF2TX_CHAN0_ENA_SHIFT 8 /* AIF2TX_CHAN0_ENA */928#define WM8996_AIF2TX_CHAN0_ENA_WIDTH 1 /* AIF2TX_CHAN0_ENA */929#define WM8996_AIF1TX_CHAN5_ENA 0x0020 /* AIF1TX_CHAN5_ENA */930#define WM8996_AIF1TX_CHAN5_ENA_MASK 0x0020 /* AIF1TX_CHAN5_ENA */931#define WM8996_AIF1TX_CHAN5_ENA_SHIFT 5 /* AIF1TX_CHAN5_ENA */932#define WM8996_AIF1TX_CHAN5_ENA_WIDTH 1 /* AIF1TX_CHAN5_ENA */933#define WM8996_AIF1TX_CHAN4_ENA 0x0010 /* AIF1TX_CHAN4_ENA */934#define WM8996_AIF1TX_CHAN4_ENA_MASK 0x0010 /* AIF1TX_CHAN4_ENA */935#define WM8996_AIF1TX_CHAN4_ENA_SHIFT 4 /* AIF1TX_CHAN4_ENA */936#define WM8996_AIF1TX_CHAN4_ENA_WIDTH 1 /* AIF1TX_CHAN4_ENA */937#define WM8996_AIF1TX_CHAN3_ENA 0x0008 /* AIF1TX_CHAN3_ENA */938#define WM8996_AIF1TX_CHAN3_ENA_MASK 0x0008 /* AIF1TX_CHAN3_ENA */939#define WM8996_AIF1TX_CHAN3_ENA_SHIFT 3 /* AIF1TX_CHAN3_ENA */940#define WM8996_AIF1TX_CHAN3_ENA_WIDTH 1 /* AIF1TX_CHAN3_ENA */941#define WM8996_AIF1TX_CHAN2_ENA 0x0004 /* AIF1TX_CHAN2_ENA */942#define WM8996_AIF1TX_CHAN2_ENA_MASK 0x0004 /* AIF1TX_CHAN2_ENA */943#define WM8996_AIF1TX_CHAN2_ENA_SHIFT 2 /* AIF1TX_CHAN2_ENA */944#define WM8996_AIF1TX_CHAN2_ENA_WIDTH 1 /* AIF1TX_CHAN2_ENA */945#define WM8996_AIF1TX_CHAN1_ENA 0x0002 /* AIF1TX_CHAN1_ENA */946#define WM8996_AIF1TX_CHAN1_ENA_MASK 0x0002 /* AIF1TX_CHAN1_ENA */947#define WM8996_AIF1TX_CHAN1_ENA_SHIFT 1 /* AIF1TX_CHAN1_ENA */948#define WM8996_AIF1TX_CHAN1_ENA_WIDTH 1 /* AIF1TX_CHAN1_ENA */949#define WM8996_AIF1TX_CHAN0_ENA 0x0001 /* AIF1TX_CHAN0_ENA */950#define WM8996_AIF1TX_CHAN0_ENA_MASK 0x0001 /* AIF1TX_CHAN0_ENA */951#define WM8996_AIF1TX_CHAN0_ENA_SHIFT 0 /* AIF1TX_CHAN0_ENA */952#define WM8996_AIF1TX_CHAN0_ENA_WIDTH 1 /* AIF1TX_CHAN0_ENA */953 954/*955 * R7 (0x07) - Power Management (7)956 */957#define WM8996_DMIC2_FN 0x0200 /* DMIC2_FN */958#define WM8996_DMIC2_FN_MASK 0x0200 /* DMIC2_FN */959#define WM8996_DMIC2_FN_SHIFT 9 /* DMIC2_FN */960#define WM8996_DMIC2_FN_WIDTH 1 /* DMIC2_FN */961#define WM8996_DMIC1_FN 0x0100 /* DMIC1_FN */962#define WM8996_DMIC1_FN_MASK 0x0100 /* DMIC1_FN */963#define WM8996_DMIC1_FN_SHIFT 8 /* DMIC1_FN */964#define WM8996_DMIC1_FN_WIDTH 1 /* DMIC1_FN */965#define WM8996_ADC_DMIC_DSP2R_ENA 0x0080 /* ADC_DMIC_DSP2R_ENA */966#define WM8996_ADC_DMIC_DSP2R_ENA_MASK 0x0080 /* ADC_DMIC_DSP2R_ENA */967#define WM8996_ADC_DMIC_DSP2R_ENA_SHIFT 7 /* ADC_DMIC_DSP2R_ENA */968#define WM8996_ADC_DMIC_DSP2R_ENA_WIDTH 1 /* ADC_DMIC_DSP2R_ENA */969#define WM8996_ADC_DMIC_DSP2L_ENA 0x0040 /* ADC_DMIC_DSP2L_ENA */970#define WM8996_ADC_DMIC_DSP2L_ENA_MASK 0x0040 /* ADC_DMIC_DSP2L_ENA */971#define WM8996_ADC_DMIC_DSP2L_ENA_SHIFT 6 /* ADC_DMIC_DSP2L_ENA */972#define WM8996_ADC_DMIC_DSP2L_ENA_WIDTH 1 /* ADC_DMIC_DSP2L_ENA */973#define WM8996_ADC_DMIC_SRC2_MASK 0x0030 /* ADC_DMIC_SRC2 - [5:4] */974#define WM8996_ADC_DMIC_SRC2_SHIFT 4 /* ADC_DMIC_SRC2 - [5:4] */975#define WM8996_ADC_DMIC_SRC2_WIDTH 2 /* ADC_DMIC_SRC2 - [5:4] */976#define WM8996_ADC_DMIC_DSP1R_ENA 0x0008 /* ADC_DMIC_DSP1R_ENA */977#define WM8996_ADC_DMIC_DSP1R_ENA_MASK 0x0008 /* ADC_DMIC_DSP1R_ENA */978#define WM8996_ADC_DMIC_DSP1R_ENA_SHIFT 3 /* ADC_DMIC_DSP1R_ENA */979#define WM8996_ADC_DMIC_DSP1R_ENA_WIDTH 1 /* ADC_DMIC_DSP1R_ENA */980#define WM8996_ADC_DMIC_DSP1L_ENA 0x0004 /* ADC_DMIC_DSP1L_ENA */981#define WM8996_ADC_DMIC_DSP1L_ENA_MASK 0x0004 /* ADC_DMIC_DSP1L_ENA */982#define WM8996_ADC_DMIC_DSP1L_ENA_SHIFT 2 /* ADC_DMIC_DSP1L_ENA */983#define WM8996_ADC_DMIC_DSP1L_ENA_WIDTH 1 /* ADC_DMIC_DSP1L_ENA */984#define WM8996_ADC_DMIC_SRC1_MASK 0x0003 /* ADC_DMIC_SRC1 - [1:0] */985#define WM8996_ADC_DMIC_SRC1_SHIFT 0 /* ADC_DMIC_SRC1 - [1:0] */986#define WM8996_ADC_DMIC_SRC1_WIDTH 2 /* ADC_DMIC_SRC1 - [1:0] */987 988/*989 * R8 (0x08) - Power Management (8)990 */991#define WM8996_AIF2TX_SRC_MASK 0x00C0 /* AIF2TX_SRC - [7:6] */992#define WM8996_AIF2TX_SRC_SHIFT 6 /* AIF2TX_SRC - [7:6] */993#define WM8996_AIF2TX_SRC_WIDTH 2 /* AIF2TX_SRC - [7:6] */994#define WM8996_DSP2RX_SRC 0x0010 /* DSP2RX_SRC */995#define WM8996_DSP2RX_SRC_MASK 0x0010 /* DSP2RX_SRC */996#define WM8996_DSP2RX_SRC_SHIFT 4 /* DSP2RX_SRC */997#define WM8996_DSP2RX_SRC_WIDTH 1 /* DSP2RX_SRC */998#define WM8996_DSP1RX_SRC 0x0001 /* DSP1RX_SRC */999#define WM8996_DSP1RX_SRC_MASK 0x0001 /* DSP1RX_SRC */1000#define WM8996_DSP1RX_SRC_SHIFT 0 /* DSP1RX_SRC */1001#define WM8996_DSP1RX_SRC_WIDTH 1 /* DSP1RX_SRC */1002 1003/*1004 * R16 (0x10) - Left Line Input Volume1005 */1006#define WM8996_IN1_VU 0x0080 /* IN1_VU */1007#define WM8996_IN1_VU_MASK 0x0080 /* IN1_VU */1008#define WM8996_IN1_VU_SHIFT 7 /* IN1_VU */1009#define WM8996_IN1_VU_WIDTH 1 /* IN1_VU */1010#define WM8996_IN1L_ZC 0x0020 /* IN1L_ZC */1011#define WM8996_IN1L_ZC_MASK 0x0020 /* IN1L_ZC */1012#define WM8996_IN1L_ZC_SHIFT 5 /* IN1L_ZC */1013#define WM8996_IN1L_ZC_WIDTH 1 /* IN1L_ZC */1014#define WM8996_IN1L_VOL_MASK 0x001F /* IN1L_VOL - [4:0] */1015#define WM8996_IN1L_VOL_SHIFT 0 /* IN1L_VOL - [4:0] */1016#define WM8996_IN1L_VOL_WIDTH 5 /* IN1L_VOL - [4:0] */1017 1018/*1019 * R17 (0x11) - Right Line Input Volume1020 */1021#define WM8996_IN1_VU 0x0080 /* IN1_VU */1022#define WM8996_IN1_VU_MASK 0x0080 /* IN1_VU */1023#define WM8996_IN1_VU_SHIFT 7 /* IN1_VU */1024#define WM8996_IN1_VU_WIDTH 1 /* IN1_VU */1025#define WM8996_IN1R_ZC 0x0020 /* IN1R_ZC */1026#define WM8996_IN1R_ZC_MASK 0x0020 /* IN1R_ZC */1027#define WM8996_IN1R_ZC_SHIFT 5 /* IN1R_ZC */1028#define WM8996_IN1R_ZC_WIDTH 1 /* IN1R_ZC */1029#define WM8996_IN1R_VOL_MASK 0x001F /* IN1R_VOL - [4:0] */1030#define WM8996_IN1R_VOL_SHIFT 0 /* IN1R_VOL - [4:0] */1031#define WM8996_IN1R_VOL_WIDTH 5 /* IN1R_VOL - [4:0] */1032 1033/*1034 * R18 (0x12) - Line Input Control1035 */1036#define WM8996_INL_MODE_MASK 0x000C /* INL_MODE - [3:2] */1037#define WM8996_INL_MODE_SHIFT 2 /* INL_MODE - [3:2] */1038#define WM8996_INL_MODE_WIDTH 2 /* INL_MODE - [3:2] */1039#define WM8996_INR_MODE_MASK 0x0003 /* INR_MODE - [1:0] */1040#define WM8996_INR_MODE_SHIFT 0 /* INR_MODE - [1:0] */1041#define WM8996_INR_MODE_WIDTH 2 /* INR_MODE - [1:0] */1042 1043/*1044 * R21 (0x15) - DAC1 HPOUT1 Volume1045 */1046#define WM8996_DAC1R_HPOUT1R_VOL_MASK 0x00F0 /* DAC1R_HPOUT1R_VOL - [7:4] */1047#define WM8996_DAC1R_HPOUT1R_VOL_SHIFT 4 /* DAC1R_HPOUT1R_VOL - [7:4] */1048#define WM8996_DAC1R_HPOUT1R_VOL_WIDTH 4 /* DAC1R_HPOUT1R_VOL - [7:4] */1049#define WM8996_DAC1L_HPOUT1L_VOL_MASK 0x000F /* DAC1L_HPOUT1L_VOL - [3:0] */1050#define WM8996_DAC1L_HPOUT1L_VOL_SHIFT 0 /* DAC1L_HPOUT1L_VOL - [3:0] */1051#define WM8996_DAC1L_HPOUT1L_VOL_WIDTH 4 /* DAC1L_HPOUT1L_VOL - [3:0] */1052 1053/*1054 * R22 (0x16) - DAC2 HPOUT2 Volume1055 */1056#define WM8996_DAC2R_HPOUT2R_VOL_MASK 0x00F0 /* DAC2R_HPOUT2R_VOL - [7:4] */1057#define WM8996_DAC2R_HPOUT2R_VOL_SHIFT 4 /* DAC2R_HPOUT2R_VOL - [7:4] */1058#define WM8996_DAC2R_HPOUT2R_VOL_WIDTH 4 /* DAC2R_HPOUT2R_VOL - [7:4] */1059#define WM8996_DAC2L_HPOUT2L_VOL_MASK 0x000F /* DAC2L_HPOUT2L_VOL - [3:0] */1060#define WM8996_DAC2L_HPOUT2L_VOL_SHIFT 0 /* DAC2L_HPOUT2L_VOL - [3:0] */1061#define WM8996_DAC2L_HPOUT2L_VOL_WIDTH 4 /* DAC2L_HPOUT2L_VOL - [3:0] */1062 1063/*1064 * R24 (0x18) - DAC1 Left Volume1065 */1066#define WM8996_DAC1L_MUTE 0x0200 /* DAC1L_MUTE */1067#define WM8996_DAC1L_MUTE_MASK 0x0200 /* DAC1L_MUTE */1068#define WM8996_DAC1L_MUTE_SHIFT 9 /* DAC1L_MUTE */1069#define WM8996_DAC1L_MUTE_WIDTH 1 /* DAC1L_MUTE */1070#define WM8996_DAC1_VU 0x0100 /* DAC1_VU */1071#define WM8996_DAC1_VU_MASK 0x0100 /* DAC1_VU */1072#define WM8996_DAC1_VU_SHIFT 8 /* DAC1_VU */1073#define WM8996_DAC1_VU_WIDTH 1 /* DAC1_VU */1074#define WM8996_DAC1L_VOL_MASK 0x00FF /* DAC1L_VOL - [7:0] */1075#define WM8996_DAC1L_VOL_SHIFT 0 /* DAC1L_VOL - [7:0] */1076#define WM8996_DAC1L_VOL_WIDTH 8 /* DAC1L_VOL - [7:0] */1077 1078/*1079 * R25 (0x19) - DAC1 Right Volume1080 */1081#define WM8996_DAC1R_MUTE 0x0200 /* DAC1R_MUTE */1082#define WM8996_DAC1R_MUTE_MASK 0x0200 /* DAC1R_MUTE */1083#define WM8996_DAC1R_MUTE_SHIFT 9 /* DAC1R_MUTE */1084#define WM8996_DAC1R_MUTE_WIDTH 1 /* DAC1R_MUTE */1085#define WM8996_DAC1_VU 0x0100 /* DAC1_VU */1086#define WM8996_DAC1_VU_MASK 0x0100 /* DAC1_VU */1087#define WM8996_DAC1_VU_SHIFT 8 /* DAC1_VU */1088#define WM8996_DAC1_VU_WIDTH 1 /* DAC1_VU */1089#define WM8996_DAC1R_VOL_MASK 0x00FF /* DAC1R_VOL - [7:0] */1090#define WM8996_DAC1R_VOL_SHIFT 0 /* DAC1R_VOL - [7:0] */1091#define WM8996_DAC1R_VOL_WIDTH 8 /* DAC1R_VOL - [7:0] */1092 1093/*1094 * R26 (0x1A) - DAC2 Left Volume1095 */1096#define WM8996_DAC2L_MUTE 0x0200 /* DAC2L_MUTE */1097#define WM8996_DAC2L_MUTE_MASK 0x0200 /* DAC2L_MUTE */1098#define WM8996_DAC2L_MUTE_SHIFT 9 /* DAC2L_MUTE */1099#define WM8996_DAC2L_MUTE_WIDTH 1 /* DAC2L_MUTE */1100#define WM8996_DAC2_VU 0x0100 /* DAC2_VU */1101#define WM8996_DAC2_VU_MASK 0x0100 /* DAC2_VU */1102#define WM8996_DAC2_VU_SHIFT 8 /* DAC2_VU */1103#define WM8996_DAC2_VU_WIDTH 1 /* DAC2_VU */1104#define WM8996_DAC2L_VOL_MASK 0x00FF /* DAC2L_VOL - [7:0] */1105#define WM8996_DAC2L_VOL_SHIFT 0 /* DAC2L_VOL - [7:0] */1106#define WM8996_DAC2L_VOL_WIDTH 8 /* DAC2L_VOL - [7:0] */1107 1108/*1109 * R27 (0x1B) - DAC2 Right Volume1110 */1111#define WM8996_DAC2R_MUTE 0x0200 /* DAC2R_MUTE */1112#define WM8996_DAC2R_MUTE_MASK 0x0200 /* DAC2R_MUTE */1113#define WM8996_DAC2R_MUTE_SHIFT 9 /* DAC2R_MUTE */1114#define WM8996_DAC2R_MUTE_WIDTH 1 /* DAC2R_MUTE */1115#define WM8996_DAC2_VU 0x0100 /* DAC2_VU */1116#define WM8996_DAC2_VU_MASK 0x0100 /* DAC2_VU */1117#define WM8996_DAC2_VU_SHIFT 8 /* DAC2_VU */1118#define WM8996_DAC2_VU_WIDTH 1 /* DAC2_VU */1119#define WM8996_DAC2R_VOL_MASK 0x00FF /* DAC2R_VOL - [7:0] */1120#define WM8996_DAC2R_VOL_SHIFT 0 /* DAC2R_VOL - [7:0] */1121#define WM8996_DAC2R_VOL_WIDTH 8 /* DAC2R_VOL - [7:0] */1122 1123/*1124 * R28 (0x1C) - Output1 Left Volume1125 */1126#define WM8996_DAC1_VU 0x0100 /* DAC1_VU */1127#define WM8996_DAC1_VU_MASK 0x0100 /* DAC1_VU */1128#define WM8996_DAC1_VU_SHIFT 8 /* DAC1_VU */1129#define WM8996_DAC1_VU_WIDTH 1 /* DAC1_VU */1130#define WM8996_HPOUT1L_ZC 0x0080 /* HPOUT1L_ZC */1131#define WM8996_HPOUT1L_ZC_MASK 0x0080 /* HPOUT1L_ZC */1132#define WM8996_HPOUT1L_ZC_SHIFT 7 /* HPOUT1L_ZC */1133#define WM8996_HPOUT1L_ZC_WIDTH 1 /* HPOUT1L_ZC */1134#define WM8996_HPOUT1L_VOL_MASK 0x000F /* HPOUT1L_VOL - [3:0] */1135#define WM8996_HPOUT1L_VOL_SHIFT 0 /* HPOUT1L_VOL - [3:0] */1136#define WM8996_HPOUT1L_VOL_WIDTH 4 /* HPOUT1L_VOL - [3:0] */1137 1138/*1139 * R29 (0x1D) - Output1 Right Volume1140 */1141#define WM8996_DAC1_VU 0x0100 /* DAC1_VU */1142#define WM8996_DAC1_VU_MASK 0x0100 /* DAC1_VU */1143#define WM8996_DAC1_VU_SHIFT 8 /* DAC1_VU */1144#define WM8996_DAC1_VU_WIDTH 1 /* DAC1_VU */1145#define WM8996_HPOUT1R_ZC 0x0080 /* HPOUT1R_ZC */1146#define WM8996_HPOUT1R_ZC_MASK 0x0080 /* HPOUT1R_ZC */1147#define WM8996_HPOUT1R_ZC_SHIFT 7 /* HPOUT1R_ZC */1148#define WM8996_HPOUT1R_ZC_WIDTH 1 /* HPOUT1R_ZC */1149#define WM8996_HPOUT1R_VOL_MASK 0x000F /* HPOUT1R_VOL - [3:0] */1150#define WM8996_HPOUT1R_VOL_SHIFT 0 /* HPOUT1R_VOL - [3:0] */1151#define WM8996_HPOUT1R_VOL_WIDTH 4 /* HPOUT1R_VOL - [3:0] */1152 1153/*1154 * R30 (0x1E) - Output2 Left Volume1155 */1156#define WM8996_DAC2_VU 0x0100 /* DAC2_VU */1157#define WM8996_DAC2_VU_MASK 0x0100 /* DAC2_VU */1158#define WM8996_DAC2_VU_SHIFT 8 /* DAC2_VU */1159#define WM8996_DAC2_VU_WIDTH 1 /* DAC2_VU */1160#define WM8996_HPOUT2L_ZC 0x0080 /* HPOUT2L_ZC */1161#define WM8996_HPOUT2L_ZC_MASK 0x0080 /* HPOUT2L_ZC */1162#define WM8996_HPOUT2L_ZC_SHIFT 7 /* HPOUT2L_ZC */1163#define WM8996_HPOUT2L_ZC_WIDTH 1 /* HPOUT2L_ZC */1164#define WM8996_HPOUT2L_VOL_MASK 0x000F /* HPOUT2L_VOL - [3:0] */1165#define WM8996_HPOUT2L_VOL_SHIFT 0 /* HPOUT2L_VOL - [3:0] */1166#define WM8996_HPOUT2L_VOL_WIDTH 4 /* HPOUT2L_VOL - [3:0] */1167 1168/*1169 * R31 (0x1F) - Output2 Right Volume1170 */1171#define WM8996_DAC2_VU 0x0100 /* DAC2_VU */1172#define WM8996_DAC2_VU_MASK 0x0100 /* DAC2_VU */1173#define WM8996_DAC2_VU_SHIFT 8 /* DAC2_VU */1174#define WM8996_DAC2_VU_WIDTH 1 /* DAC2_VU */1175#define WM8996_HPOUT2R_ZC 0x0080 /* HPOUT2R_ZC */1176#define WM8996_HPOUT2R_ZC_MASK 0x0080 /* HPOUT2R_ZC */1177#define WM8996_HPOUT2R_ZC_SHIFT 7 /* HPOUT2R_ZC */1178#define WM8996_HPOUT2R_ZC_WIDTH 1 /* HPOUT2R_ZC */1179#define WM8996_HPOUT2R_VOL_MASK 0x000F /* HPOUT2R_VOL - [3:0] */1180#define WM8996_HPOUT2R_VOL_SHIFT 0 /* HPOUT2R_VOL - [3:0] */1181#define WM8996_HPOUT2R_VOL_WIDTH 4 /* HPOUT2R_VOL - [3:0] */1182 1183/*1184 * R32 (0x20) - MICBIAS (1)1185 */1186#define WM8996_MICB1_RATE 0x0020 /* MICB1_RATE */1187#define WM8996_MICB1_RATE_MASK 0x0020 /* MICB1_RATE */1188#define WM8996_MICB1_RATE_SHIFT 5 /* MICB1_RATE */1189#define WM8996_MICB1_RATE_WIDTH 1 /* MICB1_RATE */1190#define WM8996_MICB1_MODE 0x0010 /* MICB1_MODE */1191#define WM8996_MICB1_MODE_MASK 0x0010 /* MICB1_MODE */1192#define WM8996_MICB1_MODE_SHIFT 4 /* MICB1_MODE */1193#define WM8996_MICB1_MODE_WIDTH 1 /* MICB1_MODE */1194#define WM8996_MICB1_LVL_MASK 0x000E /* MICB1_LVL - [3:1] */1195#define WM8996_MICB1_LVL_SHIFT 1 /* MICB1_LVL - [3:1] */1196#define WM8996_MICB1_LVL_WIDTH 3 /* MICB1_LVL - [3:1] */1197#define WM8996_MICB1_DISCH 0x0001 /* MICB1_DISCH */1198#define WM8996_MICB1_DISCH_MASK 0x0001 /* MICB1_DISCH */1199#define WM8996_MICB1_DISCH_SHIFT 0 /* MICB1_DISCH */1200#define WM8996_MICB1_DISCH_WIDTH 1 /* MICB1_DISCH */1201 1202/*1203 * R33 (0x21) - MICBIAS (2)1204 */1205#define WM8996_MICB2_RATE 0x0020 /* MICB2_RATE */1206#define WM8996_MICB2_RATE_MASK 0x0020 /* MICB2_RATE */1207#define WM8996_MICB2_RATE_SHIFT 5 /* MICB2_RATE */1208#define WM8996_MICB2_RATE_WIDTH 1 /* MICB2_RATE */1209#define WM8996_MICB2_MODE 0x0010 /* MICB2_MODE */1210#define WM8996_MICB2_MODE_MASK 0x0010 /* MICB2_MODE */1211#define WM8996_MICB2_MODE_SHIFT 4 /* MICB2_MODE */1212#define WM8996_MICB2_MODE_WIDTH 1 /* MICB2_MODE */1213#define WM8996_MICB2_LVL_MASK 0x000E /* MICB2_LVL - [3:1] */1214#define WM8996_MICB2_LVL_SHIFT 1 /* MICB2_LVL - [3:1] */1215#define WM8996_MICB2_LVL_WIDTH 3 /* MICB2_LVL - [3:1] */1216#define WM8996_MICB2_DISCH 0x0001 /* MICB2_DISCH */1217#define WM8996_MICB2_DISCH_MASK 0x0001 /* MICB2_DISCH */1218#define WM8996_MICB2_DISCH_SHIFT 0 /* MICB2_DISCH */1219#define WM8996_MICB2_DISCH_WIDTH 1 /* MICB2_DISCH */1220 1221/*1222 * R40 (0x28) - LDO 11223 */1224#define WM8996_LDO1_MODE 0x0020 /* LDO1_MODE */1225#define WM8996_LDO1_MODE_MASK 0x0020 /* LDO1_MODE */1226#define WM8996_LDO1_MODE_SHIFT 5 /* LDO1_MODE */1227#define WM8996_LDO1_MODE_WIDTH 1 /* LDO1_MODE */1228#define WM8996_LDO1_VSEL_MASK 0x0006 /* LDO1_VSEL - [2:1] */1229#define WM8996_LDO1_VSEL_SHIFT 1 /* LDO1_VSEL - [2:1] */1230#define WM8996_LDO1_VSEL_WIDTH 2 /* LDO1_VSEL - [2:1] */1231#define WM8996_LDO1_DISCH 0x0001 /* LDO1_DISCH */1232#define WM8996_LDO1_DISCH_MASK 0x0001 /* LDO1_DISCH */1233#define WM8996_LDO1_DISCH_SHIFT 0 /* LDO1_DISCH */1234#define WM8996_LDO1_DISCH_WIDTH 1 /* LDO1_DISCH */1235 1236/*1237 * R41 (0x29) - LDO 21238 */1239#define WM8996_LDO2_MODE 0x0020 /* LDO2_MODE */1240#define WM8996_LDO2_MODE_MASK 0x0020 /* LDO2_MODE */1241#define WM8996_LDO2_MODE_SHIFT 5 /* LDO2_MODE */1242#define WM8996_LDO2_MODE_WIDTH 1 /* LDO2_MODE */1243#define WM8996_LDO2_VSEL_MASK 0x001E /* LDO2_VSEL - [4:1] */1244#define WM8996_LDO2_VSEL_SHIFT 1 /* LDO2_VSEL - [4:1] */1245#define WM8996_LDO2_VSEL_WIDTH 4 /* LDO2_VSEL - [4:1] */1246#define WM8996_LDO2_DISCH 0x0001 /* LDO2_DISCH */1247#define WM8996_LDO2_DISCH_MASK 0x0001 /* LDO2_DISCH */1248#define WM8996_LDO2_DISCH_SHIFT 0 /* LDO2_DISCH */1249#define WM8996_LDO2_DISCH_WIDTH 1 /* LDO2_DISCH */1250 1251/*1252 * R48 (0x30) - Accessory Detect Mode 11253 */1254#define WM8996_JD_MODE_MASK 0x0003 /* JD_MODE - [1:0] */1255#define WM8996_JD_MODE_SHIFT 0 /* JD_MODE - [1:0] */1256#define WM8996_JD_MODE_WIDTH 2 /* JD_MODE - [1:0] */1257 1258/*1259 * R49 (0x31) - Accessory Detect Mode 21260 */1261#define WM8996_HPOUT1FB_SRC 0x0004 /* HPOUT1FB_SRC */1262#define WM8996_HPOUT1FB_SRC_MASK 0x0004 /* HPOUT1FB_SRC */1263#define WM8996_HPOUT1FB_SRC_SHIFT 2 /* HPOUT1FB_SRC */1264#define WM8996_HPOUT1FB_SRC_WIDTH 1 /* HPOUT1FB_SRC */1265#define WM8996_MICD_SRC 0x0002 /* MICD_SRC */1266#define WM8996_MICD_SRC_MASK 0x0002 /* MICD_SRC */1267#define WM8996_MICD_SRC_SHIFT 1 /* MICD_SRC */1268#define WM8996_MICD_SRC_WIDTH 1 /* MICD_SRC */1269#define WM8996_MICD_BIAS_SRC 0x0001 /* MICD_BIAS_SRC */1270#define WM8996_MICD_BIAS_SRC_MASK 0x0001 /* MICD_BIAS_SRC */1271#define WM8996_MICD_BIAS_SRC_SHIFT 0 /* MICD_BIAS_SRC */1272#define WM8996_MICD_BIAS_SRC_WIDTH 1 /* MICD_BIAS_SRC */1273 1274/*1275 * R52 (0x34) - Headphone Detect 11276 */1277#define WM8996_HP_HOLDTIME_MASK 0x00E0 /* HP_HOLDTIME - [7:5] */1278#define WM8996_HP_HOLDTIME_SHIFT 5 /* HP_HOLDTIME - [7:5] */1279#define WM8996_HP_HOLDTIME_WIDTH 3 /* HP_HOLDTIME - [7:5] */1280#define WM8996_HP_CLK_DIV_MASK 0x0018 /* HP_CLK_DIV - [4:3] */1281#define WM8996_HP_CLK_DIV_SHIFT 3 /* HP_CLK_DIV - [4:3] */1282#define WM8996_HP_CLK_DIV_WIDTH 2 /* HP_CLK_DIV - [4:3] */1283#define WM8996_HP_STEP_SIZE 0x0002 /* HP_STEP_SIZE */1284#define WM8996_HP_STEP_SIZE_MASK 0x0002 /* HP_STEP_SIZE */1285#define WM8996_HP_STEP_SIZE_SHIFT 1 /* HP_STEP_SIZE */1286#define WM8996_HP_STEP_SIZE_WIDTH 1 /* HP_STEP_SIZE */1287#define WM8996_HP_POLL 0x0001 /* HP_POLL */1288#define WM8996_HP_POLL_MASK 0x0001 /* HP_POLL */1289#define WM8996_HP_POLL_SHIFT 0 /* HP_POLL */1290#define WM8996_HP_POLL_WIDTH 1 /* HP_POLL */1291 1292/*1293 * R53 (0x35) - Headphone Detect 21294 */1295#define WM8996_HP_DONE 0x0080 /* HP_DONE */1296#define WM8996_HP_DONE_MASK 0x0080 /* HP_DONE */1297#define WM8996_HP_DONE_SHIFT 7 /* HP_DONE */1298#define WM8996_HP_DONE_WIDTH 1 /* HP_DONE */1299#define WM8996_HP_LVL_MASK 0x007F /* HP_LVL - [6:0] */1300#define WM8996_HP_LVL_SHIFT 0 /* HP_LVL - [6:0] */1301#define WM8996_HP_LVL_WIDTH 7 /* HP_LVL - [6:0] */1302 1303/*1304 * R56 (0x38) - Mic Detect 11305 */1306#define WM8996_MICD_BIAS_STARTTIME_MASK 0xF000 /* MICD_BIAS_STARTTIME - [15:12] */1307#define WM8996_MICD_BIAS_STARTTIME_SHIFT 12 /* MICD_BIAS_STARTTIME - [15:12] */1308#define WM8996_MICD_BIAS_STARTTIME_WIDTH 4 /* MICD_BIAS_STARTTIME - [15:12] */1309#define WM8996_MICD_RATE_MASK 0x0F00 /* MICD_RATE - [11:8] */1310#define WM8996_MICD_RATE_SHIFT 8 /* MICD_RATE - [11:8] */1311#define WM8996_MICD_RATE_WIDTH 4 /* MICD_RATE - [11:8] */1312#define WM8996_MICD_DBTIME 0x0002 /* MICD_DBTIME */1313#define WM8996_MICD_DBTIME_MASK 0x0002 /* MICD_DBTIME */1314#define WM8996_MICD_DBTIME_SHIFT 1 /* MICD_DBTIME */1315#define WM8996_MICD_DBTIME_WIDTH 1 /* MICD_DBTIME */1316#define WM8996_MICD_ENA 0x0001 /* MICD_ENA */1317#define WM8996_MICD_ENA_MASK 0x0001 /* MICD_ENA */1318#define WM8996_MICD_ENA_SHIFT 0 /* MICD_ENA */1319#define WM8996_MICD_ENA_WIDTH 1 /* MICD_ENA */1320 1321/*1322 * R57 (0x39) - Mic Detect 21323 */1324#define WM8996_MICD_LVL_SEL_MASK 0x00FF /* MICD_LVL_SEL - [7:0] */1325#define WM8996_MICD_LVL_SEL_SHIFT 0 /* MICD_LVL_SEL - [7:0] */1326#define WM8996_MICD_LVL_SEL_WIDTH 8 /* MICD_LVL_SEL - [7:0] */1327 1328/*1329 * R58 (0x3A) - Mic Detect 31330 */1331#define WM8996_MICD_LVL_MASK 0x07FC /* MICD_LVL - [10:2] */1332#define WM8996_MICD_LVL_SHIFT 2 /* MICD_LVL - [10:2] */1333#define WM8996_MICD_LVL_WIDTH 9 /* MICD_LVL - [10:2] */1334#define WM8996_MICD_VALID 0x0002 /* MICD_VALID */1335#define WM8996_MICD_VALID_MASK 0x0002 /* MICD_VALID */1336#define WM8996_MICD_VALID_SHIFT 1 /* MICD_VALID */1337#define WM8996_MICD_VALID_WIDTH 1 /* MICD_VALID */1338#define WM8996_MICD_STS 0x0001 /* MICD_STS */1339#define WM8996_MICD_STS_MASK 0x0001 /* MICD_STS */1340#define WM8996_MICD_STS_SHIFT 0 /* MICD_STS */1341#define WM8996_MICD_STS_WIDTH 1 /* MICD_STS */1342 1343/*1344 * R64 (0x40) - Charge Pump (1)1345 */1346#define WM8996_CP_ENA 0x8000 /* CP_ENA */1347#define WM8996_CP_ENA_MASK 0x8000 /* CP_ENA */1348#define WM8996_CP_ENA_SHIFT 15 /* CP_ENA */1349#define WM8996_CP_ENA_WIDTH 1 /* CP_ENA */1350 1351/*1352 * R65 (0x41) - Charge Pump (2)1353 */1354#define WM8996_CP_DISCH 0x8000 /* CP_DISCH */1355#define WM8996_CP_DISCH_MASK 0x8000 /* CP_DISCH */1356#define WM8996_CP_DISCH_SHIFT 15 /* CP_DISCH */1357#define WM8996_CP_DISCH_WIDTH 1 /* CP_DISCH */1358 1359/*1360 * R80 (0x50) - DC Servo (1)1361 */1362#define WM8996_DCS_ENA_CHAN_3 0x0008 /* DCS_ENA_CHAN_3 */1363#define WM8996_DCS_ENA_CHAN_3_MASK 0x0008 /* DCS_ENA_CHAN_3 */1364#define WM8996_DCS_ENA_CHAN_3_SHIFT 3 /* DCS_ENA_CHAN_3 */1365#define WM8996_DCS_ENA_CHAN_3_WIDTH 1 /* DCS_ENA_CHAN_3 */1366#define WM8996_DCS_ENA_CHAN_2 0x0004 /* DCS_ENA_CHAN_2 */1367#define WM8996_DCS_ENA_CHAN_2_MASK 0x0004 /* DCS_ENA_CHAN_2 */1368#define WM8996_DCS_ENA_CHAN_2_SHIFT 2 /* DCS_ENA_CHAN_2 */1369#define WM8996_DCS_ENA_CHAN_2_WIDTH 1 /* DCS_ENA_CHAN_2 */1370#define WM8996_DCS_ENA_CHAN_1 0x0002 /* DCS_ENA_CHAN_1 */1371#define WM8996_DCS_ENA_CHAN_1_MASK 0x0002 /* DCS_ENA_CHAN_1 */1372#define WM8996_DCS_ENA_CHAN_1_SHIFT 1 /* DCS_ENA_CHAN_1 */1373#define WM8996_DCS_ENA_CHAN_1_WIDTH 1 /* DCS_ENA_CHAN_1 */1374#define WM8996_DCS_ENA_CHAN_0 0x0001 /* DCS_ENA_CHAN_0 */1375#define WM8996_DCS_ENA_CHAN_0_MASK 0x0001 /* DCS_ENA_CHAN_0 */1376#define WM8996_DCS_ENA_CHAN_0_SHIFT 0 /* DCS_ENA_CHAN_0 */1377#define WM8996_DCS_ENA_CHAN_0_WIDTH 1 /* DCS_ENA_CHAN_0 */1378 1379/*1380 * R81 (0x51) - DC Servo (2)1381 */1382#define WM8996_DCS_TRIG_SINGLE_3 0x8000 /* DCS_TRIG_SINGLE_3 */1383#define WM8996_DCS_TRIG_SINGLE_3_MASK 0x8000 /* DCS_TRIG_SINGLE_3 */1384#define WM8996_DCS_TRIG_SINGLE_3_SHIFT 15 /* DCS_TRIG_SINGLE_3 */1385#define WM8996_DCS_TRIG_SINGLE_3_WIDTH 1 /* DCS_TRIG_SINGLE_3 */1386#define WM8996_DCS_TRIG_SINGLE_2 0x4000 /* DCS_TRIG_SINGLE_2 */1387#define WM8996_DCS_TRIG_SINGLE_2_MASK 0x4000 /* DCS_TRIG_SINGLE_2 */1388#define WM8996_DCS_TRIG_SINGLE_2_SHIFT 14 /* DCS_TRIG_SINGLE_2 */1389#define WM8996_DCS_TRIG_SINGLE_2_WIDTH 1 /* DCS_TRIG_SINGLE_2 */1390#define WM8996_DCS_TRIG_SINGLE_1 0x2000 /* DCS_TRIG_SINGLE_1 */1391#define WM8996_DCS_TRIG_SINGLE_1_MASK 0x2000 /* DCS_TRIG_SINGLE_1 */1392#define WM8996_DCS_TRIG_SINGLE_1_SHIFT 13 /* DCS_TRIG_SINGLE_1 */1393#define WM8996_DCS_TRIG_SINGLE_1_WIDTH 1 /* DCS_TRIG_SINGLE_1 */1394#define WM8996_DCS_TRIG_SINGLE_0 0x1000 /* DCS_TRIG_SINGLE_0 */1395#define WM8996_DCS_TRIG_SINGLE_0_MASK 0x1000 /* DCS_TRIG_SINGLE_0 */1396#define WM8996_DCS_TRIG_SINGLE_0_SHIFT 12 /* DCS_TRIG_SINGLE_0 */1397#define WM8996_DCS_TRIG_SINGLE_0_WIDTH 1 /* DCS_TRIG_SINGLE_0 */1398#define WM8996_DCS_TRIG_SERIES_3 0x0800 /* DCS_TRIG_SERIES_3 */1399#define WM8996_DCS_TRIG_SERIES_3_MASK 0x0800 /* DCS_TRIG_SERIES_3 */1400#define WM8996_DCS_TRIG_SERIES_3_SHIFT 11 /* DCS_TRIG_SERIES_3 */1401#define WM8996_DCS_TRIG_SERIES_3_WIDTH 1 /* DCS_TRIG_SERIES_3 */1402#define WM8996_DCS_TRIG_SERIES_2 0x0400 /* DCS_TRIG_SERIES_2 */1403#define WM8996_DCS_TRIG_SERIES_2_MASK 0x0400 /* DCS_TRIG_SERIES_2 */1404#define WM8996_DCS_TRIG_SERIES_2_SHIFT 10 /* DCS_TRIG_SERIES_2 */1405#define WM8996_DCS_TRIG_SERIES_2_WIDTH 1 /* DCS_TRIG_SERIES_2 */1406#define WM8996_DCS_TRIG_SERIES_1 0x0200 /* DCS_TRIG_SERIES_1 */1407#define WM8996_DCS_TRIG_SERIES_1_MASK 0x0200 /* DCS_TRIG_SERIES_1 */1408#define WM8996_DCS_TRIG_SERIES_1_SHIFT 9 /* DCS_TRIG_SERIES_1 */1409#define WM8996_DCS_TRIG_SERIES_1_WIDTH 1 /* DCS_TRIG_SERIES_1 */1410#define WM8996_DCS_TRIG_SERIES_0 0x0100 /* DCS_TRIG_SERIES_0 */1411#define WM8996_DCS_TRIG_SERIES_0_MASK 0x0100 /* DCS_TRIG_SERIES_0 */1412#define WM8996_DCS_TRIG_SERIES_0_SHIFT 8 /* DCS_TRIG_SERIES_0 */1413#define WM8996_DCS_TRIG_SERIES_0_WIDTH 1 /* DCS_TRIG_SERIES_0 */1414#define WM8996_DCS_TRIG_STARTUP_3 0x0080 /* DCS_TRIG_STARTUP_3 */1415#define WM8996_DCS_TRIG_STARTUP_3_MASK 0x0080 /* DCS_TRIG_STARTUP_3 */1416#define WM8996_DCS_TRIG_STARTUP_3_SHIFT 7 /* DCS_TRIG_STARTUP_3 */1417#define WM8996_DCS_TRIG_STARTUP_3_WIDTH 1 /* DCS_TRIG_STARTUP_3 */1418#define WM8996_DCS_TRIG_STARTUP_2 0x0040 /* DCS_TRIG_STARTUP_2 */1419#define WM8996_DCS_TRIG_STARTUP_2_MASK 0x0040 /* DCS_TRIG_STARTUP_2 */1420#define WM8996_DCS_TRIG_STARTUP_2_SHIFT 6 /* DCS_TRIG_STARTUP_2 */1421#define WM8996_DCS_TRIG_STARTUP_2_WIDTH 1 /* DCS_TRIG_STARTUP_2 */1422#define WM8996_DCS_TRIG_STARTUP_1 0x0020 /* DCS_TRIG_STARTUP_1 */1423#define WM8996_DCS_TRIG_STARTUP_1_MASK 0x0020 /* DCS_TRIG_STARTUP_1 */1424#define WM8996_DCS_TRIG_STARTUP_1_SHIFT 5 /* DCS_TRIG_STARTUP_1 */1425#define WM8996_DCS_TRIG_STARTUP_1_WIDTH 1 /* DCS_TRIG_STARTUP_1 */1426#define WM8996_DCS_TRIG_STARTUP_0 0x0010 /* DCS_TRIG_STARTUP_0 */1427#define WM8996_DCS_TRIG_STARTUP_0_MASK 0x0010 /* DCS_TRIG_STARTUP_0 */1428#define WM8996_DCS_TRIG_STARTUP_0_SHIFT 4 /* DCS_TRIG_STARTUP_0 */1429#define WM8996_DCS_TRIG_STARTUP_0_WIDTH 1 /* DCS_TRIG_STARTUP_0 */1430#define WM8996_DCS_TRIG_DAC_WR_3 0x0008 /* DCS_TRIG_DAC_WR_3 */1431#define WM8996_DCS_TRIG_DAC_WR_3_MASK 0x0008 /* DCS_TRIG_DAC_WR_3 */1432#define WM8996_DCS_TRIG_DAC_WR_3_SHIFT 3 /* DCS_TRIG_DAC_WR_3 */1433#define WM8996_DCS_TRIG_DAC_WR_3_WIDTH 1 /* DCS_TRIG_DAC_WR_3 */1434#define WM8996_DCS_TRIG_DAC_WR_2 0x0004 /* DCS_TRIG_DAC_WR_2 */1435#define WM8996_DCS_TRIG_DAC_WR_2_MASK 0x0004 /* DCS_TRIG_DAC_WR_2 */1436#define WM8996_DCS_TRIG_DAC_WR_2_SHIFT 2 /* DCS_TRIG_DAC_WR_2 */1437#define WM8996_DCS_TRIG_DAC_WR_2_WIDTH 1 /* DCS_TRIG_DAC_WR_2 */1438#define WM8996_DCS_TRIG_DAC_WR_1 0x0002 /* DCS_TRIG_DAC_WR_1 */1439#define WM8996_DCS_TRIG_DAC_WR_1_MASK 0x0002 /* DCS_TRIG_DAC_WR_1 */1440#define WM8996_DCS_TRIG_DAC_WR_1_SHIFT 1 /* DCS_TRIG_DAC_WR_1 */1441#define WM8996_DCS_TRIG_DAC_WR_1_WIDTH 1 /* DCS_TRIG_DAC_WR_1 */1442#define WM8996_DCS_TRIG_DAC_WR_0 0x0001 /* DCS_TRIG_DAC_WR_0 */1443#define WM8996_DCS_TRIG_DAC_WR_0_MASK 0x0001 /* DCS_TRIG_DAC_WR_0 */1444#define WM8996_DCS_TRIG_DAC_WR_0_SHIFT 0 /* DCS_TRIG_DAC_WR_0 */1445#define WM8996_DCS_TRIG_DAC_WR_0_WIDTH 1 /* DCS_TRIG_DAC_WR_0 */1446 1447/*1448 * R82 (0x52) - DC Servo (3)1449 */1450#define WM8996_DCS_TIMER_PERIOD_23_MASK 0x0F00 /* DCS_TIMER_PERIOD_23 - [11:8] */1451#define WM8996_DCS_TIMER_PERIOD_23_SHIFT 8 /* DCS_TIMER_PERIOD_23 - [11:8] */1452#define WM8996_DCS_TIMER_PERIOD_23_WIDTH 4 /* DCS_TIMER_PERIOD_23 - [11:8] */1453#define WM8996_DCS_TIMER_PERIOD_01_MASK 0x000F /* DCS_TIMER_PERIOD_01 - [3:0] */1454#define WM8996_DCS_TIMER_PERIOD_01_SHIFT 0 /* DCS_TIMER_PERIOD_01 - [3:0] */1455#define WM8996_DCS_TIMER_PERIOD_01_WIDTH 4 /* DCS_TIMER_PERIOD_01 - [3:0] */1456 1457/*1458 * R84 (0x54) - DC Servo (5)1459 */1460#define WM8996_DCS_SERIES_NO_23_MASK 0x7F00 /* DCS_SERIES_NO_23 - [14:8] */1461#define WM8996_DCS_SERIES_NO_23_SHIFT 8 /* DCS_SERIES_NO_23 - [14:8] */1462#define WM8996_DCS_SERIES_NO_23_WIDTH 7 /* DCS_SERIES_NO_23 - [14:8] */1463#define WM8996_DCS_SERIES_NO_01_MASK 0x007F /* DCS_SERIES_NO_01 - [6:0] */1464#define WM8996_DCS_SERIES_NO_01_SHIFT 0 /* DCS_SERIES_NO_01 - [6:0] */1465#define WM8996_DCS_SERIES_NO_01_WIDTH 7 /* DCS_SERIES_NO_01 - [6:0] */1466 1467/*1468 * R85 (0x55) - DC Servo (6)1469 */1470#define WM8996_DCS_DAC_WR_VAL_3_MASK 0xFF00 /* DCS_DAC_WR_VAL_3 - [15:8] */1471#define WM8996_DCS_DAC_WR_VAL_3_SHIFT 8 /* DCS_DAC_WR_VAL_3 - [15:8] */1472#define WM8996_DCS_DAC_WR_VAL_3_WIDTH 8 /* DCS_DAC_WR_VAL_3 - [15:8] */1473#define WM8996_DCS_DAC_WR_VAL_2_MASK 0x00FF /* DCS_DAC_WR_VAL_2 - [7:0] */1474#define WM8996_DCS_DAC_WR_VAL_2_SHIFT 0 /* DCS_DAC_WR_VAL_2 - [7:0] */1475#define WM8996_DCS_DAC_WR_VAL_2_WIDTH 8 /* DCS_DAC_WR_VAL_2 - [7:0] */1476 1477/*1478 * R86 (0x56) - DC Servo (7)1479 */1480#define WM8996_DCS_DAC_WR_VAL_1_MASK 0xFF00 /* DCS_DAC_WR_VAL_1 - [15:8] */1481#define WM8996_DCS_DAC_WR_VAL_1_SHIFT 8 /* DCS_DAC_WR_VAL_1 - [15:8] */1482#define WM8996_DCS_DAC_WR_VAL_1_WIDTH 8 /* DCS_DAC_WR_VAL_1 - [15:8] */1483#define WM8996_DCS_DAC_WR_VAL_0_MASK 0x00FF /* DCS_DAC_WR_VAL_0 - [7:0] */1484#define WM8996_DCS_DAC_WR_VAL_0_SHIFT 0 /* DCS_DAC_WR_VAL_0 - [7:0] */1485#define WM8996_DCS_DAC_WR_VAL_0_WIDTH 8 /* DCS_DAC_WR_VAL_0 - [7:0] */1486 1487/*1488 * R87 (0x57) - DC Servo Readback 01489 */1490#define WM8996_DCS_CAL_COMPLETE_MASK 0x0F00 /* DCS_CAL_COMPLETE - [11:8] */1491#define WM8996_DCS_CAL_COMPLETE_SHIFT 8 /* DCS_CAL_COMPLETE - [11:8] */1492#define WM8996_DCS_CAL_COMPLETE_WIDTH 4 /* DCS_CAL_COMPLETE - [11:8] */1493#define WM8996_DCS_DAC_WR_COMPLETE_MASK 0x00F0 /* DCS_DAC_WR_COMPLETE - [7:4] */1494#define WM8996_DCS_DAC_WR_COMPLETE_SHIFT 4 /* DCS_DAC_WR_COMPLETE - [7:4] */1495#define WM8996_DCS_DAC_WR_COMPLETE_WIDTH 4 /* DCS_DAC_WR_COMPLETE - [7:4] */1496#define WM8996_DCS_STARTUP_COMPLETE_MASK 0x000F /* DCS_STARTUP_COMPLETE - [3:0] */1497#define WM8996_DCS_STARTUP_COMPLETE_SHIFT 0 /* DCS_STARTUP_COMPLETE - [3:0] */1498#define WM8996_DCS_STARTUP_COMPLETE_WIDTH 4 /* DCS_STARTUP_COMPLETE - [3:0] */1499 1500/*1501 * R96 (0x60) - Analogue HP (1)1502 */1503#define WM8996_HPOUT1L_RMV_SHORT 0x0080 /* HPOUT1L_RMV_SHORT */1504#define WM8996_HPOUT1L_RMV_SHORT_MASK 0x0080 /* HPOUT1L_RMV_SHORT */1505#define WM8996_HPOUT1L_RMV_SHORT_SHIFT 7 /* HPOUT1L_RMV_SHORT */1506#define WM8996_HPOUT1L_RMV_SHORT_WIDTH 1 /* HPOUT1L_RMV_SHORT */1507#define WM8996_HPOUT1L_OUTP 0x0040 /* HPOUT1L_OUTP */1508#define WM8996_HPOUT1L_OUTP_MASK 0x0040 /* HPOUT1L_OUTP */1509#define WM8996_HPOUT1L_OUTP_SHIFT 6 /* HPOUT1L_OUTP */1510#define WM8996_HPOUT1L_OUTP_WIDTH 1 /* HPOUT1L_OUTP */1511#define WM8996_HPOUT1L_DLY 0x0020 /* HPOUT1L_DLY */1512#define WM8996_HPOUT1L_DLY_MASK 0x0020 /* HPOUT1L_DLY */1513#define WM8996_HPOUT1L_DLY_SHIFT 5 /* HPOUT1L_DLY */1514#define WM8996_HPOUT1L_DLY_WIDTH 1 /* HPOUT1L_DLY */1515#define WM8996_HPOUT1R_RMV_SHORT 0x0008 /* HPOUT1R_RMV_SHORT */1516#define WM8996_HPOUT1R_RMV_SHORT_MASK 0x0008 /* HPOUT1R_RMV_SHORT */1517#define WM8996_HPOUT1R_RMV_SHORT_SHIFT 3 /* HPOUT1R_RMV_SHORT */1518#define WM8996_HPOUT1R_RMV_SHORT_WIDTH 1 /* HPOUT1R_RMV_SHORT */1519#define WM8996_HPOUT1R_OUTP 0x0004 /* HPOUT1R_OUTP */1520#define WM8996_HPOUT1R_OUTP_MASK 0x0004 /* HPOUT1R_OUTP */1521#define WM8996_HPOUT1R_OUTP_SHIFT 2 /* HPOUT1R_OUTP */1522#define WM8996_HPOUT1R_OUTP_WIDTH 1 /* HPOUT1R_OUTP */1523#define WM8996_HPOUT1R_DLY 0x0002 /* HPOUT1R_DLY */1524#define WM8996_HPOUT1R_DLY_MASK 0x0002 /* HPOUT1R_DLY */1525#define WM8996_HPOUT1R_DLY_SHIFT 1 /* HPOUT1R_DLY */1526#define WM8996_HPOUT1R_DLY_WIDTH 1 /* HPOUT1R_DLY */1527 1528/*1529 * R97 (0x61) - Analogue HP (2)1530 */1531#define WM8996_HPOUT2L_RMV_SHORT 0x0080 /* HPOUT2L_RMV_SHORT */1532#define WM8996_HPOUT2L_RMV_SHORT_MASK 0x0080 /* HPOUT2L_RMV_SHORT */1533#define WM8996_HPOUT2L_RMV_SHORT_SHIFT 7 /* HPOUT2L_RMV_SHORT */1534#define WM8996_HPOUT2L_RMV_SHORT_WIDTH 1 /* HPOUT2L_RMV_SHORT */1535#define WM8996_HPOUT2L_OUTP 0x0040 /* HPOUT2L_OUTP */1536#define WM8996_HPOUT2L_OUTP_MASK 0x0040 /* HPOUT2L_OUTP */1537#define WM8996_HPOUT2L_OUTP_SHIFT 6 /* HPOUT2L_OUTP */1538#define WM8996_HPOUT2L_OUTP_WIDTH 1 /* HPOUT2L_OUTP */1539#define WM8996_HPOUT2L_DLY 0x0020 /* HPOUT2L_DLY */1540#define WM8996_HPOUT2L_DLY_MASK 0x0020 /* HPOUT2L_DLY */1541#define WM8996_HPOUT2L_DLY_SHIFT 5 /* HPOUT2L_DLY */1542#define WM8996_HPOUT2L_DLY_WIDTH 1 /* HPOUT2L_DLY */1543#define WM8996_HPOUT2R_RMV_SHORT 0x0008 /* HPOUT2R_RMV_SHORT */1544#define WM8996_HPOUT2R_RMV_SHORT_MASK 0x0008 /* HPOUT2R_RMV_SHORT */1545#define WM8996_HPOUT2R_RMV_SHORT_SHIFT 3 /* HPOUT2R_RMV_SHORT */1546#define WM8996_HPOUT2R_RMV_SHORT_WIDTH 1 /* HPOUT2R_RMV_SHORT */1547#define WM8996_HPOUT2R_OUTP 0x0004 /* HPOUT2R_OUTP */1548#define WM8996_HPOUT2R_OUTP_MASK 0x0004 /* HPOUT2R_OUTP */1549#define WM8996_HPOUT2R_OUTP_SHIFT 2 /* HPOUT2R_OUTP */1550#define WM8996_HPOUT2R_OUTP_WIDTH 1 /* HPOUT2R_OUTP */1551#define WM8996_HPOUT2R_DLY 0x0002 /* HPOUT2R_DLY */1552#define WM8996_HPOUT2R_DLY_MASK 0x0002 /* HPOUT2R_DLY */1553#define WM8996_HPOUT2R_DLY_SHIFT 1 /* HPOUT2R_DLY */1554#define WM8996_HPOUT2R_DLY_WIDTH 1 /* HPOUT2R_DLY */1555 1556/*1557 * R256 (0x100) - Chip Revision1558 */1559#define WM8996_CHIP_REV_MASK 0x000F /* CHIP_REV - [3:0] */1560#define WM8996_CHIP_REV_SHIFT 0 /* CHIP_REV - [3:0] */1561#define WM8996_CHIP_REV_WIDTH 4 /* CHIP_REV - [3:0] */1562 1563/*1564 * R257 (0x101) - Control Interface (1)1565 */1566#define WM8996_REG_SYNC 0x8000 /* REG_SYNC */1567#define WM8996_REG_SYNC_MASK 0x8000 /* REG_SYNC */1568#define WM8996_REG_SYNC_SHIFT 15 /* REG_SYNC */1569#define WM8996_REG_SYNC_WIDTH 1 /* REG_SYNC */1570#define WM8996_AUTO_INC 0x0004 /* AUTO_INC */1571#define WM8996_AUTO_INC_MASK 0x0004 /* AUTO_INC */1572#define WM8996_AUTO_INC_SHIFT 2 /* AUTO_INC */1573#define WM8996_AUTO_INC_WIDTH 1 /* AUTO_INC */1574 1575/*1576 * R272 (0x110) - Write Sequencer Ctrl (1)1577 */1578#define WM8996_WSEQ_ENA 0x8000 /* WSEQ_ENA */1579#define WM8996_WSEQ_ENA_MASK 0x8000 /* WSEQ_ENA */1580#define WM8996_WSEQ_ENA_SHIFT 15 /* WSEQ_ENA */1581#define WM8996_WSEQ_ENA_WIDTH 1 /* WSEQ_ENA */1582#define WM8996_WSEQ_ABORT 0x0200 /* WSEQ_ABORT */1583#define WM8996_WSEQ_ABORT_MASK 0x0200 /* WSEQ_ABORT */1584#define WM8996_WSEQ_ABORT_SHIFT 9 /* WSEQ_ABORT */1585#define WM8996_WSEQ_ABORT_WIDTH 1 /* WSEQ_ABORT */1586#define WM8996_WSEQ_START 0x0100 /* WSEQ_START */1587#define WM8996_WSEQ_START_MASK 0x0100 /* WSEQ_START */1588#define WM8996_WSEQ_START_SHIFT 8 /* WSEQ_START */1589#define WM8996_WSEQ_START_WIDTH 1 /* WSEQ_START */1590#define WM8996_WSEQ_START_INDEX_MASK 0x007F /* WSEQ_START_INDEX - [6:0] */1591#define WM8996_WSEQ_START_INDEX_SHIFT 0 /* WSEQ_START_INDEX - [6:0] */1592#define WM8996_WSEQ_START_INDEX_WIDTH 7 /* WSEQ_START_INDEX - [6:0] */1593 1594/*1595 * R273 (0x111) - Write Sequencer Ctrl (2)1596 */1597#define WM8996_WSEQ_BUSY 0x0100 /* WSEQ_BUSY */1598#define WM8996_WSEQ_BUSY_MASK 0x0100 /* WSEQ_BUSY */1599#define WM8996_WSEQ_BUSY_SHIFT 8 /* WSEQ_BUSY */1600#define WM8996_WSEQ_BUSY_WIDTH 1 /* WSEQ_BUSY */1601#define WM8996_WSEQ_CURRENT_INDEX_MASK 0x007F /* WSEQ_CURRENT_INDEX - [6:0] */1602#define WM8996_WSEQ_CURRENT_INDEX_SHIFT 0 /* WSEQ_CURRENT_INDEX - [6:0] */1603#define WM8996_WSEQ_CURRENT_INDEX_WIDTH 7 /* WSEQ_CURRENT_INDEX - [6:0] */1604 1605/*1606 * R512 (0x200) - AIF Clocking (1)1607 */1608#define WM8996_SYSCLK_SRC_MASK 0x0018 /* SYSCLK_SRC - [4:3] */1609#define WM8996_SYSCLK_SRC_SHIFT 3 /* SYSCLK_SRC - [4:3] */1610#define WM8996_SYSCLK_SRC_WIDTH 2 /* SYSCLK_SRC - [4:3] */1611#define WM8996_SYSCLK_INV 0x0004 /* SYSCLK_INV */1612#define WM8996_SYSCLK_INV_MASK 0x0004 /* SYSCLK_INV */1613#define WM8996_SYSCLK_INV_SHIFT 2 /* SYSCLK_INV */1614#define WM8996_SYSCLK_INV_WIDTH 1 /* SYSCLK_INV */1615#define WM8996_SYSCLK_DIV 0x0002 /* SYSCLK_DIV */1616#define WM8996_SYSCLK_DIV_MASK 0x0002 /* SYSCLK_DIV */1617#define WM8996_SYSCLK_DIV_SHIFT 1 /* SYSCLK_DIV */1618#define WM8996_SYSCLK_DIV_WIDTH 1 /* SYSCLK_DIV */1619#define WM8996_SYSCLK_ENA 0x0001 /* SYSCLK_ENA */1620#define WM8996_SYSCLK_ENA_MASK 0x0001 /* SYSCLK_ENA */1621#define WM8996_SYSCLK_ENA_SHIFT 0 /* SYSCLK_ENA */1622#define WM8996_SYSCLK_ENA_WIDTH 1 /* SYSCLK_ENA */1623 1624/*1625 * R513 (0x201) - AIF Clocking (2)1626 */1627#define WM8996_DSP2_DIV_MASK 0x0018 /* DSP2_DIV - [4:3] */1628#define WM8996_DSP2_DIV_SHIFT 3 /* DSP2_DIV - [4:3] */1629#define WM8996_DSP2_DIV_WIDTH 2 /* DSP2_DIV - [4:3] */1630#define WM8996_DSP1_DIV_MASK 0x0003 /* DSP1_DIV - [1:0] */1631#define WM8996_DSP1_DIV_SHIFT 0 /* DSP1_DIV - [1:0] */1632#define WM8996_DSP1_DIV_WIDTH 2 /* DSP1_DIV - [1:0] */1633 1634/*1635 * R520 (0x208) - Clocking (1)1636 */1637#define WM8996_LFCLK_ENA 0x0020 /* LFCLK_ENA */1638#define WM8996_LFCLK_ENA_MASK 0x0020 /* LFCLK_ENA */1639#define WM8996_LFCLK_ENA_SHIFT 5 /* LFCLK_ENA */1640#define WM8996_LFCLK_ENA_WIDTH 1 /* LFCLK_ENA */1641#define WM8996_TOCLK_ENA 0x0010 /* TOCLK_ENA */1642#define WM8996_TOCLK_ENA_MASK 0x0010 /* TOCLK_ENA */1643#define WM8996_TOCLK_ENA_SHIFT 4 /* TOCLK_ENA */1644#define WM8996_TOCLK_ENA_WIDTH 1 /* TOCLK_ENA */1645#define WM8996_AIFCLK_ENA 0x0004 /* AIFCLK_ENA */1646#define WM8996_AIFCLK_ENA_MASK 0x0004 /* AIFCLK_ENA */1647#define WM8996_AIFCLK_ENA_SHIFT 2 /* AIFCLK_ENA */1648#define WM8996_AIFCLK_ENA_WIDTH 1 /* AIFCLK_ENA */1649#define WM8996_SYSDSPCLK_ENA 0x0002 /* SYSDSPCLK_ENA */1650#define WM8996_SYSDSPCLK_ENA_MASK 0x0002 /* SYSDSPCLK_ENA */1651#define WM8996_SYSDSPCLK_ENA_SHIFT 1 /* SYSDSPCLK_ENA */1652#define WM8996_SYSDSPCLK_ENA_WIDTH 1 /* SYSDSPCLK_ENA */1653 1654/*1655 * R521 (0x209) - Clocking (2)1656 */1657#define WM8996_TOCLK_DIV_MASK 0x0700 /* TOCLK_DIV - [10:8] */1658#define WM8996_TOCLK_DIV_SHIFT 8 /* TOCLK_DIV - [10:8] */1659#define WM8996_TOCLK_DIV_WIDTH 3 /* TOCLK_DIV - [10:8] */1660#define WM8996_DBCLK_DIV_MASK 0x00F0 /* DBCLK_DIV - [7:4] */1661#define WM8996_DBCLK_DIV_SHIFT 4 /* DBCLK_DIV - [7:4] */1662#define WM8996_DBCLK_DIV_WIDTH 4 /* DBCLK_DIV - [7:4] */1663#define WM8996_OPCLK_DIV_MASK 0x0007 /* OPCLK_DIV - [2:0] */1664#define WM8996_OPCLK_DIV_SHIFT 0 /* OPCLK_DIV - [2:0] */1665#define WM8996_OPCLK_DIV_WIDTH 3 /* OPCLK_DIV - [2:0] */1666 1667/*1668 * R528 (0x210) - AIF Rate1669 */1670#define WM8996_SYSCLK_RATE 0x0001 /* SYSCLK_RATE */1671#define WM8996_SYSCLK_RATE_MASK 0x0001 /* SYSCLK_RATE */1672#define WM8996_SYSCLK_RATE_SHIFT 0 /* SYSCLK_RATE */1673#define WM8996_SYSCLK_RATE_WIDTH 1 /* SYSCLK_RATE */1674 1675/*1676 * R544 (0x220) - FLL Control (1)1677 */1678#define WM8996_FLL_OSC_ENA 0x0002 /* FLL_OSC_ENA */1679#define WM8996_FLL_OSC_ENA_MASK 0x0002 /* FLL_OSC_ENA */1680#define WM8996_FLL_OSC_ENA_SHIFT 1 /* FLL_OSC_ENA */1681#define WM8996_FLL_OSC_ENA_WIDTH 1 /* FLL_OSC_ENA */1682#define WM8996_FLL_ENA 0x0001 /* FLL_ENA */1683#define WM8996_FLL_ENA_MASK 0x0001 /* FLL_ENA */1684#define WM8996_FLL_ENA_SHIFT 0 /* FLL_ENA */1685#define WM8996_FLL_ENA_WIDTH 1 /* FLL_ENA */1686 1687/*1688 * R545 (0x221) - FLL Control (2)1689 */1690#define WM8996_FLL_OUTDIV_MASK 0x3F00 /* FLL_OUTDIV - [13:8] */1691#define WM8996_FLL_OUTDIV_SHIFT 8 /* FLL_OUTDIV - [13:8] */1692#define WM8996_FLL_OUTDIV_WIDTH 6 /* FLL_OUTDIV - [13:8] */1693#define WM8996_FLL_FRATIO_MASK 0x0007 /* FLL_FRATIO - [2:0] */1694#define WM8996_FLL_FRATIO_SHIFT 0 /* FLL_FRATIO - [2:0] */1695#define WM8996_FLL_FRATIO_WIDTH 3 /* FLL_FRATIO - [2:0] */1696 1697/*1698 * R546 (0x222) - FLL Control (3)1699 */1700#define WM8996_FLL_THETA_MASK 0xFFFF /* FLL_THETA - [15:0] */1701#define WM8996_FLL_THETA_SHIFT 0 /* FLL_THETA - [15:0] */1702#define WM8996_FLL_THETA_WIDTH 16 /* FLL_THETA - [15:0] */1703 1704/*1705 * R547 (0x223) - FLL Control (4)1706 */1707#define WM8996_FLL_N_MASK 0x7FE0 /* FLL_N - [14:5] */1708#define WM8996_FLL_N_SHIFT 5 /* FLL_N - [14:5] */1709#define WM8996_FLL_N_WIDTH 10 /* FLL_N - [14:5] */1710#define WM8996_FLL_LOOP_GAIN_MASK 0x000F /* FLL_LOOP_GAIN - [3:0] */1711#define WM8996_FLL_LOOP_GAIN_SHIFT 0 /* FLL_LOOP_GAIN - [3:0] */1712#define WM8996_FLL_LOOP_GAIN_WIDTH 4 /* FLL_LOOP_GAIN - [3:0] */1713 1714/*1715 * R548 (0x224) - FLL Control (5)1716 */1717#define WM8996_FLL_FRC_NCO_VAL_MASK 0x1F80 /* FLL_FRC_NCO_VAL - [12:7] */1718#define WM8996_FLL_FRC_NCO_VAL_SHIFT 7 /* FLL_FRC_NCO_VAL - [12:7] */1719#define WM8996_FLL_FRC_NCO_VAL_WIDTH 6 /* FLL_FRC_NCO_VAL - [12:7] */1720#define WM8996_FLL_FRC_NCO 0x0040 /* FLL_FRC_NCO */1721#define WM8996_FLL_FRC_NCO_MASK 0x0040 /* FLL_FRC_NCO */1722#define WM8996_FLL_FRC_NCO_SHIFT 6 /* FLL_FRC_NCO */1723#define WM8996_FLL_FRC_NCO_WIDTH 1 /* FLL_FRC_NCO */1724#define WM8996_FLL_REFCLK_DIV_MASK 0x0018 /* FLL_REFCLK_DIV - [4:3] */1725#define WM8996_FLL_REFCLK_DIV_SHIFT 3 /* FLL_REFCLK_DIV - [4:3] */1726#define WM8996_FLL_REFCLK_DIV_WIDTH 2 /* FLL_REFCLK_DIV - [4:3] */1727#define WM8996_FLL_REF_FREQ 0x0004 /* FLL_REF_FREQ */1728#define WM8996_FLL_REF_FREQ_MASK 0x0004 /* FLL_REF_FREQ */1729#define WM8996_FLL_REF_FREQ_SHIFT 2 /* FLL_REF_FREQ */1730#define WM8996_FLL_REF_FREQ_WIDTH 1 /* FLL_REF_FREQ */1731#define WM8996_FLL_REFCLK_SRC_MASK 0x0003 /* FLL_REFCLK_SRC - [1:0] */1732#define WM8996_FLL_REFCLK_SRC_SHIFT 0 /* FLL_REFCLK_SRC - [1:0] */1733#define WM8996_FLL_REFCLK_SRC_WIDTH 2 /* FLL_REFCLK_SRC - [1:0] */1734 1735/*1736 * R549 (0x225) - FLL Control (6)1737 */1738#define WM8996_FLL_REFCLK_SRC_STS_MASK 0x000C /* FLL_REFCLK_SRC_STS - [3:2] */1739#define WM8996_FLL_REFCLK_SRC_STS_SHIFT 2 /* FLL_REFCLK_SRC_STS - [3:2] */1740#define WM8996_FLL_REFCLK_SRC_STS_WIDTH 2 /* FLL_REFCLK_SRC_STS - [3:2] */1741#define WM8996_FLL_SWITCH_CLK 0x0001 /* FLL_SWITCH_CLK */1742#define WM8996_FLL_SWITCH_CLK_MASK 0x0001 /* FLL_SWITCH_CLK */1743#define WM8996_FLL_SWITCH_CLK_SHIFT 0 /* FLL_SWITCH_CLK */1744#define WM8996_FLL_SWITCH_CLK_WIDTH 1 /* FLL_SWITCH_CLK */1745 1746/*1747 * R550 (0x226) - FLL EFS 11748 */1749#define WM8996_FLL_LAMBDA_MASK 0xFFFF /* FLL_LAMBDA - [15:0] */1750#define WM8996_FLL_LAMBDA_SHIFT 0 /* FLL_LAMBDA - [15:0] */1751#define WM8996_FLL_LAMBDA_WIDTH 16 /* FLL_LAMBDA - [15:0] */1752 1753/*1754 * R551 (0x227) - FLL EFS 21755 */1756#define WM8996_FLL_LFSR_SEL_MASK 0x0006 /* FLL_LFSR_SEL - [2:1] */1757#define WM8996_FLL_LFSR_SEL_SHIFT 1 /* FLL_LFSR_SEL - [2:1] */1758#define WM8996_FLL_LFSR_SEL_WIDTH 2 /* FLL_LFSR_SEL - [2:1] */1759#define WM8996_FLL_EFS_ENA 0x0001 /* FLL_EFS_ENA */1760#define WM8996_FLL_EFS_ENA_MASK 0x0001 /* FLL_EFS_ENA */1761#define WM8996_FLL_EFS_ENA_SHIFT 0 /* FLL_EFS_ENA */1762#define WM8996_FLL_EFS_ENA_WIDTH 1 /* FLL_EFS_ENA */1763 1764/*1765 * R768 (0x300) - AIF1 Control1766 */1767#define WM8996_AIF1_TRI 0x0004 /* AIF1_TRI */1768#define WM8996_AIF1_TRI_MASK 0x0004 /* AIF1_TRI */1769#define WM8996_AIF1_TRI_SHIFT 2 /* AIF1_TRI */1770#define WM8996_AIF1_TRI_WIDTH 1 /* AIF1_TRI */1771#define WM8996_AIF1_FMT_MASK 0x0003 /* AIF1_FMT - [1:0] */1772#define WM8996_AIF1_FMT_SHIFT 0 /* AIF1_FMT - [1:0] */1773#define WM8996_AIF1_FMT_WIDTH 2 /* AIF1_FMT - [1:0] */1774 1775/*1776 * R769 (0x301) - AIF1 BCLK1777 */1778#define WM8996_AIF1_BCLK_INV 0x0400 /* AIF1_BCLK_INV */1779#define WM8996_AIF1_BCLK_INV_MASK 0x0400 /* AIF1_BCLK_INV */1780#define WM8996_AIF1_BCLK_INV_SHIFT 10 /* AIF1_BCLK_INV */1781#define WM8996_AIF1_BCLK_INV_WIDTH 1 /* AIF1_BCLK_INV */1782#define WM8996_AIF1_BCLK_FRC 0x0200 /* AIF1_BCLK_FRC */1783#define WM8996_AIF1_BCLK_FRC_MASK 0x0200 /* AIF1_BCLK_FRC */1784#define WM8996_AIF1_BCLK_FRC_SHIFT 9 /* AIF1_BCLK_FRC */1785#define WM8996_AIF1_BCLK_FRC_WIDTH 1 /* AIF1_BCLK_FRC */1786#define WM8996_AIF1_BCLK_MSTR 0x0100 /* AIF1_BCLK_MSTR */1787#define WM8996_AIF1_BCLK_MSTR_MASK 0x0100 /* AIF1_BCLK_MSTR */1788#define WM8996_AIF1_BCLK_MSTR_SHIFT 8 /* AIF1_BCLK_MSTR */1789#define WM8996_AIF1_BCLK_MSTR_WIDTH 1 /* AIF1_BCLK_MSTR */1790#define WM8996_AIF1_BCLK_DIV_MASK 0x000F /* AIF1_BCLK_DIV - [3:0] */1791#define WM8996_AIF1_BCLK_DIV_SHIFT 0 /* AIF1_BCLK_DIV - [3:0] */1792#define WM8996_AIF1_BCLK_DIV_WIDTH 4 /* AIF1_BCLK_DIV - [3:0] */1793 1794/*1795 * R770 (0x302) - AIF1 TX LRCLK(1)1796 */1797#define WM8996_AIF1TX_RATE_MASK 0x07FF /* AIF1TX_RATE - [10:0] */1798#define WM8996_AIF1TX_RATE_SHIFT 0 /* AIF1TX_RATE - [10:0] */1799#define WM8996_AIF1TX_RATE_WIDTH 11 /* AIF1TX_RATE - [10:0] */1800 1801/*1802 * R771 (0x303) - AIF1 TX LRCLK(2)1803 */1804#define WM8996_AIF1TX_LRCLK_MODE 0x0008 /* AIF1TX_LRCLK_MODE */1805#define WM8996_AIF1TX_LRCLK_MODE_MASK 0x0008 /* AIF1TX_LRCLK_MODE */1806#define WM8996_AIF1TX_LRCLK_MODE_SHIFT 3 /* AIF1TX_LRCLK_MODE */1807#define WM8996_AIF1TX_LRCLK_MODE_WIDTH 1 /* AIF1TX_LRCLK_MODE */1808#define WM8996_AIF1TX_LRCLK_INV 0x0004 /* AIF1TX_LRCLK_INV */1809#define WM8996_AIF1TX_LRCLK_INV_MASK 0x0004 /* AIF1TX_LRCLK_INV */1810#define WM8996_AIF1TX_LRCLK_INV_SHIFT 2 /* AIF1TX_LRCLK_INV */1811#define WM8996_AIF1TX_LRCLK_INV_WIDTH 1 /* AIF1TX_LRCLK_INV */1812#define WM8996_AIF1TX_LRCLK_FRC 0x0002 /* AIF1TX_LRCLK_FRC */1813#define WM8996_AIF1TX_LRCLK_FRC_MASK 0x0002 /* AIF1TX_LRCLK_FRC */1814#define WM8996_AIF1TX_LRCLK_FRC_SHIFT 1 /* AIF1TX_LRCLK_FRC */1815#define WM8996_AIF1TX_LRCLK_FRC_WIDTH 1 /* AIF1TX_LRCLK_FRC */1816#define WM8996_AIF1TX_LRCLK_MSTR 0x0001 /* AIF1TX_LRCLK_MSTR */1817#define WM8996_AIF1TX_LRCLK_MSTR_MASK 0x0001 /* AIF1TX_LRCLK_MSTR */1818#define WM8996_AIF1TX_LRCLK_MSTR_SHIFT 0 /* AIF1TX_LRCLK_MSTR */1819#define WM8996_AIF1TX_LRCLK_MSTR_WIDTH 1 /* AIF1TX_LRCLK_MSTR */1820 1821/*1822 * R772 (0x304) - AIF1 RX LRCLK(1)1823 */1824#define WM8996_AIF1RX_RATE_MASK 0x07FF /* AIF1RX_RATE - [10:0] */1825#define WM8996_AIF1RX_RATE_SHIFT 0 /* AIF1RX_RATE - [10:0] */1826#define WM8996_AIF1RX_RATE_WIDTH 11 /* AIF1RX_RATE - [10:0] */1827 1828/*1829 * R773 (0x305) - AIF1 RX LRCLK(2)1830 */1831#define WM8996_AIF1RX_LRCLK_INV 0x0004 /* AIF1RX_LRCLK_INV */1832#define WM8996_AIF1RX_LRCLK_INV_MASK 0x0004 /* AIF1RX_LRCLK_INV */1833#define WM8996_AIF1RX_LRCLK_INV_SHIFT 2 /* AIF1RX_LRCLK_INV */1834#define WM8996_AIF1RX_LRCLK_INV_WIDTH 1 /* AIF1RX_LRCLK_INV */1835#define WM8996_AIF1RX_LRCLK_FRC 0x0002 /* AIF1RX_LRCLK_FRC */1836#define WM8996_AIF1RX_LRCLK_FRC_MASK 0x0002 /* AIF1RX_LRCLK_FRC */1837#define WM8996_AIF1RX_LRCLK_FRC_SHIFT 1 /* AIF1RX_LRCLK_FRC */1838#define WM8996_AIF1RX_LRCLK_FRC_WIDTH 1 /* AIF1RX_LRCLK_FRC */1839#define WM8996_AIF1RX_LRCLK_MSTR 0x0001 /* AIF1RX_LRCLK_MSTR */1840#define WM8996_AIF1RX_LRCLK_MSTR_MASK 0x0001 /* AIF1RX_LRCLK_MSTR */1841#define WM8996_AIF1RX_LRCLK_MSTR_SHIFT 0 /* AIF1RX_LRCLK_MSTR */1842#define WM8996_AIF1RX_LRCLK_MSTR_WIDTH 1 /* AIF1RX_LRCLK_MSTR */1843 1844/*1845 * R774 (0x306) - AIF1TX Data Configuration (1)1846 */1847#define WM8996_AIF1TX_WL_MASK 0xFF00 /* AIF1TX_WL - [15:8] */1848#define WM8996_AIF1TX_WL_SHIFT 8 /* AIF1TX_WL - [15:8] */1849#define WM8996_AIF1TX_WL_WIDTH 8 /* AIF1TX_WL - [15:8] */1850#define WM8996_AIF1TX_SLOT_LEN_MASK 0x00FF /* AIF1TX_SLOT_LEN - [7:0] */1851#define WM8996_AIF1TX_SLOT_LEN_SHIFT 0 /* AIF1TX_SLOT_LEN - [7:0] */1852#define WM8996_AIF1TX_SLOT_LEN_WIDTH 8 /* AIF1TX_SLOT_LEN - [7:0] */1853 1854/*1855 * R775 (0x307) - AIF1TX Data Configuration (2)1856 */1857#define WM8996_AIF1TX_DAT_TRI 0x0001 /* AIF1TX_DAT_TRI */1858#define WM8996_AIF1TX_DAT_TRI_MASK 0x0001 /* AIF1TX_DAT_TRI */1859#define WM8996_AIF1TX_DAT_TRI_SHIFT 0 /* AIF1TX_DAT_TRI */1860#define WM8996_AIF1TX_DAT_TRI_WIDTH 1 /* AIF1TX_DAT_TRI */1861 1862/*1863 * R776 (0x308) - AIF1RX Data Configuration1864 */1865#define WM8996_AIF1RX_WL_MASK 0xFF00 /* AIF1RX_WL - [15:8] */1866#define WM8996_AIF1RX_WL_SHIFT 8 /* AIF1RX_WL - [15:8] */1867#define WM8996_AIF1RX_WL_WIDTH 8 /* AIF1RX_WL - [15:8] */1868#define WM8996_AIF1RX_SLOT_LEN_MASK 0x00FF /* AIF1RX_SLOT_LEN - [7:0] */1869#define WM8996_AIF1RX_SLOT_LEN_SHIFT 0 /* AIF1RX_SLOT_LEN - [7:0] */1870#define WM8996_AIF1RX_SLOT_LEN_WIDTH 8 /* AIF1RX_SLOT_LEN - [7:0] */1871 1872/*1873 * R777 (0x309) - AIF1TX Channel 0 Configuration1874 */1875#define WM8996_AIF1TX_CHAN0_DAT_INV 0x8000 /* AIF1TX_CHAN0_DAT_INV */1876#define WM8996_AIF1TX_CHAN0_DAT_INV_MASK 0x8000 /* AIF1TX_CHAN0_DAT_INV */1877#define WM8996_AIF1TX_CHAN0_DAT_INV_SHIFT 15 /* AIF1TX_CHAN0_DAT_INV */1878#define WM8996_AIF1TX_CHAN0_DAT_INV_WIDTH 1 /* AIF1TX_CHAN0_DAT_INV */1879#define WM8996_AIF1TX_CHAN0_SPACING_MASK 0x7E00 /* AIF1TX_CHAN0_SPACING - [14:9] */1880#define WM8996_AIF1TX_CHAN0_SPACING_SHIFT 9 /* AIF1TX_CHAN0_SPACING - [14:9] */1881#define WM8996_AIF1TX_CHAN0_SPACING_WIDTH 6 /* AIF1TX_CHAN0_SPACING - [14:9] */1882#define WM8996_AIF1TX_CHAN0_SLOTS_MASK 0x01C0 /* AIF1TX_CHAN0_SLOTS - [8:6] */1883#define WM8996_AIF1TX_CHAN0_SLOTS_SHIFT 6 /* AIF1TX_CHAN0_SLOTS - [8:6] */1884#define WM8996_AIF1TX_CHAN0_SLOTS_WIDTH 3 /* AIF1TX_CHAN0_SLOTS - [8:6] */1885#define WM8996_AIF1TX_CHAN0_START_SLOT_MASK 0x003F /* AIF1TX_CHAN0_START_SLOT - [5:0] */1886#define WM8996_AIF1TX_CHAN0_START_SLOT_SHIFT 0 /* AIF1TX_CHAN0_START_SLOT - [5:0] */1887#define WM8996_AIF1TX_CHAN0_START_SLOT_WIDTH 6 /* AIF1TX_CHAN0_START_SLOT - [5:0] */1888 1889/*1890 * R778 (0x30A) - AIF1TX Channel 1 Configuration1891 */1892#define WM8996_AIF1TX_CHAN1_DAT_INV 0x8000 /* AIF1TX_CHAN1_DAT_INV */1893#define WM8996_AIF1TX_CHAN1_DAT_INV_MASK 0x8000 /* AIF1TX_CHAN1_DAT_INV */1894#define WM8996_AIF1TX_CHAN1_DAT_INV_SHIFT 15 /* AIF1TX_CHAN1_DAT_INV */1895#define WM8996_AIF1TX_CHAN1_DAT_INV_WIDTH 1 /* AIF1TX_CHAN1_DAT_INV */1896#define WM8996_AIF1TX_CHAN1_SPACING_MASK 0x7E00 /* AIF1TX_CHAN1_SPACING - [14:9] */1897#define WM8996_AIF1TX_CHAN1_SPACING_SHIFT 9 /* AIF1TX_CHAN1_SPACING - [14:9] */1898#define WM8996_AIF1TX_CHAN1_SPACING_WIDTH 6 /* AIF1TX_CHAN1_SPACING - [14:9] */1899#define WM8996_AIF1TX_CHAN1_SLOTS_MASK 0x01C0 /* AIF1TX_CHAN1_SLOTS - [8:6] */1900#define WM8996_AIF1TX_CHAN1_SLOTS_SHIFT 6 /* AIF1TX_CHAN1_SLOTS - [8:6] */1901#define WM8996_AIF1TX_CHAN1_SLOTS_WIDTH 3 /* AIF1TX_CHAN1_SLOTS - [8:6] */1902#define WM8996_AIF1TX_CHAN1_START_SLOT_MASK 0x003F /* AIF1TX_CHAN1_START_SLOT - [5:0] */1903#define WM8996_AIF1TX_CHAN1_START_SLOT_SHIFT 0 /* AIF1TX_CHAN1_START_SLOT - [5:0] */1904#define WM8996_AIF1TX_CHAN1_START_SLOT_WIDTH 6 /* AIF1TX_CHAN1_START_SLOT - [5:0] */1905 1906/*1907 * R779 (0x30B) - AIF1TX Channel 2 Configuration1908 */1909#define WM8996_AIF1TX_CHAN2_DAT_INV 0x8000 /* AIF1TX_CHAN2_DAT_INV */1910#define WM8996_AIF1TX_CHAN2_DAT_INV_MASK 0x8000 /* AIF1TX_CHAN2_DAT_INV */1911#define WM8996_AIF1TX_CHAN2_DAT_INV_SHIFT 15 /* AIF1TX_CHAN2_DAT_INV */1912#define WM8996_AIF1TX_CHAN2_DAT_INV_WIDTH 1 /* AIF1TX_CHAN2_DAT_INV */1913#define WM8996_AIF1TX_CHAN2_SPACING_MASK 0x7E00 /* AIF1TX_CHAN2_SPACING - [14:9] */1914#define WM8996_AIF1TX_CHAN2_SPACING_SHIFT 9 /* AIF1TX_CHAN2_SPACING - [14:9] */1915#define WM8996_AIF1TX_CHAN2_SPACING_WIDTH 6 /* AIF1TX_CHAN2_SPACING - [14:9] */1916#define WM8996_AIF1TX_CHAN2_SLOTS_MASK 0x01C0 /* AIF1TX_CHAN2_SLOTS - [8:6] */1917#define WM8996_AIF1TX_CHAN2_SLOTS_SHIFT 6 /* AIF1TX_CHAN2_SLOTS - [8:6] */1918#define WM8996_AIF1TX_CHAN2_SLOTS_WIDTH 3 /* AIF1TX_CHAN2_SLOTS - [8:6] */1919#define WM8996_AIF1TX_CHAN2_START_SLOT_MASK 0x003F /* AIF1TX_CHAN2_START_SLOT - [5:0] */1920#define WM8996_AIF1TX_CHAN2_START_SLOT_SHIFT 0 /* AIF1TX_CHAN2_START_SLOT - [5:0] */1921#define WM8996_AIF1TX_CHAN2_START_SLOT_WIDTH 6 /* AIF1TX_CHAN2_START_SLOT - [5:0] */1922 1923/*1924 * R780 (0x30C) - AIF1TX Channel 3 Configuration1925 */1926#define WM8996_AIF1TX_CHAN3_DAT_INV 0x8000 /* AIF1TX_CHAN3_DAT_INV */1927#define WM8996_AIF1TX_CHAN3_DAT_INV_MASK 0x8000 /* AIF1TX_CHAN3_DAT_INV */1928#define WM8996_AIF1TX_CHAN3_DAT_INV_SHIFT 15 /* AIF1TX_CHAN3_DAT_INV */1929#define WM8996_AIF1TX_CHAN3_DAT_INV_WIDTH 1 /* AIF1TX_CHAN3_DAT_INV */1930#define WM8996_AIF1TX_CHAN3_SPACING_MASK 0x7E00 /* AIF1TX_CHAN3_SPACING - [14:9] */1931#define WM8996_AIF1TX_CHAN3_SPACING_SHIFT 9 /* AIF1TX_CHAN3_SPACING - [14:9] */1932#define WM8996_AIF1TX_CHAN3_SPACING_WIDTH 6 /* AIF1TX_CHAN3_SPACING - [14:9] */1933#define WM8996_AIF1TX_CHAN3_SLOTS_MASK 0x01C0 /* AIF1TX_CHAN3_SLOTS - [8:6] */1934#define WM8996_AIF1TX_CHAN3_SLOTS_SHIFT 6 /* AIF1TX_CHAN3_SLOTS - [8:6] */1935#define WM8996_AIF1TX_CHAN3_SLOTS_WIDTH 3 /* AIF1TX_CHAN3_SLOTS - [8:6] */1936#define WM8996_AIF1TX_CHAN3_START_SLOT_MASK 0x003F /* AIF1TX_CHAN3_START_SLOT - [5:0] */1937#define WM8996_AIF1TX_CHAN3_START_SLOT_SHIFT 0 /* AIF1TX_CHAN3_START_SLOT - [5:0] */1938#define WM8996_AIF1TX_CHAN3_START_SLOT_WIDTH 6 /* AIF1TX_CHAN3_START_SLOT - [5:0] */1939 1940/*1941 * R781 (0x30D) - AIF1TX Channel 4 Configuration1942 */1943#define WM8996_AIF1TX_CHAN4_DAT_INV 0x8000 /* AIF1TX_CHAN4_DAT_INV */1944#define WM8996_AIF1TX_CHAN4_DAT_INV_MASK 0x8000 /* AIF1TX_CHAN4_DAT_INV */1945#define WM8996_AIF1TX_CHAN4_DAT_INV_SHIFT 15 /* AIF1TX_CHAN4_DAT_INV */1946#define WM8996_AIF1TX_CHAN4_DAT_INV_WIDTH 1 /* AIF1TX_CHAN4_DAT_INV */1947#define WM8996_AIF1TX_CHAN4_SPACING_MASK 0x7E00 /* AIF1TX_CHAN4_SPACING - [14:9] */1948#define WM8996_AIF1TX_CHAN4_SPACING_SHIFT 9 /* AIF1TX_CHAN4_SPACING - [14:9] */1949#define WM8996_AIF1TX_CHAN4_SPACING_WIDTH 6 /* AIF1TX_CHAN4_SPACING - [14:9] */1950#define WM8996_AIF1TX_CHAN4_SLOTS_MASK 0x01C0 /* AIF1TX_CHAN4_SLOTS - [8:6] */1951#define WM8996_AIF1TX_CHAN4_SLOTS_SHIFT 6 /* AIF1TX_CHAN4_SLOTS - [8:6] */1952#define WM8996_AIF1TX_CHAN4_SLOTS_WIDTH 3 /* AIF1TX_CHAN4_SLOTS - [8:6] */1953#define WM8996_AIF1TX_CHAN4_START_SLOT_MASK 0x003F /* AIF1TX_CHAN4_START_SLOT - [5:0] */1954#define WM8996_AIF1TX_CHAN4_START_SLOT_SHIFT 0 /* AIF1TX_CHAN4_START_SLOT - [5:0] */1955#define WM8996_AIF1TX_CHAN4_START_SLOT_WIDTH 6 /* AIF1TX_CHAN4_START_SLOT - [5:0] */1956 1957/*1958 * R782 (0x30E) - AIF1TX Channel 5 Configuration1959 */1960#define WM8996_AIF1TX_CHAN5_DAT_INV 0x8000 /* AIF1TX_CHAN5_DAT_INV */1961#define WM8996_AIF1TX_CHAN5_DAT_INV_MASK 0x8000 /* AIF1TX_CHAN5_DAT_INV */1962#define WM8996_AIF1TX_CHAN5_DAT_INV_SHIFT 15 /* AIF1TX_CHAN5_DAT_INV */1963#define WM8996_AIF1TX_CHAN5_DAT_INV_WIDTH 1 /* AIF1TX_CHAN5_DAT_INV */1964#define WM8996_AIF1TX_CHAN5_SPACING_MASK 0x7E00 /* AIF1TX_CHAN5_SPACING - [14:9] */1965#define WM8996_AIF1TX_CHAN5_SPACING_SHIFT 9 /* AIF1TX_CHAN5_SPACING - [14:9] */1966#define WM8996_AIF1TX_CHAN5_SPACING_WIDTH 6 /* AIF1TX_CHAN5_SPACING - [14:9] */1967#define WM8996_AIF1TX_CHAN5_SLOTS_MASK 0x01C0 /* AIF1TX_CHAN5_SLOTS - [8:6] */1968#define WM8996_AIF1TX_CHAN5_SLOTS_SHIFT 6 /* AIF1TX_CHAN5_SLOTS - [8:6] */1969#define WM8996_AIF1TX_CHAN5_SLOTS_WIDTH 3 /* AIF1TX_CHAN5_SLOTS - [8:6] */1970#define WM8996_AIF1TX_CHAN5_START_SLOT_MASK 0x003F /* AIF1TX_CHAN5_START_SLOT - [5:0] */1971#define WM8996_AIF1TX_CHAN5_START_SLOT_SHIFT 0 /* AIF1TX_CHAN5_START_SLOT - [5:0] */1972#define WM8996_AIF1TX_CHAN5_START_SLOT_WIDTH 6 /* AIF1TX_CHAN5_START_SLOT - [5:0] */1973 1974/*1975 * R783 (0x30F) - AIF1RX Channel 0 Configuration1976 */1977#define WM8996_AIF1RX_CHAN0_DAT_INV 0x8000 /* AIF1RX_CHAN0_DAT_INV */1978#define WM8996_AIF1RX_CHAN0_DAT_INV_MASK 0x8000 /* AIF1RX_CHAN0_DAT_INV */1979#define WM8996_AIF1RX_CHAN0_DAT_INV_SHIFT 15 /* AIF1RX_CHAN0_DAT_INV */1980#define WM8996_AIF1RX_CHAN0_DAT_INV_WIDTH 1 /* AIF1RX_CHAN0_DAT_INV */1981#define WM8996_AIF1RX_CHAN0_SPACING_MASK 0x7E00 /* AIF1RX_CHAN0_SPACING - [14:9] */1982#define WM8996_AIF1RX_CHAN0_SPACING_SHIFT 9 /* AIF1RX_CHAN0_SPACING - [14:9] */1983#define WM8996_AIF1RX_CHAN0_SPACING_WIDTH 6 /* AIF1RX_CHAN0_SPACING - [14:9] */1984#define WM8996_AIF1RX_CHAN0_SLOTS_MASK 0x01C0 /* AIF1RX_CHAN0_SLOTS - [8:6] */1985#define WM8996_AIF1RX_CHAN0_SLOTS_SHIFT 6 /* AIF1RX_CHAN0_SLOTS - [8:6] */1986#define WM8996_AIF1RX_CHAN0_SLOTS_WIDTH 3 /* AIF1RX_CHAN0_SLOTS - [8:6] */1987#define WM8996_AIF1RX_CHAN0_START_SLOT_MASK 0x003F /* AIF1RX_CHAN0_START_SLOT - [5:0] */1988#define WM8996_AIF1RX_CHAN0_START_SLOT_SHIFT 0 /* AIF1RX_CHAN0_START_SLOT - [5:0] */1989#define WM8996_AIF1RX_CHAN0_START_SLOT_WIDTH 6 /* AIF1RX_CHAN0_START_SLOT - [5:0] */1990 1991/*1992 * R784 (0x310) - AIF1RX Channel 1 Configuration1993 */1994#define WM8996_AIF1RX_CHAN1_DAT_INV 0x8000 /* AIF1RX_CHAN1_DAT_INV */1995#define WM8996_AIF1RX_CHAN1_DAT_INV_MASK 0x8000 /* AIF1RX_CHAN1_DAT_INV */1996#define WM8996_AIF1RX_CHAN1_DAT_INV_SHIFT 15 /* AIF1RX_CHAN1_DAT_INV */1997#define WM8996_AIF1RX_CHAN1_DAT_INV_WIDTH 1 /* AIF1RX_CHAN1_DAT_INV */1998#define WM8996_AIF1RX_CHAN1_SPACING_MASK 0x7E00 /* AIF1RX_CHAN1_SPACING - [14:9] */1999#define WM8996_AIF1RX_CHAN1_SPACING_SHIFT 9 /* AIF1RX_CHAN1_SPACING - [14:9] */2000#define WM8996_AIF1RX_CHAN1_SPACING_WIDTH 6 /* AIF1RX_CHAN1_SPACING - [14:9] */2001#define WM8996_AIF1RX_CHAN1_SLOTS_MASK 0x01C0 /* AIF1RX_CHAN1_SLOTS - [8:6] */2002#define WM8996_AIF1RX_CHAN1_SLOTS_SHIFT 6 /* AIF1RX_CHAN1_SLOTS - [8:6] */2003#define WM8996_AIF1RX_CHAN1_SLOTS_WIDTH 3 /* AIF1RX_CHAN1_SLOTS - [8:6] */2004#define WM8996_AIF1RX_CHAN1_START_SLOT_MASK 0x003F /* AIF1RX_CHAN1_START_SLOT - [5:0] */2005#define WM8996_AIF1RX_CHAN1_START_SLOT_SHIFT 0 /* AIF1RX_CHAN1_START_SLOT - [5:0] */2006#define WM8996_AIF1RX_CHAN1_START_SLOT_WIDTH 6 /* AIF1RX_CHAN1_START_SLOT - [5:0] */2007 2008/*2009 * R785 (0x311) - AIF1RX Channel 2 Configuration2010 */2011#define WM8996_AIF1RX_CHAN2_DAT_INV 0x8000 /* AIF1RX_CHAN2_DAT_INV */2012#define WM8996_AIF1RX_CHAN2_DAT_INV_MASK 0x8000 /* AIF1RX_CHAN2_DAT_INV */2013#define WM8996_AIF1RX_CHAN2_DAT_INV_SHIFT 15 /* AIF1RX_CHAN2_DAT_INV */2014#define WM8996_AIF1RX_CHAN2_DAT_INV_WIDTH 1 /* AIF1RX_CHAN2_DAT_INV */2015#define WM8996_AIF1RX_CHAN2_SPACING_MASK 0x7E00 /* AIF1RX_CHAN2_SPACING - [14:9] */2016#define WM8996_AIF1RX_CHAN2_SPACING_SHIFT 9 /* AIF1RX_CHAN2_SPACING - [14:9] */2017#define WM8996_AIF1RX_CHAN2_SPACING_WIDTH 6 /* AIF1RX_CHAN2_SPACING - [14:9] */2018#define WM8996_AIF1RX_CHAN2_SLOTS_MASK 0x01C0 /* AIF1RX_CHAN2_SLOTS - [8:6] */2019#define WM8996_AIF1RX_CHAN2_SLOTS_SHIFT 6 /* AIF1RX_CHAN2_SLOTS - [8:6] */2020#define WM8996_AIF1RX_CHAN2_SLOTS_WIDTH 3 /* AIF1RX_CHAN2_SLOTS - [8:6] */2021#define WM8996_AIF1RX_CHAN2_START_SLOT_MASK 0x003F /* AIF1RX_CHAN2_START_SLOT - [5:0] */2022#define WM8996_AIF1RX_CHAN2_START_SLOT_SHIFT 0 /* AIF1RX_CHAN2_START_SLOT - [5:0] */2023#define WM8996_AIF1RX_CHAN2_START_SLOT_WIDTH 6 /* AIF1RX_CHAN2_START_SLOT - [5:0] */2024 2025/*2026 * R786 (0x312) - AIF1RX Channel 3 Configuration2027 */2028#define WM8996_AIF1RX_CHAN3_DAT_INV 0x8000 /* AIF1RX_CHAN3_DAT_INV */2029#define WM8996_AIF1RX_CHAN3_DAT_INV_MASK 0x8000 /* AIF1RX_CHAN3_DAT_INV */2030#define WM8996_AIF1RX_CHAN3_DAT_INV_SHIFT 15 /* AIF1RX_CHAN3_DAT_INV */2031#define WM8996_AIF1RX_CHAN3_DAT_INV_WIDTH 1 /* AIF1RX_CHAN3_DAT_INV */2032#define WM8996_AIF1RX_CHAN3_SPACING_MASK 0x7E00 /* AIF1RX_CHAN3_SPACING - [14:9] */2033#define WM8996_AIF1RX_CHAN3_SPACING_SHIFT 9 /* AIF1RX_CHAN3_SPACING - [14:9] */2034#define WM8996_AIF1RX_CHAN3_SPACING_WIDTH 6 /* AIF1RX_CHAN3_SPACING - [14:9] */2035#define WM8996_AIF1RX_CHAN3_SLOTS_MASK 0x01C0 /* AIF1RX_CHAN3_SLOTS - [8:6] */2036#define WM8996_AIF1RX_CHAN3_SLOTS_SHIFT 6 /* AIF1RX_CHAN3_SLOTS - [8:6] */2037#define WM8996_AIF1RX_CHAN3_SLOTS_WIDTH 3 /* AIF1RX_CHAN3_SLOTS - [8:6] */2038#define WM8996_AIF1RX_CHAN3_START_SLOT_MASK 0x003F /* AIF1RX_CHAN3_START_SLOT - [5:0] */2039#define WM8996_AIF1RX_CHAN3_START_SLOT_SHIFT 0 /* AIF1RX_CHAN3_START_SLOT - [5:0] */2040#define WM8996_AIF1RX_CHAN3_START_SLOT_WIDTH 6 /* AIF1RX_CHAN3_START_SLOT - [5:0] */2041 2042/*2043 * R787 (0x313) - AIF1RX Channel 4 Configuration2044 */2045#define WM8996_AIF1RX_CHAN4_DAT_INV 0x8000 /* AIF1RX_CHAN4_DAT_INV */2046#define WM8996_AIF1RX_CHAN4_DAT_INV_MASK 0x8000 /* AIF1RX_CHAN4_DAT_INV */2047#define WM8996_AIF1RX_CHAN4_DAT_INV_SHIFT 15 /* AIF1RX_CHAN4_DAT_INV */2048#define WM8996_AIF1RX_CHAN4_DAT_INV_WIDTH 1 /* AIF1RX_CHAN4_DAT_INV */2049#define WM8996_AIF1RX_CHAN4_SPACING_MASK 0x7E00 /* AIF1RX_CHAN4_SPACING - [14:9] */2050#define WM8996_AIF1RX_CHAN4_SPACING_SHIFT 9 /* AIF1RX_CHAN4_SPACING - [14:9] */2051#define WM8996_AIF1RX_CHAN4_SPACING_WIDTH 6 /* AIF1RX_CHAN4_SPACING - [14:9] */2052#define WM8996_AIF1RX_CHAN4_SLOTS_MASK 0x01C0 /* AIF1RX_CHAN4_SLOTS - [8:6] */2053#define WM8996_AIF1RX_CHAN4_SLOTS_SHIFT 6 /* AIF1RX_CHAN4_SLOTS - [8:6] */2054#define WM8996_AIF1RX_CHAN4_SLOTS_WIDTH 3 /* AIF1RX_CHAN4_SLOTS - [8:6] */2055#define WM8996_AIF1RX_CHAN4_START_SLOT_MASK 0x003F /* AIF1RX_CHAN4_START_SLOT - [5:0] */2056#define WM8996_AIF1RX_CHAN4_START_SLOT_SHIFT 0 /* AIF1RX_CHAN4_START_SLOT - [5:0] */2057#define WM8996_AIF1RX_CHAN4_START_SLOT_WIDTH 6 /* AIF1RX_CHAN4_START_SLOT - [5:0] */2058 2059/*2060 * R788 (0x314) - AIF1RX Channel 5 Configuration2061 */2062#define WM8996_AIF1RX_CHAN5_DAT_INV 0x8000 /* AIF1RX_CHAN5_DAT_INV */2063#define WM8996_AIF1RX_CHAN5_DAT_INV_MASK 0x8000 /* AIF1RX_CHAN5_DAT_INV */2064#define WM8996_AIF1RX_CHAN5_DAT_INV_SHIFT 15 /* AIF1RX_CHAN5_DAT_INV */2065#define WM8996_AIF1RX_CHAN5_DAT_INV_WIDTH 1 /* AIF1RX_CHAN5_DAT_INV */2066#define WM8996_AIF1RX_CHAN5_SPACING_MASK 0x7E00 /* AIF1RX_CHAN5_SPACING - [14:9] */2067#define WM8996_AIF1RX_CHAN5_SPACING_SHIFT 9 /* AIF1RX_CHAN5_SPACING - [14:9] */2068#define WM8996_AIF1RX_CHAN5_SPACING_WIDTH 6 /* AIF1RX_CHAN5_SPACING - [14:9] */2069#define WM8996_AIF1RX_CHAN5_SLOTS_MASK 0x01C0 /* AIF1RX_CHAN5_SLOTS - [8:6] */2070#define WM8996_AIF1RX_CHAN5_SLOTS_SHIFT 6 /* AIF1RX_CHAN5_SLOTS - [8:6] */2071#define WM8996_AIF1RX_CHAN5_SLOTS_WIDTH 3 /* AIF1RX_CHAN5_SLOTS - [8:6] */2072#define WM8996_AIF1RX_CHAN5_START_SLOT_MASK 0x003F /* AIF1RX_CHAN5_START_SLOT - [5:0] */2073#define WM8996_AIF1RX_CHAN5_START_SLOT_SHIFT 0 /* AIF1RX_CHAN5_START_SLOT - [5:0] */2074#define WM8996_AIF1RX_CHAN5_START_SLOT_WIDTH 6 /* AIF1RX_CHAN5_START_SLOT - [5:0] */2075 2076/*2077 * R789 (0x315) - AIF1RX Mono Configuration2078 */2079#define WM8996_AIF1RX_CHAN4_MONO_MODE 0x0004 /* AIF1RX_CHAN4_MONO_MODE */2080#define WM8996_AIF1RX_CHAN4_MONO_MODE_MASK 0x0004 /* AIF1RX_CHAN4_MONO_MODE */2081#define WM8996_AIF1RX_CHAN4_MONO_MODE_SHIFT 2 /* AIF1RX_CHAN4_MONO_MODE */2082#define WM8996_AIF1RX_CHAN4_MONO_MODE_WIDTH 1 /* AIF1RX_CHAN4_MONO_MODE */2083#define WM8996_AIF1RX_CHAN2_MONO_MODE 0x0002 /* AIF1RX_CHAN2_MONO_MODE */2084#define WM8996_AIF1RX_CHAN2_MONO_MODE_MASK 0x0002 /* AIF1RX_CHAN2_MONO_MODE */2085#define WM8996_AIF1RX_CHAN2_MONO_MODE_SHIFT 1 /* AIF1RX_CHAN2_MONO_MODE */2086#define WM8996_AIF1RX_CHAN2_MONO_MODE_WIDTH 1 /* AIF1RX_CHAN2_MONO_MODE */2087#define WM8996_AIF1RX_CHAN0_MONO_MODE 0x0001 /* AIF1RX_CHAN0_MONO_MODE */2088#define WM8996_AIF1RX_CHAN0_MONO_MODE_MASK 0x0001 /* AIF1RX_CHAN0_MONO_MODE */2089#define WM8996_AIF1RX_CHAN0_MONO_MODE_SHIFT 0 /* AIF1RX_CHAN0_MONO_MODE */2090#define WM8996_AIF1RX_CHAN0_MONO_MODE_WIDTH 1 /* AIF1RX_CHAN0_MONO_MODE */2091 2092/*2093 * R794 (0x31A) - AIF1TX Test2094 */2095#define WM8996_AIF1TX45_DITHER_ENA 0x0004 /* AIF1TX45_DITHER_ENA */2096#define WM8996_AIF1TX45_DITHER_ENA_MASK 0x0004 /* AIF1TX45_DITHER_ENA */2097#define WM8996_AIF1TX45_DITHER_ENA_SHIFT 2 /* AIF1TX45_DITHER_ENA */2098#define WM8996_AIF1TX45_DITHER_ENA_WIDTH 1 /* AIF1TX45_DITHER_ENA */2099#define WM8996_AIF1TX23_DITHER_ENA 0x0002 /* AIF1TX23_DITHER_ENA */2100#define WM8996_AIF1TX23_DITHER_ENA_MASK 0x0002 /* AIF1TX23_DITHER_ENA */2101#define WM8996_AIF1TX23_DITHER_ENA_SHIFT 1 /* AIF1TX23_DITHER_ENA */2102#define WM8996_AIF1TX23_DITHER_ENA_WIDTH 1 /* AIF1TX23_DITHER_ENA */2103#define WM8996_AIF1TX01_DITHER_ENA 0x0001 /* AIF1TX01_DITHER_ENA */2104#define WM8996_AIF1TX01_DITHER_ENA_MASK 0x0001 /* AIF1TX01_DITHER_ENA */2105#define WM8996_AIF1TX01_DITHER_ENA_SHIFT 0 /* AIF1TX01_DITHER_ENA */2106#define WM8996_AIF1TX01_DITHER_ENA_WIDTH 1 /* AIF1TX01_DITHER_ENA */2107 2108/*2109 * R800 (0x320) - AIF2 Control2110 */2111#define WM8996_AIF2_TRI 0x0004 /* AIF2_TRI */2112#define WM8996_AIF2_TRI_MASK 0x0004 /* AIF2_TRI */2113#define WM8996_AIF2_TRI_SHIFT 2 /* AIF2_TRI */2114#define WM8996_AIF2_TRI_WIDTH 1 /* AIF2_TRI */2115#define WM8996_AIF2_FMT_MASK 0x0003 /* AIF2_FMT - [1:0] */2116#define WM8996_AIF2_FMT_SHIFT 0 /* AIF2_FMT - [1:0] */2117#define WM8996_AIF2_FMT_WIDTH 2 /* AIF2_FMT - [1:0] */2118 2119/*2120 * R801 (0x321) - AIF2 BCLK2121 */2122#define WM8996_AIF2_BCLK_INV 0x0400 /* AIF2_BCLK_INV */2123#define WM8996_AIF2_BCLK_INV_MASK 0x0400 /* AIF2_BCLK_INV */2124#define WM8996_AIF2_BCLK_INV_SHIFT 10 /* AIF2_BCLK_INV */2125#define WM8996_AIF2_BCLK_INV_WIDTH 1 /* AIF2_BCLK_INV */2126#define WM8996_AIF2_BCLK_FRC 0x0200 /* AIF2_BCLK_FRC */2127#define WM8996_AIF2_BCLK_FRC_MASK 0x0200 /* AIF2_BCLK_FRC */2128#define WM8996_AIF2_BCLK_FRC_SHIFT 9 /* AIF2_BCLK_FRC */2129#define WM8996_AIF2_BCLK_FRC_WIDTH 1 /* AIF2_BCLK_FRC */2130#define WM8996_AIF2_BCLK_MSTR 0x0100 /* AIF2_BCLK_MSTR */2131#define WM8996_AIF2_BCLK_MSTR_MASK 0x0100 /* AIF2_BCLK_MSTR */2132#define WM8996_AIF2_BCLK_MSTR_SHIFT 8 /* AIF2_BCLK_MSTR */2133#define WM8996_AIF2_BCLK_MSTR_WIDTH 1 /* AIF2_BCLK_MSTR */2134#define WM8996_AIF2_BCLK_DIV_MASK 0x000F /* AIF2_BCLK_DIV - [3:0] */2135#define WM8996_AIF2_BCLK_DIV_SHIFT 0 /* AIF2_BCLK_DIV - [3:0] */2136#define WM8996_AIF2_BCLK_DIV_WIDTH 4 /* AIF2_BCLK_DIV - [3:0] */2137 2138/*2139 * R802 (0x322) - AIF2 TX LRCLK(1)2140 */2141#define WM8996_AIF2TX_RATE_MASK 0x07FF /* AIF2TX_RATE - [10:0] */2142#define WM8996_AIF2TX_RATE_SHIFT 0 /* AIF2TX_RATE - [10:0] */2143#define WM8996_AIF2TX_RATE_WIDTH 11 /* AIF2TX_RATE - [10:0] */2144 2145/*2146 * R803 (0x323) - AIF2 TX LRCLK(2)2147 */2148#define WM8996_AIF2TX_LRCLK_MODE 0x0008 /* AIF2TX_LRCLK_MODE */2149#define WM8996_AIF2TX_LRCLK_MODE_MASK 0x0008 /* AIF2TX_LRCLK_MODE */2150#define WM8996_AIF2TX_LRCLK_MODE_SHIFT 3 /* AIF2TX_LRCLK_MODE */2151#define WM8996_AIF2TX_LRCLK_MODE_WIDTH 1 /* AIF2TX_LRCLK_MODE */2152#define WM8996_AIF2TX_LRCLK_INV 0x0004 /* AIF2TX_LRCLK_INV */2153#define WM8996_AIF2TX_LRCLK_INV_MASK 0x0004 /* AIF2TX_LRCLK_INV */2154#define WM8996_AIF2TX_LRCLK_INV_SHIFT 2 /* AIF2TX_LRCLK_INV */2155#define WM8996_AIF2TX_LRCLK_INV_WIDTH 1 /* AIF2TX_LRCLK_INV */2156#define WM8996_AIF2TX_LRCLK_FRC 0x0002 /* AIF2TX_LRCLK_FRC */2157#define WM8996_AIF2TX_LRCLK_FRC_MASK 0x0002 /* AIF2TX_LRCLK_FRC */2158#define WM8996_AIF2TX_LRCLK_FRC_SHIFT 1 /* AIF2TX_LRCLK_FRC */2159#define WM8996_AIF2TX_LRCLK_FRC_WIDTH 1 /* AIF2TX_LRCLK_FRC */2160#define WM8996_AIF2TX_LRCLK_MSTR 0x0001 /* AIF2TX_LRCLK_MSTR */2161#define WM8996_AIF2TX_LRCLK_MSTR_MASK 0x0001 /* AIF2TX_LRCLK_MSTR */2162#define WM8996_AIF2TX_LRCLK_MSTR_SHIFT 0 /* AIF2TX_LRCLK_MSTR */2163#define WM8996_AIF2TX_LRCLK_MSTR_WIDTH 1 /* AIF2TX_LRCLK_MSTR */2164 2165/*2166 * R804 (0x324) - AIF2 RX LRCLK(1)2167 */2168#define WM8996_AIF2RX_RATE_MASK 0x07FF /* AIF2RX_RATE - [10:0] */2169#define WM8996_AIF2RX_RATE_SHIFT 0 /* AIF2RX_RATE - [10:0] */2170#define WM8996_AIF2RX_RATE_WIDTH 11 /* AIF2RX_RATE - [10:0] */2171 2172/*2173 * R805 (0x325) - AIF2 RX LRCLK(2)2174 */2175#define WM8996_AIF2RX_LRCLK_INV 0x0004 /* AIF2RX_LRCLK_INV */2176#define WM8996_AIF2RX_LRCLK_INV_MASK 0x0004 /* AIF2RX_LRCLK_INV */2177#define WM8996_AIF2RX_LRCLK_INV_SHIFT 2 /* AIF2RX_LRCLK_INV */2178#define WM8996_AIF2RX_LRCLK_INV_WIDTH 1 /* AIF2RX_LRCLK_INV */2179#define WM8996_AIF2RX_LRCLK_FRC 0x0002 /* AIF2RX_LRCLK_FRC */2180#define WM8996_AIF2RX_LRCLK_FRC_MASK 0x0002 /* AIF2RX_LRCLK_FRC */2181#define WM8996_AIF2RX_LRCLK_FRC_SHIFT 1 /* AIF2RX_LRCLK_FRC */2182#define WM8996_AIF2RX_LRCLK_FRC_WIDTH 1 /* AIF2RX_LRCLK_FRC */2183#define WM8996_AIF2RX_LRCLK_MSTR 0x0001 /* AIF2RX_LRCLK_MSTR */2184#define WM8996_AIF2RX_LRCLK_MSTR_MASK 0x0001 /* AIF2RX_LRCLK_MSTR */2185#define WM8996_AIF2RX_LRCLK_MSTR_SHIFT 0 /* AIF2RX_LRCLK_MSTR */2186#define WM8996_AIF2RX_LRCLK_MSTR_WIDTH 1 /* AIF2RX_LRCLK_MSTR */2187 2188/*2189 * R806 (0x326) - AIF2TX Data Configuration (1)2190 */2191#define WM8996_AIF2TX_WL_MASK 0xFF00 /* AIF2TX_WL - [15:8] */2192#define WM8996_AIF2TX_WL_SHIFT 8 /* AIF2TX_WL - [15:8] */2193#define WM8996_AIF2TX_WL_WIDTH 8 /* AIF2TX_WL - [15:8] */2194#define WM8996_AIF2TX_SLOT_LEN_MASK 0x00FF /* AIF2TX_SLOT_LEN - [7:0] */2195#define WM8996_AIF2TX_SLOT_LEN_SHIFT 0 /* AIF2TX_SLOT_LEN - [7:0] */2196#define WM8996_AIF2TX_SLOT_LEN_WIDTH 8 /* AIF2TX_SLOT_LEN - [7:0] */2197 2198/*2199 * R807 (0x327) - AIF2TX Data Configuration (2)2200 */2201#define WM8996_AIF2TX_DAT_TRI 0x0001 /* AIF2TX_DAT_TRI */2202#define WM8996_AIF2TX_DAT_TRI_MASK 0x0001 /* AIF2TX_DAT_TRI */2203#define WM8996_AIF2TX_DAT_TRI_SHIFT 0 /* AIF2TX_DAT_TRI */2204#define WM8996_AIF2TX_DAT_TRI_WIDTH 1 /* AIF2TX_DAT_TRI */2205 2206/*2207 * R808 (0x328) - AIF2RX Data Configuration2208 */2209#define WM8996_AIF2RX_WL_MASK 0xFF00 /* AIF2RX_WL - [15:8] */2210#define WM8996_AIF2RX_WL_SHIFT 8 /* AIF2RX_WL - [15:8] */2211#define WM8996_AIF2RX_WL_WIDTH 8 /* AIF2RX_WL - [15:8] */2212#define WM8996_AIF2RX_SLOT_LEN_MASK 0x00FF /* AIF2RX_SLOT_LEN - [7:0] */2213#define WM8996_AIF2RX_SLOT_LEN_SHIFT 0 /* AIF2RX_SLOT_LEN - [7:0] */2214#define WM8996_AIF2RX_SLOT_LEN_WIDTH 8 /* AIF2RX_SLOT_LEN - [7:0] */2215 2216/*2217 * R809 (0x329) - AIF2TX Channel 0 Configuration2218 */2219#define WM8996_AIF2TX_CHAN0_DAT_INV 0x8000 /* AIF2TX_CHAN0_DAT_INV */2220#define WM8996_AIF2TX_CHAN0_DAT_INV_MASK 0x8000 /* AIF2TX_CHAN0_DAT_INV */2221#define WM8996_AIF2TX_CHAN0_DAT_INV_SHIFT 15 /* AIF2TX_CHAN0_DAT_INV */2222#define WM8996_AIF2TX_CHAN0_DAT_INV_WIDTH 1 /* AIF2TX_CHAN0_DAT_INV */2223#define WM8996_AIF2TX_CHAN0_SPACING_MASK 0x7E00 /* AIF2TX_CHAN0_SPACING - [14:9] */2224#define WM8996_AIF2TX_CHAN0_SPACING_SHIFT 9 /* AIF2TX_CHAN0_SPACING - [14:9] */2225#define WM8996_AIF2TX_CHAN0_SPACING_WIDTH 6 /* AIF2TX_CHAN0_SPACING - [14:9] */2226#define WM8996_AIF2TX_CHAN0_SLOTS_MASK 0x01C0 /* AIF2TX_CHAN0_SLOTS - [8:6] */2227#define WM8996_AIF2TX_CHAN0_SLOTS_SHIFT 6 /* AIF2TX_CHAN0_SLOTS - [8:6] */2228#define WM8996_AIF2TX_CHAN0_SLOTS_WIDTH 3 /* AIF2TX_CHAN0_SLOTS - [8:6] */2229#define WM8996_AIF2TX_CHAN0_START_SLOT_MASK 0x003F /* AIF2TX_CHAN0_START_SLOT - [5:0] */2230#define WM8996_AIF2TX_CHAN0_START_SLOT_SHIFT 0 /* AIF2TX_CHAN0_START_SLOT - [5:0] */2231#define WM8996_AIF2TX_CHAN0_START_SLOT_WIDTH 6 /* AIF2TX_CHAN0_START_SLOT - [5:0] */2232 2233/*2234 * R810 (0x32A) - AIF2TX Channel 1 Configuration2235 */2236#define WM8996_AIF2TX_CHAN1_DAT_INV 0x8000 /* AIF2TX_CHAN1_DAT_INV */2237#define WM8996_AIF2TX_CHAN1_DAT_INV_MASK 0x8000 /* AIF2TX_CHAN1_DAT_INV */2238#define WM8996_AIF2TX_CHAN1_DAT_INV_SHIFT 15 /* AIF2TX_CHAN1_DAT_INV */2239#define WM8996_AIF2TX_CHAN1_DAT_INV_WIDTH 1 /* AIF2TX_CHAN1_DAT_INV */2240#define WM8996_AIF2TX_CHAN1_SPACING_MASK 0x7E00 /* AIF2TX_CHAN1_SPACING - [14:9] */2241#define WM8996_AIF2TX_CHAN1_SPACING_SHIFT 9 /* AIF2TX_CHAN1_SPACING - [14:9] */2242#define WM8996_AIF2TX_CHAN1_SPACING_WIDTH 6 /* AIF2TX_CHAN1_SPACING - [14:9] */2243#define WM8996_AIF2TX_CHAN1_SLOTS_MASK 0x01C0 /* AIF2TX_CHAN1_SLOTS - [8:6] */2244#define WM8996_AIF2TX_CHAN1_SLOTS_SHIFT 6 /* AIF2TX_CHAN1_SLOTS - [8:6] */2245#define WM8996_AIF2TX_CHAN1_SLOTS_WIDTH 3 /* AIF2TX_CHAN1_SLOTS - [8:6] */2246#define WM8996_AIF2TX_CHAN1_START_SLOT_MASK 0x003F /* AIF2TX_CHAN1_START_SLOT - [5:0] */2247#define WM8996_AIF2TX_CHAN1_START_SLOT_SHIFT 0 /* AIF2TX_CHAN1_START_SLOT - [5:0] */2248#define WM8996_AIF2TX_CHAN1_START_SLOT_WIDTH 6 /* AIF2TX_CHAN1_START_SLOT - [5:0] */2249 2250/*2251 * R811 (0x32B) - AIF2RX Channel 0 Configuration2252 */2253#define WM8996_AIF2RX_CHAN0_DAT_INV 0x8000 /* AIF2RX_CHAN0_DAT_INV */2254#define WM8996_AIF2RX_CHAN0_DAT_INV_MASK 0x8000 /* AIF2RX_CHAN0_DAT_INV */2255#define WM8996_AIF2RX_CHAN0_DAT_INV_SHIFT 15 /* AIF2RX_CHAN0_DAT_INV */2256#define WM8996_AIF2RX_CHAN0_DAT_INV_WIDTH 1 /* AIF2RX_CHAN0_DAT_INV */2257#define WM8996_AIF2RX_CHAN0_SPACING_MASK 0x7E00 /* AIF2RX_CHAN0_SPACING - [14:9] */2258#define WM8996_AIF2RX_CHAN0_SPACING_SHIFT 9 /* AIF2RX_CHAN0_SPACING - [14:9] */2259#define WM8996_AIF2RX_CHAN0_SPACING_WIDTH 6 /* AIF2RX_CHAN0_SPACING - [14:9] */2260#define WM8996_AIF2RX_CHAN0_SLOTS_MASK 0x01C0 /* AIF2RX_CHAN0_SLOTS - [8:6] */2261#define WM8996_AIF2RX_CHAN0_SLOTS_SHIFT 6 /* AIF2RX_CHAN0_SLOTS - [8:6] */2262#define WM8996_AIF2RX_CHAN0_SLOTS_WIDTH 3 /* AIF2RX_CHAN0_SLOTS - [8:6] */2263#define WM8996_AIF2RX_CHAN0_START_SLOT_MASK 0x003F /* AIF2RX_CHAN0_START_SLOT - [5:0] */2264#define WM8996_AIF2RX_CHAN0_START_SLOT_SHIFT 0 /* AIF2RX_CHAN0_START_SLOT - [5:0] */2265#define WM8996_AIF2RX_CHAN0_START_SLOT_WIDTH 6 /* AIF2RX_CHAN0_START_SLOT - [5:0] */2266 2267/*2268 * R812 (0x32C) - AIF2RX Channel 1 Configuration2269 */2270#define WM8996_AIF2RX_CHAN1_DAT_INV 0x8000 /* AIF2RX_CHAN1_DAT_INV */2271#define WM8996_AIF2RX_CHAN1_DAT_INV_MASK 0x8000 /* AIF2RX_CHAN1_DAT_INV */2272#define WM8996_AIF2RX_CHAN1_DAT_INV_SHIFT 15 /* AIF2RX_CHAN1_DAT_INV */2273#define WM8996_AIF2RX_CHAN1_DAT_INV_WIDTH 1 /* AIF2RX_CHAN1_DAT_INV */2274#define WM8996_AIF2RX_CHAN1_SPACING_MASK 0x7E00 /* AIF2RX_CHAN1_SPACING - [14:9] */2275#define WM8996_AIF2RX_CHAN1_SPACING_SHIFT 9 /* AIF2RX_CHAN1_SPACING - [14:9] */2276#define WM8996_AIF2RX_CHAN1_SPACING_WIDTH 6 /* AIF2RX_CHAN1_SPACING - [14:9] */2277#define WM8996_AIF2RX_CHAN1_SLOTS_MASK 0x01C0 /* AIF2RX_CHAN1_SLOTS - [8:6] */2278#define WM8996_AIF2RX_CHAN1_SLOTS_SHIFT 6 /* AIF2RX_CHAN1_SLOTS - [8:6] */2279#define WM8996_AIF2RX_CHAN1_SLOTS_WIDTH 3 /* AIF2RX_CHAN1_SLOTS - [8:6] */2280#define WM8996_AIF2RX_CHAN1_START_SLOT_MASK 0x003F /* AIF2RX_CHAN1_START_SLOT - [5:0] */2281#define WM8996_AIF2RX_CHAN1_START_SLOT_SHIFT 0 /* AIF2RX_CHAN1_START_SLOT - [5:0] */2282#define WM8996_AIF2RX_CHAN1_START_SLOT_WIDTH 6 /* AIF2RX_CHAN1_START_SLOT - [5:0] */2283 2284/*2285 * R813 (0x32D) - AIF2RX Mono Configuration2286 */2287#define WM8996_AIF2RX_CHAN0_MONO_MODE 0x0001 /* AIF2RX_CHAN0_MONO_MODE */2288#define WM8996_AIF2RX_CHAN0_MONO_MODE_MASK 0x0001 /* AIF2RX_CHAN0_MONO_MODE */2289#define WM8996_AIF2RX_CHAN0_MONO_MODE_SHIFT 0 /* AIF2RX_CHAN0_MONO_MODE */2290#define WM8996_AIF2RX_CHAN0_MONO_MODE_WIDTH 1 /* AIF2RX_CHAN0_MONO_MODE */2291 2292/*2293 * R815 (0x32F) - AIF2TX Test2294 */2295#define WM8996_AIF2TX_DITHER_ENA 0x0001 /* AIF2TX_DITHER_ENA */2296#define WM8996_AIF2TX_DITHER_ENA_MASK 0x0001 /* AIF2TX_DITHER_ENA */2297#define WM8996_AIF2TX_DITHER_ENA_SHIFT 0 /* AIF2TX_DITHER_ENA */2298#define WM8996_AIF2TX_DITHER_ENA_WIDTH 1 /* AIF2TX_DITHER_ENA */2299 2300/*2301 * R1024 (0x400) - DSP1 TX Left Volume2302 */2303#define WM8996_DSP1TX_VU 0x0100 /* DSP1TX_VU */2304#define WM8996_DSP1TX_VU_MASK 0x0100 /* DSP1TX_VU */2305#define WM8996_DSP1TX_VU_SHIFT 8 /* DSP1TX_VU */2306#define WM8996_DSP1TX_VU_WIDTH 1 /* DSP1TX_VU */2307#define WM8996_DSP1TXL_VOL_MASK 0x00FF /* DSP1TXL_VOL - [7:0] */2308#define WM8996_DSP1TXL_VOL_SHIFT 0 /* DSP1TXL_VOL - [7:0] */2309#define WM8996_DSP1TXL_VOL_WIDTH 8 /* DSP1TXL_VOL - [7:0] */2310 2311/*2312 * R1025 (0x401) - DSP1 TX Right Volume2313 */2314#define WM8996_DSP1TX_VU 0x0100 /* DSP1TX_VU */2315#define WM8996_DSP1TX_VU_MASK 0x0100 /* DSP1TX_VU */2316#define WM8996_DSP1TX_VU_SHIFT 8 /* DSP1TX_VU */2317#define WM8996_DSP1TX_VU_WIDTH 1 /* DSP1TX_VU */2318#define WM8996_DSP1TXR_VOL_MASK 0x00FF /* DSP1TXR_VOL - [7:0] */2319#define WM8996_DSP1TXR_VOL_SHIFT 0 /* DSP1TXR_VOL - [7:0] */2320#define WM8996_DSP1TXR_VOL_WIDTH 8 /* DSP1TXR_VOL - [7:0] */2321 2322/*2323 * R1026 (0x402) - DSP1 RX Left Volume2324 */2325#define WM8996_DSP1RX_VU 0x0100 /* DSP1RX_VU */2326#define WM8996_DSP1RX_VU_MASK 0x0100 /* DSP1RX_VU */2327#define WM8996_DSP1RX_VU_SHIFT 8 /* DSP1RX_VU */2328#define WM8996_DSP1RX_VU_WIDTH 1 /* DSP1RX_VU */2329#define WM8996_DSP1RXL_VOL_MASK 0x00FF /* DSP1RXL_VOL - [7:0] */2330#define WM8996_DSP1RXL_VOL_SHIFT 0 /* DSP1RXL_VOL - [7:0] */2331#define WM8996_DSP1RXL_VOL_WIDTH 8 /* DSP1RXL_VOL - [7:0] */2332 2333/*2334 * R1027 (0x403) - DSP1 RX Right Volume2335 */2336#define WM8996_DSP1RX_VU 0x0100 /* DSP1RX_VU */2337#define WM8996_DSP1RX_VU_MASK 0x0100 /* DSP1RX_VU */2338#define WM8996_DSP1RX_VU_SHIFT 8 /* DSP1RX_VU */2339#define WM8996_DSP1RX_VU_WIDTH 1 /* DSP1RX_VU */2340#define WM8996_DSP1RXR_VOL_MASK 0x00FF /* DSP1RXR_VOL - [7:0] */2341#define WM8996_DSP1RXR_VOL_SHIFT 0 /* DSP1RXR_VOL - [7:0] */2342#define WM8996_DSP1RXR_VOL_WIDTH 8 /* DSP1RXR_VOL - [7:0] */2343 2344/*2345 * R1040 (0x410) - DSP1 TX Filters2346 */2347#define WM8996_DSP1TX_NF 0x2000 /* DSP1TX_NF */2348#define WM8996_DSP1TX_NF_MASK 0x2000 /* DSP1TX_NF */2349#define WM8996_DSP1TX_NF_SHIFT 13 /* DSP1TX_NF */2350#define WM8996_DSP1TX_NF_WIDTH 1 /* DSP1TX_NF */2351#define WM8996_DSP1TXL_HPF 0x1000 /* DSP1TXL_HPF */2352#define WM8996_DSP1TXL_HPF_MASK 0x1000 /* DSP1TXL_HPF */2353#define WM8996_DSP1TXL_HPF_SHIFT 12 /* DSP1TXL_HPF */2354#define WM8996_DSP1TXL_HPF_WIDTH 1 /* DSP1TXL_HPF */2355#define WM8996_DSP1TXR_HPF 0x0800 /* DSP1TXR_HPF */2356#define WM8996_DSP1TXR_HPF_MASK 0x0800 /* DSP1TXR_HPF */2357#define WM8996_DSP1TXR_HPF_SHIFT 11 /* DSP1TXR_HPF */2358#define WM8996_DSP1TXR_HPF_WIDTH 1 /* DSP1TXR_HPF */2359#define WM8996_DSP1TX_HPF_MODE_MASK 0x0018 /* DSP1TX_HPF_MODE - [4:3] */2360#define WM8996_DSP1TX_HPF_MODE_SHIFT 3 /* DSP1TX_HPF_MODE - [4:3] */2361#define WM8996_DSP1TX_HPF_MODE_WIDTH 2 /* DSP1TX_HPF_MODE - [4:3] */2362#define WM8996_DSP1TX_HPF_CUT_MASK 0x0007 /* DSP1TX_HPF_CUT - [2:0] */2363#define WM8996_DSP1TX_HPF_CUT_SHIFT 0 /* DSP1TX_HPF_CUT - [2:0] */2364#define WM8996_DSP1TX_HPF_CUT_WIDTH 3 /* DSP1TX_HPF_CUT - [2:0] */2365 2366/*2367 * R1056 (0x420) - DSP1 RX Filters (1)2368 */2369#define WM8996_DSP1RX_MUTE 0x0200 /* DSP1RX_MUTE */2370#define WM8996_DSP1RX_MUTE_MASK 0x0200 /* DSP1RX_MUTE */2371#define WM8996_DSP1RX_MUTE_SHIFT 9 /* DSP1RX_MUTE */2372#define WM8996_DSP1RX_MUTE_WIDTH 1 /* DSP1RX_MUTE */2373#define WM8996_DSP1RX_MONO 0x0080 /* DSP1RX_MONO */2374#define WM8996_DSP1RX_MONO_MASK 0x0080 /* DSP1RX_MONO */2375#define WM8996_DSP1RX_MONO_SHIFT 7 /* DSP1RX_MONO */2376#define WM8996_DSP1RX_MONO_WIDTH 1 /* DSP1RX_MONO */2377#define WM8996_DSP1RX_MUTERATE 0x0020 /* DSP1RX_MUTERATE */2378#define WM8996_DSP1RX_MUTERATE_MASK 0x0020 /* DSP1RX_MUTERATE */2379#define WM8996_DSP1RX_MUTERATE_SHIFT 5 /* DSP1RX_MUTERATE */2380#define WM8996_DSP1RX_MUTERATE_WIDTH 1 /* DSP1RX_MUTERATE */2381#define WM8996_DSP1RX_UNMUTE_RAMP 0x0010 /* DSP1RX_UNMUTE_RAMP */2382#define WM8996_DSP1RX_UNMUTE_RAMP_MASK 0x0010 /* DSP1RX_UNMUTE_RAMP */2383#define WM8996_DSP1RX_UNMUTE_RAMP_SHIFT 4 /* DSP1RX_UNMUTE_RAMP */2384#define WM8996_DSP1RX_UNMUTE_RAMP_WIDTH 1 /* DSP1RX_UNMUTE_RAMP */2385 2386/*2387 * R1057 (0x421) - DSP1 RX Filters (2)2388 */2389#define WM8996_DSP1RX_3D_GAIN_MASK 0x3E00 /* DSP1RX_3D_GAIN - [13:9] */2390#define WM8996_DSP1RX_3D_GAIN_SHIFT 9 /* DSP1RX_3D_GAIN - [13:9] */2391#define WM8996_DSP1RX_3D_GAIN_WIDTH 5 /* DSP1RX_3D_GAIN - [13:9] */2392#define WM8996_DSP1RX_3D_ENA 0x0100 /* DSP1RX_3D_ENA */2393#define WM8996_DSP1RX_3D_ENA_MASK 0x0100 /* DSP1RX_3D_ENA */2394#define WM8996_DSP1RX_3D_ENA_SHIFT 8 /* DSP1RX_3D_ENA */2395#define WM8996_DSP1RX_3D_ENA_WIDTH 1 /* DSP1RX_3D_ENA */2396 2397/*2398 * R1088 (0x440) - DSP1 DRC (1)2399 */2400#define WM8996_DSP1DRC_SIG_DET_RMS_MASK 0xF800 /* DSP1DRC_SIG_DET_RMS - [15:11] */2401#define WM8996_DSP1DRC_SIG_DET_RMS_SHIFT 11 /* DSP1DRC_SIG_DET_RMS - [15:11] */2402#define WM8996_DSP1DRC_SIG_DET_RMS_WIDTH 5 /* DSP1DRC_SIG_DET_RMS - [15:11] */2403#define WM8996_DSP1DRC_SIG_DET_PK_MASK 0x0600 /* DSP1DRC_SIG_DET_PK - [10:9] */2404#define WM8996_DSP1DRC_SIG_DET_PK_SHIFT 9 /* DSP1DRC_SIG_DET_PK - [10:9] */2405#define WM8996_DSP1DRC_SIG_DET_PK_WIDTH 2 /* DSP1DRC_SIG_DET_PK - [10:9] */2406#define WM8996_DSP1DRC_NG_ENA 0x0100 /* DSP1DRC_NG_ENA */2407#define WM8996_DSP1DRC_NG_ENA_MASK 0x0100 /* DSP1DRC_NG_ENA */2408#define WM8996_DSP1DRC_NG_ENA_SHIFT 8 /* DSP1DRC_NG_ENA */2409#define WM8996_DSP1DRC_NG_ENA_WIDTH 1 /* DSP1DRC_NG_ENA */2410#define WM8996_DSP1DRC_SIG_DET_MODE 0x0080 /* DSP1DRC_SIG_DET_MODE */2411#define WM8996_DSP1DRC_SIG_DET_MODE_MASK 0x0080 /* DSP1DRC_SIG_DET_MODE */2412#define WM8996_DSP1DRC_SIG_DET_MODE_SHIFT 7 /* DSP1DRC_SIG_DET_MODE */2413#define WM8996_DSP1DRC_SIG_DET_MODE_WIDTH 1 /* DSP1DRC_SIG_DET_MODE */2414#define WM8996_DSP1DRC_SIG_DET 0x0040 /* DSP1DRC_SIG_DET */2415#define WM8996_DSP1DRC_SIG_DET_MASK 0x0040 /* DSP1DRC_SIG_DET */2416#define WM8996_DSP1DRC_SIG_DET_SHIFT 6 /* DSP1DRC_SIG_DET */2417#define WM8996_DSP1DRC_SIG_DET_WIDTH 1 /* DSP1DRC_SIG_DET */2418#define WM8996_DSP1DRC_KNEE2_OP_ENA 0x0020 /* DSP1DRC_KNEE2_OP_ENA */2419#define WM8996_DSP1DRC_KNEE2_OP_ENA_MASK 0x0020 /* DSP1DRC_KNEE2_OP_ENA */2420#define WM8996_DSP1DRC_KNEE2_OP_ENA_SHIFT 5 /* DSP1DRC_KNEE2_OP_ENA */2421#define WM8996_DSP1DRC_KNEE2_OP_ENA_WIDTH 1 /* DSP1DRC_KNEE2_OP_ENA */2422#define WM8996_DSP1DRC_QR 0x0010 /* DSP1DRC_QR */2423#define WM8996_DSP1DRC_QR_MASK 0x0010 /* DSP1DRC_QR */2424#define WM8996_DSP1DRC_QR_SHIFT 4 /* DSP1DRC_QR */2425#define WM8996_DSP1DRC_QR_WIDTH 1 /* DSP1DRC_QR */2426#define WM8996_DSP1DRC_ANTICLIP 0x0008 /* DSP1DRC_ANTICLIP */2427#define WM8996_DSP1DRC_ANTICLIP_MASK 0x0008 /* DSP1DRC_ANTICLIP */2428#define WM8996_DSP1DRC_ANTICLIP_SHIFT 3 /* DSP1DRC_ANTICLIP */2429#define WM8996_DSP1DRC_ANTICLIP_WIDTH 1 /* DSP1DRC_ANTICLIP */2430#define WM8996_DSP1RX_DRC_ENA 0x0004 /* DSP1RX_DRC_ENA */2431#define WM8996_DSP1RX_DRC_ENA_MASK 0x0004 /* DSP1RX_DRC_ENA */2432#define WM8996_DSP1RX_DRC_ENA_SHIFT 2 /* DSP1RX_DRC_ENA */2433#define WM8996_DSP1RX_DRC_ENA_WIDTH 1 /* DSP1RX_DRC_ENA */2434#define WM8996_DSP1TXL_DRC_ENA 0x0002 /* DSP1TXL_DRC_ENA */2435#define WM8996_DSP1TXL_DRC_ENA_MASK 0x0002 /* DSP1TXL_DRC_ENA */2436#define WM8996_DSP1TXL_DRC_ENA_SHIFT 1 /* DSP1TXL_DRC_ENA */2437#define WM8996_DSP1TXL_DRC_ENA_WIDTH 1 /* DSP1TXL_DRC_ENA */2438#define WM8996_DSP1TXR_DRC_ENA 0x0001 /* DSP1TXR_DRC_ENA */2439#define WM8996_DSP1TXR_DRC_ENA_MASK 0x0001 /* DSP1TXR_DRC_ENA */2440#define WM8996_DSP1TXR_DRC_ENA_SHIFT 0 /* DSP1TXR_DRC_ENA */2441#define WM8996_DSP1TXR_DRC_ENA_WIDTH 1 /* DSP1TXR_DRC_ENA */2442 2443/*2444 * R1089 (0x441) - DSP1 DRC (2)2445 */2446#define WM8996_DSP1DRC_ATK_MASK 0x1E00 /* DSP1DRC_ATK - [12:9] */2447#define WM8996_DSP1DRC_ATK_SHIFT 9 /* DSP1DRC_ATK - [12:9] */2448#define WM8996_DSP1DRC_ATK_WIDTH 4 /* DSP1DRC_ATK - [12:9] */2449#define WM8996_DSP1DRC_DCY_MASK 0x01E0 /* DSP1DRC_DCY - [8:5] */2450#define WM8996_DSP1DRC_DCY_SHIFT 5 /* DSP1DRC_DCY - [8:5] */2451#define WM8996_DSP1DRC_DCY_WIDTH 4 /* DSP1DRC_DCY - [8:5] */2452#define WM8996_DSP1DRC_MINGAIN_MASK 0x001C /* DSP1DRC_MINGAIN - [4:2] */2453#define WM8996_DSP1DRC_MINGAIN_SHIFT 2 /* DSP1DRC_MINGAIN - [4:2] */2454#define WM8996_DSP1DRC_MINGAIN_WIDTH 3 /* DSP1DRC_MINGAIN - [4:2] */2455#define WM8996_DSP1DRC_MAXGAIN_MASK 0x0003 /* DSP1DRC_MAXGAIN - [1:0] */2456#define WM8996_DSP1DRC_MAXGAIN_SHIFT 0 /* DSP1DRC_MAXGAIN - [1:0] */2457#define WM8996_DSP1DRC_MAXGAIN_WIDTH 2 /* DSP1DRC_MAXGAIN - [1:0] */2458 2459/*2460 * R1090 (0x442) - DSP1 DRC (3)2461 */2462#define WM8996_DSP1DRC_NG_MINGAIN_MASK 0xF000 /* DSP1DRC_NG_MINGAIN - [15:12] */2463#define WM8996_DSP1DRC_NG_MINGAIN_SHIFT 12 /* DSP1DRC_NG_MINGAIN - [15:12] */2464#define WM8996_DSP1DRC_NG_MINGAIN_WIDTH 4 /* DSP1DRC_NG_MINGAIN - [15:12] */2465#define WM8996_DSP1DRC_NG_EXP_MASK 0x0C00 /* DSP1DRC_NG_EXP - [11:10] */2466#define WM8996_DSP1DRC_NG_EXP_SHIFT 10 /* DSP1DRC_NG_EXP - [11:10] */2467#define WM8996_DSP1DRC_NG_EXP_WIDTH 2 /* DSP1DRC_NG_EXP - [11:10] */2468#define WM8996_DSP1DRC_QR_THR_MASK 0x0300 /* DSP1DRC_QR_THR - [9:8] */2469#define WM8996_DSP1DRC_QR_THR_SHIFT 8 /* DSP1DRC_QR_THR - [9:8] */2470#define WM8996_DSP1DRC_QR_THR_WIDTH 2 /* DSP1DRC_QR_THR - [9:8] */2471#define WM8996_DSP1DRC_QR_DCY_MASK 0x00C0 /* DSP1DRC_QR_DCY - [7:6] */2472#define WM8996_DSP1DRC_QR_DCY_SHIFT 6 /* DSP1DRC_QR_DCY - [7:6] */2473#define WM8996_DSP1DRC_QR_DCY_WIDTH 2 /* DSP1DRC_QR_DCY - [7:6] */2474#define WM8996_DSP1DRC_HI_COMP_MASK 0x0038 /* DSP1DRC_HI_COMP - [5:3] */2475#define WM8996_DSP1DRC_HI_COMP_SHIFT 3 /* DSP1DRC_HI_COMP - [5:3] */2476#define WM8996_DSP1DRC_HI_COMP_WIDTH 3 /* DSP1DRC_HI_COMP - [5:3] */2477#define WM8996_DSP1DRC_LO_COMP_MASK 0x0007 /* DSP1DRC_LO_COMP - [2:0] */2478#define WM8996_DSP1DRC_LO_COMP_SHIFT 0 /* DSP1DRC_LO_COMP - [2:0] */2479#define WM8996_DSP1DRC_LO_COMP_WIDTH 3 /* DSP1DRC_LO_COMP - [2:0] */2480 2481/*2482 * R1091 (0x443) - DSP1 DRC (4)2483 */2484#define WM8996_DSP1DRC_KNEE_IP_MASK 0x07E0 /* DSP1DRC_KNEE_IP - [10:5] */2485#define WM8996_DSP1DRC_KNEE_IP_SHIFT 5 /* DSP1DRC_KNEE_IP - [10:5] */2486#define WM8996_DSP1DRC_KNEE_IP_WIDTH 6 /* DSP1DRC_KNEE_IP - [10:5] */2487#define WM8996_DSP1DRC_KNEE_OP_MASK 0x001F /* DSP1DRC_KNEE_OP - [4:0] */2488#define WM8996_DSP1DRC_KNEE_OP_SHIFT 0 /* DSP1DRC_KNEE_OP - [4:0] */2489#define WM8996_DSP1DRC_KNEE_OP_WIDTH 5 /* DSP1DRC_KNEE_OP - [4:0] */2490 2491/*2492 * R1092 (0x444) - DSP1 DRC (5)2493 */2494#define WM8996_DSP1DRC_KNEE2_IP_MASK 0x03E0 /* DSP1DRC_KNEE2_IP - [9:5] */2495#define WM8996_DSP1DRC_KNEE2_IP_SHIFT 5 /* DSP1DRC_KNEE2_IP - [9:5] */2496#define WM8996_DSP1DRC_KNEE2_IP_WIDTH 5 /* DSP1DRC_KNEE2_IP - [9:5] */2497#define WM8996_DSP1DRC_KNEE2_OP_MASK 0x001F /* DSP1DRC_KNEE2_OP - [4:0] */2498#define WM8996_DSP1DRC_KNEE2_OP_SHIFT 0 /* DSP1DRC_KNEE2_OP - [4:0] */2499#define WM8996_DSP1DRC_KNEE2_OP_WIDTH 5 /* DSP1DRC_KNEE2_OP - [4:0] */2500 2501/*2502 * R1152 (0x480) - DSP1 RX EQ Gains (1)2503 */2504#define WM8996_DSP1RX_EQ_B1_GAIN_MASK 0xF800 /* DSP1RX_EQ_B1_GAIN - [15:11] */2505#define WM8996_DSP1RX_EQ_B1_GAIN_SHIFT 11 /* DSP1RX_EQ_B1_GAIN - [15:11] */2506#define WM8996_DSP1RX_EQ_B1_GAIN_WIDTH 5 /* DSP1RX_EQ_B1_GAIN - [15:11] */2507#define WM8996_DSP1RX_EQ_B2_GAIN_MASK 0x07C0 /* DSP1RX_EQ_B2_GAIN - [10:6] */2508#define WM8996_DSP1RX_EQ_B2_GAIN_SHIFT 6 /* DSP1RX_EQ_B2_GAIN - [10:6] */2509#define WM8996_DSP1RX_EQ_B2_GAIN_WIDTH 5 /* DSP1RX_EQ_B2_GAIN - [10:6] */2510#define WM8996_DSP1RX_EQ_B3_GAIN_MASK 0x003E /* DSP1RX_EQ_B3_GAIN - [5:1] */2511#define WM8996_DSP1RX_EQ_B3_GAIN_SHIFT 1 /* DSP1RX_EQ_B3_GAIN - [5:1] */2512#define WM8996_DSP1RX_EQ_B3_GAIN_WIDTH 5 /* DSP1RX_EQ_B3_GAIN - [5:1] */2513#define WM8996_DSP1RX_EQ_ENA 0x0001 /* DSP1RX_EQ_ENA */2514#define WM8996_DSP1RX_EQ_ENA_MASK 0x0001 /* DSP1RX_EQ_ENA */2515#define WM8996_DSP1RX_EQ_ENA_SHIFT 0 /* DSP1RX_EQ_ENA */2516#define WM8996_DSP1RX_EQ_ENA_WIDTH 1 /* DSP1RX_EQ_ENA */2517 2518/*2519 * R1153 (0x481) - DSP1 RX EQ Gains (2)2520 */2521#define WM8996_DSP1RX_EQ_B4_GAIN_MASK 0xF800 /* DSP1RX_EQ_B4_GAIN - [15:11] */2522#define WM8996_DSP1RX_EQ_B4_GAIN_SHIFT 11 /* DSP1RX_EQ_B4_GAIN - [15:11] */2523#define WM8996_DSP1RX_EQ_B4_GAIN_WIDTH 5 /* DSP1RX_EQ_B4_GAIN - [15:11] */2524#define WM8996_DSP1RX_EQ_B5_GAIN_MASK 0x07C0 /* DSP1RX_EQ_B5_GAIN - [10:6] */2525#define WM8996_DSP1RX_EQ_B5_GAIN_SHIFT 6 /* DSP1RX_EQ_B5_GAIN - [10:6] */2526#define WM8996_DSP1RX_EQ_B5_GAIN_WIDTH 5 /* DSP1RX_EQ_B5_GAIN - [10:6] */2527 2528/*2529 * R1154 (0x482) - DSP1 RX EQ Band 1 A2530 */2531#define WM8996_DSP1RX_EQ_B1_A_MASK 0xFFFF /* DSP1RX_EQ_B1_A - [15:0] */2532#define WM8996_DSP1RX_EQ_B1_A_SHIFT 0 /* DSP1RX_EQ_B1_A - [15:0] */2533#define WM8996_DSP1RX_EQ_B1_A_WIDTH 16 /* DSP1RX_EQ_B1_A - [15:0] */2534 2535/*2536 * R1155 (0x483) - DSP1 RX EQ Band 1 B2537 */2538#define WM8996_DSP1RX_EQ_B1_B_MASK 0xFFFF /* DSP1RX_EQ_B1_B - [15:0] */2539#define WM8996_DSP1RX_EQ_B1_B_SHIFT 0 /* DSP1RX_EQ_B1_B - [15:0] */2540#define WM8996_DSP1RX_EQ_B1_B_WIDTH 16 /* DSP1RX_EQ_B1_B - [15:0] */2541 2542/*2543 * R1156 (0x484) - DSP1 RX EQ Band 1 PG2544 */2545#define WM8996_DSP1RX_EQ_B1_PG_MASK 0xFFFF /* DSP1RX_EQ_B1_PG - [15:0] */2546#define WM8996_DSP1RX_EQ_B1_PG_SHIFT 0 /* DSP1RX_EQ_B1_PG - [15:0] */2547#define WM8996_DSP1RX_EQ_B1_PG_WIDTH 16 /* DSP1RX_EQ_B1_PG - [15:0] */2548 2549/*2550 * R1157 (0x485) - DSP1 RX EQ Band 2 A2551 */2552#define WM8996_DSP1RX_EQ_B2_A_MASK 0xFFFF /* DSP1RX_EQ_B2_A - [15:0] */2553#define WM8996_DSP1RX_EQ_B2_A_SHIFT 0 /* DSP1RX_EQ_B2_A - [15:0] */2554#define WM8996_DSP1RX_EQ_B2_A_WIDTH 16 /* DSP1RX_EQ_B2_A - [15:0] */2555 2556/*2557 * R1158 (0x486) - DSP1 RX EQ Band 2 B2558 */2559#define WM8996_DSP1RX_EQ_B2_B_MASK 0xFFFF /* DSP1RX_EQ_B2_B - [15:0] */2560#define WM8996_DSP1RX_EQ_B2_B_SHIFT 0 /* DSP1RX_EQ_B2_B - [15:0] */2561#define WM8996_DSP1RX_EQ_B2_B_WIDTH 16 /* DSP1RX_EQ_B2_B - [15:0] */2562 2563/*2564 * R1159 (0x487) - DSP1 RX EQ Band 2 C2565 */2566#define WM8996_DSP1RX_EQ_B2_C_MASK 0xFFFF /* DSP1RX_EQ_B2_C - [15:0] */2567#define WM8996_DSP1RX_EQ_B2_C_SHIFT 0 /* DSP1RX_EQ_B2_C - [15:0] */2568#define WM8996_DSP1RX_EQ_B2_C_WIDTH 16 /* DSP1RX_EQ_B2_C - [15:0] */2569 2570/*2571 * R1160 (0x488) - DSP1 RX EQ Band 2 PG2572 */2573#define WM8996_DSP1RX_EQ_B2_PG_MASK 0xFFFF /* DSP1RX_EQ_B2_PG - [15:0] */2574#define WM8996_DSP1RX_EQ_B2_PG_SHIFT 0 /* DSP1RX_EQ_B2_PG - [15:0] */2575#define WM8996_DSP1RX_EQ_B2_PG_WIDTH 16 /* DSP1RX_EQ_B2_PG - [15:0] */2576 2577/*2578 * R1161 (0x489) - DSP1 RX EQ Band 3 A2579 */2580#define WM8996_DSP1RX_EQ_B3_A_MASK 0xFFFF /* DSP1RX_EQ_B3_A - [15:0] */2581#define WM8996_DSP1RX_EQ_B3_A_SHIFT 0 /* DSP1RX_EQ_B3_A - [15:0] */2582#define WM8996_DSP1RX_EQ_B3_A_WIDTH 16 /* DSP1RX_EQ_B3_A - [15:0] */2583 2584/*2585 * R1162 (0x48A) - DSP1 RX EQ Band 3 B2586 */2587#define WM8996_DSP1RX_EQ_B3_B_MASK 0xFFFF /* DSP1RX_EQ_B3_B - [15:0] */2588#define WM8996_DSP1RX_EQ_B3_B_SHIFT 0 /* DSP1RX_EQ_B3_B - [15:0] */2589#define WM8996_DSP1RX_EQ_B3_B_WIDTH 16 /* DSP1RX_EQ_B3_B - [15:0] */2590 2591/*2592 * R1163 (0x48B) - DSP1 RX EQ Band 3 C2593 */2594#define WM8996_DSP1RX_EQ_B3_C_MASK 0xFFFF /* DSP1RX_EQ_B3_C - [15:0] */2595#define WM8996_DSP1RX_EQ_B3_C_SHIFT 0 /* DSP1RX_EQ_B3_C - [15:0] */2596#define WM8996_DSP1RX_EQ_B3_C_WIDTH 16 /* DSP1RX_EQ_B3_C - [15:0] */2597 2598/*2599 * R1164 (0x48C) - DSP1 RX EQ Band 3 PG2600 */2601#define WM8996_DSP1RX_EQ_B3_PG_MASK 0xFFFF /* DSP1RX_EQ_B3_PG - [15:0] */2602#define WM8996_DSP1RX_EQ_B3_PG_SHIFT 0 /* DSP1RX_EQ_B3_PG - [15:0] */2603#define WM8996_DSP1RX_EQ_B3_PG_WIDTH 16 /* DSP1RX_EQ_B3_PG - [15:0] */2604 2605/*2606 * R1165 (0x48D) - DSP1 RX EQ Band 4 A2607 */2608#define WM8996_DSP1RX_EQ_B4_A_MASK 0xFFFF /* DSP1RX_EQ_B4_A - [15:0] */2609#define WM8996_DSP1RX_EQ_B4_A_SHIFT 0 /* DSP1RX_EQ_B4_A - [15:0] */2610#define WM8996_DSP1RX_EQ_B4_A_WIDTH 16 /* DSP1RX_EQ_B4_A - [15:0] */2611 2612/*2613 * R1166 (0x48E) - DSP1 RX EQ Band 4 B2614 */2615#define WM8996_DSP1RX_EQ_B4_B_MASK 0xFFFF /* DSP1RX_EQ_B4_B - [15:0] */2616#define WM8996_DSP1RX_EQ_B4_B_SHIFT 0 /* DSP1RX_EQ_B4_B - [15:0] */2617#define WM8996_DSP1RX_EQ_B4_B_WIDTH 16 /* DSP1RX_EQ_B4_B - [15:0] */2618 2619/*2620 * R1167 (0x48F) - DSP1 RX EQ Band 4 C2621 */2622#define WM8996_DSP1RX_EQ_B4_C_MASK 0xFFFF /* DSP1RX_EQ_B4_C - [15:0] */2623#define WM8996_DSP1RX_EQ_B4_C_SHIFT 0 /* DSP1RX_EQ_B4_C - [15:0] */2624#define WM8996_DSP1RX_EQ_B4_C_WIDTH 16 /* DSP1RX_EQ_B4_C - [15:0] */2625 2626/*2627 * R1168 (0x490) - DSP1 RX EQ Band 4 PG2628 */2629#define WM8996_DSP1RX_EQ_B4_PG_MASK 0xFFFF /* DSP1RX_EQ_B4_PG - [15:0] */2630#define WM8996_DSP1RX_EQ_B4_PG_SHIFT 0 /* DSP1RX_EQ_B4_PG - [15:0] */2631#define WM8996_DSP1RX_EQ_B4_PG_WIDTH 16 /* DSP1RX_EQ_B4_PG - [15:0] */2632 2633/*2634 * R1169 (0x491) - DSP1 RX EQ Band 5 A2635 */2636#define WM8996_DSP1RX_EQ_B5_A_MASK 0xFFFF /* DSP1RX_EQ_B5_A - [15:0] */2637#define WM8996_DSP1RX_EQ_B5_A_SHIFT 0 /* DSP1RX_EQ_B5_A - [15:0] */2638#define WM8996_DSP1RX_EQ_B5_A_WIDTH 16 /* DSP1RX_EQ_B5_A - [15:0] */2639 2640/*2641 * R1170 (0x492) - DSP1 RX EQ Band 5 B2642 */2643#define WM8996_DSP1RX_EQ_B5_B_MASK 0xFFFF /* DSP1RX_EQ_B5_B - [15:0] */2644#define WM8996_DSP1RX_EQ_B5_B_SHIFT 0 /* DSP1RX_EQ_B5_B - [15:0] */2645#define WM8996_DSP1RX_EQ_B5_B_WIDTH 16 /* DSP1RX_EQ_B5_B - [15:0] */2646 2647/*2648 * R1171 (0x493) - DSP1 RX EQ Band 5 PG2649 */2650#define WM8996_DSP1RX_EQ_B5_PG_MASK 0xFFFF /* DSP1RX_EQ_B5_PG - [15:0] */2651#define WM8996_DSP1RX_EQ_B5_PG_SHIFT 0 /* DSP1RX_EQ_B5_PG - [15:0] */2652#define WM8996_DSP1RX_EQ_B5_PG_WIDTH 16 /* DSP1RX_EQ_B5_PG - [15:0] */2653 2654/*2655 * R1280 (0x500) - DSP2 TX Left Volume2656 */2657#define WM8996_DSP2TX_VU 0x0100 /* DSP2TX_VU */2658#define WM8996_DSP2TX_VU_MASK 0x0100 /* DSP2TX_VU */2659#define WM8996_DSP2TX_VU_SHIFT 8 /* DSP2TX_VU */2660#define WM8996_DSP2TX_VU_WIDTH 1 /* DSP2TX_VU */2661#define WM8996_DSP2TXL_VOL_MASK 0x00FF /* DSP2TXL_VOL - [7:0] */2662#define WM8996_DSP2TXL_VOL_SHIFT 0 /* DSP2TXL_VOL - [7:0] */2663#define WM8996_DSP2TXL_VOL_WIDTH 8 /* DSP2TXL_VOL - [7:0] */2664 2665/*2666 * R1281 (0x501) - DSP2 TX Right Volume2667 */2668#define WM8996_DSP2TX_VU 0x0100 /* DSP2TX_VU */2669#define WM8996_DSP2TX_VU_MASK 0x0100 /* DSP2TX_VU */2670#define WM8996_DSP2TX_VU_SHIFT 8 /* DSP2TX_VU */2671#define WM8996_DSP2TX_VU_WIDTH 1 /* DSP2TX_VU */2672#define WM8996_DSP2TXR_VOL_MASK 0x00FF /* DSP2TXR_VOL - [7:0] */2673#define WM8996_DSP2TXR_VOL_SHIFT 0 /* DSP2TXR_VOL - [7:0] */2674#define WM8996_DSP2TXR_VOL_WIDTH 8 /* DSP2TXR_VOL - [7:0] */2675 2676/*2677 * R1282 (0x502) - DSP2 RX Left Volume2678 */2679#define WM8996_DSP2RX_VU 0x0100 /* DSP2RX_VU */2680#define WM8996_DSP2RX_VU_MASK 0x0100 /* DSP2RX_VU */2681#define WM8996_DSP2RX_VU_SHIFT 8 /* DSP2RX_VU */2682#define WM8996_DSP2RX_VU_WIDTH 1 /* DSP2RX_VU */2683#define WM8996_DSP2RXL_VOL_MASK 0x00FF /* DSP2RXL_VOL - [7:0] */2684#define WM8996_DSP2RXL_VOL_SHIFT 0 /* DSP2RXL_VOL - [7:0] */2685#define WM8996_DSP2RXL_VOL_WIDTH 8 /* DSP2RXL_VOL - [7:0] */2686 2687/*2688 * R1283 (0x503) - DSP2 RX Right Volume2689 */2690#define WM8996_DSP2RX_VU 0x0100 /* DSP2RX_VU */2691#define WM8996_DSP2RX_VU_MASK 0x0100 /* DSP2RX_VU */2692#define WM8996_DSP2RX_VU_SHIFT 8 /* DSP2RX_VU */2693#define WM8996_DSP2RX_VU_WIDTH 1 /* DSP2RX_VU */2694#define WM8996_DSP2RXR_VOL_MASK 0x00FF /* DSP2RXR_VOL - [7:0] */2695#define WM8996_DSP2RXR_VOL_SHIFT 0 /* DSP2RXR_VOL - [7:0] */2696#define WM8996_DSP2RXR_VOL_WIDTH 8 /* DSP2RXR_VOL - [7:0] */2697 2698/*2699 * R1296 (0x510) - DSP2 TX Filters2700 */2701#define WM8996_DSP2TX_NF 0x2000 /* DSP2TX_NF */2702#define WM8996_DSP2TX_NF_MASK 0x2000 /* DSP2TX_NF */2703#define WM8996_DSP2TX_NF_SHIFT 13 /* DSP2TX_NF */2704#define WM8996_DSP2TX_NF_WIDTH 1 /* DSP2TX_NF */2705#define WM8996_DSP2TXL_HPF 0x1000 /* DSP2TXL_HPF */2706#define WM8996_DSP2TXL_HPF_MASK 0x1000 /* DSP2TXL_HPF */2707#define WM8996_DSP2TXL_HPF_SHIFT 12 /* DSP2TXL_HPF */2708#define WM8996_DSP2TXL_HPF_WIDTH 1 /* DSP2TXL_HPF */2709#define WM8996_DSP2TXR_HPF 0x0800 /* DSP2TXR_HPF */2710#define WM8996_DSP2TXR_HPF_MASK 0x0800 /* DSP2TXR_HPF */2711#define WM8996_DSP2TXR_HPF_SHIFT 11 /* DSP2TXR_HPF */2712#define WM8996_DSP2TXR_HPF_WIDTH 1 /* DSP2TXR_HPF */2713#define WM8996_DSP2TX_HPF_MODE_MASK 0x0018 /* DSP2TX_HPF_MODE - [4:3] */2714#define WM8996_DSP2TX_HPF_MODE_SHIFT 3 /* DSP2TX_HPF_MODE - [4:3] */2715#define WM8996_DSP2TX_HPF_MODE_WIDTH 2 /* DSP2TX_HPF_MODE - [4:3] */2716#define WM8996_DSP2TX_HPF_CUT_MASK 0x0007 /* DSP2TX_HPF_CUT - [2:0] */2717#define WM8996_DSP2TX_HPF_CUT_SHIFT 0 /* DSP2TX_HPF_CUT - [2:0] */2718#define WM8996_DSP2TX_HPF_CUT_WIDTH 3 /* DSP2TX_HPF_CUT - [2:0] */2719 2720/*2721 * R1312 (0x520) - DSP2 RX Filters (1)2722 */2723#define WM8996_DSP2RX_MUTE 0x0200 /* DSP2RX_MUTE */2724#define WM8996_DSP2RX_MUTE_MASK 0x0200 /* DSP2RX_MUTE */2725#define WM8996_DSP2RX_MUTE_SHIFT 9 /* DSP2RX_MUTE */2726#define WM8996_DSP2RX_MUTE_WIDTH 1 /* DSP2RX_MUTE */2727#define WM8996_DSP2RX_MONO 0x0080 /* DSP2RX_MONO */2728#define WM8996_DSP2RX_MONO_MASK 0x0080 /* DSP2RX_MONO */2729#define WM8996_DSP2RX_MONO_SHIFT 7 /* DSP2RX_MONO */2730#define WM8996_DSP2RX_MONO_WIDTH 1 /* DSP2RX_MONO */2731#define WM8996_DSP2RX_MUTERATE 0x0020 /* DSP2RX_MUTERATE */2732#define WM8996_DSP2RX_MUTERATE_MASK 0x0020 /* DSP2RX_MUTERATE */2733#define WM8996_DSP2RX_MUTERATE_SHIFT 5 /* DSP2RX_MUTERATE */2734#define WM8996_DSP2RX_MUTERATE_WIDTH 1 /* DSP2RX_MUTERATE */2735#define WM8996_DSP2RX_UNMUTE_RAMP 0x0010 /* DSP2RX_UNMUTE_RAMP */2736#define WM8996_DSP2RX_UNMUTE_RAMP_MASK 0x0010 /* DSP2RX_UNMUTE_RAMP */2737#define WM8996_DSP2RX_UNMUTE_RAMP_SHIFT 4 /* DSP2RX_UNMUTE_RAMP */2738#define WM8996_DSP2RX_UNMUTE_RAMP_WIDTH 1 /* DSP2RX_UNMUTE_RAMP */2739 2740/*2741 * R1313 (0x521) - DSP2 RX Filters (2)2742 */2743#define WM8996_DSP2RX_3D_GAIN_MASK 0x3E00 /* DSP2RX_3D_GAIN - [13:9] */2744#define WM8996_DSP2RX_3D_GAIN_SHIFT 9 /* DSP2RX_3D_GAIN - [13:9] */2745#define WM8996_DSP2RX_3D_GAIN_WIDTH 5 /* DSP2RX_3D_GAIN - [13:9] */2746#define WM8996_DSP2RX_3D_ENA 0x0100 /* DSP2RX_3D_ENA */2747#define WM8996_DSP2RX_3D_ENA_MASK 0x0100 /* DSP2RX_3D_ENA */2748#define WM8996_DSP2RX_3D_ENA_SHIFT 8 /* DSP2RX_3D_ENA */2749#define WM8996_DSP2RX_3D_ENA_WIDTH 1 /* DSP2RX_3D_ENA */2750 2751/*2752 * R1344 (0x540) - DSP2 DRC (1)2753 */2754#define WM8996_DSP2DRC_SIG_DET_RMS_MASK 0xF800 /* DSP2DRC_SIG_DET_RMS - [15:11] */2755#define WM8996_DSP2DRC_SIG_DET_RMS_SHIFT 11 /* DSP2DRC_SIG_DET_RMS - [15:11] */2756#define WM8996_DSP2DRC_SIG_DET_RMS_WIDTH 5 /* DSP2DRC_SIG_DET_RMS - [15:11] */2757#define WM8996_DSP2DRC_SIG_DET_PK_MASK 0x0600 /* DSP2DRC_SIG_DET_PK - [10:9] */2758#define WM8996_DSP2DRC_SIG_DET_PK_SHIFT 9 /* DSP2DRC_SIG_DET_PK - [10:9] */2759#define WM8996_DSP2DRC_SIG_DET_PK_WIDTH 2 /* DSP2DRC_SIG_DET_PK - [10:9] */2760#define WM8996_DSP2DRC_NG_ENA 0x0100 /* DSP2DRC_NG_ENA */2761#define WM8996_DSP2DRC_NG_ENA_MASK 0x0100 /* DSP2DRC_NG_ENA */2762#define WM8996_DSP2DRC_NG_ENA_SHIFT 8 /* DSP2DRC_NG_ENA */2763#define WM8996_DSP2DRC_NG_ENA_WIDTH 1 /* DSP2DRC_NG_ENA */2764#define WM8996_DSP2DRC_SIG_DET_MODE 0x0080 /* DSP2DRC_SIG_DET_MODE */2765#define WM8996_DSP2DRC_SIG_DET_MODE_MASK 0x0080 /* DSP2DRC_SIG_DET_MODE */2766#define WM8996_DSP2DRC_SIG_DET_MODE_SHIFT 7 /* DSP2DRC_SIG_DET_MODE */2767#define WM8996_DSP2DRC_SIG_DET_MODE_WIDTH 1 /* DSP2DRC_SIG_DET_MODE */2768#define WM8996_DSP2DRC_SIG_DET 0x0040 /* DSP2DRC_SIG_DET */2769#define WM8996_DSP2DRC_SIG_DET_MASK 0x0040 /* DSP2DRC_SIG_DET */2770#define WM8996_DSP2DRC_SIG_DET_SHIFT 6 /* DSP2DRC_SIG_DET */2771#define WM8996_DSP2DRC_SIG_DET_WIDTH 1 /* DSP2DRC_SIG_DET */2772#define WM8996_DSP2DRC_KNEE2_OP_ENA 0x0020 /* DSP2DRC_KNEE2_OP_ENA */2773#define WM8996_DSP2DRC_KNEE2_OP_ENA_MASK 0x0020 /* DSP2DRC_KNEE2_OP_ENA */2774#define WM8996_DSP2DRC_KNEE2_OP_ENA_SHIFT 5 /* DSP2DRC_KNEE2_OP_ENA */2775#define WM8996_DSP2DRC_KNEE2_OP_ENA_WIDTH 1 /* DSP2DRC_KNEE2_OP_ENA */2776#define WM8996_DSP2DRC_QR 0x0010 /* DSP2DRC_QR */2777#define WM8996_DSP2DRC_QR_MASK 0x0010 /* DSP2DRC_QR */2778#define WM8996_DSP2DRC_QR_SHIFT 4 /* DSP2DRC_QR */2779#define WM8996_DSP2DRC_QR_WIDTH 1 /* DSP2DRC_QR */2780#define WM8996_DSP2DRC_ANTICLIP 0x0008 /* DSP2DRC_ANTICLIP */2781#define WM8996_DSP2DRC_ANTICLIP_MASK 0x0008 /* DSP2DRC_ANTICLIP */2782#define WM8996_DSP2DRC_ANTICLIP_SHIFT 3 /* DSP2DRC_ANTICLIP */2783#define WM8996_DSP2DRC_ANTICLIP_WIDTH 1 /* DSP2DRC_ANTICLIP */2784#define WM8996_DSP2RX_DRC_ENA 0x0004 /* DSP2RX_DRC_ENA */2785#define WM8996_DSP2RX_DRC_ENA_MASK 0x0004 /* DSP2RX_DRC_ENA */2786#define WM8996_DSP2RX_DRC_ENA_SHIFT 2 /* DSP2RX_DRC_ENA */2787#define WM8996_DSP2RX_DRC_ENA_WIDTH 1 /* DSP2RX_DRC_ENA */2788#define WM8996_DSP2TXL_DRC_ENA 0x0002 /* DSP2TXL_DRC_ENA */2789#define WM8996_DSP2TXL_DRC_ENA_MASK 0x0002 /* DSP2TXL_DRC_ENA */2790#define WM8996_DSP2TXL_DRC_ENA_SHIFT 1 /* DSP2TXL_DRC_ENA */2791#define WM8996_DSP2TXL_DRC_ENA_WIDTH 1 /* DSP2TXL_DRC_ENA */2792#define WM8996_DSP2TXR_DRC_ENA 0x0001 /* DSP2TXR_DRC_ENA */2793#define WM8996_DSP2TXR_DRC_ENA_MASK 0x0001 /* DSP2TXR_DRC_ENA */2794#define WM8996_DSP2TXR_DRC_ENA_SHIFT 0 /* DSP2TXR_DRC_ENA */2795#define WM8996_DSP2TXR_DRC_ENA_WIDTH 1 /* DSP2TXR_DRC_ENA */2796 2797/*2798 * R1345 (0x541) - DSP2 DRC (2)2799 */2800#define WM8996_DSP2DRC_ATK_MASK 0x1E00 /* DSP2DRC_ATK - [12:9] */2801#define WM8996_DSP2DRC_ATK_SHIFT 9 /* DSP2DRC_ATK - [12:9] */2802#define WM8996_DSP2DRC_ATK_WIDTH 4 /* DSP2DRC_ATK - [12:9] */2803#define WM8996_DSP2DRC_DCY_MASK 0x01E0 /* DSP2DRC_DCY - [8:5] */2804#define WM8996_DSP2DRC_DCY_SHIFT 5 /* DSP2DRC_DCY - [8:5] */2805#define WM8996_DSP2DRC_DCY_WIDTH 4 /* DSP2DRC_DCY - [8:5] */2806#define WM8996_DSP2DRC_MINGAIN_MASK 0x001C /* DSP2DRC_MINGAIN - [4:2] */2807#define WM8996_DSP2DRC_MINGAIN_SHIFT 2 /* DSP2DRC_MINGAIN - [4:2] */2808#define WM8996_DSP2DRC_MINGAIN_WIDTH 3 /* DSP2DRC_MINGAIN - [4:2] */2809#define WM8996_DSP2DRC_MAXGAIN_MASK 0x0003 /* DSP2DRC_MAXGAIN - [1:0] */2810#define WM8996_DSP2DRC_MAXGAIN_SHIFT 0 /* DSP2DRC_MAXGAIN - [1:0] */2811#define WM8996_DSP2DRC_MAXGAIN_WIDTH 2 /* DSP2DRC_MAXGAIN - [1:0] */2812 2813/*2814 * R1346 (0x542) - DSP2 DRC (3)2815 */2816#define WM8996_DSP2DRC_NG_MINGAIN_MASK 0xF000 /* DSP2DRC_NG_MINGAIN - [15:12] */2817#define WM8996_DSP2DRC_NG_MINGAIN_SHIFT 12 /* DSP2DRC_NG_MINGAIN - [15:12] */2818#define WM8996_DSP2DRC_NG_MINGAIN_WIDTH 4 /* DSP2DRC_NG_MINGAIN - [15:12] */2819#define WM8996_DSP2DRC_NG_EXP_MASK 0x0C00 /* DSP2DRC_NG_EXP - [11:10] */2820#define WM8996_DSP2DRC_NG_EXP_SHIFT 10 /* DSP2DRC_NG_EXP - [11:10] */2821#define WM8996_DSP2DRC_NG_EXP_WIDTH 2 /* DSP2DRC_NG_EXP - [11:10] */2822#define WM8996_DSP2DRC_QR_THR_MASK 0x0300 /* DSP2DRC_QR_THR - [9:8] */2823#define WM8996_DSP2DRC_QR_THR_SHIFT 8 /* DSP2DRC_QR_THR - [9:8] */2824#define WM8996_DSP2DRC_QR_THR_WIDTH 2 /* DSP2DRC_QR_THR - [9:8] */2825#define WM8996_DSP2DRC_QR_DCY_MASK 0x00C0 /* DSP2DRC_QR_DCY - [7:6] */2826#define WM8996_DSP2DRC_QR_DCY_SHIFT 6 /* DSP2DRC_QR_DCY - [7:6] */2827#define WM8996_DSP2DRC_QR_DCY_WIDTH 2 /* DSP2DRC_QR_DCY - [7:6] */2828#define WM8996_DSP2DRC_HI_COMP_MASK 0x0038 /* DSP2DRC_HI_COMP - [5:3] */2829#define WM8996_DSP2DRC_HI_COMP_SHIFT 3 /* DSP2DRC_HI_COMP - [5:3] */2830#define WM8996_DSP2DRC_HI_COMP_WIDTH 3 /* DSP2DRC_HI_COMP - [5:3] */2831#define WM8996_DSP2DRC_LO_COMP_MASK 0x0007 /* DSP2DRC_LO_COMP - [2:0] */2832#define WM8996_DSP2DRC_LO_COMP_SHIFT 0 /* DSP2DRC_LO_COMP - [2:0] */2833#define WM8996_DSP2DRC_LO_COMP_WIDTH 3 /* DSP2DRC_LO_COMP - [2:0] */2834 2835/*2836 * R1347 (0x543) - DSP2 DRC (4)2837 */2838#define WM8996_DSP2DRC_KNEE_IP_MASK 0x07E0 /* DSP2DRC_KNEE_IP - [10:5] */2839#define WM8996_DSP2DRC_KNEE_IP_SHIFT 5 /* DSP2DRC_KNEE_IP - [10:5] */2840#define WM8996_DSP2DRC_KNEE_IP_WIDTH 6 /* DSP2DRC_KNEE_IP - [10:5] */2841#define WM8996_DSP2DRC_KNEE_OP_MASK 0x001F /* DSP2DRC_KNEE_OP - [4:0] */2842#define WM8996_DSP2DRC_KNEE_OP_SHIFT 0 /* DSP2DRC_KNEE_OP - [4:0] */2843#define WM8996_DSP2DRC_KNEE_OP_WIDTH 5 /* DSP2DRC_KNEE_OP - [4:0] */2844 2845/*2846 * R1348 (0x544) - DSP2 DRC (5)2847 */2848#define WM8996_DSP2DRC_KNEE2_IP_MASK 0x03E0 /* DSP2DRC_KNEE2_IP - [9:5] */2849#define WM8996_DSP2DRC_KNEE2_IP_SHIFT 5 /* DSP2DRC_KNEE2_IP - [9:5] */2850#define WM8996_DSP2DRC_KNEE2_IP_WIDTH 5 /* DSP2DRC_KNEE2_IP - [9:5] */2851#define WM8996_DSP2DRC_KNEE2_OP_MASK 0x001F /* DSP2DRC_KNEE2_OP - [4:0] */2852#define WM8996_DSP2DRC_KNEE2_OP_SHIFT 0 /* DSP2DRC_KNEE2_OP - [4:0] */2853#define WM8996_DSP2DRC_KNEE2_OP_WIDTH 5 /* DSP2DRC_KNEE2_OP - [4:0] */2854 2855/*2856 * R1408 (0x580) - DSP2 RX EQ Gains (1)2857 */2858#define WM8996_DSP2RX_EQ_B1_GAIN_MASK 0xF800 /* DSP2RX_EQ_B1_GAIN - [15:11] */2859#define WM8996_DSP2RX_EQ_B1_GAIN_SHIFT 11 /* DSP2RX_EQ_B1_GAIN - [15:11] */2860#define WM8996_DSP2RX_EQ_B1_GAIN_WIDTH 5 /* DSP2RX_EQ_B1_GAIN - [15:11] */2861#define WM8996_DSP2RX_EQ_B2_GAIN_MASK 0x07C0 /* DSP2RX_EQ_B2_GAIN - [10:6] */2862#define WM8996_DSP2RX_EQ_B2_GAIN_SHIFT 6 /* DSP2RX_EQ_B2_GAIN - [10:6] */2863#define WM8996_DSP2RX_EQ_B2_GAIN_WIDTH 5 /* DSP2RX_EQ_B2_GAIN - [10:6] */2864#define WM8996_DSP2RX_EQ_B3_GAIN_MASK 0x003E /* DSP2RX_EQ_B3_GAIN - [5:1] */2865#define WM8996_DSP2RX_EQ_B3_GAIN_SHIFT 1 /* DSP2RX_EQ_B3_GAIN - [5:1] */2866#define WM8996_DSP2RX_EQ_B3_GAIN_WIDTH 5 /* DSP2RX_EQ_B3_GAIN - [5:1] */2867#define WM8996_DSP2RX_EQ_ENA 0x0001 /* DSP2RX_EQ_ENA */2868#define WM8996_DSP2RX_EQ_ENA_MASK 0x0001 /* DSP2RX_EQ_ENA */2869#define WM8996_DSP2RX_EQ_ENA_SHIFT 0 /* DSP2RX_EQ_ENA */2870#define WM8996_DSP2RX_EQ_ENA_WIDTH 1 /* DSP2RX_EQ_ENA */2871 2872/*2873 * R1409 (0x581) - DSP2 RX EQ Gains (2)2874 */2875#define WM8996_DSP2RX_EQ_B4_GAIN_MASK 0xF800 /* DSP2RX_EQ_B4_GAIN - [15:11] */2876#define WM8996_DSP2RX_EQ_B4_GAIN_SHIFT 11 /* DSP2RX_EQ_B4_GAIN - [15:11] */2877#define WM8996_DSP2RX_EQ_B4_GAIN_WIDTH 5 /* DSP2RX_EQ_B4_GAIN - [15:11] */2878#define WM8996_DSP2RX_EQ_B5_GAIN_MASK 0x07C0 /* DSP2RX_EQ_B5_GAIN - [10:6] */2879#define WM8996_DSP2RX_EQ_B5_GAIN_SHIFT 6 /* DSP2RX_EQ_B5_GAIN - [10:6] */2880#define WM8996_DSP2RX_EQ_B5_GAIN_WIDTH 5 /* DSP2RX_EQ_B5_GAIN - [10:6] */2881 2882/*2883 * R1410 (0x582) - DSP2 RX EQ Band 1 A2884 */2885#define WM8996_DSP2RX_EQ_B1_A_MASK 0xFFFF /* DSP2RX_EQ_B1_A - [15:0] */2886#define WM8996_DSP2RX_EQ_B1_A_SHIFT 0 /* DSP2RX_EQ_B1_A - [15:0] */2887#define WM8996_DSP2RX_EQ_B1_A_WIDTH 16 /* DSP2RX_EQ_B1_A - [15:0] */2888 2889/*2890 * R1411 (0x583) - DSP2 RX EQ Band 1 B2891 */2892#define WM8996_DSP2RX_EQ_B1_B_MASK 0xFFFF /* DSP2RX_EQ_B1_B - [15:0] */2893#define WM8996_DSP2RX_EQ_B1_B_SHIFT 0 /* DSP2RX_EQ_B1_B - [15:0] */2894#define WM8996_DSP2RX_EQ_B1_B_WIDTH 16 /* DSP2RX_EQ_B1_B - [15:0] */2895 2896/*2897 * R1412 (0x584) - DSP2 RX EQ Band 1 PG2898 */2899#define WM8996_DSP2RX_EQ_B1_PG_MASK 0xFFFF /* DSP2RX_EQ_B1_PG - [15:0] */2900#define WM8996_DSP2RX_EQ_B1_PG_SHIFT 0 /* DSP2RX_EQ_B1_PG - [15:0] */2901#define WM8996_DSP2RX_EQ_B1_PG_WIDTH 16 /* DSP2RX_EQ_B1_PG - [15:0] */2902 2903/*2904 * R1413 (0x585) - DSP2 RX EQ Band 2 A2905 */2906#define WM8996_DSP2RX_EQ_B2_A_MASK 0xFFFF /* DSP2RX_EQ_B2_A - [15:0] */2907#define WM8996_DSP2RX_EQ_B2_A_SHIFT 0 /* DSP2RX_EQ_B2_A - [15:0] */2908#define WM8996_DSP2RX_EQ_B2_A_WIDTH 16 /* DSP2RX_EQ_B2_A - [15:0] */2909 2910/*2911 * R1414 (0x586) - DSP2 RX EQ Band 2 B2912 */2913#define WM8996_DSP2RX_EQ_B2_B_MASK 0xFFFF /* DSP2RX_EQ_B2_B - [15:0] */2914#define WM8996_DSP2RX_EQ_B2_B_SHIFT 0 /* DSP2RX_EQ_B2_B - [15:0] */2915#define WM8996_DSP2RX_EQ_B2_B_WIDTH 16 /* DSP2RX_EQ_B2_B - [15:0] */2916 2917/*2918 * R1415 (0x587) - DSP2 RX EQ Band 2 C2919 */2920#define WM8996_DSP2RX_EQ_B2_C_MASK 0xFFFF /* DSP2RX_EQ_B2_C - [15:0] */2921#define WM8996_DSP2RX_EQ_B2_C_SHIFT 0 /* DSP2RX_EQ_B2_C - [15:0] */2922#define WM8996_DSP2RX_EQ_B2_C_WIDTH 16 /* DSP2RX_EQ_B2_C - [15:0] */2923 2924/*2925 * R1416 (0x588) - DSP2 RX EQ Band 2 PG2926 */2927#define WM8996_DSP2RX_EQ_B2_PG_MASK 0xFFFF /* DSP2RX_EQ_B2_PG - [15:0] */2928#define WM8996_DSP2RX_EQ_B2_PG_SHIFT 0 /* DSP2RX_EQ_B2_PG - [15:0] */2929#define WM8996_DSP2RX_EQ_B2_PG_WIDTH 16 /* DSP2RX_EQ_B2_PG - [15:0] */2930 2931/*2932 * R1417 (0x589) - DSP2 RX EQ Band 3 A2933 */2934#define WM8996_DSP2RX_EQ_B3_A_MASK 0xFFFF /* DSP2RX_EQ_B3_A - [15:0] */2935#define WM8996_DSP2RX_EQ_B3_A_SHIFT 0 /* DSP2RX_EQ_B3_A - [15:0] */2936#define WM8996_DSP2RX_EQ_B3_A_WIDTH 16 /* DSP2RX_EQ_B3_A - [15:0] */2937 2938/*2939 * R1418 (0x58A) - DSP2 RX EQ Band 3 B2940 */2941#define WM8996_DSP2RX_EQ_B3_B_MASK 0xFFFF /* DSP2RX_EQ_B3_B - [15:0] */2942#define WM8996_DSP2RX_EQ_B3_B_SHIFT 0 /* DSP2RX_EQ_B3_B - [15:0] */2943#define WM8996_DSP2RX_EQ_B3_B_WIDTH 16 /* DSP2RX_EQ_B3_B - [15:0] */2944 2945/*2946 * R1419 (0x58B) - DSP2 RX EQ Band 3 C2947 */2948#define WM8996_DSP2RX_EQ_B3_C_MASK 0xFFFF /* DSP2RX_EQ_B3_C - [15:0] */2949#define WM8996_DSP2RX_EQ_B3_C_SHIFT 0 /* DSP2RX_EQ_B3_C - [15:0] */2950#define WM8996_DSP2RX_EQ_B3_C_WIDTH 16 /* DSP2RX_EQ_B3_C - [15:0] */2951 2952/*2953 * R1420 (0x58C) - DSP2 RX EQ Band 3 PG2954 */2955#define WM8996_DSP2RX_EQ_B3_PG_MASK 0xFFFF /* DSP2RX_EQ_B3_PG - [15:0] */2956#define WM8996_DSP2RX_EQ_B3_PG_SHIFT 0 /* DSP2RX_EQ_B3_PG - [15:0] */2957#define WM8996_DSP2RX_EQ_B3_PG_WIDTH 16 /* DSP2RX_EQ_B3_PG - [15:0] */2958 2959/*2960 * R1421 (0x58D) - DSP2 RX EQ Band 4 A2961 */2962#define WM8996_DSP2RX_EQ_B4_A_MASK 0xFFFF /* DSP2RX_EQ_B4_A - [15:0] */2963#define WM8996_DSP2RX_EQ_B4_A_SHIFT 0 /* DSP2RX_EQ_B4_A - [15:0] */2964#define WM8996_DSP2RX_EQ_B4_A_WIDTH 16 /* DSP2RX_EQ_B4_A - [15:0] */2965 2966/*2967 * R1422 (0x58E) - DSP2 RX EQ Band 4 B2968 */2969#define WM8996_DSP2RX_EQ_B4_B_MASK 0xFFFF /* DSP2RX_EQ_B4_B - [15:0] */2970#define WM8996_DSP2RX_EQ_B4_B_SHIFT 0 /* DSP2RX_EQ_B4_B - [15:0] */2971#define WM8996_DSP2RX_EQ_B4_B_WIDTH 16 /* DSP2RX_EQ_B4_B - [15:0] */2972 2973/*2974 * R1423 (0x58F) - DSP2 RX EQ Band 4 C2975 */2976#define WM8996_DSP2RX_EQ_B4_C_MASK 0xFFFF /* DSP2RX_EQ_B4_C - [15:0] */2977#define WM8996_DSP2RX_EQ_B4_C_SHIFT 0 /* DSP2RX_EQ_B4_C - [15:0] */2978#define WM8996_DSP2RX_EQ_B4_C_WIDTH 16 /* DSP2RX_EQ_B4_C - [15:0] */2979 2980/*2981 * R1424 (0x590) - DSP2 RX EQ Band 4 PG2982 */2983#define WM8996_DSP2RX_EQ_B4_PG_MASK 0xFFFF /* DSP2RX_EQ_B4_PG - [15:0] */2984#define WM8996_DSP2RX_EQ_B4_PG_SHIFT 0 /* DSP2RX_EQ_B4_PG - [15:0] */2985#define WM8996_DSP2RX_EQ_B4_PG_WIDTH 16 /* DSP2RX_EQ_B4_PG - [15:0] */2986 2987/*2988 * R1425 (0x591) - DSP2 RX EQ Band 5 A2989 */2990#define WM8996_DSP2RX_EQ_B5_A_MASK 0xFFFF /* DSP2RX_EQ_B5_A - [15:0] */2991#define WM8996_DSP2RX_EQ_B5_A_SHIFT 0 /* DSP2RX_EQ_B5_A - [15:0] */2992#define WM8996_DSP2RX_EQ_B5_A_WIDTH 16 /* DSP2RX_EQ_B5_A - [15:0] */2993 2994/*2995 * R1426 (0x592) - DSP2 RX EQ Band 5 B2996 */2997#define WM8996_DSP2RX_EQ_B5_B_MASK 0xFFFF /* DSP2RX_EQ_B5_B - [15:0] */2998#define WM8996_DSP2RX_EQ_B5_B_SHIFT 0 /* DSP2RX_EQ_B5_B - [15:0] */2999#define WM8996_DSP2RX_EQ_B5_B_WIDTH 16 /* DSP2RX_EQ_B5_B - [15:0] */3000 3001/*3002 * R1427 (0x593) - DSP2 RX EQ Band 5 PG3003 */3004#define WM8996_DSP2RX_EQ_B5_PG_MASK 0xFFFF /* DSP2RX_EQ_B5_PG - [15:0] */3005#define WM8996_DSP2RX_EQ_B5_PG_SHIFT 0 /* DSP2RX_EQ_B5_PG - [15:0] */3006#define WM8996_DSP2RX_EQ_B5_PG_WIDTH 16 /* DSP2RX_EQ_B5_PG - [15:0] */3007 3008/*3009 * R1536 (0x600) - DAC1 Mixer Volumes3010 */3011#define WM8996_ADCR_DAC1_VOL_MASK 0x03E0 /* ADCR_DAC1_VOL - [9:5] */3012#define WM8996_ADCR_DAC1_VOL_SHIFT 5 /* ADCR_DAC1_VOL - [9:5] */3013#define WM8996_ADCR_DAC1_VOL_WIDTH 5 /* ADCR_DAC1_VOL - [9:5] */3014#define WM8996_ADCL_DAC1_VOL_MASK 0x001F /* ADCL_DAC1_VOL - [4:0] */3015#define WM8996_ADCL_DAC1_VOL_SHIFT 0 /* ADCL_DAC1_VOL - [4:0] */3016#define WM8996_ADCL_DAC1_VOL_WIDTH 5 /* ADCL_DAC1_VOL - [4:0] */3017 3018/*3019 * R1537 (0x601) - DAC1 Left Mixer Routing3020 */3021#define WM8996_ADCR_TO_DAC1L 0x0020 /* ADCR_TO_DAC1L */3022#define WM8996_ADCR_TO_DAC1L_MASK 0x0020 /* ADCR_TO_DAC1L */3023#define WM8996_ADCR_TO_DAC1L_SHIFT 5 /* ADCR_TO_DAC1L */3024#define WM8996_ADCR_TO_DAC1L_WIDTH 1 /* ADCR_TO_DAC1L */3025#define WM8996_ADCL_TO_DAC1L 0x0010 /* ADCL_TO_DAC1L */3026#define WM8996_ADCL_TO_DAC1L_MASK 0x0010 /* ADCL_TO_DAC1L */3027#define WM8996_ADCL_TO_DAC1L_SHIFT 4 /* ADCL_TO_DAC1L */3028#define WM8996_ADCL_TO_DAC1L_WIDTH 1 /* ADCL_TO_DAC1L */3029#define WM8996_DSP2RXL_TO_DAC1L 0x0002 /* DSP2RXL_TO_DAC1L */3030#define WM8996_DSP2RXL_TO_DAC1L_MASK 0x0002 /* DSP2RXL_TO_DAC1L */3031#define WM8996_DSP2RXL_TO_DAC1L_SHIFT 1 /* DSP2RXL_TO_DAC1L */3032#define WM8996_DSP2RXL_TO_DAC1L_WIDTH 1 /* DSP2RXL_TO_DAC1L */3033#define WM8996_DSP1RXL_TO_DAC1L 0x0001 /* DSP1RXL_TO_DAC1L */3034#define WM8996_DSP1RXL_TO_DAC1L_MASK 0x0001 /* DSP1RXL_TO_DAC1L */3035#define WM8996_DSP1RXL_TO_DAC1L_SHIFT 0 /* DSP1RXL_TO_DAC1L */3036#define WM8996_DSP1RXL_TO_DAC1L_WIDTH 1 /* DSP1RXL_TO_DAC1L */3037 3038/*3039 * R1538 (0x602) - DAC1 Right Mixer Routing3040 */3041#define WM8996_ADCR_TO_DAC1R 0x0020 /* ADCR_TO_DAC1R */3042#define WM8996_ADCR_TO_DAC1R_MASK 0x0020 /* ADCR_TO_DAC1R */3043#define WM8996_ADCR_TO_DAC1R_SHIFT 5 /* ADCR_TO_DAC1R */3044#define WM8996_ADCR_TO_DAC1R_WIDTH 1 /* ADCR_TO_DAC1R */3045#define WM8996_ADCL_TO_DAC1R 0x0010 /* ADCL_TO_DAC1R */3046#define WM8996_ADCL_TO_DAC1R_MASK 0x0010 /* ADCL_TO_DAC1R */3047#define WM8996_ADCL_TO_DAC1R_SHIFT 4 /* ADCL_TO_DAC1R */3048#define WM8996_ADCL_TO_DAC1R_WIDTH 1 /* ADCL_TO_DAC1R */3049#define WM8996_DSP2RXR_TO_DAC1R 0x0002 /* DSP2RXR_TO_DAC1R */3050#define WM8996_DSP2RXR_TO_DAC1R_MASK 0x0002 /* DSP2RXR_TO_DAC1R */3051#define WM8996_DSP2RXR_TO_DAC1R_SHIFT 1 /* DSP2RXR_TO_DAC1R */3052#define WM8996_DSP2RXR_TO_DAC1R_WIDTH 1 /* DSP2RXR_TO_DAC1R */3053#define WM8996_DSP1RXR_TO_DAC1R 0x0001 /* DSP1RXR_TO_DAC1R */3054#define WM8996_DSP1RXR_TO_DAC1R_MASK 0x0001 /* DSP1RXR_TO_DAC1R */3055#define WM8996_DSP1RXR_TO_DAC1R_SHIFT 0 /* DSP1RXR_TO_DAC1R */3056#define WM8996_DSP1RXR_TO_DAC1R_WIDTH 1 /* DSP1RXR_TO_DAC1R */3057 3058/*3059 * R1539 (0x603) - DAC2 Mixer Volumes3060 */3061#define WM8996_ADCR_DAC2_VOL_MASK 0x03E0 /* ADCR_DAC2_VOL - [9:5] */3062#define WM8996_ADCR_DAC2_VOL_SHIFT 5 /* ADCR_DAC2_VOL - [9:5] */3063#define WM8996_ADCR_DAC2_VOL_WIDTH 5 /* ADCR_DAC2_VOL - [9:5] */3064#define WM8996_ADCL_DAC2_VOL_MASK 0x001F /* ADCL_DAC2_VOL - [4:0] */3065#define WM8996_ADCL_DAC2_VOL_SHIFT 0 /* ADCL_DAC2_VOL - [4:0] */3066#define WM8996_ADCL_DAC2_VOL_WIDTH 5 /* ADCL_DAC2_VOL - [4:0] */3067 3068/*3069 * R1540 (0x604) - DAC2 Left Mixer Routing3070 */3071#define WM8996_ADCR_TO_DAC2L 0x0020 /* ADCR_TO_DAC2L */3072#define WM8996_ADCR_TO_DAC2L_MASK 0x0020 /* ADCR_TO_DAC2L */3073#define WM8996_ADCR_TO_DAC2L_SHIFT 5 /* ADCR_TO_DAC2L */3074#define WM8996_ADCR_TO_DAC2L_WIDTH 1 /* ADCR_TO_DAC2L */3075#define WM8996_ADCL_TO_DAC2L 0x0010 /* ADCL_TO_DAC2L */3076#define WM8996_ADCL_TO_DAC2L_MASK 0x0010 /* ADCL_TO_DAC2L */3077#define WM8996_ADCL_TO_DAC2L_SHIFT 4 /* ADCL_TO_DAC2L */3078#define WM8996_ADCL_TO_DAC2L_WIDTH 1 /* ADCL_TO_DAC2L */3079#define WM8996_DSP2RXL_TO_DAC2L 0x0002 /* DSP2RXL_TO_DAC2L */3080#define WM8996_DSP2RXL_TO_DAC2L_MASK 0x0002 /* DSP2RXL_TO_DAC2L */3081#define WM8996_DSP2RXL_TO_DAC2L_SHIFT 1 /* DSP2RXL_TO_DAC2L */3082#define WM8996_DSP2RXL_TO_DAC2L_WIDTH 1 /* DSP2RXL_TO_DAC2L */3083#define WM8996_DSP1RXL_TO_DAC2L 0x0001 /* DSP1RXL_TO_DAC2L */3084#define WM8996_DSP1RXL_TO_DAC2L_MASK 0x0001 /* DSP1RXL_TO_DAC2L */3085#define WM8996_DSP1RXL_TO_DAC2L_SHIFT 0 /* DSP1RXL_TO_DAC2L */3086#define WM8996_DSP1RXL_TO_DAC2L_WIDTH 1 /* DSP1RXL_TO_DAC2L */3087 3088/*3089 * R1541 (0x605) - DAC2 Right Mixer Routing3090 */3091#define WM8996_ADCR_TO_DAC2R 0x0020 /* ADCR_TO_DAC2R */3092#define WM8996_ADCR_TO_DAC2R_MASK 0x0020 /* ADCR_TO_DAC2R */3093#define WM8996_ADCR_TO_DAC2R_SHIFT 5 /* ADCR_TO_DAC2R */3094#define WM8996_ADCR_TO_DAC2R_WIDTH 1 /* ADCR_TO_DAC2R */3095#define WM8996_ADCL_TO_DAC2R 0x0010 /* ADCL_TO_DAC2R */3096#define WM8996_ADCL_TO_DAC2R_MASK 0x0010 /* ADCL_TO_DAC2R */3097#define WM8996_ADCL_TO_DAC2R_SHIFT 4 /* ADCL_TO_DAC2R */3098#define WM8996_ADCL_TO_DAC2R_WIDTH 1 /* ADCL_TO_DAC2R */3099#define WM8996_DSP2RXR_TO_DAC2R 0x0002 /* DSP2RXR_TO_DAC2R */3100#define WM8996_DSP2RXR_TO_DAC2R_MASK 0x0002 /* DSP2RXR_TO_DAC2R */3101#define WM8996_DSP2RXR_TO_DAC2R_SHIFT 1 /* DSP2RXR_TO_DAC2R */3102#define WM8996_DSP2RXR_TO_DAC2R_WIDTH 1 /* DSP2RXR_TO_DAC2R */3103#define WM8996_DSP1RXR_TO_DAC2R 0x0001 /* DSP1RXR_TO_DAC2R */3104#define WM8996_DSP1RXR_TO_DAC2R_MASK 0x0001 /* DSP1RXR_TO_DAC2R */3105#define WM8996_DSP1RXR_TO_DAC2R_SHIFT 0 /* DSP1RXR_TO_DAC2R */3106#define WM8996_DSP1RXR_TO_DAC2R_WIDTH 1 /* DSP1RXR_TO_DAC2R */3107 3108/*3109 * R1542 (0x606) - DSP1 TX Left Mixer Routing3110 */3111#define WM8996_ADC1L_TO_DSP1TXL 0x0002 /* ADC1L_TO_DSP1TXL */3112#define WM8996_ADC1L_TO_DSP1TXL_MASK 0x0002 /* ADC1L_TO_DSP1TXL */3113#define WM8996_ADC1L_TO_DSP1TXL_SHIFT 1 /* ADC1L_TO_DSP1TXL */3114#define WM8996_ADC1L_TO_DSP1TXL_WIDTH 1 /* ADC1L_TO_DSP1TXL */3115#define WM8996_DACL_TO_DSP1TXL 0x0001 /* DACL_TO_DSP1TXL */3116#define WM8996_DACL_TO_DSP1TXL_MASK 0x0001 /* DACL_TO_DSP1TXL */3117#define WM8996_DACL_TO_DSP1TXL_SHIFT 0 /* DACL_TO_DSP1TXL */3118#define WM8996_DACL_TO_DSP1TXL_WIDTH 1 /* DACL_TO_DSP1TXL */3119 3120/*3121 * R1543 (0x607) - DSP1 TX Right Mixer Routing3122 */3123#define WM8996_ADC1R_TO_DSP1TXR 0x0002 /* ADC1R_TO_DSP1TXR */3124#define WM8996_ADC1R_TO_DSP1TXR_MASK 0x0002 /* ADC1R_TO_DSP1TXR */3125#define WM8996_ADC1R_TO_DSP1TXR_SHIFT 1 /* ADC1R_TO_DSP1TXR */3126#define WM8996_ADC1R_TO_DSP1TXR_WIDTH 1 /* ADC1R_TO_DSP1TXR */3127#define WM8996_DACR_TO_DSP1TXR 0x0001 /* DACR_TO_DSP1TXR */3128#define WM8996_DACR_TO_DSP1TXR_MASK 0x0001 /* DACR_TO_DSP1TXR */3129#define WM8996_DACR_TO_DSP1TXR_SHIFT 0 /* DACR_TO_DSP1TXR */3130#define WM8996_DACR_TO_DSP1TXR_WIDTH 1 /* DACR_TO_DSP1TXR */3131 3132/*3133 * R1544 (0x608) - DSP2 TX Left Mixer Routing3134 */3135#define WM8996_ADC2L_TO_DSP2TXL 0x0002 /* ADC2L_TO_DSP2TXL */3136#define WM8996_ADC2L_TO_DSP2TXL_MASK 0x0002 /* ADC2L_TO_DSP2TXL */3137#define WM8996_ADC2L_TO_DSP2TXL_SHIFT 1 /* ADC2L_TO_DSP2TXL */3138#define WM8996_ADC2L_TO_DSP2TXL_WIDTH 1 /* ADC2L_TO_DSP2TXL */3139#define WM8996_DACL_TO_DSP2TXL 0x0001 /* DACL_TO_DSP2TXL */3140#define WM8996_DACL_TO_DSP2TXL_MASK 0x0001 /* DACL_TO_DSP2TXL */3141#define WM8996_DACL_TO_DSP2TXL_SHIFT 0 /* DACL_TO_DSP2TXL */3142#define WM8996_DACL_TO_DSP2TXL_WIDTH 1 /* DACL_TO_DSP2TXL */3143 3144/*3145 * R1545 (0x609) - DSP2 TX Right Mixer Routing3146 */3147#define WM8996_ADC2R_TO_DSP2TXR 0x0002 /* ADC2R_TO_DSP2TXR */3148#define WM8996_ADC2R_TO_DSP2TXR_MASK 0x0002 /* ADC2R_TO_DSP2TXR */3149#define WM8996_ADC2R_TO_DSP2TXR_SHIFT 1 /* ADC2R_TO_DSP2TXR */3150#define WM8996_ADC2R_TO_DSP2TXR_WIDTH 1 /* ADC2R_TO_DSP2TXR */3151#define WM8996_DACR_TO_DSP2TXR 0x0001 /* DACR_TO_DSP2TXR */3152#define WM8996_DACR_TO_DSP2TXR_MASK 0x0001 /* DACR_TO_DSP2TXR */3153#define WM8996_DACR_TO_DSP2TXR_SHIFT 0 /* DACR_TO_DSP2TXR */3154#define WM8996_DACR_TO_DSP2TXR_WIDTH 1 /* DACR_TO_DSP2TXR */3155 3156/*3157 * R1546 (0x60A) - DSP TX Mixer Select3158 */3159#define WM8996_DAC_TO_DSPTX_SRC 0x0001 /* DAC_TO_DSPTX_SRC */3160#define WM8996_DAC_TO_DSPTX_SRC_MASK 0x0001 /* DAC_TO_DSPTX_SRC */3161#define WM8996_DAC_TO_DSPTX_SRC_SHIFT 0 /* DAC_TO_DSPTX_SRC */3162#define WM8996_DAC_TO_DSPTX_SRC_WIDTH 1 /* DAC_TO_DSPTX_SRC */3163 3164/*3165 * R1552 (0x610) - DAC Softmute3166 */3167#define WM8996_DAC_SOFTMUTEMODE 0x0002 /* DAC_SOFTMUTEMODE */3168#define WM8996_DAC_SOFTMUTEMODE_MASK 0x0002 /* DAC_SOFTMUTEMODE */3169#define WM8996_DAC_SOFTMUTEMODE_SHIFT 1 /* DAC_SOFTMUTEMODE */3170#define WM8996_DAC_SOFTMUTEMODE_WIDTH 1 /* DAC_SOFTMUTEMODE */3171#define WM8996_DAC_MUTERATE 0x0001 /* DAC_MUTERATE */3172#define WM8996_DAC_MUTERATE_MASK 0x0001 /* DAC_MUTERATE */3173#define WM8996_DAC_MUTERATE_SHIFT 0 /* DAC_MUTERATE */3174#define WM8996_DAC_MUTERATE_WIDTH 1 /* DAC_MUTERATE */3175 3176/*3177 * R1568 (0x620) - Oversampling3178 */3179#define WM8996_SPK_OSR128 0x0008 /* SPK_OSR128 */3180#define WM8996_SPK_OSR128_MASK 0x0008 /* SPK_OSR128 */3181#define WM8996_SPK_OSR128_SHIFT 3 /* SPK_OSR128 */3182#define WM8996_SPK_OSR128_WIDTH 1 /* SPK_OSR128 */3183#define WM8996_DMIC_OSR64 0x0004 /* DMIC_OSR64 */3184#define WM8996_DMIC_OSR64_MASK 0x0004 /* DMIC_OSR64 */3185#define WM8996_DMIC_OSR64_SHIFT 2 /* DMIC_OSR64 */3186#define WM8996_DMIC_OSR64_WIDTH 1 /* DMIC_OSR64 */3187#define WM8996_ADC_OSR128 0x0002 /* ADC_OSR128 */3188#define WM8996_ADC_OSR128_MASK 0x0002 /* ADC_OSR128 */3189#define WM8996_ADC_OSR128_SHIFT 1 /* ADC_OSR128 */3190#define WM8996_ADC_OSR128_WIDTH 1 /* ADC_OSR128 */3191#define WM8996_DAC_OSR128 0x0001 /* DAC_OSR128 */3192#define WM8996_DAC_OSR128_MASK 0x0001 /* DAC_OSR128 */3193#define WM8996_DAC_OSR128_SHIFT 0 /* DAC_OSR128 */3194#define WM8996_DAC_OSR128_WIDTH 1 /* DAC_OSR128 */3195 3196/*3197 * R1569 (0x621) - Sidetone3198 */3199#define WM8996_ST_LPF 0x1000 /* ST_LPF */3200#define WM8996_ST_LPF_MASK 0x1000 /* ST_LPF */3201#define WM8996_ST_LPF_SHIFT 12 /* ST_LPF */3202#define WM8996_ST_LPF_WIDTH 1 /* ST_LPF */3203#define WM8996_ST_HPF_CUT_MASK 0x0380 /* ST_HPF_CUT - [9:7] */3204#define WM8996_ST_HPF_CUT_SHIFT 7 /* ST_HPF_CUT - [9:7] */3205#define WM8996_ST_HPF_CUT_WIDTH 3 /* ST_HPF_CUT - [9:7] */3206#define WM8996_ST_HPF 0x0040 /* ST_HPF */3207#define WM8996_ST_HPF_MASK 0x0040 /* ST_HPF */3208#define WM8996_ST_HPF_SHIFT 6 /* ST_HPF */3209#define WM8996_ST_HPF_WIDTH 1 /* ST_HPF */3210#define WM8996_STR_SEL 0x0002 /* STR_SEL */3211#define WM8996_STR_SEL_MASK 0x0002 /* STR_SEL */3212#define WM8996_STR_SEL_SHIFT 1 /* STR_SEL */3213#define WM8996_STR_SEL_WIDTH 1 /* STR_SEL */3214#define WM8996_STL_SEL 0x0001 /* STL_SEL */3215#define WM8996_STL_SEL_MASK 0x0001 /* STL_SEL */3216#define WM8996_STL_SEL_SHIFT 0 /* STL_SEL */3217#define WM8996_STL_SEL_WIDTH 1 /* STL_SEL */3218 3219/*3220 * R1792 (0x700) - GPIO 13221 */3222#define WM8996_GP1_DIR 0x8000 /* GP1_DIR */3223#define WM8996_GP1_DIR_MASK 0x8000 /* GP1_DIR */3224#define WM8996_GP1_DIR_SHIFT 15 /* GP1_DIR */3225#define WM8996_GP1_DIR_WIDTH 1 /* GP1_DIR */3226#define WM8996_GP1_PU 0x4000 /* GP1_PU */3227#define WM8996_GP1_PU_MASK 0x4000 /* GP1_PU */3228#define WM8996_GP1_PU_SHIFT 14 /* GP1_PU */3229#define WM8996_GP1_PU_WIDTH 1 /* GP1_PU */3230#define WM8996_GP1_PD 0x2000 /* GP1_PD */3231#define WM8996_GP1_PD_MASK 0x2000 /* GP1_PD */3232#define WM8996_GP1_PD_SHIFT 13 /* GP1_PD */3233#define WM8996_GP1_PD_WIDTH 1 /* GP1_PD */3234#define WM8996_GP1_POL 0x0400 /* GP1_POL */3235#define WM8996_GP1_POL_MASK 0x0400 /* GP1_POL */3236#define WM8996_GP1_POL_SHIFT 10 /* GP1_POL */3237#define WM8996_GP1_POL_WIDTH 1 /* GP1_POL */3238#define WM8996_GP1_OP_CFG 0x0200 /* GP1_OP_CFG */3239#define WM8996_GP1_OP_CFG_MASK 0x0200 /* GP1_OP_CFG */3240#define WM8996_GP1_OP_CFG_SHIFT 9 /* GP1_OP_CFG */3241#define WM8996_GP1_OP_CFG_WIDTH 1 /* GP1_OP_CFG */3242#define WM8996_GP1_DB 0x0100 /* GP1_DB */3243#define WM8996_GP1_DB_MASK 0x0100 /* GP1_DB */3244#define WM8996_GP1_DB_SHIFT 8 /* GP1_DB */3245#define WM8996_GP1_DB_WIDTH 1 /* GP1_DB */3246#define WM8996_GP1_LVL 0x0040 /* GP1_LVL */3247#define WM8996_GP1_LVL_MASK 0x0040 /* GP1_LVL */3248#define WM8996_GP1_LVL_SHIFT 6 /* GP1_LVL */3249#define WM8996_GP1_LVL_WIDTH 1 /* GP1_LVL */3250#define WM8996_GP1_FN_MASK 0x000F /* GP1_FN - [3:0] */3251#define WM8996_GP1_FN_SHIFT 0 /* GP1_FN - [3:0] */3252#define WM8996_GP1_FN_WIDTH 4 /* GP1_FN - [3:0] */3253 3254/*3255 * R1793 (0x701) - GPIO 23256 */3257#define WM8996_GP2_DIR 0x8000 /* GP2_DIR */3258#define WM8996_GP2_DIR_MASK 0x8000 /* GP2_DIR */3259#define WM8996_GP2_DIR_SHIFT 15 /* GP2_DIR */3260#define WM8996_GP2_DIR_WIDTH 1 /* GP2_DIR */3261#define WM8996_GP2_PU 0x4000 /* GP2_PU */3262#define WM8996_GP2_PU_MASK 0x4000 /* GP2_PU */3263#define WM8996_GP2_PU_SHIFT 14 /* GP2_PU */3264#define WM8996_GP2_PU_WIDTH 1 /* GP2_PU */3265#define WM8996_GP2_PD 0x2000 /* GP2_PD */3266#define WM8996_GP2_PD_MASK 0x2000 /* GP2_PD */3267#define WM8996_GP2_PD_SHIFT 13 /* GP2_PD */3268#define WM8996_GP2_PD_WIDTH 1 /* GP2_PD */3269#define WM8996_GP2_POL 0x0400 /* GP2_POL */3270#define WM8996_GP2_POL_MASK 0x0400 /* GP2_POL */3271#define WM8996_GP2_POL_SHIFT 10 /* GP2_POL */3272#define WM8996_GP2_POL_WIDTH 1 /* GP2_POL */3273#define WM8996_GP2_OP_CFG 0x0200 /* GP2_OP_CFG */3274#define WM8996_GP2_OP_CFG_MASK 0x0200 /* GP2_OP_CFG */3275#define WM8996_GP2_OP_CFG_SHIFT 9 /* GP2_OP_CFG */3276#define WM8996_GP2_OP_CFG_WIDTH 1 /* GP2_OP_CFG */3277#define WM8996_GP2_DB 0x0100 /* GP2_DB */3278#define WM8996_GP2_DB_MASK 0x0100 /* GP2_DB */3279#define WM8996_GP2_DB_SHIFT 8 /* GP2_DB */3280#define WM8996_GP2_DB_WIDTH 1 /* GP2_DB */3281#define WM8996_GP2_LVL 0x0040 /* GP2_LVL */3282#define WM8996_GP2_LVL_MASK 0x0040 /* GP2_LVL */3283#define WM8996_GP2_LVL_SHIFT 6 /* GP2_LVL */3284#define WM8996_GP2_LVL_WIDTH 1 /* GP2_LVL */3285#define WM8996_GP2_FN_MASK 0x000F /* GP2_FN - [3:0] */3286#define WM8996_GP2_FN_SHIFT 0 /* GP2_FN - [3:0] */3287#define WM8996_GP2_FN_WIDTH 4 /* GP2_FN - [3:0] */3288 3289/*3290 * R1794 (0x702) - GPIO 33291 */3292#define WM8996_GP3_DIR 0x8000 /* GP3_DIR */3293#define WM8996_GP3_DIR_MASK 0x8000 /* GP3_DIR */3294#define WM8996_GP3_DIR_SHIFT 15 /* GP3_DIR */3295#define WM8996_GP3_DIR_WIDTH 1 /* GP3_DIR */3296#define WM8996_GP3_PU 0x4000 /* GP3_PU */3297#define WM8996_GP3_PU_MASK 0x4000 /* GP3_PU */3298#define WM8996_GP3_PU_SHIFT 14 /* GP3_PU */3299#define WM8996_GP3_PU_WIDTH 1 /* GP3_PU */3300#define WM8996_GP3_PD 0x2000 /* GP3_PD */3301#define WM8996_GP3_PD_MASK 0x2000 /* GP3_PD */3302#define WM8996_GP3_PD_SHIFT 13 /* GP3_PD */3303#define WM8996_GP3_PD_WIDTH 1 /* GP3_PD */3304#define WM8996_GP3_POL 0x0400 /* GP3_POL */3305#define WM8996_GP3_POL_MASK 0x0400 /* GP3_POL */3306#define WM8996_GP3_POL_SHIFT 10 /* GP3_POL */3307#define WM8996_GP3_POL_WIDTH 1 /* GP3_POL */3308#define WM8996_GP3_OP_CFG 0x0200 /* GP3_OP_CFG */3309#define WM8996_GP3_OP_CFG_MASK 0x0200 /* GP3_OP_CFG */3310#define WM8996_GP3_OP_CFG_SHIFT 9 /* GP3_OP_CFG */3311#define WM8996_GP3_OP_CFG_WIDTH 1 /* GP3_OP_CFG */3312#define WM8996_GP3_DB 0x0100 /* GP3_DB */3313#define WM8996_GP3_DB_MASK 0x0100 /* GP3_DB */3314#define WM8996_GP3_DB_SHIFT 8 /* GP3_DB */3315#define WM8996_GP3_DB_WIDTH 1 /* GP3_DB */3316#define WM8996_GP3_LVL 0x0040 /* GP3_LVL */3317#define WM8996_GP3_LVL_MASK 0x0040 /* GP3_LVL */3318#define WM8996_GP3_LVL_SHIFT 6 /* GP3_LVL */3319#define WM8996_GP3_LVL_WIDTH 1 /* GP3_LVL */3320#define WM8996_GP3_FN_MASK 0x000F /* GP3_FN - [3:0] */3321#define WM8996_GP3_FN_SHIFT 0 /* GP3_FN - [3:0] */3322#define WM8996_GP3_FN_WIDTH 4 /* GP3_FN - [3:0] */3323 3324/*3325 * R1795 (0x703) - GPIO 43326 */3327#define WM8996_GP4_DIR 0x8000 /* GP4_DIR */3328#define WM8996_GP4_DIR_MASK 0x8000 /* GP4_DIR */3329#define WM8996_GP4_DIR_SHIFT 15 /* GP4_DIR */3330#define WM8996_GP4_DIR_WIDTH 1 /* GP4_DIR */3331#define WM8996_GP4_PU 0x4000 /* GP4_PU */3332#define WM8996_GP4_PU_MASK 0x4000 /* GP4_PU */3333#define WM8996_GP4_PU_SHIFT 14 /* GP4_PU */3334#define WM8996_GP4_PU_WIDTH 1 /* GP4_PU */3335#define WM8996_GP4_PD 0x2000 /* GP4_PD */3336#define WM8996_GP4_PD_MASK 0x2000 /* GP4_PD */3337#define WM8996_GP4_PD_SHIFT 13 /* GP4_PD */3338#define WM8996_GP4_PD_WIDTH 1 /* GP4_PD */3339#define WM8996_GP4_POL 0x0400 /* GP4_POL */3340#define WM8996_GP4_POL_MASK 0x0400 /* GP4_POL */3341#define WM8996_GP4_POL_SHIFT 10 /* GP4_POL */3342#define WM8996_GP4_POL_WIDTH 1 /* GP4_POL */3343#define WM8996_GP4_OP_CFG 0x0200 /* GP4_OP_CFG */3344#define WM8996_GP4_OP_CFG_MASK 0x0200 /* GP4_OP_CFG */3345#define WM8996_GP4_OP_CFG_SHIFT 9 /* GP4_OP_CFG */3346#define WM8996_GP4_OP_CFG_WIDTH 1 /* GP4_OP_CFG */3347#define WM8996_GP4_DB 0x0100 /* GP4_DB */3348#define WM8996_GP4_DB_MASK 0x0100 /* GP4_DB */3349#define WM8996_GP4_DB_SHIFT 8 /* GP4_DB */3350#define WM8996_GP4_DB_WIDTH 1 /* GP4_DB */3351#define WM8996_GP4_LVL 0x0040 /* GP4_LVL */3352#define WM8996_GP4_LVL_MASK 0x0040 /* GP4_LVL */3353#define WM8996_GP4_LVL_SHIFT 6 /* GP4_LVL */3354#define WM8996_GP4_LVL_WIDTH 1 /* GP4_LVL */3355#define WM8996_GP4_FN_MASK 0x000F /* GP4_FN - [3:0] */3356#define WM8996_GP4_FN_SHIFT 0 /* GP4_FN - [3:0] */3357#define WM8996_GP4_FN_WIDTH 4 /* GP4_FN - [3:0] */3358 3359/*3360 * R1796 (0x704) - GPIO 53361 */3362#define WM8996_GP5_DIR 0x8000 /* GP5_DIR */3363#define WM8996_GP5_DIR_MASK 0x8000 /* GP5_DIR */3364#define WM8996_GP5_DIR_SHIFT 15 /* GP5_DIR */3365#define WM8996_GP5_DIR_WIDTH 1 /* GP5_DIR */3366#define WM8996_GP5_PU 0x4000 /* GP5_PU */3367#define WM8996_GP5_PU_MASK 0x4000 /* GP5_PU */3368#define WM8996_GP5_PU_SHIFT 14 /* GP5_PU */3369#define WM8996_GP5_PU_WIDTH 1 /* GP5_PU */3370#define WM8996_GP5_PD 0x2000 /* GP5_PD */3371#define WM8996_GP5_PD_MASK 0x2000 /* GP5_PD */3372#define WM8996_GP5_PD_SHIFT 13 /* GP5_PD */3373#define WM8996_GP5_PD_WIDTH 1 /* GP5_PD */3374#define WM8996_GP5_POL 0x0400 /* GP5_POL */3375#define WM8996_GP5_POL_MASK 0x0400 /* GP5_POL */3376#define WM8996_GP5_POL_SHIFT 10 /* GP5_POL */3377#define WM8996_GP5_POL_WIDTH 1 /* GP5_POL */3378#define WM8996_GP5_OP_CFG 0x0200 /* GP5_OP_CFG */3379#define WM8996_GP5_OP_CFG_MASK 0x0200 /* GP5_OP_CFG */3380#define WM8996_GP5_OP_CFG_SHIFT 9 /* GP5_OP_CFG */3381#define WM8996_GP5_OP_CFG_WIDTH 1 /* GP5_OP_CFG */3382#define WM8996_GP5_DB 0x0100 /* GP5_DB */3383#define WM8996_GP5_DB_MASK 0x0100 /* GP5_DB */3384#define WM8996_GP5_DB_SHIFT 8 /* GP5_DB */3385#define WM8996_GP5_DB_WIDTH 1 /* GP5_DB */3386#define WM8996_GP5_LVL 0x0040 /* GP5_LVL */3387#define WM8996_GP5_LVL_MASK 0x0040 /* GP5_LVL */3388#define WM8996_GP5_LVL_SHIFT 6 /* GP5_LVL */3389#define WM8996_GP5_LVL_WIDTH 1 /* GP5_LVL */3390#define WM8996_GP5_FN_MASK 0x000F /* GP5_FN - [3:0] */3391#define WM8996_GP5_FN_SHIFT 0 /* GP5_FN - [3:0] */3392#define WM8996_GP5_FN_WIDTH 4 /* GP5_FN - [3:0] */3393 3394/*3395 * R1824 (0x720) - Pull Control (1)3396 */3397#define WM8996_DMICDAT2_PD 0x1000 /* DMICDAT2_PD */3398#define WM8996_DMICDAT2_PD_MASK 0x1000 /* DMICDAT2_PD */3399#define WM8996_DMICDAT2_PD_SHIFT 12 /* DMICDAT2_PD */3400#define WM8996_DMICDAT2_PD_WIDTH 1 /* DMICDAT2_PD */3401#define WM8996_DMICDAT1_PD 0x0400 /* DMICDAT1_PD */3402#define WM8996_DMICDAT1_PD_MASK 0x0400 /* DMICDAT1_PD */3403#define WM8996_DMICDAT1_PD_SHIFT 10 /* DMICDAT1_PD */3404#define WM8996_DMICDAT1_PD_WIDTH 1 /* DMICDAT1_PD */3405#define WM8996_MCLK2_PU 0x0200 /* MCLK2_PU */3406#define WM8996_MCLK2_PU_MASK 0x0200 /* MCLK2_PU */3407#define WM8996_MCLK2_PU_SHIFT 9 /* MCLK2_PU */3408#define WM8996_MCLK2_PU_WIDTH 1 /* MCLK2_PU */3409#define WM8996_MCLK2_PD 0x0100 /* MCLK2_PD */3410#define WM8996_MCLK2_PD_MASK 0x0100 /* MCLK2_PD */3411#define WM8996_MCLK2_PD_SHIFT 8 /* MCLK2_PD */3412#define WM8996_MCLK2_PD_WIDTH 1 /* MCLK2_PD */3413#define WM8996_MCLK1_PU 0x0080 /* MCLK1_PU */3414#define WM8996_MCLK1_PU_MASK 0x0080 /* MCLK1_PU */3415#define WM8996_MCLK1_PU_SHIFT 7 /* MCLK1_PU */3416#define WM8996_MCLK1_PU_WIDTH 1 /* MCLK1_PU */3417#define WM8996_MCLK1_PD 0x0040 /* MCLK1_PD */3418#define WM8996_MCLK1_PD_MASK 0x0040 /* MCLK1_PD */3419#define WM8996_MCLK1_PD_SHIFT 6 /* MCLK1_PD */3420#define WM8996_MCLK1_PD_WIDTH 1 /* MCLK1_PD */3421#define WM8996_DACDAT1_PU 0x0020 /* DACDAT1_PU */3422#define WM8996_DACDAT1_PU_MASK 0x0020 /* DACDAT1_PU */3423#define WM8996_DACDAT1_PU_SHIFT 5 /* DACDAT1_PU */3424#define WM8996_DACDAT1_PU_WIDTH 1 /* DACDAT1_PU */3425#define WM8996_DACDAT1_PD 0x0010 /* DACDAT1_PD */3426#define WM8996_DACDAT1_PD_MASK 0x0010 /* DACDAT1_PD */3427#define WM8996_DACDAT1_PD_SHIFT 4 /* DACDAT1_PD */3428#define WM8996_DACDAT1_PD_WIDTH 1 /* DACDAT1_PD */3429#define WM8996_DACLRCLK1_PU 0x0008 /* DACLRCLK1_PU */3430#define WM8996_DACLRCLK1_PU_MASK 0x0008 /* DACLRCLK1_PU */3431#define WM8996_DACLRCLK1_PU_SHIFT 3 /* DACLRCLK1_PU */3432#define WM8996_DACLRCLK1_PU_WIDTH 1 /* DACLRCLK1_PU */3433#define WM8996_DACLRCLK1_PD 0x0004 /* DACLRCLK1_PD */3434#define WM8996_DACLRCLK1_PD_MASK 0x0004 /* DACLRCLK1_PD */3435#define WM8996_DACLRCLK1_PD_SHIFT 2 /* DACLRCLK1_PD */3436#define WM8996_DACLRCLK1_PD_WIDTH 1 /* DACLRCLK1_PD */3437#define WM8996_BCLK1_PU 0x0002 /* BCLK1_PU */3438#define WM8996_BCLK1_PU_MASK 0x0002 /* BCLK1_PU */3439#define WM8996_BCLK1_PU_SHIFT 1 /* BCLK1_PU */3440#define WM8996_BCLK1_PU_WIDTH 1 /* BCLK1_PU */3441#define WM8996_BCLK1_PD 0x0001 /* BCLK1_PD */3442#define WM8996_BCLK1_PD_MASK 0x0001 /* BCLK1_PD */3443#define WM8996_BCLK1_PD_SHIFT 0 /* BCLK1_PD */3444#define WM8996_BCLK1_PD_WIDTH 1 /* BCLK1_PD */3445 3446/*3447 * R1825 (0x721) - Pull Control (2)3448 */3449#define WM8996_LDO1ENA_PD 0x0100 /* LDO1ENA_PD */3450#define WM8996_LDO1ENA_PD_MASK 0x0100 /* LDO1ENA_PD */3451#define WM8996_LDO1ENA_PD_SHIFT 8 /* LDO1ENA_PD */3452#define WM8996_LDO1ENA_PD_WIDTH 1 /* LDO1ENA_PD */3453#define WM8996_ADDR_PD 0x0040 /* ADDR_PD */3454#define WM8996_ADDR_PD_MASK 0x0040 /* ADDR_PD */3455#define WM8996_ADDR_PD_SHIFT 6 /* ADDR_PD */3456#define WM8996_ADDR_PD_WIDTH 1 /* ADDR_PD */3457#define WM8996_DACDAT2_PU 0x0020 /* DACDAT2_PU */3458#define WM8996_DACDAT2_PU_MASK 0x0020 /* DACDAT2_PU */3459#define WM8996_DACDAT2_PU_SHIFT 5 /* DACDAT2_PU */3460#define WM8996_DACDAT2_PU_WIDTH 1 /* DACDAT2_PU */3461#define WM8996_DACDAT2_PD 0x0010 /* DACDAT2_PD */3462#define WM8996_DACDAT2_PD_MASK 0x0010 /* DACDAT2_PD */3463#define WM8996_DACDAT2_PD_SHIFT 4 /* DACDAT2_PD */3464#define WM8996_DACDAT2_PD_WIDTH 1 /* DACDAT2_PD */3465#define WM8996_DACLRCLK2_PU 0x0008 /* DACLRCLK2_PU */3466#define WM8996_DACLRCLK2_PU_MASK 0x0008 /* DACLRCLK2_PU */3467#define WM8996_DACLRCLK2_PU_SHIFT 3 /* DACLRCLK2_PU */3468#define WM8996_DACLRCLK2_PU_WIDTH 1 /* DACLRCLK2_PU */3469#define WM8996_DACLRCLK2_PD 0x0004 /* DACLRCLK2_PD */3470#define WM8996_DACLRCLK2_PD_MASK 0x0004 /* DACLRCLK2_PD */3471#define WM8996_DACLRCLK2_PD_SHIFT 2 /* DACLRCLK2_PD */3472#define WM8996_DACLRCLK2_PD_WIDTH 1 /* DACLRCLK2_PD */3473#define WM8996_BCLK2_PU 0x0002 /* BCLK2_PU */3474#define WM8996_BCLK2_PU_MASK 0x0002 /* BCLK2_PU */3475#define WM8996_BCLK2_PU_SHIFT 1 /* BCLK2_PU */3476#define WM8996_BCLK2_PU_WIDTH 1 /* BCLK2_PU */3477#define WM8996_BCLK2_PD 0x0001 /* BCLK2_PD */3478#define WM8996_BCLK2_PD_MASK 0x0001 /* BCLK2_PD */3479#define WM8996_BCLK2_PD_SHIFT 0 /* BCLK2_PD */3480#define WM8996_BCLK2_PD_WIDTH 1 /* BCLK2_PD */3481 3482/*3483 * R1840 (0x730) - Interrupt Status 13484 */3485#define WM8996_GP5_EINT 0x0010 /* GP5_EINT */3486#define WM8996_GP5_EINT_MASK 0x0010 /* GP5_EINT */3487#define WM8996_GP5_EINT_SHIFT 4 /* GP5_EINT */3488#define WM8996_GP5_EINT_WIDTH 1 /* GP5_EINT */3489#define WM8996_GP4_EINT 0x0008 /* GP4_EINT */3490#define WM8996_GP4_EINT_MASK 0x0008 /* GP4_EINT */3491#define WM8996_GP4_EINT_SHIFT 3 /* GP4_EINT */3492#define WM8996_GP4_EINT_WIDTH 1 /* GP4_EINT */3493#define WM8996_GP3_EINT 0x0004 /* GP3_EINT */3494#define WM8996_GP3_EINT_MASK 0x0004 /* GP3_EINT */3495#define WM8996_GP3_EINT_SHIFT 2 /* GP3_EINT */3496#define WM8996_GP3_EINT_WIDTH 1 /* GP3_EINT */3497#define WM8996_GP2_EINT 0x0002 /* GP2_EINT */3498#define WM8996_GP2_EINT_MASK 0x0002 /* GP2_EINT */3499#define WM8996_GP2_EINT_SHIFT 1 /* GP2_EINT */3500#define WM8996_GP2_EINT_WIDTH 1 /* GP2_EINT */3501#define WM8996_GP1_EINT 0x0001 /* GP1_EINT */3502#define WM8996_GP1_EINT_MASK 0x0001 /* GP1_EINT */3503#define WM8996_GP1_EINT_SHIFT 0 /* GP1_EINT */3504#define WM8996_GP1_EINT_WIDTH 1 /* GP1_EINT */3505 3506/*3507 * R1841 (0x731) - Interrupt Status 23508 */3509#define WM8996_DCS_DONE_23_EINT 0x1000 /* DCS_DONE_23_EINT */3510#define WM8996_DCS_DONE_23_EINT_MASK 0x1000 /* DCS_DONE_23_EINT */3511#define WM8996_DCS_DONE_23_EINT_SHIFT 12 /* DCS_DONE_23_EINT */3512#define WM8996_DCS_DONE_23_EINT_WIDTH 1 /* DCS_DONE_23_EINT */3513#define WM8996_DCS_DONE_01_EINT 0x0800 /* DCS_DONE_01_EINT */3514#define WM8996_DCS_DONE_01_EINT_MASK 0x0800 /* DCS_DONE_01_EINT */3515#define WM8996_DCS_DONE_01_EINT_SHIFT 11 /* DCS_DONE_01_EINT */3516#define WM8996_DCS_DONE_01_EINT_WIDTH 1 /* DCS_DONE_01_EINT */3517#define WM8996_WSEQ_DONE_EINT 0x0400 /* WSEQ_DONE_EINT */3518#define WM8996_WSEQ_DONE_EINT_MASK 0x0400 /* WSEQ_DONE_EINT */3519#define WM8996_WSEQ_DONE_EINT_SHIFT 10 /* WSEQ_DONE_EINT */3520#define WM8996_WSEQ_DONE_EINT_WIDTH 1 /* WSEQ_DONE_EINT */3521#define WM8996_FIFOS_ERR_EINT 0x0200 /* FIFOS_ERR_EINT */3522#define WM8996_FIFOS_ERR_EINT_MASK 0x0200 /* FIFOS_ERR_EINT */3523#define WM8996_FIFOS_ERR_EINT_SHIFT 9 /* FIFOS_ERR_EINT */3524#define WM8996_FIFOS_ERR_EINT_WIDTH 1 /* FIFOS_ERR_EINT */3525#define WM8996_DSP2DRC_SIG_DET_EINT 0x0080 /* DSP2DRC_SIG_DET_EINT */3526#define WM8996_DSP2DRC_SIG_DET_EINT_MASK 0x0080 /* DSP2DRC_SIG_DET_EINT */3527#define WM8996_DSP2DRC_SIG_DET_EINT_SHIFT 7 /* DSP2DRC_SIG_DET_EINT */3528#define WM8996_DSP2DRC_SIG_DET_EINT_WIDTH 1 /* DSP2DRC_SIG_DET_EINT */3529#define WM8996_DSP1DRC_SIG_DET_EINT 0x0040 /* DSP1DRC_SIG_DET_EINT */3530#define WM8996_DSP1DRC_SIG_DET_EINT_MASK 0x0040 /* DSP1DRC_SIG_DET_EINT */3531#define WM8996_DSP1DRC_SIG_DET_EINT_SHIFT 6 /* DSP1DRC_SIG_DET_EINT */3532#define WM8996_DSP1DRC_SIG_DET_EINT_WIDTH 1 /* DSP1DRC_SIG_DET_EINT */3533#define WM8996_FLL_SW_CLK_DONE_EINT 0x0008 /* FLL_SW_CLK_DONE_EINT */3534#define WM8996_FLL_SW_CLK_DONE_EINT_MASK 0x0008 /* FLL_SW_CLK_DONE_EINT */3535#define WM8996_FLL_SW_CLK_DONE_EINT_SHIFT 3 /* FLL_SW_CLK_DONE_EINT */3536#define WM8996_FLL_SW_CLK_DONE_EINT_WIDTH 1 /* FLL_SW_CLK_DONE_EINT */3537#define WM8996_FLL_LOCK_EINT 0x0004 /* FLL_LOCK_EINT */3538#define WM8996_FLL_LOCK_EINT_MASK 0x0004 /* FLL_LOCK_EINT */3539#define WM8996_FLL_LOCK_EINT_SHIFT 2 /* FLL_LOCK_EINT */3540#define WM8996_FLL_LOCK_EINT_WIDTH 1 /* FLL_LOCK_EINT */3541#define WM8996_HP_DONE_EINT 0x0002 /* HP_DONE_EINT */3542#define WM8996_HP_DONE_EINT_MASK 0x0002 /* HP_DONE_EINT */3543#define WM8996_HP_DONE_EINT_SHIFT 1 /* HP_DONE_EINT */3544#define WM8996_HP_DONE_EINT_WIDTH 1 /* HP_DONE_EINT */3545#define WM8996_MICD_EINT 0x0001 /* MICD_EINT */3546#define WM8996_MICD_EINT_MASK 0x0001 /* MICD_EINT */3547#define WM8996_MICD_EINT_SHIFT 0 /* MICD_EINT */3548#define WM8996_MICD_EINT_WIDTH 1 /* MICD_EINT */3549 3550/*3551 * R1842 (0x732) - Interrupt Raw Status 23552 */3553#define WM8996_DCS_DONE_23_STS 0x1000 /* DCS_DONE_23_STS */3554#define WM8996_DCS_DONE_23_STS_MASK 0x1000 /* DCS_DONE_23_STS */3555#define WM8996_DCS_DONE_23_STS_SHIFT 12 /* DCS_DONE_23_STS */3556#define WM8996_DCS_DONE_23_STS_WIDTH 1 /* DCS_DONE_23_STS */3557#define WM8996_DCS_DONE_01_STS 0x0800 /* DCS_DONE_01_STS */3558#define WM8996_DCS_DONE_01_STS_MASK 0x0800 /* DCS_DONE_01_STS */3559#define WM8996_DCS_DONE_01_STS_SHIFT 11 /* DCS_DONE_01_STS */3560#define WM8996_DCS_DONE_01_STS_WIDTH 1 /* DCS_DONE_01_STS */3561#define WM8996_WSEQ_DONE_STS 0x0400 /* WSEQ_DONE_STS */3562#define WM8996_WSEQ_DONE_STS_MASK 0x0400 /* WSEQ_DONE_STS */3563#define WM8996_WSEQ_DONE_STS_SHIFT 10 /* WSEQ_DONE_STS */3564#define WM8996_WSEQ_DONE_STS_WIDTH 1 /* WSEQ_DONE_STS */3565#define WM8996_FIFOS_ERR_STS 0x0200 /* FIFOS_ERR_STS */3566#define WM8996_FIFOS_ERR_STS_MASK 0x0200 /* FIFOS_ERR_STS */3567#define WM8996_FIFOS_ERR_STS_SHIFT 9 /* FIFOS_ERR_STS */3568#define WM8996_FIFOS_ERR_STS_WIDTH 1 /* FIFOS_ERR_STS */3569#define WM8996_DSP2DRC_SIG_DET_STS 0x0080 /* DSP2DRC_SIG_DET_STS */3570#define WM8996_DSP2DRC_SIG_DET_STS_MASK 0x0080 /* DSP2DRC_SIG_DET_STS */3571#define WM8996_DSP2DRC_SIG_DET_STS_SHIFT 7 /* DSP2DRC_SIG_DET_STS */3572#define WM8996_DSP2DRC_SIG_DET_STS_WIDTH 1 /* DSP2DRC_SIG_DET_STS */3573#define WM8996_DSP1DRC_SIG_DET_STS 0x0040 /* DSP1DRC_SIG_DET_STS */3574#define WM8996_DSP1DRC_SIG_DET_STS_MASK 0x0040 /* DSP1DRC_SIG_DET_STS */3575#define WM8996_DSP1DRC_SIG_DET_STS_SHIFT 6 /* DSP1DRC_SIG_DET_STS */3576#define WM8996_DSP1DRC_SIG_DET_STS_WIDTH 1 /* DSP1DRC_SIG_DET_STS */3577#define WM8996_FLL_LOCK_STS 0x0004 /* FLL_LOCK_STS */3578#define WM8996_FLL_LOCK_STS_MASK 0x0004 /* FLL_LOCK_STS */3579#define WM8996_FLL_LOCK_STS_SHIFT 2 /* FLL_LOCK_STS */3580#define WM8996_FLL_LOCK_STS_WIDTH 1 /* FLL_LOCK_STS */3581 3582/*3583 * R1848 (0x738) - Interrupt Status 1 Mask3584 */3585#define WM8996_IM_GP5_EINT 0x0010 /* IM_GP5_EINT */3586#define WM8996_IM_GP5_EINT_MASK 0x0010 /* IM_GP5_EINT */3587#define WM8996_IM_GP5_EINT_SHIFT 4 /* IM_GP5_EINT */3588#define WM8996_IM_GP5_EINT_WIDTH 1 /* IM_GP5_EINT */3589#define WM8996_IM_GP4_EINT 0x0008 /* IM_GP4_EINT */3590#define WM8996_IM_GP4_EINT_MASK 0x0008 /* IM_GP4_EINT */3591#define WM8996_IM_GP4_EINT_SHIFT 3 /* IM_GP4_EINT */3592#define WM8996_IM_GP4_EINT_WIDTH 1 /* IM_GP4_EINT */3593#define WM8996_IM_GP3_EINT 0x0004 /* IM_GP3_EINT */3594#define WM8996_IM_GP3_EINT_MASK 0x0004 /* IM_GP3_EINT */3595#define WM8996_IM_GP3_EINT_SHIFT 2 /* IM_GP3_EINT */3596#define WM8996_IM_GP3_EINT_WIDTH 1 /* IM_GP3_EINT */3597#define WM8996_IM_GP2_EINT 0x0002 /* IM_GP2_EINT */3598#define WM8996_IM_GP2_EINT_MASK 0x0002 /* IM_GP2_EINT */3599#define WM8996_IM_GP2_EINT_SHIFT 1 /* IM_GP2_EINT */3600#define WM8996_IM_GP2_EINT_WIDTH 1 /* IM_GP2_EINT */3601#define WM8996_IM_GP1_EINT 0x0001 /* IM_GP1_EINT */3602#define WM8996_IM_GP1_EINT_MASK 0x0001 /* IM_GP1_EINT */3603#define WM8996_IM_GP1_EINT_SHIFT 0 /* IM_GP1_EINT */3604#define WM8996_IM_GP1_EINT_WIDTH 1 /* IM_GP1_EINT */3605 3606/*3607 * R1849 (0x739) - Interrupt Status 2 Mask3608 */3609#define WM8996_IM_DCS_DONE_23_EINT 0x1000 /* IM_DCS_DONE_23_EINT */3610#define WM8996_IM_DCS_DONE_23_EINT_MASK 0x1000 /* IM_DCS_DONE_23_EINT */3611#define WM8996_IM_DCS_DONE_23_EINT_SHIFT 12 /* IM_DCS_DONE_23_EINT */3612#define WM8996_IM_DCS_DONE_23_EINT_WIDTH 1 /* IM_DCS_DONE_23_EINT */3613#define WM8996_IM_DCS_DONE_01_EINT 0x0800 /* IM_DCS_DONE_01_EINT */3614#define WM8996_IM_DCS_DONE_01_EINT_MASK 0x0800 /* IM_DCS_DONE_01_EINT */3615#define WM8996_IM_DCS_DONE_01_EINT_SHIFT 11 /* IM_DCS_DONE_01_EINT */3616#define WM8996_IM_DCS_DONE_01_EINT_WIDTH 1 /* IM_DCS_DONE_01_EINT */3617#define WM8996_IM_WSEQ_DONE_EINT 0x0400 /* IM_WSEQ_DONE_EINT */3618#define WM8996_IM_WSEQ_DONE_EINT_MASK 0x0400 /* IM_WSEQ_DONE_EINT */3619#define WM8996_IM_WSEQ_DONE_EINT_SHIFT 10 /* IM_WSEQ_DONE_EINT */3620#define WM8996_IM_WSEQ_DONE_EINT_WIDTH 1 /* IM_WSEQ_DONE_EINT */3621#define WM8996_IM_FIFOS_ERR_EINT 0x0200 /* IM_FIFOS_ERR_EINT */3622#define WM8996_IM_FIFOS_ERR_EINT_MASK 0x0200 /* IM_FIFOS_ERR_EINT */3623#define WM8996_IM_FIFOS_ERR_EINT_SHIFT 9 /* IM_FIFOS_ERR_EINT */3624#define WM8996_IM_FIFOS_ERR_EINT_WIDTH 1 /* IM_FIFOS_ERR_EINT */3625#define WM8996_IM_DSP2DRC_SIG_DET_EINT 0x0080 /* IM_DSP2DRC_SIG_DET_EINT */3626#define WM8996_IM_DSP2DRC_SIG_DET_EINT_MASK 0x0080 /* IM_DSP2DRC_SIG_DET_EINT */3627#define WM8996_IM_DSP2DRC_SIG_DET_EINT_SHIFT 7 /* IM_DSP2DRC_SIG_DET_EINT */3628#define WM8996_IM_DSP2DRC_SIG_DET_EINT_WIDTH 1 /* IM_DSP2DRC_SIG_DET_EINT */3629#define WM8996_IM_DSP1DRC_SIG_DET_EINT 0x0040 /* IM_DSP1DRC_SIG_DET_EINT */3630#define WM8996_IM_DSP1DRC_SIG_DET_EINT_MASK 0x0040 /* IM_DSP1DRC_SIG_DET_EINT */3631#define WM8996_IM_DSP1DRC_SIG_DET_EINT_SHIFT 6 /* IM_DSP1DRC_SIG_DET_EINT */3632#define WM8996_IM_DSP1DRC_SIG_DET_EINT_WIDTH 1 /* IM_DSP1DRC_SIG_DET_EINT */3633#define WM8996_IM_FLL_SW_CLK_DONE_EINT 0x0008 /* IM_FLL_SW_CLK_DONE_EINT */3634#define WM8996_IM_FLL_SW_CLK_DONE_EINT_MASK 0x0008 /* IM_FLL_SW_CLK_DONE_EINT */3635#define WM8996_IM_FLL_SW_CLK_DONE_EINT_SHIFT 3 /* IM_FLL_SW_CLK_DONE_EINT */3636#define WM8996_IM_FLL_SW_CLK_DONE_EINT_WIDTH 1 /* IM_FLL_SW_CLK_DONE_EINT */3637#define WM8996_IM_FLL_LOCK_EINT 0x0004 /* IM_FLL_LOCK_EINT */3638#define WM8996_IM_FLL_LOCK_EINT_MASK 0x0004 /* IM_FLL_LOCK_EINT */3639#define WM8996_IM_FLL_LOCK_EINT_SHIFT 2 /* IM_FLL_LOCK_EINT */3640#define WM8996_IM_FLL_LOCK_EINT_WIDTH 1 /* IM_FLL_LOCK_EINT */3641#define WM8996_IM_HP_DONE_EINT 0x0002 /* IM_HP_DONE_EINT */3642#define WM8996_IM_HP_DONE_EINT_MASK 0x0002 /* IM_HP_DONE_EINT */3643#define WM8996_IM_HP_DONE_EINT_SHIFT 1 /* IM_HP_DONE_EINT */3644#define WM8996_IM_HP_DONE_EINT_WIDTH 1 /* IM_HP_DONE_EINT */3645#define WM8996_IM_MICD_EINT 0x0001 /* IM_MICD_EINT */3646#define WM8996_IM_MICD_EINT_MASK 0x0001 /* IM_MICD_EINT */3647#define WM8996_IM_MICD_EINT_SHIFT 0 /* IM_MICD_EINT */3648#define WM8996_IM_MICD_EINT_WIDTH 1 /* IM_MICD_EINT */3649 3650/*3651 * R1856 (0x740) - Interrupt Control3652 */3653#define WM8996_IM_IRQ 0x0001 /* IM_IRQ */3654#define WM8996_IM_IRQ_MASK 0x0001 /* IM_IRQ */3655#define WM8996_IM_IRQ_SHIFT 0 /* IM_IRQ */3656#define WM8996_IM_IRQ_WIDTH 1 /* IM_IRQ */3657 3658/*3659 * R2048 (0x800) - Left PDM Speaker3660 */3661#define WM8996_SPKL_ENA 0x0010 /* SPKL_ENA */3662#define WM8996_SPKL_ENA_MASK 0x0010 /* SPKL_ENA */3663#define WM8996_SPKL_ENA_SHIFT 4 /* SPKL_ENA */3664#define WM8996_SPKL_ENA_WIDTH 1 /* SPKL_ENA */3665#define WM8996_SPKL_MUTE 0x0008 /* SPKL_MUTE */3666#define WM8996_SPKL_MUTE_MASK 0x0008 /* SPKL_MUTE */3667#define WM8996_SPKL_MUTE_SHIFT 3 /* SPKL_MUTE */3668#define WM8996_SPKL_MUTE_WIDTH 1 /* SPKL_MUTE */3669#define WM8996_SPKL_MUTE_ZC 0x0004 /* SPKL_MUTE_ZC */3670#define WM8996_SPKL_MUTE_ZC_MASK 0x0004 /* SPKL_MUTE_ZC */3671#define WM8996_SPKL_MUTE_ZC_SHIFT 2 /* SPKL_MUTE_ZC */3672#define WM8996_SPKL_MUTE_ZC_WIDTH 1 /* SPKL_MUTE_ZC */3673#define WM8996_SPKL_SRC_MASK 0x0003 /* SPKL_SRC - [1:0] */3674#define WM8996_SPKL_SRC_SHIFT 0 /* SPKL_SRC - [1:0] */3675#define WM8996_SPKL_SRC_WIDTH 2 /* SPKL_SRC - [1:0] */3676 3677/*3678 * R2049 (0x801) - Right PDM Speaker3679 */3680#define WM8996_SPKR_ENA 0x0010 /* SPKR_ENA */3681#define WM8996_SPKR_ENA_MASK 0x0010 /* SPKR_ENA */3682#define WM8996_SPKR_ENA_SHIFT 4 /* SPKR_ENA */3683#define WM8996_SPKR_ENA_WIDTH 1 /* SPKR_ENA */3684#define WM8996_SPKR_MUTE 0x0008 /* SPKR_MUTE */3685#define WM8996_SPKR_MUTE_MASK 0x0008 /* SPKR_MUTE */3686#define WM8996_SPKR_MUTE_SHIFT 3 /* SPKR_MUTE */3687#define WM8996_SPKR_MUTE_WIDTH 1 /* SPKR_MUTE */3688#define WM8996_SPKR_MUTE_ZC 0x0004 /* SPKR_MUTE_ZC */3689#define WM8996_SPKR_MUTE_ZC_MASK 0x0004 /* SPKR_MUTE_ZC */3690#define WM8996_SPKR_MUTE_ZC_SHIFT 2 /* SPKR_MUTE_ZC */3691#define WM8996_SPKR_MUTE_ZC_WIDTH 1 /* SPKR_MUTE_ZC */3692#define WM8996_SPKR_SRC_MASK 0x0003 /* SPKR_SRC - [1:0] */3693#define WM8996_SPKR_SRC_SHIFT 0 /* SPKR_SRC - [1:0] */3694#define WM8996_SPKR_SRC_WIDTH 2 /* SPKR_SRC - [1:0] */3695 3696/*3697 * R2050 (0x802) - PDM Speaker Mute Sequence3698 */3699#define WM8996_SPK_MUTE_ENDIAN 0x0100 /* SPK_MUTE_ENDIAN */3700#define WM8996_SPK_MUTE_ENDIAN_MASK 0x0100 /* SPK_MUTE_ENDIAN */3701#define WM8996_SPK_MUTE_ENDIAN_SHIFT 8 /* SPK_MUTE_ENDIAN */3702#define WM8996_SPK_MUTE_ENDIAN_WIDTH 1 /* SPK_MUTE_ENDIAN */3703#define WM8996_SPK_MUTE_SEQ1_MASK 0x00FF /* SPK_MUTE_SEQ1 - [7:0] */3704#define WM8996_SPK_MUTE_SEQ1_SHIFT 0 /* SPK_MUTE_SEQ1 - [7:0] */3705#define WM8996_SPK_MUTE_SEQ1_WIDTH 8 /* SPK_MUTE_SEQ1 - [7:0] */3706 3707/*3708 * R2051 (0x803) - PDM Speaker Volume3709 */3710#define WM8996_SPKR_VOL_MASK 0x00F0 /* SPKR_VOL - [7:4] */3711#define WM8996_SPKR_VOL_SHIFT 4 /* SPKR_VOL - [7:4] */3712#define WM8996_SPKR_VOL_WIDTH 4 /* SPKR_VOL - [7:4] */3713#define WM8996_SPKL_VOL_MASK 0x000F /* SPKL_VOL - [3:0] */3714#define WM8996_SPKL_VOL_SHIFT 0 /* SPKL_VOL - [3:0] */3715#define WM8996_SPKL_VOL_WIDTH 4 /* SPKL_VOL - [3:0] */3716 3717#endif3718