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1/* SPDX-License-Identifier: GPL-2.0 */2/*3 * mpc8610-pcm.h - ALSA PCM interface for the Freescale MPC8610 SoC4 */5 6#ifndef _MPC8610_PCM_H7#define _MPC8610_PCM_H8 9struct ccsr_dma {10 u8 res0[0x100];11 struct ccsr_dma_channel {12 __be32 mr; /* Mode register */13 __be32 sr; /* Status register */14 __be32 eclndar; /* Current link descriptor extended addr reg */15 __be32 clndar; /* Current link descriptor address register */16 __be32 satr; /* Source attributes register */17 __be32 sar; /* Source address register */18 __be32 datr; /* Destination attributes register */19 __be32 dar; /* Destination address register */20 __be32 bcr; /* Byte count register */21 __be32 enlndar; /* Next link descriptor extended address reg */22 __be32 nlndar; /* Next link descriptor address register */23 u8 res1[4];24 __be32 eclsdar; /* Current list descriptor extended addr reg */25 __be32 clsdar; /* Current list descriptor address register */26 __be32 enlsdar; /* Next list descriptor extended address reg */27 __be32 nlsdar; /* Next list descriptor address register */28 __be32 ssr; /* Source stride register */29 __be32 dsr; /* Destination stride register */30 u8 res2[0x38];31 } channel[4];32 __be32 dgsr;33};34 35#define CCSR_DMA_MR_BWC_DISABLED 0x0F00000036#define CCSR_DMA_MR_BWC_SHIFT 2437#define CCSR_DMA_MR_BWC_MASK 0x0F00000038#define CCSR_DMA_MR_BWC(x) \39 ((ilog2(x) << CCSR_DMA_MR_BWC_SHIFT) & CCSR_DMA_MR_BWC_MASK)40#define CCSR_DMA_MR_EMP_EN 0x0020000041#define CCSR_DMA_MR_EMS_EN 0x0004000042#define CCSR_DMA_MR_DAHTS_MASK 0x0003000043#define CCSR_DMA_MR_DAHTS_1 0x0000000044#define CCSR_DMA_MR_DAHTS_2 0x0001000045#define CCSR_DMA_MR_DAHTS_4 0x0002000046#define CCSR_DMA_MR_DAHTS_8 0x0003000047#define CCSR_DMA_MR_SAHTS_MASK 0x0000C00048#define CCSR_DMA_MR_SAHTS_1 0x0000000049#define CCSR_DMA_MR_SAHTS_2 0x0000400050#define CCSR_DMA_MR_SAHTS_4 0x0000800051#define CCSR_DMA_MR_SAHTS_8 0x0000C00052#define CCSR_DMA_MR_DAHE 0x0000200053#define CCSR_DMA_MR_SAHE 0x0000100054#define CCSR_DMA_MR_SRW 0x0000040055#define CCSR_DMA_MR_EOSIE 0x0000020056#define CCSR_DMA_MR_EOLNIE 0x0000010057#define CCSR_DMA_MR_EOLSIE 0x0000008058#define CCSR_DMA_MR_EIE 0x0000004059#define CCSR_DMA_MR_XFE 0x0000002060#define CCSR_DMA_MR_CDSM_SWSM 0x0000001061#define CCSR_DMA_MR_CA 0x0000000862#define CCSR_DMA_MR_CTM 0x0000000463#define CCSR_DMA_MR_CC 0x0000000264#define CCSR_DMA_MR_CS 0x0000000165 66#define CCSR_DMA_SR_TE 0x0000008067#define CCSR_DMA_SR_CH 0x0000002068#define CCSR_DMA_SR_PE 0x0000001069#define CCSR_DMA_SR_EOLNI 0x0000000870#define CCSR_DMA_SR_CB 0x0000000471#define CCSR_DMA_SR_EOSI 0x0000000272#define CCSR_DMA_SR_EOLSI 0x0000000173 74/* ECLNDAR takes bits 32-36 of the CLNDAR register */75static inline u32 CCSR_DMA_ECLNDAR_ADDR(u64 x)76{77 return (x >> 32) & 0xf;78}79 80#define CCSR_DMA_CLNDAR_ADDR(x) ((x) & 0xFFFFFFFE)81#define CCSR_DMA_CLNDAR_EOSIE 0x0000000882 83/* SATR and DATR, combined */84#define CCSR_DMA_ATR_PBATMU 0x2000000085#define CCSR_DMA_ATR_TFLOWLVL_0 0x0000000086#define CCSR_DMA_ATR_TFLOWLVL_1 0x0600000087#define CCSR_DMA_ATR_TFLOWLVL_2 0x0800000088#define CCSR_DMA_ATR_TFLOWLVL_3 0x0C00000089#define CCSR_DMA_ATR_PCIORDER 0x0200000090#define CCSR_DMA_ATR_SME 0x0100000091#define CCSR_DMA_ATR_NOSNOOP 0x0004000092#define CCSR_DMA_ATR_SNOOP 0x0005000093#define CCSR_DMA_ATR_ESAD_MASK 0x0000000F94 95/**96 * List Descriptor for extended chaining mode DMA operations.97 *98 * The CLSDAR register points to the first (in a linked-list) List99 * Descriptor. Each object must be aligned on a 32-byte boundary. Each100 * list descriptor points to a linked-list of link Descriptors.101 */102struct fsl_dma_list_descriptor {103 __be64 next; /* Address of next list descriptor */104 __be64 first_link; /* Address of first link descriptor */105 __be32 source; /* Source stride */106 __be32 dest; /* Destination stride */107 u8 res[8]; /* Reserved */108} __attribute__ ((aligned(32), packed));109 110/**111 * Link Descriptor for basic and extended chaining mode DMA operations.112 *113 * A Link Descriptor points to a single DMA buffer. Each link descriptor114 * must be aligned on a 32-byte boundary.115 */116struct fsl_dma_link_descriptor {117 __be32 source_attr; /* Programmed into SATR register */118 __be32 source_addr; /* Programmed into SAR register */119 __be32 dest_attr; /* Programmed into DATR register */120 __be32 dest_addr; /* Programmed into DAR register */121 __be64 next; /* Address of next link descriptor */122 __be32 count; /* Byte count */123 u8 res[4]; /* Reserved */124} __attribute__ ((aligned(32), packed));125 126#endif127