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1/* SPDX-License-Identifier: GPL-2.0 */2/*3 * fsl_esai.h - ALSA ESAI interface for the Freescale i.MX SoC4 *5 * Copyright (C) 2014 Freescale Semiconductor, Inc.6 *7 * Author: Nicolin Chen <Guangyu.Chen@freescale.com>8 */9 10#ifndef _FSL_ESAI_DAI_H11#define _FSL_ESAI_DAI_H12 13/* ESAI Register Map */14#define REG_ESAI_ETDR 0x0015#define REG_ESAI_ERDR 0x0416#define REG_ESAI_ECR 0x0817#define REG_ESAI_ESR 0x0C18#define REG_ESAI_TFCR 0x1019#define REG_ESAI_TFSR 0x1420#define REG_ESAI_RFCR 0x1821#define REG_ESAI_RFSR 0x1C22#define REG_ESAI_xFCR(tx) (tx ? REG_ESAI_TFCR : REG_ESAI_RFCR)23#define REG_ESAI_xFSR(tx) (tx ? REG_ESAI_TFSR : REG_ESAI_RFSR)24#define REG_ESAI_TX0 0x8025#define REG_ESAI_TX1 0x8426#define REG_ESAI_TX2 0x8827#define REG_ESAI_TX3 0x8C28#define REG_ESAI_TX4 0x9029#define REG_ESAI_TX5 0x9430#define REG_ESAI_TSR 0x9831#define REG_ESAI_RX0 0xA032#define REG_ESAI_RX1 0xA433#define REG_ESAI_RX2 0xA834#define REG_ESAI_RX3 0xAC35#define REG_ESAI_SAISR 0xCC36#define REG_ESAI_SAICR 0xD037#define REG_ESAI_TCR 0xD438#define REG_ESAI_TCCR 0xD839#define REG_ESAI_RCR 0xDC40#define REG_ESAI_RCCR 0xE041#define REG_ESAI_xCR(tx) (tx ? REG_ESAI_TCR : REG_ESAI_RCR)42#define REG_ESAI_xCCR(tx) (tx ? REG_ESAI_TCCR : REG_ESAI_RCCR)43#define REG_ESAI_TSMA 0xE444#define REG_ESAI_TSMB 0xE845#define REG_ESAI_RSMA 0xEC46#define REG_ESAI_RSMB 0xF047#define REG_ESAI_xSMA(tx) (tx ? REG_ESAI_TSMA : REG_ESAI_RSMA)48#define REG_ESAI_xSMB(tx) (tx ? REG_ESAI_TSMB : REG_ESAI_RSMB)49#define REG_ESAI_PRRC 0xF850#define REG_ESAI_PCRC 0xFC51 52/* ESAI Control Register -- REG_ESAI_ECR 0x8 */53#define ESAI_ECR_ETI_SHIFT 1954#define ESAI_ECR_ETI_MASK (1 << ESAI_ECR_ETI_SHIFT)55#define ESAI_ECR_ETI (1 << ESAI_ECR_ETI_SHIFT)56#define ESAI_ECR_ETO_SHIFT 1857#define ESAI_ECR_ETO_MASK (1 << ESAI_ECR_ETO_SHIFT)58#define ESAI_ECR_ETO (1 << ESAI_ECR_ETO_SHIFT)59#define ESAI_ECR_ERI_SHIFT 1760#define ESAI_ECR_ERI_MASK (1 << ESAI_ECR_ERI_SHIFT)61#define ESAI_ECR_ERI (1 << ESAI_ECR_ERI_SHIFT)62#define ESAI_ECR_ERO_SHIFT 1663#define ESAI_ECR_ERO_MASK (1 << ESAI_ECR_ERO_SHIFT)64#define ESAI_ECR_ERO (1 << ESAI_ECR_ERO_SHIFT)65#define ESAI_ECR_ERST_SHIFT 166#define ESAI_ECR_ERST_MASK (1 << ESAI_ECR_ERST_SHIFT)67#define ESAI_ECR_ERST (1 << ESAI_ECR_ERST_SHIFT)68#define ESAI_ECR_ESAIEN_SHIFT 069#define ESAI_ECR_ESAIEN_MASK (1 << ESAI_ECR_ESAIEN_SHIFT)70#define ESAI_ECR_ESAIEN (1 << ESAI_ECR_ESAIEN_SHIFT)71 72/* ESAI Status Register -- REG_ESAI_ESR 0xC */73#define ESAI_ESR_TINIT_SHIFT 1074#define ESAI_ESR_TINIT_MASK (1 << ESAI_ESR_TINIT_SHIFT)75#define ESAI_ESR_TINIT (1 << ESAI_ESR_TINIT_SHIFT)76#define ESAI_ESR_RFF_SHIFT 977#define ESAI_ESR_RFF_MASK (1 << ESAI_ESR_RFF_SHIFT)78#define ESAI_ESR_RFF (1 << ESAI_ESR_RFF_SHIFT)79#define ESAI_ESR_TFE_SHIFT 880#define ESAI_ESR_TFE_MASK (1 << ESAI_ESR_TFE_SHIFT)81#define ESAI_ESR_TFE (1 << ESAI_ESR_TFE_SHIFT)82#define ESAI_ESR_TLS_SHIFT 783#define ESAI_ESR_TLS_MASK (1 << ESAI_ESR_TLS_SHIFT)84#define ESAI_ESR_TLS (1 << ESAI_ESR_TLS_SHIFT)85#define ESAI_ESR_TDE_SHIFT 686#define ESAI_ESR_TDE_MASK (1 << ESAI_ESR_TDE_SHIFT)87#define ESAI_ESR_TDE (1 << ESAI_ESR_TDE_SHIFT)88#define ESAI_ESR_TED_SHIFT 589#define ESAI_ESR_TED_MASK (1 << ESAI_ESR_TED_SHIFT)90#define ESAI_ESR_TED (1 << ESAI_ESR_TED_SHIFT)91#define ESAI_ESR_TD_SHIFT 492#define ESAI_ESR_TD_MASK (1 << ESAI_ESR_TD_SHIFT)93#define ESAI_ESR_TD (1 << ESAI_ESR_TD_SHIFT)94#define ESAI_ESR_RLS_SHIFT 395#define ESAI_ESR_RLS_MASK (1 << ESAI_ESR_RLS_SHIFT)96#define ESAI_ESR_RLS (1 << ESAI_ESR_RLS_SHIFT)97#define ESAI_ESR_RDE_SHIFT 298#define ESAI_ESR_RDE_MASK (1 << ESAI_ESR_RDE_SHIFT)99#define ESAI_ESR_RDE (1 << ESAI_ESR_RDE_SHIFT)100#define ESAI_ESR_RED_SHIFT 1101#define ESAI_ESR_RED_MASK (1 << ESAI_ESR_RED_SHIFT)102#define ESAI_ESR_RED (1 << ESAI_ESR_RED_SHIFT)103#define ESAI_ESR_RD_SHIFT 0104#define ESAI_ESR_RD_MASK (1 << ESAI_ESR_RD_SHIFT)105#define ESAI_ESR_RD (1 << ESAI_ESR_RD_SHIFT)106 107/*108 * Transmit FIFO Configuration Register -- REG_ESAI_TFCR 0x10109 * Receive FIFO Configuration Register -- REG_ESAI_RFCR 0x18110 */111#define ESAI_xFCR_TIEN_SHIFT 19112#define ESAI_xFCR_TIEN_MASK (1 << ESAI_xFCR_TIEN_SHIFT)113#define ESAI_xFCR_TIEN (1 << ESAI_xFCR_TIEN_SHIFT)114#define ESAI_xFCR_REXT_SHIFT 19115#define ESAI_xFCR_REXT_MASK (1 << ESAI_xFCR_REXT_SHIFT)116#define ESAI_xFCR_REXT (1 << ESAI_xFCR_REXT_SHIFT)117#define ESAI_xFCR_xWA_SHIFT 16118#define ESAI_xFCR_xWA_WIDTH 3119#define ESAI_xFCR_xWA_MASK (((1 << ESAI_xFCR_xWA_WIDTH) - 1) << ESAI_xFCR_xWA_SHIFT)120#define ESAI_xFCR_xWA(v) (((8 - ((v) >> 2)) << ESAI_xFCR_xWA_SHIFT) & ESAI_xFCR_xWA_MASK)121#define ESAI_xFCR_xFWM_SHIFT 8122#define ESAI_xFCR_xFWM_WIDTH 8123#define ESAI_xFCR_xFWM_MASK (((1 << ESAI_xFCR_xFWM_WIDTH) - 1) << ESAI_xFCR_xFWM_SHIFT)124#define ESAI_xFCR_xFWM(v) ((((v) - 1) << ESAI_xFCR_xFWM_SHIFT) & ESAI_xFCR_xFWM_MASK)125#define ESAI_xFCR_xE_SHIFT 2126#define ESAI_xFCR_TE_WIDTH 6127#define ESAI_xFCR_RE_WIDTH 4128#define ESAI_xFCR_TE_MASK (((1 << ESAI_xFCR_TE_WIDTH) - 1) << ESAI_xFCR_xE_SHIFT)129#define ESAI_xFCR_RE_MASK (((1 << ESAI_xFCR_RE_WIDTH) - 1) << ESAI_xFCR_xE_SHIFT)130#define ESAI_xFCR_TE(x) ((ESAI_xFCR_TE_MASK >> (ESAI_xFCR_TE_WIDTH - x)) & ESAI_xFCR_TE_MASK)131#define ESAI_xFCR_RE(x) ((ESAI_xFCR_RE_MASK >> (ESAI_xFCR_RE_WIDTH - x)) & ESAI_xFCR_RE_MASK)132#define ESAI_xFCR_xFR_SHIFT 1133#define ESAI_xFCR_xFR_MASK (1 << ESAI_xFCR_xFR_SHIFT)134#define ESAI_xFCR_xFR (1 << ESAI_xFCR_xFR_SHIFT)135#define ESAI_xFCR_xFEN_SHIFT 0136#define ESAI_xFCR_xFEN_MASK (1 << ESAI_xFCR_xFEN_SHIFT)137#define ESAI_xFCR_xFEN (1 << ESAI_xFCR_xFEN_SHIFT)138 139/*140 * Transmit FIFO Status Register -- REG_ESAI_TFSR 0x14141 * Receive FIFO Status Register --REG_ESAI_RFSR 0x1C142 */143#define ESAI_xFSR_NTFO_SHIFT 12144#define ESAI_xFSR_NRFI_SHIFT 12145#define ESAI_xFSR_NTFI_SHIFT 8146#define ESAI_xFSR_NRFO_SHIFT 8147#define ESAI_xFSR_NTFx_WIDTH 3148#define ESAI_xFSR_NRFx_WIDTH 2149#define ESAI_xFSR_NTFO_MASK (((1 << ESAI_xFSR_NTFx_WIDTH) - 1) << ESAI_xFSR_NTFO_SHIFT)150#define ESAI_xFSR_NTFI_MASK (((1 << ESAI_xFSR_NTFx_WIDTH) - 1) << ESAI_xFSR_NTFI_SHIFT)151#define ESAI_xFSR_NRFO_MASK (((1 << ESAI_xFSR_NRFx_WIDTH) - 1) << ESAI_xFSR_NRFO_SHIFT)152#define ESAI_xFSR_NRFI_MASK (((1 << ESAI_xFSR_NRFx_WIDTH) - 1) << ESAI_xFSR_NRFI_SHIFT)153#define ESAI_xFSR_xFCNT_SHIFT 0154#define ESAI_xFSR_xFCNT_WIDTH 8155#define ESAI_xFSR_xFCNT_MASK (((1 << ESAI_xFSR_xFCNT_WIDTH) - 1) << ESAI_xFSR_xFCNT_SHIFT)156 157/* ESAI Transmit Slot Register -- REG_ESAI_TSR 0x98 */158#define ESAI_TSR_SHIFT 0159#define ESAI_TSR_WIDTH 24160#define ESAI_TSR_MASK (((1 << ESAI_TSR_WIDTH) - 1) << ESAI_TSR_SHIFT)161 162/* Serial Audio Interface Status Register -- REG_ESAI_SAISR 0xCC */163#define ESAI_SAISR_TODFE_SHIFT 17164#define ESAI_SAISR_TODFE_MASK (1 << ESAI_SAISR_TODFE_SHIFT)165#define ESAI_SAISR_TODFE (1 << ESAI_SAISR_TODFE_SHIFT)166#define ESAI_SAISR_TEDE_SHIFT 16167#define ESAI_SAISR_TEDE_MASK (1 << ESAI_SAISR_TEDE_SHIFT)168#define ESAI_SAISR_TEDE (1 << ESAI_SAISR_TEDE_SHIFT)169#define ESAI_SAISR_TDE_SHIFT 15170#define ESAI_SAISR_TDE_MASK (1 << ESAI_SAISR_TDE_SHIFT)171#define ESAI_SAISR_TDE (1 << ESAI_SAISR_TDE_SHIFT)172#define ESAI_SAISR_TUE_SHIFT 14173#define ESAI_SAISR_TUE_MASK (1 << ESAI_SAISR_TUE_SHIFT)174#define ESAI_SAISR_TUE (1 << ESAI_SAISR_TUE_SHIFT)175#define ESAI_SAISR_TFS_SHIFT 13176#define ESAI_SAISR_TFS_MASK (1 << ESAI_SAISR_TFS_SHIFT)177#define ESAI_SAISR_TFS (1 << ESAI_SAISR_TFS_SHIFT)178#define ESAI_SAISR_RODF_SHIFT 10179#define ESAI_SAISR_RODF_MASK (1 << ESAI_SAISR_RODF_SHIFT)180#define ESAI_SAISR_RODF (1 << ESAI_SAISR_RODF_SHIFT)181#define ESAI_SAISR_REDF_SHIFT 9182#define ESAI_SAISR_REDF_MASK (1 << ESAI_SAISR_REDF_SHIFT)183#define ESAI_SAISR_REDF (1 << ESAI_SAISR_REDF_SHIFT)184#define ESAI_SAISR_RDF_SHIFT 8185#define ESAI_SAISR_RDF_MASK (1 << ESAI_SAISR_RDF_SHIFT)186#define ESAI_SAISR_RDF (1 << ESAI_SAISR_RDF_SHIFT)187#define ESAI_SAISR_ROE_SHIFT 7188#define ESAI_SAISR_ROE_MASK (1 << ESAI_SAISR_ROE_SHIFT)189#define ESAI_SAISR_ROE (1 << ESAI_SAISR_ROE_SHIFT)190#define ESAI_SAISR_RFS_SHIFT 6191#define ESAI_SAISR_RFS_MASK (1 << ESAI_SAISR_RFS_SHIFT)192#define ESAI_SAISR_RFS (1 << ESAI_SAISR_RFS_SHIFT)193#define ESAI_SAISR_IF2_SHIFT 2194#define ESAI_SAISR_IF2_MASK (1 << ESAI_SAISR_IF2_SHIFT)195#define ESAI_SAISR_IF2 (1 << ESAI_SAISR_IF2_SHIFT)196#define ESAI_SAISR_IF1_SHIFT 1197#define ESAI_SAISR_IF1_MASK (1 << ESAI_SAISR_IF1_SHIFT)198#define ESAI_SAISR_IF1 (1 << ESAI_SAISR_IF1_SHIFT)199#define ESAI_SAISR_IF0_SHIFT 0200#define ESAI_SAISR_IF0_MASK (1 << ESAI_SAISR_IF0_SHIFT)201#define ESAI_SAISR_IF0 (1 << ESAI_SAISR_IF0_SHIFT)202 203/* Serial Audio Interface Control Register -- REG_ESAI_SAICR 0xD0 */204#define ESAI_SAICR_ALC_SHIFT 8205#define ESAI_SAICR_ALC_MASK (1 << ESAI_SAICR_ALC_SHIFT)206#define ESAI_SAICR_ALC (1 << ESAI_SAICR_ALC_SHIFT)207#define ESAI_SAICR_TEBE_SHIFT 7208#define ESAI_SAICR_TEBE_MASK (1 << ESAI_SAICR_TEBE_SHIFT)209#define ESAI_SAICR_TEBE (1 << ESAI_SAICR_TEBE_SHIFT)210#define ESAI_SAICR_SYNC_SHIFT 6211#define ESAI_SAICR_SYNC_MASK (1 << ESAI_SAICR_SYNC_SHIFT)212#define ESAI_SAICR_SYNC (1 << ESAI_SAICR_SYNC_SHIFT)213#define ESAI_SAICR_OF2_SHIFT 2214#define ESAI_SAICR_OF2_MASK (1 << ESAI_SAICR_OF2_SHIFT)215#define ESAI_SAICR_OF2 (1 << ESAI_SAICR_OF2_SHIFT)216#define ESAI_SAICR_OF1_SHIFT 1217#define ESAI_SAICR_OF1_MASK (1 << ESAI_SAICR_OF1_SHIFT)218#define ESAI_SAICR_OF1 (1 << ESAI_SAICR_OF1_SHIFT)219#define ESAI_SAICR_OF0_SHIFT 0220#define ESAI_SAICR_OF0_MASK (1 << ESAI_SAICR_OF0_SHIFT)221#define ESAI_SAICR_OF0 (1 << ESAI_SAICR_OF0_SHIFT)222 223/*224 * Transmit Control Register -- REG_ESAI_TCR 0xD4225 * Receive Control Register -- REG_ESAI_RCR 0xDC226 */227#define ESAI_xCR_xLIE_SHIFT 23228#define ESAI_xCR_xLIE_MASK (1 << ESAI_xCR_xLIE_SHIFT)229#define ESAI_xCR_xLIE (1 << ESAI_xCR_xLIE_SHIFT)230#define ESAI_xCR_xIE_SHIFT 22231#define ESAI_xCR_xIE_MASK (1 << ESAI_xCR_xIE_SHIFT)232#define ESAI_xCR_xIE (1 << ESAI_xCR_xIE_SHIFT)233#define ESAI_xCR_xEDIE_SHIFT 21234#define ESAI_xCR_xEDIE_MASK (1 << ESAI_xCR_xEDIE_SHIFT)235#define ESAI_xCR_xEDIE (1 << ESAI_xCR_xEDIE_SHIFT)236#define ESAI_xCR_xEIE_SHIFT 20237#define ESAI_xCR_xEIE_MASK (1 << ESAI_xCR_xEIE_SHIFT)238#define ESAI_xCR_xEIE (1 << ESAI_xCR_xEIE_SHIFT)239#define ESAI_xCR_xPR_SHIFT 19240#define ESAI_xCR_xPR_MASK (1 << ESAI_xCR_xPR_SHIFT)241#define ESAI_xCR_xPR (1 << ESAI_xCR_xPR_SHIFT)242#define ESAI_xCR_PADC_SHIFT 17243#define ESAI_xCR_PADC_MASK (1 << ESAI_xCR_PADC_SHIFT)244#define ESAI_xCR_PADC (1 << ESAI_xCR_PADC_SHIFT)245#define ESAI_xCR_xFSR_SHIFT 16246#define ESAI_xCR_xFSR_MASK (1 << ESAI_xCR_xFSR_SHIFT)247#define ESAI_xCR_xFSR (1 << ESAI_xCR_xFSR_SHIFT)248#define ESAI_xCR_xFSL_SHIFT 15249#define ESAI_xCR_xFSL_MASK (1 << ESAI_xCR_xFSL_SHIFT)250#define ESAI_xCR_xFSL (1 << ESAI_xCR_xFSL_SHIFT)251#define ESAI_xCR_xSWS_SHIFT 10252#define ESAI_xCR_xSWS_WIDTH 5253#define ESAI_xCR_xSWS_MASK (((1 << ESAI_xCR_xSWS_WIDTH) - 1) << ESAI_xCR_xSWS_SHIFT)254#define ESAI_xCR_xSWS(s, w) ((w < 24 ? (s - w + ((w - 8) >> 2)) : (s < 32 ? 0x1e : 0x1f)) << ESAI_xCR_xSWS_SHIFT)255#define ESAI_xCR_xMOD_SHIFT 8256#define ESAI_xCR_xMOD_WIDTH 2257#define ESAI_xCR_xMOD_MASK (((1 << ESAI_xCR_xMOD_WIDTH) - 1) << ESAI_xCR_xMOD_SHIFT)258#define ESAI_xCR_xMOD_ONDEMAND (0x1 << ESAI_xCR_xMOD_SHIFT)259#define ESAI_xCR_xMOD_NETWORK (0x1 << ESAI_xCR_xMOD_SHIFT)260#define ESAI_xCR_xMOD_AC97 (0x3 << ESAI_xCR_xMOD_SHIFT)261#define ESAI_xCR_xWA_SHIFT 7262#define ESAI_xCR_xWA_MASK (1 << ESAI_xCR_xWA_SHIFT)263#define ESAI_xCR_xWA (1 << ESAI_xCR_xWA_SHIFT)264#define ESAI_xCR_xSHFD_SHIFT 6265#define ESAI_xCR_xSHFD_MASK (1 << ESAI_xCR_xSHFD_SHIFT)266#define ESAI_xCR_xSHFD (1 << ESAI_xCR_xSHFD_SHIFT)267#define ESAI_xCR_xE_SHIFT 0268#define ESAI_xCR_TE_WIDTH 6269#define ESAI_xCR_RE_WIDTH 4270#define ESAI_xCR_TE_MASK (((1 << ESAI_xCR_TE_WIDTH) - 1) << ESAI_xCR_xE_SHIFT)271#define ESAI_xCR_RE_MASK (((1 << ESAI_xCR_RE_WIDTH) - 1) << ESAI_xCR_xE_SHIFT)272#define ESAI_xCR_TE(x) ((ESAI_xCR_TE_MASK >> (ESAI_xCR_TE_WIDTH - x)) & ESAI_xCR_TE_MASK)273#define ESAI_xCR_RE(x) ((ESAI_xCR_RE_MASK >> (ESAI_xCR_RE_WIDTH - x)) & ESAI_xCR_RE_MASK)274 275/*276 * Transmit Clock Control Register -- REG_ESAI_TCCR 0xD8277 * Receive Clock Control Register -- REG_ESAI_RCCR 0xE0278 */279#define ESAI_xCCR_xHCKD_SHIFT 23280#define ESAI_xCCR_xHCKD_MASK (1 << ESAI_xCCR_xHCKD_SHIFT)281#define ESAI_xCCR_xHCKD (1 << ESAI_xCCR_xHCKD_SHIFT)282#define ESAI_xCCR_xFSD_SHIFT 22283#define ESAI_xCCR_xFSD_MASK (1 << ESAI_xCCR_xFSD_SHIFT)284#define ESAI_xCCR_xFSD (1 << ESAI_xCCR_xFSD_SHIFT)285#define ESAI_xCCR_xCKD_SHIFT 21286#define ESAI_xCCR_xCKD_MASK (1 << ESAI_xCCR_xCKD_SHIFT)287#define ESAI_xCCR_xCKD (1 << ESAI_xCCR_xCKD_SHIFT)288#define ESAI_xCCR_xHCKP_SHIFT 20289#define ESAI_xCCR_xHCKP_MASK (1 << ESAI_xCCR_xHCKP_SHIFT)290#define ESAI_xCCR_xHCKP (1 << ESAI_xCCR_xHCKP_SHIFT)291#define ESAI_xCCR_xFSP_SHIFT 19292#define ESAI_xCCR_xFSP_MASK (1 << ESAI_xCCR_xFSP_SHIFT)293#define ESAI_xCCR_xFSP (1 << ESAI_xCCR_xFSP_SHIFT)294#define ESAI_xCCR_xCKP_SHIFT 18295#define ESAI_xCCR_xCKP_MASK (1 << ESAI_xCCR_xCKP_SHIFT)296#define ESAI_xCCR_xCKP (1 << ESAI_xCCR_xCKP_SHIFT)297#define ESAI_xCCR_xFP_SHIFT 14298#define ESAI_xCCR_xFP_WIDTH 4299#define ESAI_xCCR_xFP_MASK (((1 << ESAI_xCCR_xFP_WIDTH) - 1) << ESAI_xCCR_xFP_SHIFT)300#define ESAI_xCCR_xFP(v) ((((v) - 1) << ESAI_xCCR_xFP_SHIFT) & ESAI_xCCR_xFP_MASK)301#define ESAI_xCCR_xDC_SHIFT 9302#define ESAI_xCCR_xDC_WIDTH 5303#define ESAI_xCCR_xDC_MASK (((1 << ESAI_xCCR_xDC_WIDTH) - 1) << ESAI_xCCR_xDC_SHIFT)304#define ESAI_xCCR_xDC(v) ((((v) - 1) << ESAI_xCCR_xDC_SHIFT) & ESAI_xCCR_xDC_MASK)305#define ESAI_xCCR_xPSR_SHIFT 8306#define ESAI_xCCR_xPSR_MASK (1 << ESAI_xCCR_xPSR_SHIFT)307#define ESAI_xCCR_xPSR_BYPASS (1 << ESAI_xCCR_xPSR_SHIFT)308#define ESAI_xCCR_xPSR_DIV8 (0 << ESAI_xCCR_xPSR_SHIFT)309#define ESAI_xCCR_xPM_SHIFT 0310#define ESAI_xCCR_xPM_WIDTH 8311#define ESAI_xCCR_xPM_MASK (((1 << ESAI_xCCR_xPM_WIDTH) - 1) << ESAI_xCCR_xPM_SHIFT)312#define ESAI_xCCR_xPM(v) ((((v) - 1) << ESAI_xCCR_xPM_SHIFT) & ESAI_xCCR_xPM_MASK)313 314/* Transmit Slot Mask Register A/B -- REG_ESAI_TSMA/B 0xE4 ~ 0xF0 */315#define ESAI_xSMA_xS_SHIFT 0316#define ESAI_xSMA_xS_WIDTH 16317#define ESAI_xSMA_xS_MASK (((1 << ESAI_xSMA_xS_WIDTH) - 1) << ESAI_xSMA_xS_SHIFT)318#define ESAI_xSMA_xS(v) ((v) & ESAI_xSMA_xS_MASK)319#define ESAI_xSMB_xS_SHIFT 0320#define ESAI_xSMB_xS_WIDTH 16321#define ESAI_xSMB_xS_MASK (((1 << ESAI_xSMB_xS_WIDTH) - 1) << ESAI_xSMB_xS_SHIFT)322#define ESAI_xSMB_xS(v) (((v) >> ESAI_xSMA_xS_WIDTH) & ESAI_xSMB_xS_MASK)323 324/* Port C Direction Register -- REG_ESAI_PRRC 0xF8 */325#define ESAI_PRRC_PDC_SHIFT 0326#define ESAI_PRRC_PDC_WIDTH 12327#define ESAI_PRRC_PDC_MASK (((1 << ESAI_PRRC_PDC_WIDTH) - 1) << ESAI_PRRC_PDC_SHIFT)328#define ESAI_PRRC_PDC(v) ((v) & ESAI_PRRC_PDC_MASK)329 330/* Port C Control Register -- REG_ESAI_PCRC 0xFC */331#define ESAI_PCRC_PC_SHIFT 0332#define ESAI_PCRC_PC_WIDTH 12333#define ESAI_PCRC_PC_MASK (((1 << ESAI_PCRC_PC_WIDTH) - 1) << ESAI_PCRC_PC_SHIFT)334#define ESAI_PCRC_PC(v) ((v) & ESAI_PCRC_PC_MASK)335 336#define ESAI_GPIO 0xfff337 338/* ESAI clock source */339#define ESAI_HCKT_FSYS 0340#define ESAI_HCKT_EXTAL 1341#define ESAI_HCKR_FSYS 2342#define ESAI_HCKR_EXTAL 3343 344/* ESAI clock divider */345#define ESAI_TX_DIV_PSR 0346#define ESAI_TX_DIV_PM 1347#define ESAI_TX_DIV_FP 2348#define ESAI_RX_DIV_PSR 3349#define ESAI_RX_DIV_PM 4350#define ESAI_RX_DIV_FP 5351#endif /* _FSL_ESAI_DAI_H */352