1411 lines · c
1// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause2// Copyright 2018 NXP3 4#include <linux/bitfield.h>5#include <linux/clk.h>6#include <linux/device.h>7#include <linux/interrupt.h>8#include <linux/kobject.h>9#include <linux/kernel.h>10#include <linux/module.h>11#include <linux/of.h>12#include <linux/of_address.h>13#include <linux/of_irq.h>14#include <linux/of_platform.h>15#include <linux/pm_runtime.h>16#include <linux/regmap.h>17#include <linux/sysfs.h>18#include <linux/types.h>19#include <linux/dma/imx-dma.h>20#include <sound/dmaengine_pcm.h>21#include <sound/pcm.h>22#include <sound/soc.h>23#include <sound/tlv.h>24#include <sound/core.h>25 26#include "fsl_micfil.h"27#include "fsl_utils.h"28 29#define MICFIL_OSR_DEFAULT 1630 31#define MICFIL_NUM_RATES 732#define MICFIL_CLK_SRC_NUM 333/* clock source ids */34#define MICFIL_AUDIO_PLL1 035#define MICFIL_AUDIO_PLL2 136#define MICFIL_CLK_EXT3 237 38enum quality {39 QUALITY_HIGH,40 QUALITY_MEDIUM,41 QUALITY_LOW,42 QUALITY_VLOW0,43 QUALITY_VLOW1,44 QUALITY_VLOW2,45};46 47struct fsl_micfil {48 struct platform_device *pdev;49 struct regmap *regmap;50 const struct fsl_micfil_soc_data *soc;51 struct clk *busclk;52 struct clk *mclk;53 struct clk *pll8k_clk;54 struct clk *pll11k_clk;55 struct clk *clk_src[MICFIL_CLK_SRC_NUM];56 struct snd_dmaengine_dai_dma_data dma_params_rx;57 struct sdma_peripheral_config sdmacfg;58 struct snd_soc_card *card;59 struct snd_pcm_hw_constraint_list constraint_rates;60 unsigned int constraint_rates_list[MICFIL_NUM_RATES];61 unsigned int dataline;62 char name[32];63 int irq[MICFIL_IRQ_LINES];64 enum quality quality;65 int dc_remover;66 int vad_init_mode;67 int vad_enabled;68 int vad_detected;69 struct fsl_micfil_verid verid;70 struct fsl_micfil_param param;71};72 73struct fsl_micfil_soc_data {74 unsigned int fifos;75 unsigned int fifo_depth;76 unsigned int dataline;77 bool imx;78 bool use_edma;79 bool use_verid;80 bool volume_sx;81 u64 formats;82};83 84static struct fsl_micfil_soc_data fsl_micfil_imx8mm = {85 .imx = true,86 .fifos = 8,87 .fifo_depth = 8,88 .dataline = 0xf,89 .formats = SNDRV_PCM_FMTBIT_S16_LE,90 .volume_sx = true,91};92 93static struct fsl_micfil_soc_data fsl_micfil_imx8mp = {94 .imx = true,95 .fifos = 8,96 .fifo_depth = 32,97 .dataline = 0xf,98 .formats = SNDRV_PCM_FMTBIT_S32_LE,99 .volume_sx = false,100};101 102static struct fsl_micfil_soc_data fsl_micfil_imx93 = {103 .imx = true,104 .fifos = 8,105 .fifo_depth = 32,106 .dataline = 0xf,107 .formats = SNDRV_PCM_FMTBIT_S32_LE,108 .use_edma = true,109 .use_verid = true,110 .volume_sx = false,111};112 113static const struct of_device_id fsl_micfil_dt_ids[] = {114 { .compatible = "fsl,imx8mm-micfil", .data = &fsl_micfil_imx8mm },115 { .compatible = "fsl,imx8mp-micfil", .data = &fsl_micfil_imx8mp },116 { .compatible = "fsl,imx93-micfil", .data = &fsl_micfil_imx93 },117 {}118};119MODULE_DEVICE_TABLE(of, fsl_micfil_dt_ids);120 121static const char * const micfil_quality_select_texts[] = {122 [QUALITY_HIGH] = "High",123 [QUALITY_MEDIUM] = "Medium",124 [QUALITY_LOW] = "Low",125 [QUALITY_VLOW0] = "VLow0",126 [QUALITY_VLOW1] = "Vlow1",127 [QUALITY_VLOW2] = "Vlow2",128};129 130static const struct soc_enum fsl_micfil_quality_enum =131 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(micfil_quality_select_texts),132 micfil_quality_select_texts);133 134static DECLARE_TLV_DB_SCALE(gain_tlv, 0, 100, 0);135 136static int micfil_set_quality(struct fsl_micfil *micfil)137{138 u32 qsel;139 140 switch (micfil->quality) {141 case QUALITY_HIGH:142 qsel = MICFIL_QSEL_HIGH_QUALITY;143 break;144 case QUALITY_MEDIUM:145 qsel = MICFIL_QSEL_MEDIUM_QUALITY;146 break;147 case QUALITY_LOW:148 qsel = MICFIL_QSEL_LOW_QUALITY;149 break;150 case QUALITY_VLOW0:151 qsel = MICFIL_QSEL_VLOW0_QUALITY;152 break;153 case QUALITY_VLOW1:154 qsel = MICFIL_QSEL_VLOW1_QUALITY;155 break;156 case QUALITY_VLOW2:157 qsel = MICFIL_QSEL_VLOW2_QUALITY;158 break;159 }160 161 return regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL2,162 MICFIL_CTRL2_QSEL,163 FIELD_PREP(MICFIL_CTRL2_QSEL, qsel));164}165 166static int micfil_quality_get(struct snd_kcontrol *kcontrol,167 struct snd_ctl_elem_value *ucontrol)168{169 struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);170 struct fsl_micfil *micfil = snd_soc_component_get_drvdata(cmpnt);171 172 ucontrol->value.integer.value[0] = micfil->quality;173 174 return 0;175}176 177static int micfil_quality_set(struct snd_kcontrol *kcontrol,178 struct snd_ctl_elem_value *ucontrol)179{180 struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);181 struct fsl_micfil *micfil = snd_soc_component_get_drvdata(cmpnt);182 183 micfil->quality = ucontrol->value.integer.value[0];184 185 return micfil_set_quality(micfil);186}187 188static const char * const micfil_hwvad_enable[] = {189 "Disable (Record only)",190 "Enable (Record with Vad)",191};192 193static const char * const micfil_hwvad_init_mode[] = {194 "Envelope mode", "Energy mode",195};196 197static const char * const micfil_hwvad_hpf_texts[] = {198 "Filter bypass",199 "Cut-off @1750Hz",200 "Cut-off @215Hz",201 "Cut-off @102Hz",202};203 204/*205 * DC Remover Control206 * Filter Bypassed 1 1207 * Cut-off @21Hz 0 0208 * Cut-off @83Hz 0 1209 * Cut-off @152HZ 1 0210 */211static const char * const micfil_dc_remover_texts[] = {212 "Cut-off @21Hz", "Cut-off @83Hz",213 "Cut-off @152Hz", "Bypass",214};215 216static const struct soc_enum hwvad_enable_enum =217 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(micfil_hwvad_enable),218 micfil_hwvad_enable);219static const struct soc_enum hwvad_init_mode_enum =220 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(micfil_hwvad_init_mode),221 micfil_hwvad_init_mode);222static const struct soc_enum hwvad_hpf_enum =223 SOC_ENUM_SINGLE(REG_MICFIL_VAD0_CTRL2, 0,224 ARRAY_SIZE(micfil_hwvad_hpf_texts),225 micfil_hwvad_hpf_texts);226static const struct soc_enum fsl_micfil_dc_remover_enum =227 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(micfil_dc_remover_texts),228 micfil_dc_remover_texts);229 230static int micfil_put_dc_remover_state(struct snd_kcontrol *kcontrol,231 struct snd_ctl_elem_value *ucontrol)232{233 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;234 struct snd_soc_component *comp = snd_kcontrol_chip(kcontrol);235 struct fsl_micfil *micfil = snd_soc_component_get_drvdata(comp);236 unsigned int *item = ucontrol->value.enumerated.item;237 int val = snd_soc_enum_item_to_val(e, item[0]);238 int i = 0, ret = 0;239 u32 reg_val = 0;240 241 if (val < 0 || val > 3)242 return -EINVAL;243 244 micfil->dc_remover = val;245 246 /* Calculate total value for all channels */247 for (i = 0; i < MICFIL_OUTPUT_CHANNELS; i++)248 reg_val |= val << MICFIL_DC_CHX_SHIFT(i);249 250 /* Update DC Remover mode for all channels */251 ret = snd_soc_component_update_bits(comp, REG_MICFIL_DC_CTRL,252 MICFIL_DC_CTRL_CONFIG, reg_val);253 if (ret < 0)254 return ret;255 256 return 0;257}258 259static int micfil_get_dc_remover_state(struct snd_kcontrol *kcontrol,260 struct snd_ctl_elem_value *ucontrol)261{262 struct snd_soc_component *comp = snd_kcontrol_chip(kcontrol);263 struct fsl_micfil *micfil = snd_soc_component_get_drvdata(comp);264 265 ucontrol->value.enumerated.item[0] = micfil->dc_remover;266 267 return 0;268}269 270static int hwvad_put_enable(struct snd_kcontrol *kcontrol,271 struct snd_ctl_elem_value *ucontrol)272{273 struct snd_soc_component *comp = snd_kcontrol_chip(kcontrol);274 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;275 unsigned int *item = ucontrol->value.enumerated.item;276 struct fsl_micfil *micfil = snd_soc_component_get_drvdata(comp);277 int val = snd_soc_enum_item_to_val(e, item[0]);278 279 micfil->vad_enabled = val;280 281 return 0;282}283 284static int hwvad_get_enable(struct snd_kcontrol *kcontrol,285 struct snd_ctl_elem_value *ucontrol)286{287 struct snd_soc_component *comp = snd_kcontrol_chip(kcontrol);288 struct fsl_micfil *micfil = snd_soc_component_get_drvdata(comp);289 290 ucontrol->value.enumerated.item[0] = micfil->vad_enabled;291 292 return 0;293}294 295static int hwvad_put_init_mode(struct snd_kcontrol *kcontrol,296 struct snd_ctl_elem_value *ucontrol)297{298 struct snd_soc_component *comp = snd_kcontrol_chip(kcontrol);299 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;300 unsigned int *item = ucontrol->value.enumerated.item;301 struct fsl_micfil *micfil = snd_soc_component_get_drvdata(comp);302 int val = snd_soc_enum_item_to_val(e, item[0]);303 304 /* 0 - Envelope-based Mode305 * 1 - Energy-based Mode306 */307 micfil->vad_init_mode = val;308 309 return 0;310}311 312static int hwvad_get_init_mode(struct snd_kcontrol *kcontrol,313 struct snd_ctl_elem_value *ucontrol)314{315 struct snd_soc_component *comp = snd_kcontrol_chip(kcontrol);316 struct fsl_micfil *micfil = snd_soc_component_get_drvdata(comp);317 318 ucontrol->value.enumerated.item[0] = micfil->vad_init_mode;319 320 return 0;321}322 323static int hwvad_detected(struct snd_kcontrol *kcontrol,324 struct snd_ctl_elem_value *ucontrol)325{326 struct snd_soc_component *comp = snd_kcontrol_chip(kcontrol);327 struct fsl_micfil *micfil = snd_soc_component_get_drvdata(comp);328 329 ucontrol->value.enumerated.item[0] = micfil->vad_detected;330 331 return 0;332}333 334static const struct snd_kcontrol_new fsl_micfil_volume_controls[] = {335 SOC_SINGLE_TLV("CH0 Volume", REG_MICFIL_OUT_CTRL,336 MICFIL_OUTGAIN_CHX_SHIFT(0), 0xF, 0, gain_tlv),337 SOC_SINGLE_TLV("CH1 Volume", REG_MICFIL_OUT_CTRL,338 MICFIL_OUTGAIN_CHX_SHIFT(1), 0xF, 0, gain_tlv),339 SOC_SINGLE_TLV("CH2 Volume", REG_MICFIL_OUT_CTRL,340 MICFIL_OUTGAIN_CHX_SHIFT(2), 0xF, 0, gain_tlv),341 SOC_SINGLE_TLV("CH3 Volume", REG_MICFIL_OUT_CTRL,342 MICFIL_OUTGAIN_CHX_SHIFT(3), 0xF, 0, gain_tlv),343 SOC_SINGLE_TLV("CH4 Volume", REG_MICFIL_OUT_CTRL,344 MICFIL_OUTGAIN_CHX_SHIFT(4), 0xF, 0, gain_tlv),345 SOC_SINGLE_TLV("CH5 Volume", REG_MICFIL_OUT_CTRL,346 MICFIL_OUTGAIN_CHX_SHIFT(5), 0xF, 0, gain_tlv),347 SOC_SINGLE_TLV("CH6 Volume", REG_MICFIL_OUT_CTRL,348 MICFIL_OUTGAIN_CHX_SHIFT(6), 0xF, 0, gain_tlv),349 SOC_SINGLE_TLV("CH7 Volume", REG_MICFIL_OUT_CTRL,350 MICFIL_OUTGAIN_CHX_SHIFT(7), 0xF, 0, gain_tlv),351};352 353static const struct snd_kcontrol_new fsl_micfil_volume_sx_controls[] = {354 SOC_SINGLE_SX_TLV("CH0 Volume", REG_MICFIL_OUT_CTRL,355 MICFIL_OUTGAIN_CHX_SHIFT(0), 0x8, 0xF, gain_tlv),356 SOC_SINGLE_SX_TLV("CH1 Volume", REG_MICFIL_OUT_CTRL,357 MICFIL_OUTGAIN_CHX_SHIFT(1), 0x8, 0xF, gain_tlv),358 SOC_SINGLE_SX_TLV("CH2 Volume", REG_MICFIL_OUT_CTRL,359 MICFIL_OUTGAIN_CHX_SHIFT(2), 0x8, 0xF, gain_tlv),360 SOC_SINGLE_SX_TLV("CH3 Volume", REG_MICFIL_OUT_CTRL,361 MICFIL_OUTGAIN_CHX_SHIFT(3), 0x8, 0xF, gain_tlv),362 SOC_SINGLE_SX_TLV("CH4 Volume", REG_MICFIL_OUT_CTRL,363 MICFIL_OUTGAIN_CHX_SHIFT(4), 0x8, 0xF, gain_tlv),364 SOC_SINGLE_SX_TLV("CH5 Volume", REG_MICFIL_OUT_CTRL,365 MICFIL_OUTGAIN_CHX_SHIFT(5), 0x8, 0xF, gain_tlv),366 SOC_SINGLE_SX_TLV("CH6 Volume", REG_MICFIL_OUT_CTRL,367 MICFIL_OUTGAIN_CHX_SHIFT(6), 0x8, 0xF, gain_tlv),368 SOC_SINGLE_SX_TLV("CH7 Volume", REG_MICFIL_OUT_CTRL,369 MICFIL_OUTGAIN_CHX_SHIFT(7), 0x8, 0xF, gain_tlv),370};371 372static const struct snd_kcontrol_new fsl_micfil_snd_controls[] = {373 SOC_ENUM_EXT("MICFIL Quality Select",374 fsl_micfil_quality_enum,375 micfil_quality_get, micfil_quality_set),376 SOC_ENUM_EXT("HWVAD Enablement Switch", hwvad_enable_enum,377 hwvad_get_enable, hwvad_put_enable),378 SOC_ENUM_EXT("HWVAD Initialization Mode", hwvad_init_mode_enum,379 hwvad_get_init_mode, hwvad_put_init_mode),380 SOC_ENUM("HWVAD High-Pass Filter", hwvad_hpf_enum),381 SOC_SINGLE("HWVAD ZCD Switch", REG_MICFIL_VAD0_ZCD, 0, 1, 0),382 SOC_SINGLE("HWVAD ZCD Auto Threshold Switch",383 REG_MICFIL_VAD0_ZCD, 2, 1, 0),384 SOC_ENUM_EXT("MICFIL DC Remover Control", fsl_micfil_dc_remover_enum,385 micfil_get_dc_remover_state, micfil_put_dc_remover_state),386 SOC_SINGLE("HWVAD Input Gain", REG_MICFIL_VAD0_CTRL2, 8, 15, 0),387 SOC_SINGLE("HWVAD Sound Gain", REG_MICFIL_VAD0_SCONFIG, 0, 15, 0),388 SOC_SINGLE("HWVAD Noise Gain", REG_MICFIL_VAD0_NCONFIG, 0, 15, 0),389 SOC_SINGLE_RANGE("HWVAD Detector Frame Time", REG_MICFIL_VAD0_CTRL2, 16, 0, 63, 0),390 SOC_SINGLE("HWVAD Detector Initialization Time", REG_MICFIL_VAD0_CTRL1, 8, 31, 0),391 SOC_SINGLE("HWVAD Noise Filter Adjustment", REG_MICFIL_VAD0_NCONFIG, 8, 31, 0),392 SOC_SINGLE("HWVAD ZCD Threshold", REG_MICFIL_VAD0_ZCD, 16, 1023, 0),393 SOC_SINGLE("HWVAD ZCD Adjustment", REG_MICFIL_VAD0_ZCD, 8, 15, 0),394 SOC_SINGLE("HWVAD ZCD And Behavior Switch",395 REG_MICFIL_VAD0_ZCD, 4, 1, 0),396 SOC_SINGLE_BOOL_EXT("VAD Detected", 0, hwvad_detected, NULL),397};398 399static int fsl_micfil_use_verid(struct device *dev)400{401 struct fsl_micfil *micfil = dev_get_drvdata(dev);402 unsigned int val;403 int ret;404 405 if (!micfil->soc->use_verid)406 return 0;407 408 ret = regmap_read(micfil->regmap, REG_MICFIL_VERID, &val);409 if (ret < 0)410 return ret;411 412 dev_dbg(dev, "VERID: 0x%016X\n", val);413 414 micfil->verid.version = val &415 (MICFIL_VERID_MAJOR_MASK | MICFIL_VERID_MINOR_MASK);416 micfil->verid.version >>= MICFIL_VERID_MINOR_SHIFT;417 micfil->verid.feature = val & MICFIL_VERID_FEATURE_MASK;418 419 ret = regmap_read(micfil->regmap, REG_MICFIL_PARAM, &val);420 if (ret < 0)421 return ret;422 423 dev_dbg(dev, "PARAM: 0x%016X\n", val);424 425 micfil->param.hwvad_num = (val & MICFIL_PARAM_NUM_HWVAD_MASK) >>426 MICFIL_PARAM_NUM_HWVAD_SHIFT;427 micfil->param.hwvad_zcd = val & MICFIL_PARAM_HWVAD_ZCD;428 micfil->param.hwvad_energy_mode = val & MICFIL_PARAM_HWVAD_ENERGY_MODE;429 micfil->param.hwvad = val & MICFIL_PARAM_HWVAD;430 micfil->param.dc_out_bypass = val & MICFIL_PARAM_DC_OUT_BYPASS;431 micfil->param.dc_in_bypass = val & MICFIL_PARAM_DC_IN_BYPASS;432 micfil->param.low_power = val & MICFIL_PARAM_LOW_POWER;433 micfil->param.fil_out_width = val & MICFIL_PARAM_FIL_OUT_WIDTH;434 micfil->param.fifo_ptrwid = (val & MICFIL_PARAM_FIFO_PTRWID_MASK) >>435 MICFIL_PARAM_FIFO_PTRWID_SHIFT;436 micfil->param.npair = (val & MICFIL_PARAM_NPAIR_MASK) >>437 MICFIL_PARAM_NPAIR_SHIFT;438 439 return 0;440}441 442/* The SRES is a self-negated bit which provides the CPU with the443 * capability to initialize the PDM Interface module through the444 * slave-bus interface. This bit always reads as zero, and this445 * bit is only effective when MDIS is cleared446 */447static int fsl_micfil_reset(struct device *dev)448{449 struct fsl_micfil *micfil = dev_get_drvdata(dev);450 int ret;451 452 ret = regmap_clear_bits(micfil->regmap, REG_MICFIL_CTRL1,453 MICFIL_CTRL1_MDIS);454 if (ret)455 return ret;456 457 ret = regmap_set_bits(micfil->regmap, REG_MICFIL_CTRL1,458 MICFIL_CTRL1_SRES);459 if (ret)460 return ret;461 462 /*463 * SRES is self-cleared bit, but REG_MICFIL_CTRL1 is defined464 * as non-volatile register, so SRES still remain in regmap465 * cache after set, that every update of REG_MICFIL_CTRL1,466 * software reset happens. so clear it explicitly.467 */468 ret = regmap_clear_bits(micfil->regmap, REG_MICFIL_CTRL1,469 MICFIL_CTRL1_SRES);470 if (ret)471 return ret;472 473 /*474 * Set SRES should clear CHnF flags, But even add delay here475 * the CHnF may not be cleared sometimes, so clear CHnF explicitly.476 */477 ret = regmap_write_bits(micfil->regmap, REG_MICFIL_STAT, 0xFF, 0xFF);478 if (ret)479 return ret;480 481 return 0;482}483 484static int fsl_micfil_startup(struct snd_pcm_substream *substream,485 struct snd_soc_dai *dai)486{487 struct fsl_micfil *micfil = snd_soc_dai_get_drvdata(dai);488 unsigned int rates[MICFIL_NUM_RATES] = {8000, 11025, 16000, 22050, 32000, 44100, 48000};489 int i, j, k = 0;490 u64 clk_rate;491 492 if (!micfil) {493 dev_err(dai->dev, "micfil dai priv_data not set\n");494 return -EINVAL;495 }496 497 micfil->constraint_rates.list = micfil->constraint_rates_list;498 micfil->constraint_rates.count = 0;499 500 for (j = 0; j < MICFIL_NUM_RATES; j++) {501 for (i = 0; i < MICFIL_CLK_SRC_NUM; i++) {502 clk_rate = clk_get_rate(micfil->clk_src[i]);503 if (clk_rate != 0 && do_div(clk_rate, rates[j]) == 0) {504 micfil->constraint_rates_list[k++] = rates[j];505 micfil->constraint_rates.count++;506 break;507 }508 }509 }510 511 if (micfil->constraint_rates.count > 0)512 snd_pcm_hw_constraint_list(substream->runtime, 0,513 SNDRV_PCM_HW_PARAM_RATE,514 &micfil->constraint_rates);515 516 return 0;517}518 519/* Enable/disable hwvad interrupts */520static int fsl_micfil_configure_hwvad_interrupts(struct fsl_micfil *micfil, int enable)521{522 u32 vadie_reg = enable ? MICFIL_VAD0_CTRL1_IE : 0;523 u32 vaderie_reg = enable ? MICFIL_VAD0_CTRL1_ERIE : 0;524 525 /* Voice Activity Detector Error Interruption */526 regmap_update_bits(micfil->regmap, REG_MICFIL_VAD0_CTRL1,527 MICFIL_VAD0_CTRL1_ERIE, vaderie_reg);528 529 /* Voice Activity Detector Interruption */530 regmap_update_bits(micfil->regmap, REG_MICFIL_VAD0_CTRL1,531 MICFIL_VAD0_CTRL1_IE, vadie_reg);532 533 return 0;534}535 536/* Configuration done only in energy-based initialization mode */537static int fsl_micfil_init_hwvad_energy_mode(struct fsl_micfil *micfil)538{539 /* Keep the VADFRENDIS bitfield cleared. */540 regmap_clear_bits(micfil->regmap, REG_MICFIL_VAD0_CTRL2,541 MICFIL_VAD0_CTRL2_FRENDIS);542 543 /* Keep the VADPREFEN bitfield cleared. */544 regmap_clear_bits(micfil->regmap, REG_MICFIL_VAD0_CTRL2,545 MICFIL_VAD0_CTRL2_PREFEN);546 547 /* Keep the VADSFILEN bitfield cleared. */548 regmap_clear_bits(micfil->regmap, REG_MICFIL_VAD0_SCONFIG,549 MICFIL_VAD0_SCONFIG_SFILEN);550 551 /* Keep the VADSMAXEN bitfield cleared. */552 regmap_clear_bits(micfil->regmap, REG_MICFIL_VAD0_SCONFIG,553 MICFIL_VAD0_SCONFIG_SMAXEN);554 555 /* Keep the VADNFILAUTO bitfield asserted. */556 regmap_set_bits(micfil->regmap, REG_MICFIL_VAD0_NCONFIG,557 MICFIL_VAD0_NCONFIG_NFILAUT);558 559 /* Keep the VADNMINEN bitfield cleared. */560 regmap_clear_bits(micfil->regmap, REG_MICFIL_VAD0_NCONFIG,561 MICFIL_VAD0_NCONFIG_NMINEN);562 563 /* Keep the VADNDECEN bitfield cleared. */564 regmap_clear_bits(micfil->regmap, REG_MICFIL_VAD0_NCONFIG,565 MICFIL_VAD0_NCONFIG_NDECEN);566 567 /* Keep the VADNOREN bitfield cleared. */568 regmap_clear_bits(micfil->regmap, REG_MICFIL_VAD0_NCONFIG,569 MICFIL_VAD0_NCONFIG_NOREN);570 571 return 0;572}573 574/* Configuration done only in envelope-based initialization mode */575static int fsl_micfil_init_hwvad_envelope_mode(struct fsl_micfil *micfil)576{577 /* Assert the VADFRENDIS bitfield */578 regmap_set_bits(micfil->regmap, REG_MICFIL_VAD0_CTRL2,579 MICFIL_VAD0_CTRL2_FRENDIS);580 581 /* Assert the VADPREFEN bitfield. */582 regmap_set_bits(micfil->regmap, REG_MICFIL_VAD0_CTRL2,583 MICFIL_VAD0_CTRL2_PREFEN);584 585 /* Assert the VADSFILEN bitfield. */586 regmap_set_bits(micfil->regmap, REG_MICFIL_VAD0_SCONFIG,587 MICFIL_VAD0_SCONFIG_SFILEN);588 589 /* Assert the VADSMAXEN bitfield. */590 regmap_set_bits(micfil->regmap, REG_MICFIL_VAD0_SCONFIG,591 MICFIL_VAD0_SCONFIG_SMAXEN);592 593 /* Clear the VADNFILAUTO bitfield */594 regmap_clear_bits(micfil->regmap, REG_MICFIL_VAD0_NCONFIG,595 MICFIL_VAD0_NCONFIG_NFILAUT);596 597 /* Assert the VADNMINEN bitfield. */598 regmap_set_bits(micfil->regmap, REG_MICFIL_VAD0_NCONFIG,599 MICFIL_VAD0_NCONFIG_NMINEN);600 601 /* Assert the VADNDECEN bitfield. */602 regmap_set_bits(micfil->regmap, REG_MICFIL_VAD0_NCONFIG,603 MICFIL_VAD0_NCONFIG_NDECEN);604 605 /* Assert VADNOREN bitfield. */606 regmap_set_bits(micfil->regmap, REG_MICFIL_VAD0_NCONFIG,607 MICFIL_VAD0_NCONFIG_NOREN);608 609 return 0;610}611 612/*613 * Hardware Voice Active Detection: The HWVAD takes data from the input614 * of a selected PDM microphone to detect if there is any615 * voice activity. When a voice activity is detected, an interrupt could616 * be delivered to the system. Initialization in section 8.4:617 * Can work in two modes:618 * -> Eneveope-based mode (section 8.4.1)619 * -> Energy-based mode (section 8.4.2)620 *621 * It is important to remark that the HWVAD detector could be enabled622 * or reset only when the MICFIL isn't running i.e. when the BSY_FIL623 * bit in STAT register is cleared624 */625static int fsl_micfil_hwvad_enable(struct fsl_micfil *micfil)626{627 int ret;628 629 micfil->vad_detected = 0;630 631 /* envelope-based specific initialization */632 if (micfil->vad_init_mode == MICFIL_HWVAD_ENVELOPE_MODE)633 ret = fsl_micfil_init_hwvad_envelope_mode(micfil);634 else635 ret = fsl_micfil_init_hwvad_energy_mode(micfil);636 if (ret)637 return ret;638 639 /* Voice Activity Detector Internal Filters Initialization*/640 regmap_set_bits(micfil->regmap, REG_MICFIL_VAD0_CTRL1,641 MICFIL_VAD0_CTRL1_ST10);642 643 /* Voice Activity Detector Internal Filter */644 regmap_clear_bits(micfil->regmap, REG_MICFIL_VAD0_CTRL1,645 MICFIL_VAD0_CTRL1_ST10);646 647 /* Enable Interrupts */648 ret = fsl_micfil_configure_hwvad_interrupts(micfil, 1);649 if (ret)650 return ret;651 652 /* Voice Activity Detector Reset */653 regmap_set_bits(micfil->regmap, REG_MICFIL_VAD0_CTRL1,654 MICFIL_VAD0_CTRL1_RST);655 656 /* Voice Activity Detector Enabled */657 regmap_set_bits(micfil->regmap, REG_MICFIL_VAD0_CTRL1,658 MICFIL_VAD0_CTRL1_EN);659 660 return 0;661}662 663static int fsl_micfil_hwvad_disable(struct fsl_micfil *micfil)664{665 struct device *dev = &micfil->pdev->dev;666 int ret = 0;667 668 /* Disable HWVAD */669 regmap_clear_bits(micfil->regmap, REG_MICFIL_VAD0_CTRL1,670 MICFIL_VAD0_CTRL1_EN);671 672 /* Disable hwvad interrupts */673 ret = fsl_micfil_configure_hwvad_interrupts(micfil, 0);674 if (ret)675 dev_err(dev, "Failed to disable interrupts\n");676 677 return ret;678}679 680static int fsl_micfil_trigger(struct snd_pcm_substream *substream, int cmd,681 struct snd_soc_dai *dai)682{683 struct fsl_micfil *micfil = snd_soc_dai_get_drvdata(dai);684 struct device *dev = &micfil->pdev->dev;685 int ret;686 687 switch (cmd) {688 case SNDRV_PCM_TRIGGER_START:689 case SNDRV_PCM_TRIGGER_RESUME:690 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:691 ret = fsl_micfil_reset(dev);692 if (ret) {693 dev_err(dev, "failed to soft reset\n");694 return ret;695 }696 697 /* DMA Interrupt Selection - DISEL bits698 * 00 - DMA and IRQ disabled699 * 01 - DMA req enabled700 * 10 - IRQ enabled701 * 11 - reserved702 */703 ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL1,704 MICFIL_CTRL1_DISEL,705 FIELD_PREP(MICFIL_CTRL1_DISEL, MICFIL_CTRL1_DISEL_DMA));706 if (ret)707 return ret;708 709 /* Enable the module */710 ret = regmap_set_bits(micfil->regmap, REG_MICFIL_CTRL1,711 MICFIL_CTRL1_PDMIEN);712 if (ret)713 return ret;714 715 if (micfil->vad_enabled)716 fsl_micfil_hwvad_enable(micfil);717 718 break;719 case SNDRV_PCM_TRIGGER_STOP:720 case SNDRV_PCM_TRIGGER_SUSPEND:721 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:722 if (micfil->vad_enabled)723 fsl_micfil_hwvad_disable(micfil);724 725 /* Disable the module */726 ret = regmap_clear_bits(micfil->regmap, REG_MICFIL_CTRL1,727 MICFIL_CTRL1_PDMIEN);728 if (ret)729 return ret;730 731 ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL1,732 MICFIL_CTRL1_DISEL,733 FIELD_PREP(MICFIL_CTRL1_DISEL, MICFIL_CTRL1_DISEL_DISABLE));734 if (ret)735 return ret;736 break;737 default:738 return -EINVAL;739 }740 return 0;741}742 743static int fsl_micfil_reparent_rootclk(struct fsl_micfil *micfil, unsigned int sample_rate)744{745 struct device *dev = &micfil->pdev->dev;746 u64 ratio = sample_rate;747 struct clk *clk;748 int ret;749 750 /* Get root clock */751 clk = micfil->mclk;752 753 /* Disable clock first, for it was enabled by pm_runtime */754 clk_disable_unprepare(clk);755 fsl_asoc_reparent_pll_clocks(dev, clk, micfil->pll8k_clk,756 micfil->pll11k_clk, ratio);757 ret = clk_prepare_enable(clk);758 if (ret)759 return ret;760 761 return 0;762}763 764static int fsl_micfil_hw_params(struct snd_pcm_substream *substream,765 struct snd_pcm_hw_params *params,766 struct snd_soc_dai *dai)767{768 struct fsl_micfil *micfil = snd_soc_dai_get_drvdata(dai);769 unsigned int channels = params_channels(params);770 unsigned int rate = params_rate(params);771 int clk_div = 8;772 int osr = MICFIL_OSR_DEFAULT;773 int ret;774 775 /* 1. Disable the module */776 ret = regmap_clear_bits(micfil->regmap, REG_MICFIL_CTRL1,777 MICFIL_CTRL1_PDMIEN);778 if (ret)779 return ret;780 781 /* enable channels */782 ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL1,783 0xFF, ((1 << channels) - 1));784 if (ret)785 return ret;786 787 ret = fsl_micfil_reparent_rootclk(micfil, rate);788 if (ret)789 return ret;790 791 ret = clk_set_rate(micfil->mclk, rate * clk_div * osr * 8);792 if (ret)793 return ret;794 795 ret = micfil_set_quality(micfil);796 if (ret)797 return ret;798 799 ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL2,800 MICFIL_CTRL2_CLKDIV | MICFIL_CTRL2_CICOSR,801 FIELD_PREP(MICFIL_CTRL2_CLKDIV, clk_div) |802 FIELD_PREP(MICFIL_CTRL2_CICOSR, 16 - osr));803 804 /* Configure CIC OSR in VADCICOSR */805 regmap_update_bits(micfil->regmap, REG_MICFIL_VAD0_CTRL1,806 MICFIL_VAD0_CTRL1_CICOSR,807 FIELD_PREP(MICFIL_VAD0_CTRL1_CICOSR, 16 - osr));808 809 /* Configure source channel in VADCHSEL */810 regmap_update_bits(micfil->regmap, REG_MICFIL_VAD0_CTRL1,811 MICFIL_VAD0_CTRL1_CHSEL,812 FIELD_PREP(MICFIL_VAD0_CTRL1_CHSEL, (channels - 1)));813 814 micfil->dma_params_rx.peripheral_config = &micfil->sdmacfg;815 micfil->dma_params_rx.peripheral_size = sizeof(micfil->sdmacfg);816 micfil->sdmacfg.n_fifos_src = channels;817 micfil->sdmacfg.sw_done = true;818 micfil->dma_params_rx.maxburst = channels * MICFIL_DMA_MAXBURST_RX;819 if (micfil->soc->use_edma)820 micfil->dma_params_rx.maxburst = channels;821 822 return 0;823}824 825static int fsl_micfil_dai_probe(struct snd_soc_dai *cpu_dai)826{827 struct fsl_micfil *micfil = dev_get_drvdata(cpu_dai->dev);828 struct device *dev = cpu_dai->dev;829 unsigned int val = 0;830 int ret, i;831 832 micfil->quality = QUALITY_VLOW0;833 micfil->card = cpu_dai->component->card;834 835 /* set default gain to 2 */836 regmap_write(micfil->regmap, REG_MICFIL_OUT_CTRL, 0x22222222);837 838 /* set DC Remover in bypass mode*/839 for (i = 0; i < MICFIL_OUTPUT_CHANNELS; i++)840 val |= MICFIL_DC_BYPASS << MICFIL_DC_CHX_SHIFT(i);841 ret = regmap_update_bits(micfil->regmap, REG_MICFIL_DC_CTRL,842 MICFIL_DC_CTRL_CONFIG, val);843 if (ret) {844 dev_err(dev, "failed to set DC Remover mode bits\n");845 return ret;846 }847 micfil->dc_remover = MICFIL_DC_BYPASS;848 849 snd_soc_dai_init_dma_data(cpu_dai, NULL,850 &micfil->dma_params_rx);851 852 /* FIFO Watermark Control - FIFOWMK*/853 ret = regmap_update_bits(micfil->regmap, REG_MICFIL_FIFO_CTRL,854 MICFIL_FIFO_CTRL_FIFOWMK,855 FIELD_PREP(MICFIL_FIFO_CTRL_FIFOWMK, micfil->soc->fifo_depth - 1));856 if (ret)857 return ret;858 859 return 0;860}861 862static int fsl_micfil_component_probe(struct snd_soc_component *component)863{864 struct fsl_micfil *micfil = snd_soc_component_get_drvdata(component);865 866 if (micfil->soc->volume_sx)867 snd_soc_add_component_controls(component, fsl_micfil_volume_sx_controls,868 ARRAY_SIZE(fsl_micfil_volume_sx_controls));869 else870 snd_soc_add_component_controls(component, fsl_micfil_volume_controls,871 ARRAY_SIZE(fsl_micfil_volume_controls));872 873 return 0;874}875 876static const struct snd_soc_dai_ops fsl_micfil_dai_ops = {877 .probe = fsl_micfil_dai_probe,878 .startup = fsl_micfil_startup,879 .trigger = fsl_micfil_trigger,880 .hw_params = fsl_micfil_hw_params,881};882 883static struct snd_soc_dai_driver fsl_micfil_dai = {884 .capture = {885 .stream_name = "CPU-Capture",886 .channels_min = 1,887 .channels_max = 8,888 .rates = SNDRV_PCM_RATE_8000_48000,889 .formats = SNDRV_PCM_FMTBIT_S16_LE,890 },891 .ops = &fsl_micfil_dai_ops,892};893 894static const struct snd_soc_component_driver fsl_micfil_component = {895 .name = "fsl-micfil-dai",896 .probe = fsl_micfil_component_probe,897 .controls = fsl_micfil_snd_controls,898 .num_controls = ARRAY_SIZE(fsl_micfil_snd_controls),899 .legacy_dai_naming = 1,900};901 902/* REGMAP */903static const struct reg_default fsl_micfil_reg_defaults[] = {904 {REG_MICFIL_CTRL1, 0x00000000},905 {REG_MICFIL_CTRL2, 0x00000000},906 {REG_MICFIL_STAT, 0x00000000},907 {REG_MICFIL_FIFO_CTRL, 0x0000001F},908 {REG_MICFIL_FIFO_STAT, 0x00000000},909 {REG_MICFIL_DATACH0, 0x00000000},910 {REG_MICFIL_DATACH1, 0x00000000},911 {REG_MICFIL_DATACH2, 0x00000000},912 {REG_MICFIL_DATACH3, 0x00000000},913 {REG_MICFIL_DATACH4, 0x00000000},914 {REG_MICFIL_DATACH5, 0x00000000},915 {REG_MICFIL_DATACH6, 0x00000000},916 {REG_MICFIL_DATACH7, 0x00000000},917 {REG_MICFIL_DC_CTRL, 0x00000000},918 {REG_MICFIL_OUT_CTRL, 0x00000000},919 {REG_MICFIL_OUT_STAT, 0x00000000},920 {REG_MICFIL_VAD0_CTRL1, 0x00000000},921 {REG_MICFIL_VAD0_CTRL2, 0x000A0000},922 {REG_MICFIL_VAD0_STAT, 0x00000000},923 {REG_MICFIL_VAD0_SCONFIG, 0x00000000},924 {REG_MICFIL_VAD0_NCONFIG, 0x80000000},925 {REG_MICFIL_VAD0_NDATA, 0x00000000},926 {REG_MICFIL_VAD0_ZCD, 0x00000004},927};928 929static bool fsl_micfil_readable_reg(struct device *dev, unsigned int reg)930{931 struct fsl_micfil *micfil = dev_get_drvdata(dev);932 933 switch (reg) {934 case REG_MICFIL_CTRL1:935 case REG_MICFIL_CTRL2:936 case REG_MICFIL_STAT:937 case REG_MICFIL_FIFO_CTRL:938 case REG_MICFIL_FIFO_STAT:939 case REG_MICFIL_DATACH0:940 case REG_MICFIL_DATACH1:941 case REG_MICFIL_DATACH2:942 case REG_MICFIL_DATACH3:943 case REG_MICFIL_DATACH4:944 case REG_MICFIL_DATACH5:945 case REG_MICFIL_DATACH6:946 case REG_MICFIL_DATACH7:947 case REG_MICFIL_DC_CTRL:948 case REG_MICFIL_OUT_CTRL:949 case REG_MICFIL_OUT_STAT:950 case REG_MICFIL_VAD0_CTRL1:951 case REG_MICFIL_VAD0_CTRL2:952 case REG_MICFIL_VAD0_STAT:953 case REG_MICFIL_VAD0_SCONFIG:954 case REG_MICFIL_VAD0_NCONFIG:955 case REG_MICFIL_VAD0_NDATA:956 case REG_MICFIL_VAD0_ZCD:957 return true;958 case REG_MICFIL_FSYNC_CTRL:959 case REG_MICFIL_VERID:960 case REG_MICFIL_PARAM:961 if (micfil->soc->use_verid)962 return true;963 fallthrough;964 default:965 return false;966 }967}968 969static bool fsl_micfil_writeable_reg(struct device *dev, unsigned int reg)970{971 struct fsl_micfil *micfil = dev_get_drvdata(dev);972 973 switch (reg) {974 case REG_MICFIL_CTRL1:975 case REG_MICFIL_CTRL2:976 case REG_MICFIL_STAT: /* Write 1 to Clear */977 case REG_MICFIL_FIFO_CTRL:978 case REG_MICFIL_FIFO_STAT: /* Write 1 to Clear */979 case REG_MICFIL_DC_CTRL:980 case REG_MICFIL_OUT_CTRL:981 case REG_MICFIL_OUT_STAT: /* Write 1 to Clear */982 case REG_MICFIL_VAD0_CTRL1:983 case REG_MICFIL_VAD0_CTRL2:984 case REG_MICFIL_VAD0_STAT: /* Write 1 to Clear */985 case REG_MICFIL_VAD0_SCONFIG:986 case REG_MICFIL_VAD0_NCONFIG:987 case REG_MICFIL_VAD0_ZCD:988 return true;989 case REG_MICFIL_FSYNC_CTRL:990 if (micfil->soc->use_verid)991 return true;992 fallthrough;993 default:994 return false;995 }996}997 998static bool fsl_micfil_volatile_reg(struct device *dev, unsigned int reg)999{1000 switch (reg) {1001 case REG_MICFIL_STAT:1002 case REG_MICFIL_DATACH0:1003 case REG_MICFIL_DATACH1:1004 case REG_MICFIL_DATACH2:1005 case REG_MICFIL_DATACH3:1006 case REG_MICFIL_DATACH4:1007 case REG_MICFIL_DATACH5:1008 case REG_MICFIL_DATACH6:1009 case REG_MICFIL_DATACH7:1010 case REG_MICFIL_VERID:1011 case REG_MICFIL_PARAM:1012 case REG_MICFIL_VAD0_STAT:1013 case REG_MICFIL_VAD0_NDATA:1014 return true;1015 default:1016 return false;1017 }1018}1019 1020static const struct regmap_config fsl_micfil_regmap_config = {1021 .reg_bits = 32,1022 .reg_stride = 4,1023 .val_bits = 32,1024 1025 .max_register = REG_MICFIL_VAD0_ZCD,1026 .reg_defaults = fsl_micfil_reg_defaults,1027 .num_reg_defaults = ARRAY_SIZE(fsl_micfil_reg_defaults),1028 .readable_reg = fsl_micfil_readable_reg,1029 .volatile_reg = fsl_micfil_volatile_reg,1030 .writeable_reg = fsl_micfil_writeable_reg,1031 .cache_type = REGCACHE_RBTREE,1032};1033 1034/* END OF REGMAP */1035 1036static irqreturn_t micfil_isr(int irq, void *devid)1037{1038 struct fsl_micfil *micfil = (struct fsl_micfil *)devid;1039 struct platform_device *pdev = micfil->pdev;1040 u32 stat_reg;1041 u32 fifo_stat_reg;1042 u32 ctrl1_reg;1043 bool dma_enabled;1044 int i;1045 1046 regmap_read(micfil->regmap, REG_MICFIL_STAT, &stat_reg);1047 regmap_read(micfil->regmap, REG_MICFIL_CTRL1, &ctrl1_reg);1048 regmap_read(micfil->regmap, REG_MICFIL_FIFO_STAT, &fifo_stat_reg);1049 1050 dma_enabled = FIELD_GET(MICFIL_CTRL1_DISEL, ctrl1_reg) == MICFIL_CTRL1_DISEL_DMA;1051 1052 /* Channel 0-7 Output Data Flags */1053 for (i = 0; i < MICFIL_OUTPUT_CHANNELS; i++) {1054 if (stat_reg & MICFIL_STAT_CHXF(i))1055 dev_dbg(&pdev->dev,1056 "Data available in Data Channel %d\n", i);1057 /* if DMA is not enabled, field must be written with 11058 * to clear1059 */1060 if (!dma_enabled)1061 regmap_write_bits(micfil->regmap,1062 REG_MICFIL_STAT,1063 MICFIL_STAT_CHXF(i),1064 1);1065 }1066 1067 for (i = 0; i < MICFIL_FIFO_NUM; i++) {1068 if (fifo_stat_reg & MICFIL_FIFO_STAT_FIFOX_OVER(i))1069 dev_dbg(&pdev->dev,1070 "FIFO Overflow Exception flag for channel %d\n",1071 i);1072 1073 if (fifo_stat_reg & MICFIL_FIFO_STAT_FIFOX_UNDER(i))1074 dev_dbg(&pdev->dev,1075 "FIFO Underflow Exception flag for channel %d\n",1076 i);1077 }1078 1079 return IRQ_HANDLED;1080}1081 1082static irqreturn_t micfil_err_isr(int irq, void *devid)1083{1084 struct fsl_micfil *micfil = (struct fsl_micfil *)devid;1085 struct platform_device *pdev = micfil->pdev;1086 u32 stat_reg;1087 1088 regmap_read(micfil->regmap, REG_MICFIL_STAT, &stat_reg);1089 1090 if (stat_reg & MICFIL_STAT_BSY_FIL)1091 dev_dbg(&pdev->dev, "isr: Decimation Filter is running\n");1092 1093 if (stat_reg & MICFIL_STAT_FIR_RDY)1094 dev_dbg(&pdev->dev, "isr: FIR Filter Data ready\n");1095 1096 if (stat_reg & MICFIL_STAT_LOWFREQF) {1097 dev_dbg(&pdev->dev, "isr: ipg_clk_app is too low\n");1098 regmap_write_bits(micfil->regmap, REG_MICFIL_STAT,1099 MICFIL_STAT_LOWFREQF, 1);1100 }1101 1102 return IRQ_HANDLED;1103}1104 1105static irqreturn_t voice_detected_fn(int irq, void *devid)1106{1107 struct fsl_micfil *micfil = (struct fsl_micfil *)devid;1108 struct snd_kcontrol *kctl;1109 1110 if (!micfil->card)1111 return IRQ_HANDLED;1112 1113 kctl = snd_soc_card_get_kcontrol(micfil->card, "VAD Detected");1114 if (!kctl)1115 return IRQ_HANDLED;1116 1117 if (micfil->vad_detected)1118 snd_ctl_notify(micfil->card->snd_card,1119 SNDRV_CTL_EVENT_MASK_VALUE,1120 &kctl->id);1121 1122 return IRQ_HANDLED;1123}1124 1125static irqreturn_t hwvad_isr(int irq, void *devid)1126{1127 struct fsl_micfil *micfil = (struct fsl_micfil *)devid;1128 struct device *dev = &micfil->pdev->dev;1129 u32 vad0_reg;1130 int ret;1131 1132 regmap_read(micfil->regmap, REG_MICFIL_VAD0_STAT, &vad0_reg);1133 1134 /*1135 * The only difference between MICFIL_VAD0_STAT_EF and1136 * MICFIL_VAD0_STAT_IF is that the former requires Write1137 * 1 to Clear. Since both flags are set, it is enough1138 * to only read one of them1139 */1140 if (vad0_reg & MICFIL_VAD0_STAT_IF) {1141 /* Write 1 to clear */1142 regmap_write_bits(micfil->regmap, REG_MICFIL_VAD0_STAT,1143 MICFIL_VAD0_STAT_IF,1144 MICFIL_VAD0_STAT_IF);1145 1146 micfil->vad_detected = 1;1147 }1148 1149 ret = fsl_micfil_hwvad_disable(micfil);1150 if (ret)1151 dev_err(dev, "Failed to disable hwvad\n");1152 1153 return IRQ_WAKE_THREAD;1154}1155 1156static irqreturn_t hwvad_err_isr(int irq, void *devid)1157{1158 struct fsl_micfil *micfil = (struct fsl_micfil *)devid;1159 struct device *dev = &micfil->pdev->dev;1160 u32 vad0_reg;1161 1162 regmap_read(micfil->regmap, REG_MICFIL_VAD0_STAT, &vad0_reg);1163 1164 if (vad0_reg & MICFIL_VAD0_STAT_INSATF)1165 dev_dbg(dev, "voice activity input overflow/underflow detected\n");1166 1167 return IRQ_HANDLED;1168}1169 1170static int fsl_micfil_runtime_suspend(struct device *dev);1171static int fsl_micfil_runtime_resume(struct device *dev);1172 1173static int fsl_micfil_probe(struct platform_device *pdev)1174{1175 struct device_node *np = pdev->dev.of_node;1176 struct fsl_micfil *micfil;1177 struct resource *res;1178 void __iomem *regs;1179 int ret, i;1180 1181 micfil = devm_kzalloc(&pdev->dev, sizeof(*micfil), GFP_KERNEL);1182 if (!micfil)1183 return -ENOMEM;1184 1185 micfil->pdev = pdev;1186 strscpy(micfil->name, np->name, sizeof(micfil->name));1187 1188 micfil->soc = of_device_get_match_data(&pdev->dev);1189 1190 /* ipg_clk is used to control the registers1191 * ipg_clk_app is used to operate the filter1192 */1193 micfil->mclk = devm_clk_get(&pdev->dev, "ipg_clk_app");1194 if (IS_ERR(micfil->mclk)) {1195 dev_err(&pdev->dev, "failed to get core clock: %ld\n",1196 PTR_ERR(micfil->mclk));1197 return PTR_ERR(micfil->mclk);1198 }1199 1200 micfil->busclk = devm_clk_get(&pdev->dev, "ipg_clk");1201 if (IS_ERR(micfil->busclk)) {1202 dev_err(&pdev->dev, "failed to get ipg clock: %ld\n",1203 PTR_ERR(micfil->busclk));1204 return PTR_ERR(micfil->busclk);1205 }1206 1207 fsl_asoc_get_pll_clocks(&pdev->dev, &micfil->pll8k_clk,1208 &micfil->pll11k_clk);1209 1210 micfil->clk_src[MICFIL_AUDIO_PLL1] = micfil->pll8k_clk;1211 micfil->clk_src[MICFIL_AUDIO_PLL2] = micfil->pll11k_clk;1212 micfil->clk_src[MICFIL_CLK_EXT3] = devm_clk_get(&pdev->dev, "clkext3");1213 if (IS_ERR(micfil->clk_src[MICFIL_CLK_EXT3]))1214 micfil->clk_src[MICFIL_CLK_EXT3] = NULL;1215 1216 /* init regmap */1217 regs = devm_platform_get_and_ioremap_resource(pdev, 0, &res);1218 if (IS_ERR(regs))1219 return PTR_ERR(regs);1220 1221 micfil->regmap = devm_regmap_init_mmio(&pdev->dev,1222 regs,1223 &fsl_micfil_regmap_config);1224 if (IS_ERR(micfil->regmap)) {1225 dev_err(&pdev->dev, "failed to init MICFIL regmap: %ld\n",1226 PTR_ERR(micfil->regmap));1227 return PTR_ERR(micfil->regmap);1228 }1229 1230 /* dataline mask for RX */1231 ret = of_property_read_u32_index(np,1232 "fsl,dataline",1233 0,1234 &micfil->dataline);1235 if (ret)1236 micfil->dataline = 1;1237 1238 if (micfil->dataline & ~micfil->soc->dataline) {1239 dev_err(&pdev->dev, "dataline setting error, Mask is 0x%X\n",1240 micfil->soc->dataline);1241 return -EINVAL;1242 }1243 1244 /* get IRQs */1245 for (i = 0; i < MICFIL_IRQ_LINES; i++) {1246 micfil->irq[i] = platform_get_irq(pdev, i);1247 if (micfil->irq[i] < 0)1248 return micfil->irq[i];1249 }1250 1251 /* Digital Microphone interface interrupt */1252 ret = devm_request_irq(&pdev->dev, micfil->irq[0],1253 micfil_isr, IRQF_SHARED,1254 micfil->name, micfil);1255 if (ret) {1256 dev_err(&pdev->dev, "failed to claim mic interface irq %u\n",1257 micfil->irq[0]);1258 return ret;1259 }1260 1261 /* Digital Microphone interface error interrupt */1262 ret = devm_request_irq(&pdev->dev, micfil->irq[1],1263 micfil_err_isr, IRQF_SHARED,1264 micfil->name, micfil);1265 if (ret) {1266 dev_err(&pdev->dev, "failed to claim mic interface error irq %u\n",1267 micfil->irq[1]);1268 return ret;1269 }1270 1271 /* Digital Microphone interface voice activity detector event */1272 ret = devm_request_threaded_irq(&pdev->dev, micfil->irq[2],1273 hwvad_isr, voice_detected_fn,1274 IRQF_SHARED, micfil->name, micfil);1275 if (ret) {1276 dev_err(&pdev->dev, "failed to claim hwvad event irq %u\n",1277 micfil->irq[0]);1278 return ret;1279 }1280 1281 /* Digital Microphone interface voice activity detector error */1282 ret = devm_request_irq(&pdev->dev, micfil->irq[3],1283 hwvad_err_isr, IRQF_SHARED,1284 micfil->name, micfil);1285 if (ret) {1286 dev_err(&pdev->dev, "failed to claim hwvad error irq %u\n",1287 micfil->irq[1]);1288 return ret;1289 }1290 1291 micfil->dma_params_rx.chan_name = "rx";1292 micfil->dma_params_rx.addr = res->start + REG_MICFIL_DATACH0;1293 micfil->dma_params_rx.maxburst = MICFIL_DMA_MAXBURST_RX;1294 1295 platform_set_drvdata(pdev, micfil);1296 1297 pm_runtime_enable(&pdev->dev);1298 if (!pm_runtime_enabled(&pdev->dev)) {1299 ret = fsl_micfil_runtime_resume(&pdev->dev);1300 if (ret)1301 goto err_pm_disable;1302 }1303 1304 ret = pm_runtime_resume_and_get(&pdev->dev);1305 if (ret < 0)1306 goto err_pm_get_sync;1307 1308 /* Get micfil version */1309 ret = fsl_micfil_use_verid(&pdev->dev);1310 if (ret < 0)1311 dev_warn(&pdev->dev, "Error reading MICFIL version: %d\n", ret);1312 1313 ret = pm_runtime_put_sync(&pdev->dev);1314 if (ret < 0 && ret != -ENOSYS)1315 goto err_pm_get_sync;1316 1317 regcache_cache_only(micfil->regmap, true);1318 1319 /*1320 * Register platform component before registering cpu dai for there1321 * is not defer probe for platform component in snd_soc_add_pcm_runtime().1322 */1323 ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);1324 if (ret) {1325 dev_err(&pdev->dev, "failed to pcm register\n");1326 goto err_pm_disable;1327 }1328 1329 fsl_micfil_dai.capture.formats = micfil->soc->formats;1330 1331 ret = devm_snd_soc_register_component(&pdev->dev, &fsl_micfil_component,1332 &fsl_micfil_dai, 1);1333 if (ret) {1334 dev_err(&pdev->dev, "failed to register component %s\n",1335 fsl_micfil_component.name);1336 goto err_pm_disable;1337 }1338 1339 return ret;1340 1341err_pm_get_sync:1342 if (!pm_runtime_status_suspended(&pdev->dev))1343 fsl_micfil_runtime_suspend(&pdev->dev);1344err_pm_disable:1345 pm_runtime_disable(&pdev->dev);1346 1347 return ret;1348}1349 1350static void fsl_micfil_remove(struct platform_device *pdev)1351{1352 pm_runtime_disable(&pdev->dev);1353}1354 1355static int fsl_micfil_runtime_suspend(struct device *dev)1356{1357 struct fsl_micfil *micfil = dev_get_drvdata(dev);1358 1359 regcache_cache_only(micfil->regmap, true);1360 1361 clk_disable_unprepare(micfil->mclk);1362 clk_disable_unprepare(micfil->busclk);1363 1364 return 0;1365}1366 1367static int fsl_micfil_runtime_resume(struct device *dev)1368{1369 struct fsl_micfil *micfil = dev_get_drvdata(dev);1370 int ret;1371 1372 ret = clk_prepare_enable(micfil->busclk);1373 if (ret < 0)1374 return ret;1375 1376 ret = clk_prepare_enable(micfil->mclk);1377 if (ret < 0) {1378 clk_disable_unprepare(micfil->busclk);1379 return ret;1380 }1381 1382 regcache_cache_only(micfil->regmap, false);1383 regcache_mark_dirty(micfil->regmap);1384 regcache_sync(micfil->regmap);1385 1386 return 0;1387}1388 1389static const struct dev_pm_ops fsl_micfil_pm_ops = {1390 SET_RUNTIME_PM_OPS(fsl_micfil_runtime_suspend,1391 fsl_micfil_runtime_resume,1392 NULL)1393 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,1394 pm_runtime_force_resume)1395};1396 1397static struct platform_driver fsl_micfil_driver = {1398 .probe = fsl_micfil_probe,1399 .remove = fsl_micfil_remove,1400 .driver = {1401 .name = "fsl-micfil-dai",1402 .pm = &fsl_micfil_pm_ops,1403 .of_match_table = fsl_micfil_dt_ids,1404 },1405};1406module_platform_driver(fsl_micfil_driver);1407 1408MODULE_AUTHOR("Cosmin-Gabriel Samoila <cosmin.samoila@nxp.com>");1409MODULE_DESCRIPTION("NXP PDM Microphone Interface (MICFIL) driver");1410MODULE_LICENSE("Dual BSD/GPL");1411