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1// SPDX-License-Identifier: GPL-2.02//3// Freescale S/PDIF ALSA SoC Digital Audio Interface (DAI) driver4//5// Copyright (C) 2013 Freescale Semiconductor, Inc.6//7// Based on stmp3xxx_spdif_dai.c8// Vladimir Barinov <vbarinov@embeddedalley.com>9// Copyright 2008 SigmaTel, Inc10// Copyright 2008 Embedded Alley Solutions, Inc11 12#include <linux/bitrev.h>13#include <linux/clk.h>14#include <linux/module.h>15#include <linux/of.h>16#include <linux/regmap.h>17#include <linux/pm_runtime.h>18 19#include <sound/asoundef.h>20#include <sound/dmaengine_pcm.h>21#include <sound/soc.h>22 23#include "fsl_spdif.h"24#include "fsl_utils.h"25#include "imx-pcm.h"26 27#define FSL_SPDIF_TXFIFO_WML 0x828#define FSL_SPDIF_RXFIFO_WML 0x829 30#define INTR_FOR_PLAYBACK (INT_TXFIFO_RESYNC)31#define INTR_FOR_CAPTURE (INT_SYM_ERR | INT_BIT_ERR | INT_URX_FUL |\32 INT_URX_OV | INT_QRX_FUL | INT_QRX_OV |\33 INT_UQ_SYNC | INT_UQ_ERR | INT_RXFIFO_RESYNC |\34 INT_LOSS_LOCK | INT_DPLL_LOCKED)35 36#define SIE_INTR_FOR(tx) (tx ? INTR_FOR_PLAYBACK : INTR_FOR_CAPTURE)37 38/* Index list for the values that has if (DPLL Locked) condition */39static u8 srpc_dpll_locked[] = { 0x0, 0x1, 0x2, 0x3, 0x4, 0xa, 0xb };40#define SRPC_NODPLL_START1 0x541#define SRPC_NODPLL_START2 0xc42 43#define DEFAULT_RXCLK_SRC 144 45#define RX_SAMPLE_RATE_KCONTROL "RX Sample Rate"46 47/**48 * struct fsl_spdif_soc_data: soc specific data49 *50 * @imx: for imx platform51 * @shared_root_clock: flag of sharing a clock source with others;52 * so the driver shouldn't set root clock rate53 * @raw_capture_mode: if raw capture mode support54 * @cchannel_192b: if there are registers for 192bits C channel data55 * @interrupts: interrupt number56 * @tx_burst: tx maxburst size57 * @rx_burst: rx maxburst size58 * @tx_formats: tx supported data format59 */60struct fsl_spdif_soc_data {61 bool imx;62 bool shared_root_clock;63 bool raw_capture_mode;64 bool cchannel_192b;65 u32 interrupts;66 u32 tx_burst;67 u32 rx_burst;68 u64 tx_formats;69};70 71/*72 * SPDIF control structure73 * Defines channel status, subcode and Q sub74 */75struct spdif_mixer_control {76 /* spinlock to access control data */77 spinlock_t ctl_lock;78 79 /* IEC958 channel tx status bit */80 unsigned char ch_status[4];81 82 /* User bits */83 unsigned char subcode[2 * SPDIF_UBITS_SIZE];84 85 /* Q subcode part of user bits */86 unsigned char qsub[2 * SPDIF_QSUB_SIZE];87 88 /* Buffer offset for U/Q */89 u32 upos;90 u32 qpos;91 92 /* Ready buffer index of the two buffers */93 u32 ready_buf;94};95 96/**97 * struct fsl_spdif_priv - Freescale SPDIF private data98 * @soc: SPDIF soc data99 * @fsl_spdif_control: SPDIF control data100 * @cpu_dai_drv: cpu dai driver101 * @snd_card: sound card pointer102 * @rxrate_kcontrol: kcontrol for RX Sample Rate103 * @pdev: platform device pointer104 * @regmap: regmap handler105 * @dpll_locked: dpll lock flag106 * @txrate: the best rates for playback107 * @txclk_df: STC_TXCLK_DF dividers value for playback108 * @sysclk_df: STC_SYSCLK_DF dividers value for playback109 * @txclk_src: STC_TXCLK_SRC values for playback110 * @rxclk_src: SRPC_CLKSRC_SEL values for capture111 * @txclk: tx clock sources for playback112 * @rxclk: rx clock sources for capture113 * @coreclk: core clock for register access via DMA114 * @sysclk: system clock for rx clock rate measurement115 * @spbaclk: SPBA clock (optional, depending on SoC design)116 * @dma_params_tx: DMA parameters for transmit channel117 * @dma_params_rx: DMA parameters for receive channel118 * @regcache_srpc: regcache for SRPC119 * @bypass: status of bypass input to output120 * @pll8k_clk: PLL clock for the rate of multiply of 8kHz121 * @pll11k_clk: PLL clock for the rate of multiply of 11kHz122 */123struct fsl_spdif_priv {124 const struct fsl_spdif_soc_data *soc;125 struct spdif_mixer_control fsl_spdif_control;126 struct snd_soc_dai_driver cpu_dai_drv;127 struct snd_card *snd_card;128 struct snd_kcontrol *rxrate_kcontrol;129 struct platform_device *pdev;130 struct regmap *regmap;131 bool dpll_locked;132 u32 txrate[SPDIF_TXRATE_MAX];133 u8 txclk_df[SPDIF_TXRATE_MAX];134 u16 sysclk_df[SPDIF_TXRATE_MAX];135 u8 txclk_src[SPDIF_TXRATE_MAX];136 u8 rxclk_src;137 struct clk *txclk[STC_TXCLK_SRC_MAX];138 struct clk *rxclk;139 struct clk *coreclk;140 struct clk *sysclk;141 struct clk *spbaclk;142 struct snd_dmaengine_dai_dma_data dma_params_tx;143 struct snd_dmaengine_dai_dma_data dma_params_rx;144 /* regcache for SRPC */145 u32 regcache_srpc;146 bool bypass;147 struct clk *pll8k_clk;148 struct clk *pll11k_clk;149};150 151static struct fsl_spdif_soc_data fsl_spdif_vf610 = {152 .imx = false,153 .shared_root_clock = false,154 .raw_capture_mode = false,155 .interrupts = 1,156 .tx_burst = FSL_SPDIF_TXFIFO_WML,157 .rx_burst = FSL_SPDIF_RXFIFO_WML,158 .tx_formats = FSL_SPDIF_FORMATS_PLAYBACK,159};160 161static struct fsl_spdif_soc_data fsl_spdif_imx35 = {162 .imx = true,163 .shared_root_clock = false,164 .raw_capture_mode = false,165 .interrupts = 1,166 .tx_burst = FSL_SPDIF_TXFIFO_WML,167 .rx_burst = FSL_SPDIF_RXFIFO_WML,168 .tx_formats = FSL_SPDIF_FORMATS_PLAYBACK,169};170 171static struct fsl_spdif_soc_data fsl_spdif_imx6sx = {172 .imx = true,173 .shared_root_clock = true,174 .raw_capture_mode = false,175 .interrupts = 1,176 .tx_burst = FSL_SPDIF_TXFIFO_WML,177 .rx_burst = FSL_SPDIF_RXFIFO_WML,178 .tx_formats = FSL_SPDIF_FORMATS_PLAYBACK,179 180};181 182static struct fsl_spdif_soc_data fsl_spdif_imx8qm = {183 .imx = true,184 .shared_root_clock = true,185 .raw_capture_mode = false,186 .interrupts = 2,187 .tx_burst = 2, /* Applied for EDMA */188 .rx_burst = 2, /* Applied for EDMA */189 .tx_formats = SNDRV_PCM_FMTBIT_S24_LE, /* Applied for EDMA */190};191 192static struct fsl_spdif_soc_data fsl_spdif_imx8mm = {193 .imx = true,194 .shared_root_clock = false,195 .raw_capture_mode = true,196 .interrupts = 1,197 .tx_burst = FSL_SPDIF_TXFIFO_WML,198 .rx_burst = FSL_SPDIF_RXFIFO_WML,199 .tx_formats = FSL_SPDIF_FORMATS_PLAYBACK,200};201 202static struct fsl_spdif_soc_data fsl_spdif_imx8ulp = {203 .imx = true,204 .shared_root_clock = true,205 .raw_capture_mode = false,206 .interrupts = 1,207 .tx_burst = 2, /* Applied for EDMA */208 .rx_burst = 2, /* Applied for EDMA */209 .tx_formats = SNDRV_PCM_FMTBIT_S24_LE, /* Applied for EDMA */210 .cchannel_192b = true,211};212 213/* Check if clk is a root clock that does not share clock source with others */214static inline bool fsl_spdif_can_set_clk_rate(struct fsl_spdif_priv *spdif, int clk)215{216 return (clk == STC_TXCLK_SPDIF_ROOT) && !spdif->soc->shared_root_clock;217}218 219/* DPLL locked and lock loss interrupt handler */220static void spdif_irq_dpll_lock(struct fsl_spdif_priv *spdif_priv)221{222 struct regmap *regmap = spdif_priv->regmap;223 struct platform_device *pdev = spdif_priv->pdev;224 u32 locked;225 226 regmap_read(regmap, REG_SPDIF_SRPC, &locked);227 locked &= SRPC_DPLL_LOCKED;228 229 dev_dbg(&pdev->dev, "isr: Rx dpll %s \n",230 locked ? "locked" : "loss lock");231 232 spdif_priv->dpll_locked = locked ? true : false;233 234 if (spdif_priv->snd_card && spdif_priv->rxrate_kcontrol) {235 snd_ctl_notify(spdif_priv->snd_card,236 SNDRV_CTL_EVENT_MASK_VALUE,237 &spdif_priv->rxrate_kcontrol->id);238 }239}240 241/* Receiver found illegal symbol interrupt handler */242static void spdif_irq_sym_error(struct fsl_spdif_priv *spdif_priv)243{244 struct regmap *regmap = spdif_priv->regmap;245 struct platform_device *pdev = spdif_priv->pdev;246 247 dev_dbg(&pdev->dev, "isr: receiver found illegal symbol\n");248 249 /* Clear illegal symbol if DPLL unlocked since no audio stream */250 if (!spdif_priv->dpll_locked)251 regmap_update_bits(regmap, REG_SPDIF_SIE, INT_SYM_ERR, 0);252}253 254/* U/Q Channel receive register full */255static void spdif_irq_uqrx_full(struct fsl_spdif_priv *spdif_priv, char name)256{257 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;258 struct regmap *regmap = spdif_priv->regmap;259 struct platform_device *pdev = spdif_priv->pdev;260 u32 *pos, size, val, reg;261 262 switch (name) {263 case 'U':264 pos = &ctrl->upos;265 size = SPDIF_UBITS_SIZE;266 reg = REG_SPDIF_SRU;267 break;268 case 'Q':269 pos = &ctrl->qpos;270 size = SPDIF_QSUB_SIZE;271 reg = REG_SPDIF_SRQ;272 break;273 default:274 dev_err(&pdev->dev, "unsupported channel name\n");275 return;276 }277 278 dev_dbg(&pdev->dev, "isr: %c Channel receive register full\n", name);279 280 if (*pos >= size * 2) {281 *pos = 0;282 } else if (unlikely((*pos % size) + 3 > size)) {283 dev_err(&pdev->dev, "User bit receive buffer overflow\n");284 return;285 }286 287 regmap_read(regmap, reg, &val);288 ctrl->subcode[*pos++] = val >> 16;289 ctrl->subcode[*pos++] = val >> 8;290 ctrl->subcode[*pos++] = val;291}292 293/* U/Q Channel sync found */294static void spdif_irq_uq_sync(struct fsl_spdif_priv *spdif_priv)295{296 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;297 struct platform_device *pdev = spdif_priv->pdev;298 299 dev_dbg(&pdev->dev, "isr: U/Q Channel sync found\n");300 301 /* U/Q buffer reset */302 if (ctrl->qpos == 0)303 return;304 305 /* Set ready to this buffer */306 ctrl->ready_buf = (ctrl->qpos - 1) / SPDIF_QSUB_SIZE + 1;307}308 309/* U/Q Channel framing error */310static void spdif_irq_uq_err(struct fsl_spdif_priv *spdif_priv)311{312 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;313 struct regmap *regmap = spdif_priv->regmap;314 struct platform_device *pdev = spdif_priv->pdev;315 u32 val;316 317 dev_dbg(&pdev->dev, "isr: U/Q Channel framing error\n");318 319 /* Read U/Q data to clear the irq and do buffer reset */320 regmap_read(regmap, REG_SPDIF_SRU, &val);321 regmap_read(regmap, REG_SPDIF_SRQ, &val);322 323 /* Drop this U/Q buffer */324 ctrl->ready_buf = 0;325 ctrl->upos = 0;326 ctrl->qpos = 0;327}328 329/* Get spdif interrupt status and clear the interrupt */330static u32 spdif_intr_status_clear(struct fsl_spdif_priv *spdif_priv)331{332 struct regmap *regmap = spdif_priv->regmap;333 u32 val, val2;334 335 regmap_read(regmap, REG_SPDIF_SIS, &val);336 regmap_read(regmap, REG_SPDIF_SIE, &val2);337 338 regmap_write(regmap, REG_SPDIF_SIC, val & val2);339 340 return val;341}342 343static irqreturn_t spdif_isr(int irq, void *devid)344{345 struct fsl_spdif_priv *spdif_priv = (struct fsl_spdif_priv *)devid;346 struct platform_device *pdev = spdif_priv->pdev;347 u32 sis;348 349 sis = spdif_intr_status_clear(spdif_priv);350 351 if (sis & INT_DPLL_LOCKED)352 spdif_irq_dpll_lock(spdif_priv);353 354 if (sis & INT_TXFIFO_UNOV)355 dev_dbg(&pdev->dev, "isr: Tx FIFO under/overrun\n");356 357 if (sis & INT_TXFIFO_RESYNC)358 dev_dbg(&pdev->dev, "isr: Tx FIFO resync\n");359 360 if (sis & INT_CNEW)361 dev_dbg(&pdev->dev, "isr: cstatus new\n");362 363 if (sis & INT_VAL_NOGOOD)364 dev_dbg(&pdev->dev, "isr: validity flag no good\n");365 366 if (sis & INT_SYM_ERR)367 spdif_irq_sym_error(spdif_priv);368 369 if (sis & INT_BIT_ERR)370 dev_dbg(&pdev->dev, "isr: receiver found parity bit error\n");371 372 if (sis & INT_URX_FUL)373 spdif_irq_uqrx_full(spdif_priv, 'U');374 375 if (sis & INT_URX_OV)376 dev_dbg(&pdev->dev, "isr: U Channel receive register overrun\n");377 378 if (sis & INT_QRX_FUL)379 spdif_irq_uqrx_full(spdif_priv, 'Q');380 381 if (sis & INT_QRX_OV)382 dev_dbg(&pdev->dev, "isr: Q Channel receive register overrun\n");383 384 if (sis & INT_UQ_SYNC)385 spdif_irq_uq_sync(spdif_priv);386 387 if (sis & INT_UQ_ERR)388 spdif_irq_uq_err(spdif_priv);389 390 if (sis & INT_RXFIFO_UNOV)391 dev_dbg(&pdev->dev, "isr: Rx FIFO under/overrun\n");392 393 if (sis & INT_RXFIFO_RESYNC)394 dev_dbg(&pdev->dev, "isr: Rx FIFO resync\n");395 396 if (sis & INT_LOSS_LOCK)397 spdif_irq_dpll_lock(spdif_priv);398 399 /* FIXME: Write Tx FIFO to clear TxEm */400 if (sis & INT_TX_EM)401 dev_dbg(&pdev->dev, "isr: Tx FIFO empty\n");402 403 /* FIXME: Read Rx FIFO to clear RxFIFOFul */404 if (sis & INT_RXFIFO_FUL)405 dev_dbg(&pdev->dev, "isr: Rx FIFO full\n");406 407 return IRQ_HANDLED;408}409 410static int spdif_softreset(struct fsl_spdif_priv *spdif_priv)411{412 struct regmap *regmap = spdif_priv->regmap;413 u32 val, cycle = 1000;414 415 regcache_cache_bypass(regmap, true);416 417 regmap_write(regmap, REG_SPDIF_SCR, SCR_SOFT_RESET);418 419 /*420 * RESET bit would be cleared after finishing its reset procedure,421 * which typically lasts 8 cycles. 1000 cycles will keep it safe.422 */423 do {424 regmap_read(regmap, REG_SPDIF_SCR, &val);425 } while ((val & SCR_SOFT_RESET) && cycle--);426 427 regcache_cache_bypass(regmap, false);428 regcache_mark_dirty(regmap);429 regcache_sync(regmap);430 431 if (cycle)432 return 0;433 else434 return -EBUSY;435}436 437static void spdif_set_cstatus(struct spdif_mixer_control *ctrl,438 u8 mask, u8 cstatus)439{440 ctrl->ch_status[3] &= ~mask;441 ctrl->ch_status[3] |= cstatus & mask;442}443 444static void spdif_write_channel_status(struct fsl_spdif_priv *spdif_priv)445{446 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;447 struct regmap *regmap = spdif_priv->regmap;448 struct platform_device *pdev = spdif_priv->pdev;449 u32 ch_status;450 451 ch_status = (bitrev8(ctrl->ch_status[0]) << 16) |452 (bitrev8(ctrl->ch_status[1]) << 8) |453 bitrev8(ctrl->ch_status[2]);454 regmap_write(regmap, REG_SPDIF_STCSCH, ch_status);455 456 dev_dbg(&pdev->dev, "STCSCH: 0x%06x\n", ch_status);457 458 ch_status = bitrev8(ctrl->ch_status[3]) << 16;459 regmap_write(regmap, REG_SPDIF_STCSCL, ch_status);460 461 dev_dbg(&pdev->dev, "STCSCL: 0x%06x\n", ch_status);462 463 if (spdif_priv->soc->cchannel_192b) {464 ch_status = (bitrev8(ctrl->ch_status[0]) << 24) |465 (bitrev8(ctrl->ch_status[1]) << 16) |466 (bitrev8(ctrl->ch_status[2]) << 8) |467 bitrev8(ctrl->ch_status[3]);468 469 regmap_update_bits(regmap, REG_SPDIF_SCR, 0x1000000, 0x1000000);470 471 /*472 * The first 32bit should be in REG_SPDIF_STCCA_31_0 register,473 * but here we need to set REG_SPDIF_STCCA_191_160 on 8ULP474 * then can get correct result with HDMI analyzer capture.475 * There is a hardware bug here.476 */477 regmap_write(regmap, REG_SPDIF_STCCA_191_160, ch_status);478 }479}480 481/* Set SPDIF PhaseConfig register for rx clock */482static int spdif_set_rx_clksrc(struct fsl_spdif_priv *spdif_priv,483 enum spdif_gainsel gainsel, int dpll_locked)484{485 struct regmap *regmap = spdif_priv->regmap;486 u8 clksrc = spdif_priv->rxclk_src;487 488 if (clksrc >= SRPC_CLKSRC_MAX || gainsel >= GAINSEL_MULTI_MAX)489 return -EINVAL;490 491 regmap_update_bits(regmap, REG_SPDIF_SRPC,492 SRPC_CLKSRC_SEL_MASK | SRPC_GAINSEL_MASK,493 SRPC_CLKSRC_SEL_SET(clksrc) | SRPC_GAINSEL_SET(gainsel));494 495 return 0;496}497 498static int fsl_spdif_probe_txclk(struct fsl_spdif_priv *spdif_priv, enum spdif_txrate index);499 500static int spdif_set_sample_rate(struct snd_pcm_substream *substream,501 int sample_rate)502{503 struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream);504 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(snd_soc_rtd_to_cpu(rtd, 0));505 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;506 struct regmap *regmap = spdif_priv->regmap;507 struct platform_device *pdev = spdif_priv->pdev;508 unsigned long csfs = 0;509 u32 stc, mask, rate;510 u16 sysclk_df;511 u8 clk, txclk_df;512 int ret;513 514 switch (sample_rate) {515 case 22050:516 rate = SPDIF_TXRATE_22050;517 csfs = IEC958_AES3_CON_FS_22050;518 break;519 case 32000:520 rate = SPDIF_TXRATE_32000;521 csfs = IEC958_AES3_CON_FS_32000;522 break;523 case 44100:524 rate = SPDIF_TXRATE_44100;525 csfs = IEC958_AES3_CON_FS_44100;526 break;527 case 48000:528 rate = SPDIF_TXRATE_48000;529 csfs = IEC958_AES3_CON_FS_48000;530 break;531 case 88200:532 rate = SPDIF_TXRATE_88200;533 csfs = IEC958_AES3_CON_FS_88200;534 break;535 case 96000:536 rate = SPDIF_TXRATE_96000;537 csfs = IEC958_AES3_CON_FS_96000;538 break;539 case 176400:540 rate = SPDIF_TXRATE_176400;541 csfs = IEC958_AES3_CON_FS_176400;542 break;543 case 192000:544 rate = SPDIF_TXRATE_192000;545 csfs = IEC958_AES3_CON_FS_192000;546 break;547 default:548 dev_err(&pdev->dev, "unsupported sample rate %d\n", sample_rate);549 return -EINVAL;550 }551 552 ret = fsl_spdif_probe_txclk(spdif_priv, rate);553 if (ret)554 return ret;555 556 clk = spdif_priv->txclk_src[rate];557 if (clk >= STC_TXCLK_SRC_MAX) {558 dev_err(&pdev->dev, "tx clock source is out of range\n");559 return -EINVAL;560 }561 562 txclk_df = spdif_priv->txclk_df[rate];563 if (txclk_df == 0) {564 dev_err(&pdev->dev, "the txclk_df can't be zero\n");565 return -EINVAL;566 }567 568 sysclk_df = spdif_priv->sysclk_df[rate];569 570 if (!fsl_spdif_can_set_clk_rate(spdif_priv, clk))571 goto clk_set_bypass;572 573 /* The S/PDIF block needs a clock of 64 * fs * txclk_df */574 ret = clk_set_rate(spdif_priv->txclk[clk],575 64 * sample_rate * txclk_df);576 if (ret) {577 dev_err(&pdev->dev, "failed to set tx clock rate\n");578 return ret;579 }580 581clk_set_bypass:582 dev_dbg(&pdev->dev, "expected clock rate = %d\n",583 (64 * sample_rate * txclk_df * sysclk_df));584 dev_dbg(&pdev->dev, "actual clock rate = %ld\n",585 clk_get_rate(spdif_priv->txclk[clk]));586 587 /* set fs field in consumer channel status */588 spdif_set_cstatus(ctrl, IEC958_AES3_CON_FS, csfs);589 590 /* select clock source and divisor */591 stc = STC_TXCLK_ALL_EN | STC_TXCLK_SRC_SET(clk) |592 STC_TXCLK_DF(txclk_df) | STC_SYSCLK_DF(sysclk_df);593 mask = STC_TXCLK_ALL_EN_MASK | STC_TXCLK_SRC_MASK |594 STC_TXCLK_DF_MASK | STC_SYSCLK_DF_MASK;595 regmap_update_bits(regmap, REG_SPDIF_STC, mask, stc);596 597 dev_dbg(&pdev->dev, "set sample rate to %dHz for %dHz playback\n",598 spdif_priv->txrate[rate], sample_rate);599 600 return 0;601}602 603static int fsl_spdif_startup(struct snd_pcm_substream *substream,604 struct snd_soc_dai *cpu_dai)605{606 struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream);607 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(snd_soc_rtd_to_cpu(rtd, 0));608 struct platform_device *pdev = spdif_priv->pdev;609 struct regmap *regmap = spdif_priv->regmap;610 u32 scr, mask;611 int ret;612 613 /* Reset module and interrupts only for first initialization */614 if (!snd_soc_dai_active(cpu_dai)) {615 ret = spdif_softreset(spdif_priv);616 if (ret) {617 dev_err(&pdev->dev, "failed to soft reset\n");618 return ret;619 }620 621 /* Disable all the interrupts */622 regmap_update_bits(regmap, REG_SPDIF_SIE, 0xffffff, 0);623 }624 625 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {626 scr = SCR_TXFIFO_AUTOSYNC | SCR_TXFIFO_CTRL_NORMAL |627 SCR_TXSEL_NORMAL | SCR_USRC_SEL_CHIP |628 SCR_TXFIFO_FSEL_IF8;629 mask = SCR_TXFIFO_AUTOSYNC_MASK | SCR_TXFIFO_CTRL_MASK |630 SCR_TXSEL_MASK | SCR_USRC_SEL_MASK |631 SCR_TXFIFO_FSEL_MASK;632 } else {633 scr = SCR_RXFIFO_FSEL_IF8 | SCR_RXFIFO_AUTOSYNC;634 mask = SCR_RXFIFO_FSEL_MASK | SCR_RXFIFO_AUTOSYNC_MASK|635 SCR_RXFIFO_CTL_MASK | SCR_RXFIFO_OFF_MASK;636 }637 regmap_update_bits(regmap, REG_SPDIF_SCR, mask, scr);638 639 /* Power up SPDIF module */640 regmap_update_bits(regmap, REG_SPDIF_SCR, SCR_LOW_POWER, 0);641 642 return 0;643}644 645static void fsl_spdif_shutdown(struct snd_pcm_substream *substream,646 struct snd_soc_dai *cpu_dai)647{648 struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream);649 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(snd_soc_rtd_to_cpu(rtd, 0));650 struct regmap *regmap = spdif_priv->regmap;651 u32 scr, mask;652 653 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {654 scr = 0;655 mask = SCR_TXFIFO_AUTOSYNC_MASK | SCR_TXFIFO_CTRL_MASK |656 SCR_TXSEL_MASK | SCR_USRC_SEL_MASK |657 SCR_TXFIFO_FSEL_MASK;658 /* Disable TX clock */659 regmap_update_bits(regmap, REG_SPDIF_STC, STC_TXCLK_ALL_EN_MASK, 0);660 } else {661 scr = SCR_RXFIFO_OFF | SCR_RXFIFO_CTL_ZERO;662 mask = SCR_RXFIFO_FSEL_MASK | SCR_RXFIFO_AUTOSYNC_MASK|663 SCR_RXFIFO_CTL_MASK | SCR_RXFIFO_OFF_MASK;664 }665 regmap_update_bits(regmap, REG_SPDIF_SCR, mask, scr);666 667 /* Power down SPDIF module only if tx&rx are both inactive */668 if (!snd_soc_dai_active(cpu_dai)) {669 spdif_intr_status_clear(spdif_priv);670 regmap_update_bits(regmap, REG_SPDIF_SCR,671 SCR_LOW_POWER, SCR_LOW_POWER);672 }673}674 675static int spdif_reparent_rootclk(struct fsl_spdif_priv *spdif_priv, unsigned int sample_rate)676{677 struct platform_device *pdev = spdif_priv->pdev;678 struct clk *clk;679 int ret;680 681 /* Reparent clock if required condition is true */682 if (!fsl_spdif_can_set_clk_rate(spdif_priv, STC_TXCLK_SPDIF_ROOT))683 return 0;684 685 /* Get root clock */686 clk = spdif_priv->txclk[STC_TXCLK_SPDIF_ROOT];687 688 /* Disable clock first, for it was enabled by pm_runtime */689 clk_disable_unprepare(clk);690 fsl_asoc_reparent_pll_clocks(&pdev->dev, clk, spdif_priv->pll8k_clk,691 spdif_priv->pll11k_clk, sample_rate);692 ret = clk_prepare_enable(clk);693 if (ret)694 return ret;695 696 return 0;697}698static int fsl_spdif_hw_params(struct snd_pcm_substream *substream,699 struct snd_pcm_hw_params *params,700 struct snd_soc_dai *dai)701{702 struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream);703 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(snd_soc_rtd_to_cpu(rtd, 0));704 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;705 struct platform_device *pdev = spdif_priv->pdev;706 u32 sample_rate = params_rate(params);707 int ret = 0;708 709 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {710 ret = spdif_reparent_rootclk(spdif_priv, sample_rate);711 if (ret) {712 dev_err(&pdev->dev, "%s: reparent root clk failed: %d\n",713 __func__, sample_rate);714 return ret;715 }716 717 ret = spdif_set_sample_rate(substream, sample_rate);718 if (ret) {719 dev_err(&pdev->dev, "%s: set sample rate failed: %d\n",720 __func__, sample_rate);721 return ret;722 }723 spdif_set_cstatus(ctrl, IEC958_AES3_CON_CLOCK,724 IEC958_AES3_CON_CLOCK_1000PPM);725 spdif_write_channel_status(spdif_priv);726 } else {727 /* Setup rx clock source */728 ret = spdif_set_rx_clksrc(spdif_priv, SPDIF_DEFAULT_GAINSEL, 1);729 }730 731 return ret;732}733 734static int fsl_spdif_trigger(struct snd_pcm_substream *substream,735 int cmd, struct snd_soc_dai *dai)736{737 struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream);738 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(snd_soc_rtd_to_cpu(rtd, 0));739 struct regmap *regmap = spdif_priv->regmap;740 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;741 u32 intr = SIE_INTR_FOR(tx);742 u32 dmaen = SCR_DMA_xX_EN(tx);743 744 switch (cmd) {745 case SNDRV_PCM_TRIGGER_START:746 case SNDRV_PCM_TRIGGER_RESUME:747 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:748 regmap_update_bits(regmap, REG_SPDIF_SIE, intr, intr);749 regmap_update_bits(regmap, REG_SPDIF_SCR, dmaen, dmaen);750 break;751 case SNDRV_PCM_TRIGGER_STOP:752 case SNDRV_PCM_TRIGGER_SUSPEND:753 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:754 regmap_update_bits(regmap, REG_SPDIF_SCR, dmaen, 0);755 regmap_update_bits(regmap, REG_SPDIF_SIE, intr, 0);756 regmap_write(regmap, REG_SPDIF_STL, 0x0);757 regmap_write(regmap, REG_SPDIF_STR, 0x0);758 break;759 default:760 return -EINVAL;761 }762 763 return 0;764}765 766/*767 * FSL SPDIF IEC958 controller(mixer) functions768 *769 * Channel status get/put control770 * User bit value get/put control771 * Valid bit value get control772 * DPLL lock status get control773 * User bit sync mode selection control774 */775 776static int fsl_spdif_info(struct snd_kcontrol *kcontrol,777 struct snd_ctl_elem_info *uinfo)778{779 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;780 uinfo->count = 1;781 782 return 0;783}784 785static int fsl_spdif_pb_get(struct snd_kcontrol *kcontrol,786 struct snd_ctl_elem_value *uvalue)787{788 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);789 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);790 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;791 792 uvalue->value.iec958.status[0] = ctrl->ch_status[0];793 uvalue->value.iec958.status[1] = ctrl->ch_status[1];794 uvalue->value.iec958.status[2] = ctrl->ch_status[2];795 uvalue->value.iec958.status[3] = ctrl->ch_status[3];796 797 return 0;798}799 800static int fsl_spdif_pb_put(struct snd_kcontrol *kcontrol,801 struct snd_ctl_elem_value *uvalue)802{803 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);804 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);805 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;806 807 ctrl->ch_status[0] = uvalue->value.iec958.status[0];808 ctrl->ch_status[1] = uvalue->value.iec958.status[1];809 ctrl->ch_status[2] = uvalue->value.iec958.status[2];810 ctrl->ch_status[3] = uvalue->value.iec958.status[3];811 812 spdif_write_channel_status(spdif_priv);813 814 return 0;815}816 817/* Get channel status from SPDIF_RX_CCHAN register */818static int fsl_spdif_capture_get(struct snd_kcontrol *kcontrol,819 struct snd_ctl_elem_value *ucontrol)820{821 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);822 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);823 struct regmap *regmap = spdif_priv->regmap;824 u32 cstatus, val;825 826 regmap_read(regmap, REG_SPDIF_SIS, &val);827 if (!(val & INT_CNEW))828 return -EAGAIN;829 830 regmap_read(regmap, REG_SPDIF_SRCSH, &cstatus);831 ucontrol->value.iec958.status[0] = (cstatus >> 16) & 0xFF;832 ucontrol->value.iec958.status[1] = (cstatus >> 8) & 0xFF;833 ucontrol->value.iec958.status[2] = cstatus & 0xFF;834 835 regmap_read(regmap, REG_SPDIF_SRCSL, &cstatus);836 ucontrol->value.iec958.status[3] = (cstatus >> 16) & 0xFF;837 ucontrol->value.iec958.status[4] = (cstatus >> 8) & 0xFF;838 ucontrol->value.iec958.status[5] = cstatus & 0xFF;839 840 /* Clear intr */841 regmap_write(regmap, REG_SPDIF_SIC, INT_CNEW);842 843 return 0;844}845 846/*847 * Get User bits (subcode) from chip value which readed out848 * in UChannel register.849 */850static int fsl_spdif_subcode_get(struct snd_kcontrol *kcontrol,851 struct snd_ctl_elem_value *ucontrol)852{853 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);854 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);855 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;856 unsigned long flags;857 int ret = -EAGAIN;858 859 spin_lock_irqsave(&ctrl->ctl_lock, flags);860 if (ctrl->ready_buf) {861 int idx = (ctrl->ready_buf - 1) * SPDIF_UBITS_SIZE;862 memcpy(&ucontrol->value.iec958.subcode[0],863 &ctrl->subcode[idx], SPDIF_UBITS_SIZE);864 ret = 0;865 }866 spin_unlock_irqrestore(&ctrl->ctl_lock, flags);867 868 return ret;869}870 871/* Q-subcode information. The byte size is SPDIF_UBITS_SIZE/8 */872static int fsl_spdif_qinfo(struct snd_kcontrol *kcontrol,873 struct snd_ctl_elem_info *uinfo)874{875 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;876 uinfo->count = SPDIF_QSUB_SIZE;877 878 return 0;879}880 881/* Get Q subcode from chip value which readed out in QChannel register */882static int fsl_spdif_qget(struct snd_kcontrol *kcontrol,883 struct snd_ctl_elem_value *ucontrol)884{885 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);886 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);887 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;888 unsigned long flags;889 int ret = -EAGAIN;890 891 spin_lock_irqsave(&ctrl->ctl_lock, flags);892 if (ctrl->ready_buf) {893 int idx = (ctrl->ready_buf - 1) * SPDIF_QSUB_SIZE;894 memcpy(&ucontrol->value.bytes.data[0],895 &ctrl->qsub[idx], SPDIF_QSUB_SIZE);896 ret = 0;897 }898 spin_unlock_irqrestore(&ctrl->ctl_lock, flags);899 900 return ret;901}902 903/* Get valid good bit from interrupt status register */904static int fsl_spdif_rx_vbit_get(struct snd_kcontrol *kcontrol,905 struct snd_ctl_elem_value *ucontrol)906{907 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);908 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);909 struct regmap *regmap = spdif_priv->regmap;910 u32 val;911 912 regmap_read(regmap, REG_SPDIF_SIS, &val);913 ucontrol->value.integer.value[0] = (val & INT_VAL_NOGOOD) != 0;914 regmap_write(regmap, REG_SPDIF_SIC, INT_VAL_NOGOOD);915 916 return 0;917}918 919static int fsl_spdif_tx_vbit_get(struct snd_kcontrol *kcontrol,920 struct snd_ctl_elem_value *ucontrol)921{922 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);923 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);924 struct regmap *regmap = spdif_priv->regmap;925 u32 val;926 927 regmap_read(regmap, REG_SPDIF_SCR, &val);928 val = (val & SCR_VAL_MASK) >> SCR_VAL_OFFSET;929 val = 1 - val;930 ucontrol->value.integer.value[0] = val;931 932 return 0;933}934 935static int fsl_spdif_tx_vbit_put(struct snd_kcontrol *kcontrol,936 struct snd_ctl_elem_value *ucontrol)937{938 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);939 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);940 struct regmap *regmap = spdif_priv->regmap;941 u32 val = (1 - ucontrol->value.integer.value[0]) << SCR_VAL_OFFSET;942 943 regmap_update_bits(regmap, REG_SPDIF_SCR, SCR_VAL_MASK, val);944 945 return 0;946}947 948static int fsl_spdif_rx_rcm_get(struct snd_kcontrol *kcontrol,949 struct snd_ctl_elem_value *ucontrol)950{951 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);952 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);953 struct regmap *regmap = spdif_priv->regmap;954 u32 val;955 956 regmap_read(regmap, REG_SPDIF_SCR, &val);957 val = (val & SCR_RAW_CAPTURE_MODE) ? 1 : 0;958 ucontrol->value.integer.value[0] = val;959 960 return 0;961}962 963static int fsl_spdif_rx_rcm_put(struct snd_kcontrol *kcontrol,964 struct snd_ctl_elem_value *ucontrol)965{966 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);967 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);968 struct regmap *regmap = spdif_priv->regmap;969 u32 val = (ucontrol->value.integer.value[0] ? SCR_RAW_CAPTURE_MODE : 0);970 971 if (val)972 cpu_dai->driver->capture.formats |= SNDRV_PCM_FMTBIT_S32_LE;973 else974 cpu_dai->driver->capture.formats &= ~SNDRV_PCM_FMTBIT_S32_LE;975 976 regmap_update_bits(regmap, REG_SPDIF_SCR, SCR_RAW_CAPTURE_MODE, val);977 978 return 0;979}980 981static int fsl_spdif_bypass_get(struct snd_kcontrol *kcontrol,982 struct snd_ctl_elem_value *ucontrol)983{984 struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol);985 struct fsl_spdif_priv *priv = snd_soc_dai_get_drvdata(dai);986 987 ucontrol->value.integer.value[0] = priv->bypass ? 1 : 0;988 989 return 0;990}991 992static int fsl_spdif_bypass_put(struct snd_kcontrol *kcontrol,993 struct snd_ctl_elem_value *ucontrol)994{995 struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol);996 struct fsl_spdif_priv *priv = snd_soc_dai_get_drvdata(dai);997 struct snd_soc_card *card = dai->component->card;998 bool set = (ucontrol->value.integer.value[0] != 0);999 struct regmap *regmap = priv->regmap;1000 struct snd_soc_pcm_runtime *rtd;1001 u32 scr, mask;1002 int stream;1003 1004 rtd = snd_soc_get_pcm_runtime(card, card->dai_link);1005 1006 if (priv->bypass == set)1007 return 0; /* nothing to do */1008 1009 if (snd_soc_dai_active(dai)) {1010 dev_err(dai->dev, "Cannot change BYPASS mode while stream is running.\n");1011 return -EBUSY;1012 }1013 1014 pm_runtime_get_sync(dai->dev);1015 1016 if (set) {1017 /* Disable interrupts */1018 regmap_update_bits(regmap, REG_SPDIF_SIE, 0xffffff, 0);1019 1020 /* Configure BYPASS mode */1021 scr = SCR_TXSEL_RX | SCR_RXFIFO_OFF;1022 mask = SCR_RXFIFO_FSEL_MASK | SCR_RXFIFO_AUTOSYNC_MASK |1023 SCR_RXFIFO_CTL_MASK | SCR_RXFIFO_OFF_MASK | SCR_TXSEL_MASK;1024 /* Power up SPDIF module */1025 mask |= SCR_LOW_POWER;1026 } else {1027 /* Power down SPDIF module, disable TX */1028 scr = SCR_LOW_POWER | SCR_TXSEL_OFF;1029 mask = SCR_LOW_POWER | SCR_TXSEL_MASK;1030 }1031 1032 regmap_update_bits(regmap, REG_SPDIF_SCR, mask, scr);1033 1034 /* Disable playback & capture if BYPASS mode is enabled, enable otherwise */1035 for_each_pcm_streams(stream)1036 rtd->pcm->streams[stream].substream_count = (set ? 0 : 1);1037 1038 priv->bypass = set;1039 pm_runtime_put_sync(dai->dev);1040 1041 return 0;1042}1043 1044/* DPLL lock information */1045static int fsl_spdif_rxrate_info(struct snd_kcontrol *kcontrol,1046 struct snd_ctl_elem_info *uinfo)1047{1048 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;1049 uinfo->count = 1;1050 uinfo->value.integer.min = 16000;1051 uinfo->value.integer.max = 192000;1052 1053 return 0;1054}1055 1056static u32 gainsel_multi[GAINSEL_MULTI_MAX] = {1057 24, 16, 12, 8, 6, 4, 3,1058};1059 1060/* Get RX data clock rate given the SPDIF bus_clk */1061static int spdif_get_rxclk_rate(struct fsl_spdif_priv *spdif_priv,1062 enum spdif_gainsel gainsel)1063{1064 struct regmap *regmap = spdif_priv->regmap;1065 struct platform_device *pdev = spdif_priv->pdev;1066 u64 tmpval64, busclk_freq = 0;1067 u32 freqmeas, phaseconf;1068 u8 clksrc;1069 1070 regmap_read(regmap, REG_SPDIF_SRFM, &freqmeas);1071 regmap_read(regmap, REG_SPDIF_SRPC, &phaseconf);1072 1073 clksrc = (phaseconf >> SRPC_CLKSRC_SEL_OFFSET) & 0xf;1074 1075 /* Get bus clock from system */1076 if (srpc_dpll_locked[clksrc] && (phaseconf & SRPC_DPLL_LOCKED))1077 busclk_freq = clk_get_rate(spdif_priv->sysclk);1078 1079 /* FreqMeas_CLK = (BUS_CLK * FreqMeas) / 2 ^ 10 / GAINSEL / 128 */1080 tmpval64 = (u64) busclk_freq * freqmeas;1081 do_div(tmpval64, gainsel_multi[gainsel] * 1024);1082 do_div(tmpval64, 128 * 1024);1083 1084 dev_dbg(&pdev->dev, "FreqMeas: %d\n", freqmeas);1085 dev_dbg(&pdev->dev, "BusclkFreq: %lld\n", busclk_freq);1086 dev_dbg(&pdev->dev, "RxRate: %lld\n", tmpval64);1087 1088 return (int)tmpval64;1089}1090 1091/*1092 * Get DPLL lock or not info from stable interrupt status register.1093 * User application must use this control to get locked,1094 * then can do next PCM operation1095 */1096static int fsl_spdif_rxrate_get(struct snd_kcontrol *kcontrol,1097 struct snd_ctl_elem_value *ucontrol)1098{1099 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);1100 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);1101 int rate = 0;1102 1103 if (spdif_priv->dpll_locked)1104 rate = spdif_get_rxclk_rate(spdif_priv, SPDIF_DEFAULT_GAINSEL);1105 1106 ucontrol->value.integer.value[0] = rate;1107 1108 return 0;1109}1110 1111/*1112 * User bit sync mode:1113 * 1 CD User channel subcode1114 * 0 Non-CD data1115 */1116static int fsl_spdif_usync_get(struct snd_kcontrol *kcontrol,1117 struct snd_ctl_elem_value *ucontrol)1118{1119 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);1120 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);1121 struct regmap *regmap = spdif_priv->regmap;1122 u32 val;1123 1124 regmap_read(regmap, REG_SPDIF_SRCD, &val);1125 ucontrol->value.integer.value[0] = (val & SRCD_CD_USER) != 0;1126 1127 return 0;1128}1129 1130/*1131 * User bit sync mode:1132 * 1 CD User channel subcode1133 * 0 Non-CD data1134 */1135static int fsl_spdif_usync_put(struct snd_kcontrol *kcontrol,1136 struct snd_ctl_elem_value *ucontrol)1137{1138 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);1139 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);1140 struct regmap *regmap = spdif_priv->regmap;1141 u32 val = ucontrol->value.integer.value[0] << SRCD_CD_USER_OFFSET;1142 1143 regmap_update_bits(regmap, REG_SPDIF_SRCD, SRCD_CD_USER, val);1144 1145 return 0;1146}1147 1148/* FSL SPDIF IEC958 controller defines */1149static struct snd_kcontrol_new fsl_spdif_ctrls[] = {1150 /* Status cchanel controller */1151 {1152 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,1153 .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, DEFAULT),1154 .access = SNDRV_CTL_ELEM_ACCESS_READ |1155 SNDRV_CTL_ELEM_ACCESS_WRITE |1156 SNDRV_CTL_ELEM_ACCESS_VOLATILE,1157 .info = fsl_spdif_info,1158 .get = fsl_spdif_pb_get,1159 .put = fsl_spdif_pb_put,1160 },1161 {1162 .iface = SNDRV_CTL_ELEM_IFACE_PCM,1163 .name = SNDRV_CTL_NAME_IEC958("", CAPTURE, DEFAULT),1164 .access = SNDRV_CTL_ELEM_ACCESS_READ |1165 SNDRV_CTL_ELEM_ACCESS_VOLATILE,1166 .info = fsl_spdif_info,1167 .get = fsl_spdif_capture_get,1168 },1169 /* User bits controller */1170 {1171 .iface = SNDRV_CTL_ELEM_IFACE_PCM,1172 .name = "IEC958 Subcode Capture Default",1173 .access = SNDRV_CTL_ELEM_ACCESS_READ |1174 SNDRV_CTL_ELEM_ACCESS_VOLATILE,1175 .info = fsl_spdif_info,1176 .get = fsl_spdif_subcode_get,1177 },1178 {1179 .iface = SNDRV_CTL_ELEM_IFACE_PCM,1180 .name = "IEC958 Q-subcode Capture Default",1181 .access = SNDRV_CTL_ELEM_ACCESS_READ |1182 SNDRV_CTL_ELEM_ACCESS_VOLATILE,1183 .info = fsl_spdif_qinfo,1184 .get = fsl_spdif_qget,1185 },1186 /* Valid bit error controller */1187 {1188 .iface = SNDRV_CTL_ELEM_IFACE_PCM,1189 .name = "IEC958 RX V-Bit Errors",1190 .access = SNDRV_CTL_ELEM_ACCESS_READ |1191 SNDRV_CTL_ELEM_ACCESS_VOLATILE,1192 .info = snd_ctl_boolean_mono_info,1193 .get = fsl_spdif_rx_vbit_get,1194 },1195 {1196 .iface = SNDRV_CTL_ELEM_IFACE_PCM,1197 .name = "IEC958 TX V-Bit",1198 .access = SNDRV_CTL_ELEM_ACCESS_READ |1199 SNDRV_CTL_ELEM_ACCESS_WRITE |1200 SNDRV_CTL_ELEM_ACCESS_VOLATILE,1201 .info = snd_ctl_boolean_mono_info,1202 .get = fsl_spdif_tx_vbit_get,1203 .put = fsl_spdif_tx_vbit_put,1204 },1205 /* DPLL lock info get controller */1206 {1207 .iface = SNDRV_CTL_ELEM_IFACE_PCM,1208 .name = RX_SAMPLE_RATE_KCONTROL,1209 .access = SNDRV_CTL_ELEM_ACCESS_READ |1210 SNDRV_CTL_ELEM_ACCESS_VOLATILE,1211 .info = fsl_spdif_rxrate_info,1212 .get = fsl_spdif_rxrate_get,1213 },1214 /* RX bypass controller */1215 {1216 .iface = SNDRV_CTL_ELEM_IFACE_PCM,1217 .name = "Bypass Mode",1218 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE,1219 .info = snd_ctl_boolean_mono_info,1220 .get = fsl_spdif_bypass_get,1221 .put = fsl_spdif_bypass_put,1222 },1223 /* User bit sync mode set/get controller */1224 {1225 .iface = SNDRV_CTL_ELEM_IFACE_PCM,1226 .name = "IEC958 USyncMode CDText",1227 .access = SNDRV_CTL_ELEM_ACCESS_READ |1228 SNDRV_CTL_ELEM_ACCESS_WRITE |1229 SNDRV_CTL_ELEM_ACCESS_VOLATILE,1230 .info = snd_ctl_boolean_mono_info,1231 .get = fsl_spdif_usync_get,1232 .put = fsl_spdif_usync_put,1233 },1234};1235 1236static struct snd_kcontrol_new fsl_spdif_ctrls_rcm[] = {1237 {1238 .iface = SNDRV_CTL_ELEM_IFACE_PCM,1239 .name = "IEC958 Raw Capture Mode",1240 .access = SNDRV_CTL_ELEM_ACCESS_READ |1241 SNDRV_CTL_ELEM_ACCESS_WRITE |1242 SNDRV_CTL_ELEM_ACCESS_VOLATILE,1243 .info = snd_ctl_boolean_mono_info,1244 .get = fsl_spdif_rx_rcm_get,1245 .put = fsl_spdif_rx_rcm_put,1246 },1247};1248 1249static int fsl_spdif_dai_probe(struct snd_soc_dai *dai)1250{1251 struct fsl_spdif_priv *spdif_private = snd_soc_dai_get_drvdata(dai);1252 1253 snd_soc_dai_init_dma_data(dai, &spdif_private->dma_params_tx,1254 &spdif_private->dma_params_rx);1255 1256 snd_soc_add_dai_controls(dai, fsl_spdif_ctrls, ARRAY_SIZE(fsl_spdif_ctrls));1257 1258 if (spdif_private->soc->raw_capture_mode)1259 snd_soc_add_dai_controls(dai, fsl_spdif_ctrls_rcm,1260 ARRAY_SIZE(fsl_spdif_ctrls_rcm));1261 1262 spdif_private->snd_card = dai->component->card->snd_card;1263 spdif_private->rxrate_kcontrol = snd_soc_card_get_kcontrol(dai->component->card,1264 RX_SAMPLE_RATE_KCONTROL);1265 if (!spdif_private->rxrate_kcontrol)1266 dev_err(&spdif_private->pdev->dev, "failed to get %s kcontrol\n",1267 RX_SAMPLE_RATE_KCONTROL);1268 1269 /*Clear the val bit for Tx*/1270 regmap_update_bits(spdif_private->regmap, REG_SPDIF_SCR,1271 SCR_VAL_MASK, SCR_VAL_CLEAR);1272 1273 return 0;1274}1275 1276static const struct snd_soc_dai_ops fsl_spdif_dai_ops = {1277 .probe = fsl_spdif_dai_probe,1278 .startup = fsl_spdif_startup,1279 .hw_params = fsl_spdif_hw_params,1280 .trigger = fsl_spdif_trigger,1281 .shutdown = fsl_spdif_shutdown,1282};1283 1284static struct snd_soc_dai_driver fsl_spdif_dai = {1285 .playback = {1286 .stream_name = "CPU-Playback",1287 .channels_min = 2,1288 .channels_max = 2,1289 .rates = FSL_SPDIF_RATES_PLAYBACK,1290 .formats = FSL_SPDIF_FORMATS_PLAYBACK,1291 },1292 .capture = {1293 .stream_name = "CPU-Capture",1294 .channels_min = 2,1295 .channels_max = 2,1296 .rates = FSL_SPDIF_RATES_CAPTURE,1297 .formats = FSL_SPDIF_FORMATS_CAPTURE,1298 },1299 .ops = &fsl_spdif_dai_ops,1300};1301 1302static const struct snd_soc_component_driver fsl_spdif_component = {1303 .name = "fsl-spdif",1304 .legacy_dai_naming = 1,1305};1306 1307/* FSL SPDIF REGMAP */1308static const struct reg_default fsl_spdif_reg_defaults[] = {1309 {REG_SPDIF_SCR, 0x00000400},1310 {REG_SPDIF_SRCD, 0x00000000},1311 {REG_SPDIF_SIE, 0x00000000},1312 {REG_SPDIF_STL, 0x00000000},1313 {REG_SPDIF_STR, 0x00000000},1314 {REG_SPDIF_STCSCH, 0x00000000},1315 {REG_SPDIF_STCSCL, 0x00000000},1316 {REG_SPDIF_STCSPH, 0x00000000},1317 {REG_SPDIF_STCSPL, 0x00000000},1318 {REG_SPDIF_STC, 0x00020f00},1319};1320 1321static bool fsl_spdif_readable_reg(struct device *dev, unsigned int reg)1322{1323 switch (reg) {1324 case REG_SPDIF_SCR:1325 case REG_SPDIF_SRCD:1326 case REG_SPDIF_SRPC:1327 case REG_SPDIF_SIE:1328 case REG_SPDIF_SIS:1329 case REG_SPDIF_SRL:1330 case REG_SPDIF_SRR:1331 case REG_SPDIF_SRCSH:1332 case REG_SPDIF_SRCSL:1333 case REG_SPDIF_SRU:1334 case REG_SPDIF_SRQ:1335 case REG_SPDIF_STCSCH:1336 case REG_SPDIF_STCSCL:1337 case REG_SPDIF_STCSPH:1338 case REG_SPDIF_STCSPL:1339 case REG_SPDIF_SRFM:1340 case REG_SPDIF_STC:1341 case REG_SPDIF_SRCCA_31_0:1342 case REG_SPDIF_SRCCA_63_32:1343 case REG_SPDIF_SRCCA_95_64:1344 case REG_SPDIF_SRCCA_127_96:1345 case REG_SPDIF_SRCCA_159_128:1346 case REG_SPDIF_SRCCA_191_160:1347 case REG_SPDIF_STCCA_31_0:1348 case REG_SPDIF_STCCA_63_32:1349 case REG_SPDIF_STCCA_95_64:1350 case REG_SPDIF_STCCA_127_96:1351 case REG_SPDIF_STCCA_159_128:1352 case REG_SPDIF_STCCA_191_160:1353 return true;1354 default:1355 return false;1356 }1357}1358 1359static bool fsl_spdif_volatile_reg(struct device *dev, unsigned int reg)1360{1361 switch (reg) {1362 case REG_SPDIF_SRPC:1363 case REG_SPDIF_SIS:1364 case REG_SPDIF_SRL:1365 case REG_SPDIF_SRR:1366 case REG_SPDIF_SRCSH:1367 case REG_SPDIF_SRCSL:1368 case REG_SPDIF_SRU:1369 case REG_SPDIF_SRQ:1370 case REG_SPDIF_SRFM:1371 case REG_SPDIF_SRCCA_31_0:1372 case REG_SPDIF_SRCCA_63_32:1373 case REG_SPDIF_SRCCA_95_64:1374 case REG_SPDIF_SRCCA_127_96:1375 case REG_SPDIF_SRCCA_159_128:1376 case REG_SPDIF_SRCCA_191_160:1377 return true;1378 default:1379 return false;1380 }1381}1382 1383static bool fsl_spdif_writeable_reg(struct device *dev, unsigned int reg)1384{1385 switch (reg) {1386 case REG_SPDIF_SCR:1387 case REG_SPDIF_SRCD:1388 case REG_SPDIF_SRPC:1389 case REG_SPDIF_SIE:1390 case REG_SPDIF_SIC:1391 case REG_SPDIF_STL:1392 case REG_SPDIF_STR:1393 case REG_SPDIF_STCSCH:1394 case REG_SPDIF_STCSCL:1395 case REG_SPDIF_STCSPH:1396 case REG_SPDIF_STCSPL:1397 case REG_SPDIF_STC:1398 case REG_SPDIF_STCCA_31_0:1399 case REG_SPDIF_STCCA_63_32:1400 case REG_SPDIF_STCCA_95_64:1401 case REG_SPDIF_STCCA_127_96:1402 case REG_SPDIF_STCCA_159_128:1403 case REG_SPDIF_STCCA_191_160:1404 return true;1405 default:1406 return false;1407 }1408}1409 1410static const struct regmap_config fsl_spdif_regmap_config = {1411 .reg_bits = 32,1412 .reg_stride = 4,1413 .val_bits = 32,1414 1415 .max_register = REG_SPDIF_STCCA_191_160,1416 .reg_defaults = fsl_spdif_reg_defaults,1417 .num_reg_defaults = ARRAY_SIZE(fsl_spdif_reg_defaults),1418 .readable_reg = fsl_spdif_readable_reg,1419 .volatile_reg = fsl_spdif_volatile_reg,1420 .writeable_reg = fsl_spdif_writeable_reg,1421 .cache_type = REGCACHE_FLAT,1422};1423 1424static u32 fsl_spdif_txclk_caldiv(struct fsl_spdif_priv *spdif_priv,1425 struct clk *clk, u64 savesub,1426 enum spdif_txrate index, bool round)1427{1428 static const u32 rate[] = { 22050, 32000, 44100, 48000, 88200, 96000, 176400,1429 192000, };1430 bool is_sysclk = clk_is_match(clk, spdif_priv->sysclk);1431 u64 rate_ideal, rate_actual, sub;1432 u32 arate;1433 u16 sysclk_dfmin, sysclk_dfmax, sysclk_df;1434 u8 txclk_df;1435 1436 /* The sysclk has an extra divisor [2, 512] */1437 sysclk_dfmin = is_sysclk ? 2 : 1;1438 sysclk_dfmax = is_sysclk ? 512 : 1;1439 1440 for (sysclk_df = sysclk_dfmin; sysclk_df <= sysclk_dfmax; sysclk_df++) {1441 for (txclk_df = 1; txclk_df <= 128; txclk_df++) {1442 rate_ideal = rate[index] * txclk_df * 64ULL;1443 if (round)1444 rate_actual = clk_round_rate(clk, rate_ideal);1445 else1446 rate_actual = clk_get_rate(clk);1447 1448 arate = rate_actual / 64;1449 arate /= txclk_df * sysclk_df;1450 1451 if (arate == rate[index]) {1452 /* We are lucky */1453 savesub = 0;1454 spdif_priv->txclk_df[index] = txclk_df;1455 spdif_priv->sysclk_df[index] = sysclk_df;1456 spdif_priv->txrate[index] = arate;1457 goto out;1458 } else if (arate / rate[index] == 1) {1459 /* A little bigger than expect */1460 sub = (u64)(arate - rate[index]) * 100000;1461 do_div(sub, rate[index]);1462 if (sub >= savesub)1463 continue;1464 savesub = sub;1465 spdif_priv->txclk_df[index] = txclk_df;1466 spdif_priv->sysclk_df[index] = sysclk_df;1467 spdif_priv->txrate[index] = arate;1468 } else if (rate[index] / arate == 1) {1469 /* A little smaller than expect */1470 sub = (u64)(rate[index] - arate) * 100000;1471 do_div(sub, rate[index]);1472 if (sub >= savesub)1473 continue;1474 savesub = sub;1475 spdif_priv->txclk_df[index] = txclk_df;1476 spdif_priv->sysclk_df[index] = sysclk_df;1477 spdif_priv->txrate[index] = arate;1478 }1479 }1480 }1481 1482out:1483 return savesub;1484}1485 1486static int fsl_spdif_probe_txclk(struct fsl_spdif_priv *spdif_priv,1487 enum spdif_txrate index)1488{1489 static const u32 rate[] = { 22050, 32000, 44100, 48000, 88200, 96000, 176400,1490 192000, };1491 struct platform_device *pdev = spdif_priv->pdev;1492 struct device *dev = &pdev->dev;1493 u64 savesub = 100000, ret;1494 struct clk *clk;1495 int i;1496 1497 for (i = 0; i < STC_TXCLK_SRC_MAX; i++) {1498 clk = spdif_priv->txclk[i];1499 if (IS_ERR(clk)) {1500 dev_err(dev, "no rxtx%d clock in devicetree\n", i);1501 return PTR_ERR(clk);1502 }1503 if (!clk_get_rate(clk))1504 continue;1505 1506 ret = fsl_spdif_txclk_caldiv(spdif_priv, clk, savesub, index,1507 fsl_spdif_can_set_clk_rate(spdif_priv, i));1508 if (savesub == ret)1509 continue;1510 1511 savesub = ret;1512 spdif_priv->txclk_src[index] = i;1513 1514 /* To quick catch a divisor, we allow a 0.1% deviation */1515 if (savesub < 100)1516 break;1517 }1518 1519 dev_dbg(dev, "use rxtx%d as tx clock source for %dHz sample rate\n",1520 spdif_priv->txclk_src[index], rate[index]);1521 dev_dbg(dev, "use txclk df %d for %dHz sample rate\n",1522 spdif_priv->txclk_df[index], rate[index]);1523 if (clk_is_match(spdif_priv->txclk[spdif_priv->txclk_src[index]], spdif_priv->sysclk))1524 dev_dbg(dev, "use sysclk df %d for %dHz sample rate\n",1525 spdif_priv->sysclk_df[index], rate[index]);1526 dev_dbg(dev, "the best rate for %dHz sample rate is %dHz\n",1527 rate[index], spdif_priv->txrate[index]);1528 1529 return 0;1530}1531 1532static int fsl_spdif_probe(struct platform_device *pdev)1533{1534 struct fsl_spdif_priv *spdif_priv;1535 struct spdif_mixer_control *ctrl;1536 struct resource *res;1537 void __iomem *regs;1538 int irq, ret, i;1539 char tmp[16];1540 1541 spdif_priv = devm_kzalloc(&pdev->dev, sizeof(*spdif_priv), GFP_KERNEL);1542 if (!spdif_priv)1543 return -ENOMEM;1544 1545 spdif_priv->pdev = pdev;1546 1547 spdif_priv->soc = of_device_get_match_data(&pdev->dev);1548 1549 /* Initialize this copy of the CPU DAI driver structure */1550 memcpy(&spdif_priv->cpu_dai_drv, &fsl_spdif_dai, sizeof(fsl_spdif_dai));1551 spdif_priv->cpu_dai_drv.name = dev_name(&pdev->dev);1552 spdif_priv->cpu_dai_drv.playback.formats =1553 spdif_priv->soc->tx_formats;1554 1555 /* Get the addresses and IRQ */1556 regs = devm_platform_get_and_ioremap_resource(pdev, 0, &res);1557 if (IS_ERR(regs))1558 return PTR_ERR(regs);1559 1560 spdif_priv->regmap = devm_regmap_init_mmio(&pdev->dev, regs, &fsl_spdif_regmap_config);1561 if (IS_ERR(spdif_priv->regmap)) {1562 dev_err(&pdev->dev, "regmap init failed\n");1563 return PTR_ERR(spdif_priv->regmap);1564 }1565 1566 for (i = 0; i < spdif_priv->soc->interrupts; i++) {1567 irq = platform_get_irq(pdev, i);1568 if (irq < 0)1569 return irq;1570 1571 ret = devm_request_irq(&pdev->dev, irq, spdif_isr, 0,1572 dev_name(&pdev->dev), spdif_priv);1573 if (ret) {1574 dev_err(&pdev->dev, "could not claim irq %u\n", irq);1575 return ret;1576 }1577 }1578 1579 for (i = 0; i < STC_TXCLK_SRC_MAX; i++) {1580 sprintf(tmp, "rxtx%d", i);1581 spdif_priv->txclk[i] = devm_clk_get(&pdev->dev, tmp);1582 if (IS_ERR(spdif_priv->txclk[i])) {1583 dev_err(&pdev->dev, "no rxtx%d clock in devicetree\n", i);1584 return PTR_ERR(spdif_priv->txclk[i]);1585 }1586 }1587 1588 /* Get system clock for rx clock rate calculation */1589 spdif_priv->sysclk = spdif_priv->txclk[5];1590 if (IS_ERR(spdif_priv->sysclk)) {1591 dev_err(&pdev->dev, "no sys clock (rxtx5) in devicetree\n");1592 return PTR_ERR(spdif_priv->sysclk);1593 }1594 1595 /* Get core clock for data register access via DMA */1596 spdif_priv->coreclk = devm_clk_get(&pdev->dev, "core");1597 if (IS_ERR(spdif_priv->coreclk)) {1598 dev_err(&pdev->dev, "no core clock in devicetree\n");1599 return PTR_ERR(spdif_priv->coreclk);1600 }1601 1602 spdif_priv->spbaclk = devm_clk_get(&pdev->dev, "spba");1603 if (IS_ERR(spdif_priv->spbaclk))1604 dev_warn(&pdev->dev, "no spba clock in devicetree\n");1605 1606 /* Select clock source for rx/tx clock */1607 spdif_priv->rxclk = spdif_priv->txclk[1];1608 if (IS_ERR(spdif_priv->rxclk)) {1609 dev_err(&pdev->dev, "no rxtx1 clock in devicetree\n");1610 return PTR_ERR(spdif_priv->rxclk);1611 }1612 spdif_priv->rxclk_src = DEFAULT_RXCLK_SRC;1613 1614 fsl_asoc_get_pll_clocks(&pdev->dev, &spdif_priv->pll8k_clk,1615 &spdif_priv->pll11k_clk);1616 1617 /* Initial spinlock for control data */1618 ctrl = &spdif_priv->fsl_spdif_control;1619 spin_lock_init(&ctrl->ctl_lock);1620 1621 /* Init tx channel status default value */1622 ctrl->ch_status[0] = IEC958_AES0_CON_NOT_COPYRIGHT |1623 IEC958_AES0_CON_EMPHASIS_5015;1624 ctrl->ch_status[1] = IEC958_AES1_CON_DIGDIGCONV_ID;1625 ctrl->ch_status[2] = 0x00;1626 ctrl->ch_status[3] = IEC958_AES3_CON_FS_44100 |1627 IEC958_AES3_CON_CLOCK_1000PPM;1628 1629 spdif_priv->dpll_locked = false;1630 1631 spdif_priv->dma_params_tx.maxburst = spdif_priv->soc->tx_burst;1632 spdif_priv->dma_params_rx.maxburst = spdif_priv->soc->rx_burst;1633 spdif_priv->dma_params_tx.addr = res->start + REG_SPDIF_STL;1634 spdif_priv->dma_params_rx.addr = res->start + REG_SPDIF_SRL;1635 1636 /* Register with ASoC */1637 dev_set_drvdata(&pdev->dev, spdif_priv);1638 pm_runtime_enable(&pdev->dev);1639 regcache_cache_only(spdif_priv->regmap, true);1640 1641 /*1642 * Register platform component before registering cpu dai for there1643 * is not defer probe for platform component in snd_soc_add_pcm_runtime().1644 */1645 ret = imx_pcm_dma_init(pdev);1646 if (ret) {1647 dev_err_probe(&pdev->dev, ret, "imx_pcm_dma_init failed\n");1648 goto err_pm_disable;1649 }1650 1651 ret = devm_snd_soc_register_component(&pdev->dev, &fsl_spdif_component,1652 &spdif_priv->cpu_dai_drv, 1);1653 if (ret) {1654 dev_err(&pdev->dev, "failed to register DAI: %d\n", ret);1655 goto err_pm_disable;1656 }1657 1658 return ret;1659 1660err_pm_disable:1661 pm_runtime_disable(&pdev->dev);1662 return ret;1663}1664 1665static void fsl_spdif_remove(struct platform_device *pdev)1666{1667 pm_runtime_disable(&pdev->dev);1668}1669 1670static int fsl_spdif_runtime_suspend(struct device *dev)1671{1672 struct fsl_spdif_priv *spdif_priv = dev_get_drvdata(dev);1673 int i;1674 1675 /* Disable all the interrupts */1676 regmap_update_bits(spdif_priv->regmap, REG_SPDIF_SIE, 0xffffff, 0);1677 1678 regmap_read(spdif_priv->regmap, REG_SPDIF_SRPC,1679 &spdif_priv->regcache_srpc);1680 regcache_cache_only(spdif_priv->regmap, true);1681 1682 for (i = 0; i < STC_TXCLK_SRC_MAX; i++)1683 clk_disable_unprepare(spdif_priv->txclk[i]);1684 1685 if (!IS_ERR(spdif_priv->spbaclk))1686 clk_disable_unprepare(spdif_priv->spbaclk);1687 clk_disable_unprepare(spdif_priv->coreclk);1688 1689 return 0;1690}1691 1692static int fsl_spdif_runtime_resume(struct device *dev)1693{1694 struct fsl_spdif_priv *spdif_priv = dev_get_drvdata(dev);1695 int ret;1696 int i;1697 1698 ret = clk_prepare_enable(spdif_priv->coreclk);1699 if (ret) {1700 dev_err(dev, "failed to enable core clock\n");1701 return ret;1702 }1703 1704 if (!IS_ERR(spdif_priv->spbaclk)) {1705 ret = clk_prepare_enable(spdif_priv->spbaclk);1706 if (ret) {1707 dev_err(dev, "failed to enable spba clock\n");1708 goto disable_core_clk;1709 }1710 }1711 1712 for (i = 0; i < STC_TXCLK_SRC_MAX; i++) {1713 ret = clk_prepare_enable(spdif_priv->txclk[i]);1714 if (ret)1715 goto disable_tx_clk;1716 }1717 1718 regcache_cache_only(spdif_priv->regmap, false);1719 regcache_mark_dirty(spdif_priv->regmap);1720 1721 regmap_update_bits(spdif_priv->regmap, REG_SPDIF_SRPC,1722 SRPC_CLKSRC_SEL_MASK | SRPC_GAINSEL_MASK,1723 spdif_priv->regcache_srpc);1724 1725 ret = regcache_sync(spdif_priv->regmap);1726 if (ret)1727 goto disable_tx_clk;1728 1729 return 0;1730 1731disable_tx_clk:1732 for (i--; i >= 0; i--)1733 clk_disable_unprepare(spdif_priv->txclk[i]);1734 if (!IS_ERR(spdif_priv->spbaclk))1735 clk_disable_unprepare(spdif_priv->spbaclk);1736disable_core_clk:1737 clk_disable_unprepare(spdif_priv->coreclk);1738 1739 return ret;1740}1741 1742static const struct dev_pm_ops fsl_spdif_pm = {1743 SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, pm_runtime_force_resume)1744 RUNTIME_PM_OPS(fsl_spdif_runtime_suspend, fsl_spdif_runtime_resume,1745 NULL)1746};1747 1748static const struct of_device_id fsl_spdif_dt_ids[] = {1749 { .compatible = "fsl,imx35-spdif", .data = &fsl_spdif_imx35, },1750 { .compatible = "fsl,vf610-spdif", .data = &fsl_spdif_vf610, },1751 { .compatible = "fsl,imx6sx-spdif", .data = &fsl_spdif_imx6sx, },1752 { .compatible = "fsl,imx8qm-spdif", .data = &fsl_spdif_imx8qm, },1753 { .compatible = "fsl,imx8mm-spdif", .data = &fsl_spdif_imx8mm, },1754 { .compatible = "fsl,imx8ulp-spdif", .data = &fsl_spdif_imx8ulp, },1755 {}1756};1757MODULE_DEVICE_TABLE(of, fsl_spdif_dt_ids);1758 1759static struct platform_driver fsl_spdif_driver = {1760 .driver = {1761 .name = "fsl-spdif-dai",1762 .of_match_table = fsl_spdif_dt_ids,1763 .pm = pm_ptr(&fsl_spdif_pm),1764 },1765 .probe = fsl_spdif_probe,1766 .remove = fsl_spdif_remove,1767};1768 1769module_platform_driver(fsl_spdif_driver);1770 1771MODULE_AUTHOR("Freescale Semiconductor, Inc.");1772MODULE_DESCRIPTION("Freescale S/PDIF CPU DAI Driver");1773MODULE_LICENSE("GPL v2");1774MODULE_ALIAS("platform:fsl-spdif-dai");1775