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1/* SPDX-License-Identifier: GPL-2.0 */2/*3 * fsl_spdif.h - ALSA S/PDIF interface for the Freescale i.MX SoC4 *5 * Copyright (C) 2013 Freescale Semiconductor, Inc.6 *7 * Author: Nicolin Chen <b42378@freescale.com>8 *9 * Based on fsl_ssi.h10 * Author: Timur Tabi <timur@freescale.com>11 * Copyright 2007-2008 Freescale Semiconductor, Inc.12 */13 14#ifndef _FSL_SPDIF_DAI_H15#define _FSL_SPDIF_DAI_H16 17/* S/PDIF Register Map */18#define REG_SPDIF_SCR 0x0 /* SPDIF Configuration Register */19#define REG_SPDIF_SRCD 0x4 /* CDText Control Register */20#define REG_SPDIF_SRPC 0x8 /* PhaseConfig Register */21#define REG_SPDIF_SIE 0xc /* InterruptEn Register */22#define REG_SPDIF_SIS 0x10 /* InterruptStat Register */23#define REG_SPDIF_SIC 0x10 /* InterruptClear Register */24#define REG_SPDIF_SRL 0x14 /* SPDIFRxLeft Register */25#define REG_SPDIF_SRR 0x18 /* SPDIFRxRight Register */26#define REG_SPDIF_SRCSH 0x1c /* SPDIFRxCChannel_h Register */27#define REG_SPDIF_SRCSL 0x20 /* SPDIFRxCChannel_l Register */28#define REG_SPDIF_SRU 0x24 /* UchannelRx Register */29#define REG_SPDIF_SRQ 0x28 /* QchannelRx Register */30#define REG_SPDIF_STL 0x2C /* SPDIFTxLeft Register */31#define REG_SPDIF_STR 0x30 /* SPDIFTxRight Register */32#define REG_SPDIF_STCSCH 0x34 /* SPDIFTxCChannelCons_h Register */33#define REG_SPDIF_STCSCL 0x38 /* SPDIFTxCChannelCons_l Register */34#define REG_SPDIF_STCSPH 0x3C /* SPDIFTxCChannel_Prof_h Register */35#define REG_SPDIF_STCSPL 0x40 /* SPDIFTxCChannel_Prof_l Register */36#define REG_SPDIF_SRFM 0x44 /* FreqMeas Register */37#define REG_SPDIF_STC 0x50 /* SPDIFTxClk Register */38 39#define REG_SPDIF_SRCCA_31_0 0x60 /* SPDIF receive C channel register, bits 31-0 */40#define REG_SPDIF_SRCCA_63_32 0x64 /* SPDIF receive C channel register, bits 63-32 */41#define REG_SPDIF_SRCCA_95_64 0x68 /* SPDIF receive C channel register, bits 95-64 */42#define REG_SPDIF_SRCCA_127_96 0x6C /* SPDIF receive C channel register, bits 127-96 */43#define REG_SPDIF_SRCCA_159_128 0x70 /* SPDIF receive C channel register, bits 159-128 */44#define REG_SPDIF_SRCCA_191_160 0x74 /* SPDIF receive C channel register, bits 191-160 */45#define REG_SPDIF_STCCA_31_0 0x78 /* SPDIF transmit C channel register, bits 31-0 */46#define REG_SPDIF_STCCA_63_32 0x7C /* SPDIF transmit C channel register, bits 63-32 */47#define REG_SPDIF_STCCA_95_64 0x80 /* SPDIF transmit C channel register, bits 95-64 */48#define REG_SPDIF_STCCA_127_96 0x84 /* SPDIF transmit C channel register, bits 127-96 */49#define REG_SPDIF_STCCA_159_128 0x88 /* SPDIF transmit C channel register, bits 159-128 */50#define REG_SPDIF_STCCA_191_160 0x8C /* SPDIF transmit C channel register, bits 191-160 */51 52/* SPDIF Configuration register */53#define SCR_RXFIFO_CTL_OFFSET 2354#define SCR_RXFIFO_CTL_MASK (1 << SCR_RXFIFO_CTL_OFFSET)55#define SCR_RXFIFO_CTL_ZERO (1 << SCR_RXFIFO_CTL_OFFSET)56#define SCR_RXFIFO_OFF_OFFSET 2257#define SCR_RXFIFO_OFF_MASK (1 << SCR_RXFIFO_OFF_OFFSET)58#define SCR_RXFIFO_OFF (1 << SCR_RXFIFO_OFF_OFFSET)59#define SCR_RXFIFO_RST_OFFSET 2160#define SCR_RXFIFO_RST_MASK (1 << SCR_RXFIFO_RST_OFFSET)61#define SCR_RXFIFO_RST (1 << SCR_RXFIFO_RST_OFFSET)62#define SCR_RXFIFO_FSEL_OFFSET 1963#define SCR_RXFIFO_FSEL_MASK (0x3 << SCR_RXFIFO_FSEL_OFFSET)64#define SCR_RXFIFO_FSEL_IF0 (0x0 << SCR_RXFIFO_FSEL_OFFSET)65#define SCR_RXFIFO_FSEL_IF4 (0x1 << SCR_RXFIFO_FSEL_OFFSET)66#define SCR_RXFIFO_FSEL_IF8 (0x2 << SCR_RXFIFO_FSEL_OFFSET)67#define SCR_RXFIFO_FSEL_IF12 (0x3 << SCR_RXFIFO_FSEL_OFFSET)68#define SCR_RXFIFO_AUTOSYNC_OFFSET 1869#define SCR_RXFIFO_AUTOSYNC_MASK (1 << SCR_RXFIFO_AUTOSYNC_OFFSET)70#define SCR_RXFIFO_AUTOSYNC (1 << SCR_RXFIFO_AUTOSYNC_OFFSET)71#define SCR_TXFIFO_AUTOSYNC_OFFSET 1772#define SCR_TXFIFO_AUTOSYNC_MASK (1 << SCR_TXFIFO_AUTOSYNC_OFFSET)73#define SCR_TXFIFO_AUTOSYNC (1 << SCR_TXFIFO_AUTOSYNC_OFFSET)74#define SCR_TXFIFO_FSEL_OFFSET 1575#define SCR_TXFIFO_FSEL_MASK (0x3 << SCR_TXFIFO_FSEL_OFFSET)76#define SCR_TXFIFO_FSEL_IF0 (0x0 << SCR_TXFIFO_FSEL_OFFSET)77#define SCR_TXFIFO_FSEL_IF4 (0x1 << SCR_TXFIFO_FSEL_OFFSET)78#define SCR_TXFIFO_FSEL_IF8 (0x2 << SCR_TXFIFO_FSEL_OFFSET)79#define SCR_TXFIFO_FSEL_IF12 (0x3 << SCR_TXFIFO_FSEL_OFFSET)80#define SCR_RAW_CAPTURE_MODE BIT(14)81#define SCR_LOW_POWER (1 << 13)82#define SCR_SOFT_RESET (1 << 12)83#define SCR_TXFIFO_CTRL_OFFSET 1084#define SCR_TXFIFO_CTRL_MASK (0x3 << SCR_TXFIFO_CTRL_OFFSET)85#define SCR_TXFIFO_CTRL_ZERO (0x0 << SCR_TXFIFO_CTRL_OFFSET)86#define SCR_TXFIFO_CTRL_NORMAL (0x1 << SCR_TXFIFO_CTRL_OFFSET)87#define SCR_TXFIFO_CTRL_ONESAMPLE (0x2 << SCR_TXFIFO_CTRL_OFFSET)88#define SCR_DMA_RX_EN_OFFSET 989#define SCR_DMA_RX_EN_MASK (1 << SCR_DMA_RX_EN_OFFSET)90#define SCR_DMA_RX_EN (1 << SCR_DMA_RX_EN_OFFSET)91#define SCR_DMA_TX_EN_OFFSET 892#define SCR_DMA_TX_EN_MASK (1 << SCR_DMA_TX_EN_OFFSET)93#define SCR_DMA_TX_EN (1 << SCR_DMA_TX_EN_OFFSET)94#define SCR_VAL_OFFSET 595#define SCR_VAL_MASK (1 << SCR_VAL_OFFSET)96#define SCR_VAL_CLEAR (1 << SCR_VAL_OFFSET)97#define SCR_TXSEL_OFFSET 298#define SCR_TXSEL_MASK (0x7 << SCR_TXSEL_OFFSET)99#define SCR_TXSEL_OFF (0 << SCR_TXSEL_OFFSET)100#define SCR_TXSEL_RX (1 << SCR_TXSEL_OFFSET)101#define SCR_TXSEL_NORMAL (0x5 << SCR_TXSEL_OFFSET)102#define SCR_USRC_SEL_OFFSET 0x0103#define SCR_USRC_SEL_MASK (0x3 << SCR_USRC_SEL_OFFSET)104#define SCR_USRC_SEL_NONE (0x0 << SCR_USRC_SEL_OFFSET)105#define SCR_USRC_SEL_RECV (0x1 << SCR_USRC_SEL_OFFSET)106#define SCR_USRC_SEL_CHIP (0x3 << SCR_USRC_SEL_OFFSET)107 108#define SCR_DMA_xX_EN(tx) (tx ? SCR_DMA_TX_EN : SCR_DMA_RX_EN)109 110/* SPDIF CDText control */111#define SRCD_CD_USER_OFFSET 1112#define SRCD_CD_USER (1 << SRCD_CD_USER_OFFSET)113 114/* SPDIF Phase Configuration register */115#define SRPC_DPLL_LOCKED (1 << 6)116#define SRPC_CLKSRC_SEL_OFFSET 7117#define SRPC_CLKSRC_SEL_MASK (0xf << SRPC_CLKSRC_SEL_OFFSET)118#define SRPC_CLKSRC_SEL_SET(x) ((x << SRPC_CLKSRC_SEL_OFFSET) & SRPC_CLKSRC_SEL_MASK)119#define SRPC_CLKSRC_SEL_LOCKED_OFFSET1 5120#define SRPC_CLKSRC_SEL_LOCKED_OFFSET2 2121#define SRPC_GAINSEL_OFFSET 3122#define SRPC_GAINSEL_MASK (0x7 << SRPC_GAINSEL_OFFSET)123#define SRPC_GAINSEL_SET(x) ((x << SRPC_GAINSEL_OFFSET) & SRPC_GAINSEL_MASK)124 125#define SRPC_CLKSRC_MAX 16126 127enum spdif_gainsel {128 GAINSEL_MULTI_24 = 0,129 GAINSEL_MULTI_16,130 GAINSEL_MULTI_12,131 GAINSEL_MULTI_8,132 GAINSEL_MULTI_6,133 GAINSEL_MULTI_4,134 GAINSEL_MULTI_3,135};136#define GAINSEL_MULTI_MAX (GAINSEL_MULTI_3 + 1)137#define SPDIF_DEFAULT_GAINSEL GAINSEL_MULTI_8138 139/* SPDIF interrupt mask define */140#define INT_DPLL_LOCKED (1 << 20)141#define INT_TXFIFO_UNOV (1 << 19)142#define INT_TXFIFO_RESYNC (1 << 18)143#define INT_CNEW (1 << 17)144#define INT_VAL_NOGOOD (1 << 16)145#define INT_SYM_ERR (1 << 15)146#define INT_BIT_ERR (1 << 14)147#define INT_URX_FUL (1 << 10)148#define INT_URX_OV (1 << 9)149#define INT_QRX_FUL (1 << 8)150#define INT_QRX_OV (1 << 7)151#define INT_UQ_SYNC (1 << 6)152#define INT_UQ_ERR (1 << 5)153#define INT_RXFIFO_UNOV (1 << 4)154#define INT_RXFIFO_RESYNC (1 << 3)155#define INT_LOSS_LOCK (1 << 2)156#define INT_TX_EM (1 << 1)157#define INT_RXFIFO_FUL (1 << 0)158 159/* SPDIF Clock register */160#define STC_SYSCLK_DF_OFFSET 11161#define STC_SYSCLK_DF_MASK (0x1ff << STC_SYSCLK_DF_OFFSET)162#define STC_SYSCLK_DF(x) ((((x) - 1) << STC_SYSCLK_DF_OFFSET) & STC_SYSCLK_DF_MASK)163#define STC_TXCLK_SRC_OFFSET 8164#define STC_TXCLK_SRC_MASK (0x7 << STC_TXCLK_SRC_OFFSET)165#define STC_TXCLK_SRC_SET(x) ((x << STC_TXCLK_SRC_OFFSET) & STC_TXCLK_SRC_MASK)166#define STC_TXCLK_ALL_EN_OFFSET 7167#define STC_TXCLK_ALL_EN_MASK (1 << STC_TXCLK_ALL_EN_OFFSET)168#define STC_TXCLK_ALL_EN (1 << STC_TXCLK_ALL_EN_OFFSET)169#define STC_TXCLK_DF_OFFSET 0170#define STC_TXCLK_DF_MASK (0x7f << STC_TXCLK_DF_OFFSET)171#define STC_TXCLK_DF(x) ((((x) - 1) << STC_TXCLK_DF_OFFSET) & STC_TXCLK_DF_MASK)172#define STC_TXCLK_SRC_MAX 8173 174#define STC_TXCLK_SPDIF_ROOT 1175 176/* SPDIF tx rate */177enum spdif_txrate {178 SPDIF_TXRATE_22050 = 0,179 SPDIF_TXRATE_32000,180 SPDIF_TXRATE_44100,181 SPDIF_TXRATE_48000,182 SPDIF_TXRATE_88200,183 SPDIF_TXRATE_96000,184 SPDIF_TXRATE_176400,185 SPDIF_TXRATE_192000,186};187#define SPDIF_TXRATE_MAX (SPDIF_TXRATE_192000 + 1)188 189 190#define SPDIF_CSTATUS_BYTE 6191#define SPDIF_UBITS_SIZE 96192#define SPDIF_QSUB_SIZE (SPDIF_UBITS_SIZE / 8)193 194 195#define FSL_SPDIF_RATES_PLAYBACK (SNDRV_PCM_RATE_22050 | \196 SNDRV_PCM_RATE_32000 | \197 SNDRV_PCM_RATE_44100 | \198 SNDRV_PCM_RATE_48000 | \199 SNDRV_PCM_RATE_88200 | \200 SNDRV_PCM_RATE_96000 | \201 SNDRV_PCM_RATE_176400 | \202 SNDRV_PCM_RATE_192000)203 204#define FSL_SPDIF_RATES_CAPTURE (SNDRV_PCM_RATE_16000 | \205 SNDRV_PCM_RATE_32000 | \206 SNDRV_PCM_RATE_44100 | \207 SNDRV_PCM_RATE_48000 | \208 SNDRV_PCM_RATE_88200 | \209 SNDRV_PCM_RATE_64000 | \210 SNDRV_PCM_RATE_96000 | \211 SNDRV_PCM_RATE_176400 | \212 SNDRV_PCM_RATE_192000)213 214#define FSL_SPDIF_FORMATS_PLAYBACK (SNDRV_PCM_FMTBIT_S16_LE | \215 SNDRV_PCM_FMTBIT_S20_3LE | \216 SNDRV_PCM_FMTBIT_S24_LE)217 218#define FSL_SPDIF_FORMATS_CAPTURE (SNDRV_PCM_FMTBIT_S24_LE)219 220#endif /* _FSL_SPDIF_DAI_H */221