386 lines · c
1/* SPDX-License-Identifier: GPL-2.0 */2/*3 * NXP XCVR ALSA SoC Digital Audio Interface (DAI) driver4 *5 * Copyright 2019 NXP6 */7 8#ifndef __FSL_XCVR_H9#define __FSL_XCVR_H10 11#define FSL_XCVR_MODE_SPDIF 012#define FSL_XCVR_MODE_ARC 113#define FSL_XCVR_MODE_EARC 214 15/* XCVR Registers */16#define FSL_XCVR_REG_OFFSET 0x800 /* regs offset */17#define FSL_XCVR_FIFO_SIZE 0x80 /* 128 */18#define FSL_XCVR_FIFO_WMK_RX (FSL_XCVR_FIFO_SIZE >> 1) /* 64 */19#define FSL_XCVR_FIFO_WMK_TX (FSL_XCVR_FIFO_SIZE >> 1) /* 64 */20#define FSL_XCVR_MAXBURST_RX (FSL_XCVR_FIFO_WMK_RX >> 2) /* 16 */21#define FSL_XCVR_MAXBURST_TX (FSL_XCVR_FIFO_WMK_TX >> 2) /* 16 */22 23#define FSL_XCVR_RX_FIFO_ADDR 0x0C0024#define FSL_XCVR_TX_FIFO_ADDR 0x0E0025 26#define FSL_XCVR_VERSION 0x00 /* Version */27#define FSL_XCVR_EXT_CTRL 0x10 /* Control */28#define FSL_XCVR_EXT_STATUS 0x20 /* Status */29#define FSL_XCVR_EXT_IER0 0x30 /* Interrupt en 0 */30#define FSL_XCVR_EXT_IER1 0x40 /* Interrupt en 1 */31#define FSL_XCVR_EXT_ISR 0x50 /* Interrupt status */32#define FSL_XCVR_EXT_ISR_SET 0x54 /* Interrupt status */33#define FSL_XCVR_EXT_ISR_CLR 0x58 /* Interrupt status */34#define FSL_XCVR_EXT_ISR_TOG 0x5C /* Interrupt status */35#define FSL_XCVR_IER 0x70 /* Interrupt en for M0+ */36#define FSL_XCVR_ISR 0x80 /* Interrupt status */37#define FSL_XCVR_ISR_SET 0x84 /* Interrupt status set */38#define FSL_XCVR_ISR_CLR 0x88 /* Interrupt status clear */39#define FSL_XCVR_ISR_TOG 0x8C /* Interrupt status toggle */40#define FSL_XCVR_PHY_AI_CTRL 0x9041#define FSL_XCVR_PHY_AI_CTRL_SET 0x9442#define FSL_XCVR_PHY_AI_CTRL_CLR 0x9843#define FSL_XCVR_PHY_AI_CTRL_TOG 0x9C44#define FSL_XCVR_PHY_AI_WDATA 0xA045#define FSL_XCVR_PHY_AI_RDATA 0xA446#define FSL_XCVR_CLK_CTRL 0xB047#define FSL_XCVR_RX_DPTH_CTRL 0x180 /* RX datapath ctrl reg */48#define FSL_XCVR_RX_DPTH_CTRL_SET 0x18449#define FSL_XCVR_RX_DPTH_CTRL_CLR 0x18850#define FSL_XCVR_RX_DPTH_CTRL_TOG 0x18c51 52#define FSL_XCVR_RX_CS_DATA_0 0x19053#define FSL_XCVR_RX_CS_DATA_1 0x19454#define FSL_XCVR_RX_CS_DATA_2 0x19855#define FSL_XCVR_RX_CS_DATA_3 0x19C56#define FSL_XCVR_RX_CS_DATA_4 0x1A057#define FSL_XCVR_RX_CS_DATA_5 0x1A458 59#define FSL_XCVR_RX_DPTH_CNTR_CTRL 0x1C060#define FSL_XCVR_RX_DPTH_CNTR_CTRL_SET 0x1C461#define FSL_XCVR_RX_DPTH_CNTR_CTRL_CLR 0x1C862#define FSL_XCVR_RX_DPTH_CNTR_CTRL_TOG 0x1CC63 64#define FSL_XCVR_RX_DPTH_TSCR 0x1D065#define FSL_XCVR_RX_DPTH_BCR 0x1D466#define FSL_XCVR_RX_DPTH_BCTR 0x1D867#define FSL_XCVR_RX_DPTH_BCRR 0x1DC68 69#define FSL_XCVR_TX_DPTH_CTRL 0x220 /* TX datapath ctrl reg */70#define FSL_XCVR_TX_DPTH_CTRL_SET 0x22471#define FSL_XCVR_TX_DPTH_CTRL_CLR 0x22872#define FSL_XCVR_TX_DPTH_CTRL_TOG 0x22C73#define FSL_XCVR_TX_CS_DATA_0 0x230 /* TX channel status bits regs */74#define FSL_XCVR_TX_CS_DATA_1 0x23475#define FSL_XCVR_TX_CS_DATA_2 0x23876#define FSL_XCVR_TX_CS_DATA_3 0x23C77#define FSL_XCVR_TX_CS_DATA_4 0x24078#define FSL_XCVR_TX_CS_DATA_5 0x24479 80#define FSL_XCVR_TX_DPTH_CNTR_CTRL 0x26081#define FSL_XCVR_TX_DPTH_CNTR_CTRL_SET 0x26482#define FSL_XCVR_TX_DPTH_CNTR_CTRL_CLR 0x26883#define FSL_XCVR_TX_DPTH_CNTR_CTRL_TOG 0x26C84 85#define FSL_XCVR_TX_DPTH_TSCR 0x27086#define FSL_XCVR_TX_DPTH_BCR 0x27487#define FSL_XCVR_TX_DPTH_BCTR 0x27888#define FSL_XCVR_TX_DPTH_BCRR 0x27C89 90#define FSL_XCVR_DEBUG_REG_0 0x2E091#define FSL_XCVR_DEBUG_REG_1 0x2F092 93#define FSL_XCVR_MAX_REG FSL_XCVR_DEBUG_REG_194 95#define FSL_XCVR_EXT_CTRL_CORE_RESET BIT(31)96 97#define FSL_XCVR_EXT_CTRL_RX_CMDC_RESET BIT(30)98#define FSL_XCVR_EXT_CTRL_TX_CMDC_RESET BIT(29)99#define FSL_XCVR_EXT_CTRL_CMDC_RESET(t) (t ? BIT(29) : BIT(30))100 101#define FSL_XCVR_EXT_CTRL_RX_DPTH_RESET BIT(28)102#define FSL_XCVR_EXT_CTRL_TX_DPTH_RESET BIT(27)103#define FSL_XCVR_EXT_CTRL_DPTH_RESET(t) (t ? BIT(27) : BIT(28))104 105#define FSL_XCVR_EXT_CTRL_TX_RX_MODE BIT(26)106#define FSL_XCVR_EXT_CTRL_DMA_RD_DIS BIT(25)107#define FSL_XCVR_EXT_CTRL_DMA_WR_DIS BIT(24)108#define FSL_XCVR_EXT_CTRL_DMA_DIS(t) (t ? BIT(24) : BIT(25))109#define FSL_XCVR_EXT_CTRL_SPDIF_MODE BIT(23)110#define FSL_XCVR_EXT_CTRL_SLEEP_MODE BIT(21)111 112#define FSL_XCVR_EXT_CTRL_TX_FWM_SHFT 0113#define FSL_XCVR_EXT_CTRL_TX_FWM_MASK GENMASK(6, 0)114#define FSL_XCVR_EXT_CTRL_TX_FWM(i) (((i) << FSL_XCVR_EXT_CTRL_TX_FWM_SHFT) \115 & FSL_XCVR_EXT_CTRL_TX_FWM_MASK)116#define FSL_XCVR_EXT_CTRL_RX_FWM_SHFT 8117#define FSL_XCVR_EXT_CTRL_RX_FWM_MASK GENMASK(14, 8)118#define FSL_XCVR_EXT_CTRL_RX_FWM(i) (((i) << FSL_XCVR_EXT_CTRL_RX_FWM_SHFT) \119 & FSL_XCVR_EXT_CTRL_RX_FWM_MASK)120#define FSL_XCVR_EXT_CTRL_PAGE_SHFT 16121#define FSL_XCVR_EXT_CTRL_PAGE_MASK GENMASK(19, 16)122#define FSL_XCVR_EXT_CTRL_PAGE(i) (((i) << FSL_XCVR_EXT_CTRL_PAGE_SHFT) \123 & FSL_XCVR_EXT_CTRL_PAGE_MASK)124 125#define FSL_XCVR_EXT_STUS_NT_FIFO_ENTR GENMASK(7, 0)126#define FSL_XCVR_EXT_STUS_NR_FIFO_ENTR GENMASK(15, 8)127#define FSL_XCVR_EXT_STUS_CM0_SLEEPING BIT(16)128#define FSL_XCVR_EXT_STUS_CM0_DEEP_SLP BIT(17)129#define FSL_XCVR_EXT_STUS_CM0_SLP_HACK BIT(18)130#define FSL_XCVR_EXT_STUS_RX_CMDC_RSTO BIT(23)131#define FSL_XCVR_EXT_STUS_TX_CMDC_RSTO BIT(24)132#define FSL_XCVR_EXT_STUS_RX_CMDC_COTO BIT(25)133#define FSL_XCVR_EXT_STUS_TX_CMDC_COTO BIT(26)134#define FSL_XCVR_EXT_STUS_HB_STATUS BIT(27)135#define FSL_XCVR_EXT_STUS_NEW_UD4_REC BIT(28)136#define FSL_XCVR_EXT_STUS_NEW_UD5_REC BIT(29)137#define FSL_XCVR_EXT_STUS_NEW_UD6_REC BIT(30)138#define FSL_XCVR_EXT_STUS_HPD_INPUT BIT(31)139 140#define FSL_XCVR_IRQ_NEW_CS BIT(0)141#define FSL_XCVR_IRQ_NEW_UD BIT(1)142#define FSL_XCVR_IRQ_MUTE BIT(2)143#define FSL_XCVR_IRQ_CMDC_RESP_TO BIT(3)144#define FSL_XCVR_IRQ_ECC_ERR BIT(4)145#define FSL_XCVR_IRQ_PREAMBLE_MISMATCH BIT(5)146#define FSL_XCVR_IRQ_FIFO_UOFL_ERR BIT(6)147#define FSL_XCVR_IRQ_HOST_WAKEUP BIT(7)148#define FSL_XCVR_IRQ_HOST_OHPD BIT(8)149#define FSL_XCVR_IRQ_DMAC_NO_DATA_REC BIT(9)150#define FSL_XCVR_IRQ_DMAC_FMT_CHG_DET BIT(10)151#define FSL_XCVR_IRQ_HB_STATE_CHG BIT(11)152#define FSL_XCVR_IRQ_CMDC_STATUS_UPD BIT(12)153#define FSL_XCVR_IRQ_TEMP_UPD BIT(13)154#define FSL_XCVR_IRQ_DMA_RD_REQ BIT(14)155#define FSL_XCVR_IRQ_DMA_WR_REQ BIT(15)156#define FSL_XCVR_IRQ_DMAC_BME_BIT_ERR BIT(16)157#define FSL_XCVR_IRQ_PREAMBLE_MATCH BIT(17)158#define FSL_XCVR_IRQ_M_W_PRE_MISMATCH BIT(18)159#define FSL_XCVR_IRQ_B_PRE_MISMATCH BIT(19)160#define FSL_XCVR_IRQ_UNEXP_PRE_REC BIT(20)161#define FSL_XCVR_IRQ_ARC_MODE BIT(21)162#define FSL_XCVR_IRQ_CH_UD_OFLOW BIT(22)163#define FSL_XCVR_IRQ_EARC_ALL (FSL_XCVR_IRQ_NEW_CS | \164 FSL_XCVR_IRQ_NEW_UD | \165 FSL_XCVR_IRQ_MUTE | \166 FSL_XCVR_IRQ_FIFO_UOFL_ERR | \167 FSL_XCVR_IRQ_HOST_WAKEUP | \168 FSL_XCVR_IRQ_ARC_MODE)169 170#define FSL_XCVR_ISR_CMDC_TX_EN BIT(3)171#define FSL_XCVR_ISR_HPD_TGL BIT(15)172#define FSL_XCVR_ISR_DMAC_SPARE_INT BIT(19)173#define FSL_XCVR_ISR_SET_SPDIF_RX_INT BIT(20)174#define FSL_XCVR_ISR_SET_SPDIF_TX_INT BIT(21)175#define FSL_XCVR_ISR_SET_SPDIF_MODE(t) (t ? BIT(21) : BIT(20))176#define FSL_XCVR_ISR_SET_ARC_CM_INT BIT(22)177#define FSL_XCVR_ISR_SET_ARC_SE_INT BIT(23)178 179#define FSL_XCVR_PHY_AI_ADDR_MASK GENMASK(7, 0)180#define FSL_XCVR_PHY_AI_RESETN BIT(15)181#define FSL_XCVR_PHY_AI_TOG_PLL BIT(24)182#define FSL_XCVR_PHY_AI_TOG_DONE_PLL BIT(25)183#define FSL_XCVR_PHY_AI_TOG_PHY BIT(26)184#define FSL_XCVR_PHY_AI_TOG_DONE_PHY BIT(27)185#define FSL_XCVR_PHY_AI_RW_MASK BIT(31)186 187#define FSL_XCVR_RX_DPTH_CTRL_PAPB_FIFO_STATUS BIT(0)188#define FSL_XCVR_RX_DPTH_CTRL_DIS_PRE_ERR_CHK BIT(1)189#define FSL_XCVR_RX_DPTH_CTRL_DIS_NOD_REC_CHK BIT(2)190#define FSL_XCVR_RX_DPTH_CTRL_ECC_VUC_BIT_CHK BIT(3)191#define FSL_XCVR_RX_DPTH_CTRL_EN_CMP_PAR_CALC BIT(4)192#define FSL_XCVR_RX_DPTH_CTRL_RST_PKT_CNT_FIFO BIT(5)193#define FSL_XCVR_RX_DPTH_CTRL_STORE_FMT BIT(6)194#define FSL_XCVR_RX_DPTH_CTRL_EN_PAR_CALC BIT(7)195#define FSL_XCVR_RX_DPTH_CTRL_UDR BIT(8)196#define FSL_XCVR_RX_DPTH_CTRL_CSR BIT(9)197#define FSL_XCVR_RX_DPTH_CTRL_UDA BIT(10)198#define FSL_XCVR_RX_DPTH_CTRL_CSA BIT(11)199#define FSL_XCVR_RX_DPTH_CTRL_CLR_RX_FIFO BIT(12)200#define FSL_XCVR_RX_DPTH_CTRL_DIS_B_PRE_ERR_CHK BIT(13)201#define FSL_XCVR_RX_DPTH_CTRL_PABS BIT(19)202#define FSL_XCVR_RX_DPTH_CTRL_DTS_CDS BIT(20)203#define FSL_XCVR_RX_DPTH_CTRL_BLKC BIT(21)204#define FSL_XCVR_RX_DPTH_CTRL_MUTE_CTRL BIT(22)205#define FSL_XCVR_RX_DPTH_CTRL_MUTE_MODE BIT(23)206#define FSL_XCVR_RX_DPTH_CTRL_FMT_CHG_CTRL BIT(24)207#define FSL_XCVR_RX_DPTH_CTRL_FMT_CHG_MODE BIT(25)208#define FSL_XCVR_RX_DPTH_CTRL_LAYB_CTRL BIT(26)209#define FSL_XCVR_RX_DPTH_CTRL_LAYB_MODE BIT(27)210#define FSL_XCVR_RX_DPTH_CTRL_PRC BIT(28)211#define FSL_XCVR_RX_DPTH_CTRL_COMP BIT(29)212#define FSL_XCVR_RX_DPTH_CTRL_FSM GENMASK(31, 30)213 214#define FSL_XCVR_TX_DPTH_CTRL_CS_ACK BIT(0)215#define FSL_XCVR_TX_DPTH_CTRL_UD_ACK BIT(1)216#define FSL_XCVR_TX_DPTH_CTRL_CS_MOD BIT(2)217#define FSL_XCVR_TX_DPTH_CTRL_UD_MOD BIT(3)218#define FSL_XCVR_TX_DPTH_CTRL_VLD_MOD BIT(4)219#define FSL_XCVR_TX_DPTH_CTRL_FRM_VLD BIT(5)220#define FSL_XCVR_TX_DPTH_CTRL_EN_PARITY BIT(6)221#define FSL_XCVR_TX_DPTH_CTRL_EN_PREAMBLE BIT(7)222#define FSL_XCVR_TX_DPTH_CTRL_EN_ECC_INTER BIT(8)223#define FSL_XCVR_TX_DPTH_CTRL_BYPASS_FEM BIT(10)224#define FSL_XCVR_TX_DPTH_CTRL_FRM_FMT BIT(11)225#define FSL_XCVR_TX_DPTH_CTRL_STRT_DATA_TX BIT(14)226#define FSL_XCVR_TX_DPTH_CTRL_ADD_CYC_TX_OE_STR BIT(15)227#define FSL_XCVR_TX_DPTH_CTRL_ADD_CYC_TX_OE_END BIT(16)228#define FSL_XCVR_TX_DPTH_CTRL_CLK_RATIO BIT(29)229#define FSL_XCVR_TX_DPTH_CTRL_TM_NO_PRE_BME GENMASK(31, 30)230 231#define FSL_XCVR_PHY_AI_CTRL_AI_RESETN BIT(15)232 233#define FSL_XCVR_PLL_CTRL0 0x00234#define FSL_XCVR_PLL_CTRL0_SET 0x04235#define FSL_XCVR_PLL_CTRL0_CLR 0x08236#define FSL_XCVR_PLL_NUM 0x20237#define FSL_XCVR_PLL_DEN 0x30238#define FSL_XCVR_PLL_PDIV 0x40239#define FSL_XCVR_PLL_BANDGAP_SET 0x54240#define FSL_XCVR_PHY_CTRL 0x00241#define FSL_XCVR_PHY_CTRL_SET 0x04242#define FSL_XCVR_PHY_CTRL_CLR 0x08243#define FSL_XCVR_PHY_CTRL2 0x70244#define FSL_XCVR_PHY_CTRL2_SET 0x74245#define FSL_XCVR_PHY_CTRL2_CLR 0x78246 247#define FSL_XCVR_PLL_BANDGAP_EN_VBG BIT(0)248#define FSL_XCVR_PLL_CTRL0_HROFF BIT(13)249#define FSL_XCVR_PLL_CTRL0_PWP BIT(14)250#define FSL_XCVR_PLL_CTRL0_CM0_EN BIT(24)251#define FSL_XCVR_PLL_CTRL0_CM1_EN BIT(25)252#define FSL_XCVR_PLL_CTRL0_CM2_EN BIT(26)253#define FSL_XCVR_PLL_PDIVx(v, i) ((v & 0x7) << (4 * i))254 255#define FSL_XCVR_PHY_CTRL_PHY_EN BIT(0)256#define FSL_XCVR_PHY_CTRL_RX_CM_EN BIT(1)257#define FSL_XCVR_PHY_CTRL_TSDIFF_OE BIT(5)258#define FSL_XCVR_PHY_CTRL_SPDIF_EN BIT(8)259#define FSL_XCVR_PHY_CTRL_ARC_MODE_SE_EN BIT(9)260#define FSL_XCVR_PHY_CTRL_ARC_MODE_CM_EN BIT(10)261#define FSL_XCVR_PHY_CTRL_TX_CLK_MASK GENMASK(26, 25)262#define FSL_XCVR_PHY_CTRL_TX_CLK_HDMI_SS BIT(25)263#define FSL_XCVR_PHY_CTRL_TX_CLK_AUD_SS BIT(26)264#define FSL_XCVR_PHY_CTRL2_EARC_TXMS BIT(14)265 266#define FSL_XCVR_CS_DATA_0_FS_MASK GENMASK(31, 24)267#define FSL_XCVR_CS_DATA_0_FS_32000 0x3000000268#define FSL_XCVR_CS_DATA_0_FS_44100 0x0000000269#define FSL_XCVR_CS_DATA_0_FS_48000 0x2000000270#define FSL_XCVR_CS_DATA_0_FS_64000 0xB000000271#define FSL_XCVR_CS_DATA_0_FS_88200 0x8000000272#define FSL_XCVR_CS_DATA_0_FS_96000 0xA000000273#define FSL_XCVR_CS_DATA_0_FS_176400 0xC000000274#define FSL_XCVR_CS_DATA_0_FS_192000 0xE000000275 276#define FSL_XCVR_CS_DATA_0_CH_MASK 0x3A277#define FSL_XCVR_CS_DATA_0_CH_U2LPCM 0x00278#define FSL_XCVR_CS_DATA_0_CH_UMLPCM 0x20279#define FSL_XCVR_CS_DATA_0_CH_U1BAUD 0x30280 281#define FSL_XCVR_CS_DATA_1_CH_MASK 0xF000282#define FSL_XCVR_CS_DATA_1_CH_2 0x0000283#define FSL_XCVR_CS_DATA_1_CH_8 0x7000284#define FSL_XCVR_CS_DATA_1_CH_16 0xB000285#define FSL_XCVR_CS_DATA_1_CH_32 0x3000286 287/* Data memory structures */288#define FSL_XCVR_RX_CS_CTRL_0 0x20 /* First RX CS control register */289#define FSL_XCVR_RX_CS_CTRL_1 0x24 /* Second RX CS control register */290#define FSL_XCVR_RX_CS_BUFF_0 0x80 /* First RX CS buffer */291#define FSL_XCVR_RX_CS_BUFF_1 0xA0 /* Second RX CS buffer */292#define FSL_XCVR_CAP_DATA_STR 0x300 /* Capabilities data structure */293 294/* GP PLL Registers */295#define FSL_XCVR_GP_PLL_CTRL 0x00296#define FSL_XCVR_GP_PLL_CTRL_SET 0x04297#define FSL_XCVR_GP_PLL_CTRL_CLR 0x08298#define FSL_XCVR_GP_PLL_CTRL_TOG 0x0C299#define FSL_XCVR_GP_PLL_ANA_PRG 0x10300#define FSL_XCVR_GP_PLL_ANA_PRG_SET 0x14301#define FSL_XCVR_GP_PLL_ANA_PRG_CLR 0x18302#define FSL_XCVR_GP_PLL_ANA_PRG_TOG 0x1C303#define FSL_XCVR_GP_PLL_TEST 0x20304#define FSL_XCVR_GP_PLL_TEST_SET 0x24305#define FSL_XCVR_GP_PLL_TEST_CLR 0x28306#define FSL_XCVR_GP_PLL_TEST_TOG 0x2C307#define FSL_XCVR_GP_PLL_SPREAD_SPECTRUM 0x30308#define FSL_XCVR_GP_PLL_SPREAD_SPECTRUM_SET 0x34309#define FSL_XCVR_GP_PLL_SPREAD_SPECTRUM_CLR 0x38310#define FSL_XCVR_GP_PLL_SPREAD_SPECTRUM_TOG 0x3C311#define FSL_XCVR_GP_PLL_NUMERATOR 0x40312#define FSL_XCVR_GP_PLL_NUMERATOR_SET 0x44313#define FSL_XCVR_GP_PLL_NUMERATOR_CLR 0x48314#define FSL_XCVR_GP_PLL_NUMERATOR_TOG 0x4C315#define FSL_XCVR_GP_PLL_DENOMINATOR 0x50316#define FSL_XCVR_GP_PLL_DENOMINATOR_SET 0x54317#define FSL_XCVR_GP_PLL_DENOMINATOR_CLR 0x58318#define FSL_XCVR_GP_PLL_DENOMINATOR_TOG 0x5C319#define FSL_XCVR_GP_PLL_DIV 0x60320#define FSL_XCVR_GP_PLL_DIV_SET 0x64321#define FSL_XCVR_GP_PLL_DIV_CLR 0x68322#define FSL_XCVR_GP_PLL_DIV_TOG 0x6C323#define FSL_XCVR_GP_PLL_DFS_CTRL0 0x70324#define FSL_XCVR_GP_PLL_DFS_CTRL0_SET 0x74325#define FSL_XCVR_GP_PLL_DFS_CTRL0_CLR 0x78326#define FSL_XCVR_GP_PLL_DFS_CTRL0_TOG 0x7C327#define FSL_XCVR_GP_PLL_DFS_DIV0 0x80328#define FSL_XCVR_GP_PLL_DFS_DIV0_SET 0x84329#define FSL_XCVR_GP_PLL_DFS_DIV0_CLR 0x88330#define FSL_XCVR_GP_PLL_DFS_DIV0_TOG 0x8C331#define FSL_XCVR_GP_PLL_DFS_CTRL1 0x90332#define FSL_XCVR_GP_PLL_DFS_CTRL1_SET 0x94333#define FSL_XCVR_GP_PLL_DFS_CTRL1_CLR 0x98334#define FSL_XCVR_GP_PLL_DFS_CTRL1_TOG 0x9C335#define FSL_XCVR_GP_PLL_DFS_DIV1 0xA0336#define FSL_XCVR_GP_PLL_DFS_DIV1_SET 0xA4337#define FSL_XCVR_GP_PLL_DFS_DIV1_CLR 0xA8338#define FSL_XCVR_GP_PLL_DFS_DIV1_TOG 0xAC339#define FSL_XCVR_GP_PLL_DFS_CTRL2 0xB0340#define FSL_XCVR_GP_PLL_DFS_CTRL2_SET 0xB4341#define FSL_XCVR_GP_PLL_DFS_CTRL2_CLR 0xB8342#define FSL_XCVR_GP_PLL_DFS_CTRL2_TOG 0xBC343#define FSL_XCVR_GP_PLL_DFS_DIV2 0xC0344#define FSL_XCVR_GP_PLL_DFS_DIV2_SET 0xC4345#define FSL_XCVR_GP_PLL_DFS_DIV2_CLR 0xC8346#define FSL_XCVR_GP_PLL_DFS_DIV2_TOG 0xCC347#define FSL_XCVR_GP_PLL_DFS_CTRL3 0xD0348#define FSL_XCVR_GP_PLL_DFS_CTRL3_SET 0xD4349#define FSL_XCVR_GP_PLL_DFS_CTRL3_CLR 0xD8350#define FSL_XCVR_GP_PLL_DFS_CTRL3_TOG 0xDC351#define FSL_XCVR_GP_PLL_DFS_DIV3 0xE0352#define FSL_XCVR_GP_PLL_DFS_DIV3_SET 0xE4353#define FSL_XCVR_GP_PLL_DFS_DIV3_CLR 0xE8354#define FSL_XCVR_GP_PLL_DFS_DIV3_TOG 0xEC355#define FSL_XCVR_GP_PLL_STATUS 0xF0356#define FSL_XCVR_GP_PLL_STATUS_SET 0xF4357#define FSL_XCVR_GP_PLL_STATUS_CLR 0xF8358#define FSL_XCVR_GP_PLL_STATUS_TOG 0xFC359 360/* GP PLL Control Register */361#define FSL_XCVR_GP_PLL_CTRL_LBYPASS BIT(31)362#define FSL_XCVR_GP_PLL_CTRL_HCS BIT(16)363#define FSL_XCVR_GP_PLL_CTRL_MSD BIT(12)364#define FSL_XCVR_GP_PLL_CTRL_DITHER_EN3 BIT(11)365#define FSL_XCVR_GP_PLL_CTRL_DITHER_EN2 BIT(10)366#define FSL_XCVR_GP_PLL_CTRL_DITHER_EN1 BIT(9)367#define FSL_XCVR_GP_PLL_CTRL_SPREADCTL BIT(8)368#define FSL_XCVR_GP_PLL_CTRL_CLKMUX_BYPASS BIT(2)369#define FSL_XCVR_GP_PLL_CTRL_CLKMUX_EN BIT(1)370#define FSL_XCVR_GP_PLL_CTRL_POWERUP BIT(0)371 372/* GP PLL Numerator Register */373#define FSL_XCVR_GP_PLL_NUMERATOR_MFN_SHIFT 2374#define FSL_XCVR_GP_PLL_NUMERATOR_MFN GENMASK(31, 2)375 376/* GP PLL Denominator Register */377#define FSL_XCVR_GP_PLL_DENOMINATOR_MFD GENMASK(29, 0)378 379/* GP PLL Dividers Register */380#define FSL_XCVR_GP_PLL_DIV_MFI_SHIFT 16381#define FSL_XCVR_GP_PLL_DIV_MFI GENMASK(24, 16)382#define FSL_XCVR_GP_PLL_DIV_RDIV GENMASK(15, 13)383#define FSL_XCVR_GP_PLL_DIV_ODIV GENMASK(7, 0)384 385#endif /* __FSL_XCVR_H */386