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1/* SPDX-License-Identifier: GPL-2.0 */2 3#ifndef _IMX_SSI_H4#define _IMX_SSI_H5 6#define SSI_STX0 0x007#define SSI_STX1 0x048#define SSI_SRX0 0x089#define SSI_SRX1 0x0c10 11#define SSI_SCR 0x1012#define SSI_SCR_CLK_IST (1 << 9)13#define SSI_SCR_CLK_IST_SHIFT 914#define SSI_SCR_TCH_EN (1 << 8)15#define SSI_SCR_SYS_CLK_EN (1 << 7)16#define SSI_SCR_I2S_MODE_NORM (0 << 5)17#define SSI_SCR_I2S_MODE_MSTR (1 << 5)18#define SSI_SCR_I2S_MODE_SLAVE (2 << 5)19#define SSI_I2S_MODE_MASK (3 << 5)20#define SSI_SCR_SYN (1 << 4)21#define SSI_SCR_NET (1 << 3)22#define SSI_SCR_RE (1 << 2)23#define SSI_SCR_TE (1 << 1)24#define SSI_SCR_SSIEN (1 << 0)25 26#define SSI_SISR 0x1427#define SSI_SISR_MASK ((1 << 19) - 1)28#define SSI_SISR_CMDAU (1 << 18)29#define SSI_SISR_CMDDU (1 << 17)30#define SSI_SISR_RXT (1 << 16)31#define SSI_SISR_RDR1 (1 << 15)32#define SSI_SISR_RDR0 (1 << 14)33#define SSI_SISR_TDE1 (1 << 13)34#define SSI_SISR_TDE0 (1 << 12)35#define SSI_SISR_ROE1 (1 << 11)36#define SSI_SISR_ROE0 (1 << 10)37#define SSI_SISR_TUE1 (1 << 9)38#define SSI_SISR_TUE0 (1 << 8)39#define SSI_SISR_TFS (1 << 7)40#define SSI_SISR_RFS (1 << 6)41#define SSI_SISR_TLS (1 << 5)42#define SSI_SISR_RLS (1 << 4)43#define SSI_SISR_RFF1 (1 << 3)44#define SSI_SISR_RFF0 (1 << 2)45#define SSI_SISR_TFE1 (1 << 1)46#define SSI_SISR_TFE0 (1 << 0)47 48#define SSI_SIER 0x1849#define SSI_SIER_RDMAE (1 << 22)50#define SSI_SIER_RIE (1 << 21)51#define SSI_SIER_TDMAE (1 << 20)52#define SSI_SIER_TIE (1 << 19)53#define SSI_SIER_CMDAU_EN (1 << 18)54#define SSI_SIER_CMDDU_EN (1 << 17)55#define SSI_SIER_RXT_EN (1 << 16)56#define SSI_SIER_RDR1_EN (1 << 15)57#define SSI_SIER_RDR0_EN (1 << 14)58#define SSI_SIER_TDE1_EN (1 << 13)59#define SSI_SIER_TDE0_EN (1 << 12)60#define SSI_SIER_ROE1_EN (1 << 11)61#define SSI_SIER_ROE0_EN (1 << 10)62#define SSI_SIER_TUE1_EN (1 << 9)63#define SSI_SIER_TUE0_EN (1 << 8)64#define SSI_SIER_TFS_EN (1 << 7)65#define SSI_SIER_RFS_EN (1 << 6)66#define SSI_SIER_TLS_EN (1 << 5)67#define SSI_SIER_RLS_EN (1 << 4)68#define SSI_SIER_RFF1_EN (1 << 3)69#define SSI_SIER_RFF0_EN (1 << 2)70#define SSI_SIER_TFE1_EN (1 << 1)71#define SSI_SIER_TFE0_EN (1 << 0)72 73#define SSI_STCR 0x1c74#define SSI_STCR_TXBIT0 (1 << 9)75#define SSI_STCR_TFEN1 (1 << 8)76#define SSI_STCR_TFEN0 (1 << 7)77#define SSI_FIFO_ENABLE_0_SHIFT 778#define SSI_STCR_TFDIR (1 << 6)79#define SSI_STCR_TXDIR (1 << 5)80#define SSI_STCR_TSHFD (1 << 4)81#define SSI_STCR_TSCKP (1 << 3)82#define SSI_STCR_TFSI (1 << 2)83#define SSI_STCR_TFSL (1 << 1)84#define SSI_STCR_TEFS (1 << 0)85 86#define SSI_SRCR 0x2087#define SSI_SRCR_RXBIT0 (1 << 9)88#define SSI_SRCR_RFEN1 (1 << 8)89#define SSI_SRCR_RFEN0 (1 << 7)90#define SSI_FIFO_ENABLE_0_SHIFT 791#define SSI_SRCR_RFDIR (1 << 6)92#define SSI_SRCR_RXDIR (1 << 5)93#define SSI_SRCR_RSHFD (1 << 4)94#define SSI_SRCR_RSCKP (1 << 3)95#define SSI_SRCR_RFSI (1 << 2)96#define SSI_SRCR_RFSL (1 << 1)97#define SSI_SRCR_REFS (1 << 0)98 99#define SSI_SRCCR 0x28100#define SSI_SRCCR_DIV2 (1 << 18)101#define SSI_SRCCR_PSR (1 << 17)102#define SSI_SRCCR_WL(x) ((((x) - 2) >> 1) << 13)103#define SSI_SRCCR_DC(x) (((x) & 0x1f) << 8)104#define SSI_SRCCR_PM(x) (((x) & 0xff) << 0)105#define SSI_SRCCR_WL_MASK (0xf << 13)106#define SSI_SRCCR_DC_MASK (0x1f << 8)107#define SSI_SRCCR_PM_MASK (0xff << 0)108 109#define SSI_STCCR 0x24110#define SSI_STCCR_DIV2 (1 << 18)111#define SSI_STCCR_PSR (1 << 17)112#define SSI_STCCR_WL(x) ((((x) - 2) >> 1) << 13)113#define SSI_STCCR_DC(x) (((x) & 0x1f) << 8)114#define SSI_STCCR_PM(x) (((x) & 0xff) << 0)115#define SSI_STCCR_WL_MASK (0xf << 13)116#define SSI_STCCR_DC_MASK (0x1f << 8)117#define SSI_STCCR_PM_MASK (0xff << 0)118 119#define SSI_SFCSR 0x2c120#define SSI_SFCSR_RFCNT1(x) (((x) & 0xf) << 28)121#define SSI_RX_FIFO_1_COUNT_SHIFT 28122#define SSI_SFCSR_TFCNT1(x) (((x) & 0xf) << 24)123#define SSI_TX_FIFO_1_COUNT_SHIFT 24124#define SSI_SFCSR_RFWM1(x) (((x) & 0xf) << 20)125#define SSI_SFCSR_TFWM1(x) (((x) & 0xf) << 16)126#define SSI_SFCSR_RFCNT0(x) (((x) & 0xf) << 12)127#define SSI_RX_FIFO_0_COUNT_SHIFT 12128#define SSI_SFCSR_TFCNT0(x) (((x) & 0xf) << 8)129#define SSI_TX_FIFO_0_COUNT_SHIFT 8130#define SSI_SFCSR_RFWM0(x) (((x) & 0xf) << 4)131#define SSI_SFCSR_TFWM0(x) (((x) & 0xf) << 0)132#define SSI_SFCSR_RFWM0_MASK (0xf << 4)133#define SSI_SFCSR_TFWM0_MASK (0xf << 0)134 135#define SSI_STR 0x30136#define SSI_STR_TEST (1 << 15)137#define SSI_STR_RCK2TCK (1 << 14)138#define SSI_STR_RFS2TFS (1 << 13)139#define SSI_STR_RXSTATE(x) (((x) & 0xf) << 8)140#define SSI_STR_TXD2RXD (1 << 7)141#define SSI_STR_TCK2RCK (1 << 6)142#define SSI_STR_TFS2RFS (1 << 5)143#define SSI_STR_TXSTATE(x) (((x) & 0xf) << 0)144 145#define SSI_SOR 0x34146#define SSI_SOR_CLKOFF (1 << 6)147#define SSI_SOR_RX_CLR (1 << 5)148#define SSI_SOR_TX_CLR (1 << 4)149#define SSI_SOR_INIT (1 << 3)150#define SSI_SOR_WAIT(x) (((x) & 0x3) << 1)151#define SSI_SOR_WAIT_MASK (0x3 << 1)152#define SSI_SOR_SYNRST (1 << 0)153 154#define SSI_SACNT 0x38155#define SSI_SACNT_FRDIV(x) (((x) & 0x3f) << 5)156#define SSI_SACNT_WR (1 << 4)157#define SSI_SACNT_RD (1 << 3)158#define SSI_SACNT_TIF (1 << 2)159#define SSI_SACNT_FV (1 << 1)160#define SSI_SACNT_AC97EN (1 << 0)161 162#define SSI_SACADD 0x3c163#define SSI_SACDAT 0x40164#define SSI_SATAG 0x44165#define SSI_STMSK 0x48166#define SSI_SRMSK 0x4c167#define SSI_SACCST 0x50168#define SSI_SACCEN 0x54169#define SSI_SACCDIS 0x58170 171/* SSI clock sources */172#define IMX_SSP_SYS_CLK 0173 174/* SSI audio dividers */175#define IMX_SSI_TX_DIV_2 0176#define IMX_SSI_TX_DIV_PSR 1177#define IMX_SSI_TX_DIV_PM 2178#define IMX_SSI_RX_DIV_2 3179#define IMX_SSI_RX_DIV_PSR 4180#define IMX_SSI_RX_DIV_PM 5181 182#define DRV_NAME "imx-ssi"183 184#include <linux/dmaengine.h>185#include <linux/dma/imx-dma.h>186#include <sound/dmaengine_pcm.h>187#include "imx-pcm.h"188 189struct imx_ssi {190 struct platform_device *ac97_dev;191 192 struct snd_soc_dai *imx_ac97;193 struct clk *clk;194 void __iomem *base;195 int irq;196 int fiq_enable;197 unsigned int offset;198 199 unsigned int flags;200 201 void (*ac97_reset) (struct snd_ac97 *ac97);202 void (*ac97_warm_reset)(struct snd_ac97 *ac97);203 204 struct snd_dmaengine_dai_dma_data dma_params_rx;205 struct snd_dmaengine_dai_dma_data dma_params_tx;206 struct imx_dma_data filter_data_tx;207 struct imx_dma_data filter_data_rx;208 struct imx_pcm_fiq_params fiq_params;209 210 int fiq_init;211 int dma_init;212};213 214#endif /* _IMX_SSI_H */215