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1/* SPDX-License-Identifier: GPL-2.0-or-later */2/*3 * Author: Kevin Wells <kevin.wells@nxp.com>4 *5 * Copyright (C) 2008 NXP Semiconductors6 * Copyright 2023 Timesys Corporation <piotr.wojtaszczyk@timesys.com>7 */8 9#ifndef __SOUND_SOC_LPC3XXX_I2S_H10#define __SOUND_SOC_LPC3XXX_I2S_H11 12#include <linux/bitfield.h>13#include <linux/types.h>14#include <linux/regmap.h>15 16struct lpc3xxx_i2s_info {17 struct device *dev;18 struct clk *clk;19 struct mutex lock; /* To serialize user-space access */20 struct regmap *regs;21 u32 streams_in_use;22 u32 clkrate;23 int freq;24 struct snd_dmaengine_dai_dma_data playback_dma_config;25 struct snd_dmaengine_dai_dma_data capture_dma_config;26};27 28int lpc3xxx_pcm_register(struct platform_device *pdev);29 30/* I2S controller register offsets */31#define LPC3XXX_REG_I2S_DAO 0x0032#define LPC3XXX_REG_I2S_DAI 0x0433#define LPC3XXX_REG_I2S_TX_FIFO 0x0834#define LPC3XXX_REG_I2S_RX_FIFO 0x0C35#define LPC3XXX_REG_I2S_STAT 0x1036#define LPC3XXX_REG_I2S_DMA0 0x1437#define LPC3XXX_REG_I2S_DMA1 0x1838#define LPC3XXX_REG_I2S_IRQ 0x1C39#define LPC3XXX_REG_I2S_TX_RATE 0x2040#define LPC3XXX_REG_I2S_RX_RATE 0x2441 42/* i2s_daO i2s_dai register definitions */43#define LPC3XXX_I2S_WW8 FIELD_PREP(0x3, 0) /* Word width is 8bit */44#define LPC3XXX_I2S_WW16 FIELD_PREP(0x3, 1) /* Word width is 16bit */45#define LPC3XXX_I2S_WW32 FIELD_PREP(0x3, 3) /* Word width is 32bit */46#define LPC3XXX_I2S_MONO BIT(2) /* Mono */47#define LPC3XXX_I2S_STOP BIT(3) /* Stop, diables the access to FIFO, mutes the channel */48#define LPC3XXX_I2S_RESET BIT(4) /* Reset the channel */49#define LPC3XXX_I2S_WS_SEL BIT(5) /* Channel Master(0) or slave(1) mode select */50#define LPC3XXX_I2S_WS_HP(s) FIELD_PREP(0x7FC0, s) /* Word select half period - 1 */51#define LPC3XXX_I2S_MUTE BIT(15) /* Mute the channel, Transmit channel only */52 53#define LPC3XXX_I2S_WW32_HP 0x1f /* Word select half period for 32bit word width */54#define LPC3XXX_I2S_WW16_HP 0x0f /* Word select half period for 16bit word width */55#define LPC3XXX_I2S_WW8_HP 0x7 /* Word select half period for 8bit word width */56 57/* i2s_stat register definitions */58#define LPC3XXX_I2S_IRQ_STAT BIT(0)59#define LPC3XXX_I2S_DMA0_REQ BIT(1)60#define LPC3XXX_I2S_DMA1_REQ BIT(2)61 62/* i2s_dma0 Configuration register definitions */63#define LPC3XXX_I2S_DMA0_RX_EN BIT(0) /* Enable RX DMA1 */64#define LPC3XXX_I2S_DMA0_TX_EN BIT(1) /* Enable TX DMA1 */65#define LPC3XXX_I2S_DMA0_RX_DEPTH(s) FIELD_PREP(0xF00, s) /* Set the DMA1 RX Request level */66#define LPC3XXX_I2S_DMA0_TX_DEPTH(s) FIELD_PREP(0xF0000, s) /* Set the DMA1 TX Request level */67 68/* i2s_dma1 Configuration register definitions */69#define LPC3XXX_I2S_DMA1_RX_EN BIT(0) /* Enable RX DMA1 */70#define LPC3XXX_I2S_DMA1_TX_EN BIT(1) /* Enable TX DMA1 */71#define LPC3XXX_I2S_DMA1_RX_DEPTH(s) FIELD_PREP(0x700, s) /* Set the DMA1 RX Request level */72#define LPC3XXX_I2S_DMA1_TX_DEPTH(s) FIELD_PREP(0x70000, s) /* Set the DMA1 TX Request level */73 74/* i2s_irq register definitions */75#define LPC3XXX_I2S_RX_IRQ_EN BIT(0) /* Enable RX IRQ */76#define LPC3XXX_I2S_TX_IRQ_EN BIT(1) /* Enable TX IRQ */77#define LPC3XXX_I2S_IRQ_RX_DEPTH(s) FIELD_PREP(0xFF00, s) /* valid values ar 0 to 7 */78#define LPC3XXX_I2S_IRQ_TX_DEPTH(s) FIELD_PREP(0xFF0000, s) /* valid values ar 0 to 7 */79 80#endif81