157 lines · c
1/* SPDX-License-Identifier: GPL-2.0-only */2/*3 * Intel KeemBay Platform driver4 *5 * Copyright (C) 2020 Intel Corporation.6 *7 */8 9#ifndef KMB_PLATFORM_H_10#define KMB_PLATFORM_H_11 12#include <linux/bits.h>13#include <linux/bitfield.h>14#include <linux/types.h>15#include <sound/dmaengine_pcm.h>16 17/* Register values with reference to KMB databook v1.1 */18/* common register for all channel */19#define IER 0x00020#define IRER 0x00421#define ITER 0x00822#define CER 0x00C23#define CCR 0x01024#define RXFFR 0x01425#define TXFFR 0x01826 27/* Interrupt status register fields */28#define ISR_TXFO BIT(5)29#define ISR_TXFE BIT(4)30#define ISR_RXFO BIT(1)31#define ISR_RXDA BIT(0)32 33/* I2S Tx Rx Registers for all channels */34#define LRBR_LTHR(x) (0x40 * (x) + 0x020)35#define RRBR_RTHR(x) (0x40 * (x) + 0x024)36#define RER(x) (0x40 * (x) + 0x028)37#define TER(x) (0x40 * (x) + 0x02C)38#define RCR(x) (0x40 * (x) + 0x030)39#define TCR(x) (0x40 * (x) + 0x034)40#define ISR(x) (0x40 * (x) + 0x038)41#define IMR(x) (0x40 * (x) + 0x03C)42#define ROR(x) (0x40 * (x) + 0x040)43#define TOR(x) (0x40 * (x) + 0x044)44#define RFCR(x) (0x40 * (x) + 0x048)45#define TFCR(x) (0x40 * (x) + 0x04C)46#define RFF(x) (0x40 * (x) + 0x050)47#define TFF(x) (0x40 * (x) + 0x054)48 49/* I2S COMP Registers */50#define I2S_COMP_PARAM_2 0x01F051#define I2S_COMP_PARAM_1 0x01F452#define I2S_COMP_VERSION 0x01F853#define I2S_COMP_TYPE 0x01FC54 55/* PSS_GEN_CTRL_I2S_GEN_CFG_0 Registers */56#define I2S_GEN_CFG_0 0x00057#define PSS_CPR_RST_EN 0x01058#define PSS_CPR_RST_SET 0x01459#define PSS_CPR_CLK_CLR 0x00060#define PSS_CPR_AUX_RST_EN 0x07061 62#define CLOCK_PROVIDER_MODE BIT(13)63 64/* Interrupt Flag */65#define TX_INT_FLAG GENMASK(5, 4)66#define RX_INT_FLAG GENMASK(1, 0)67/*68 * Component parameter register fields - define the I2S block's69 * configuration.70 */71#define COMP1_TX_WORDSIZE_3(r) FIELD_GET(GENMASK(27, 25), (r))72#define COMP1_TX_WORDSIZE_2(r) FIELD_GET(GENMASK(24, 22), (r))73#define COMP1_TX_WORDSIZE_1(r) FIELD_GET(GENMASK(21, 19), (r))74#define COMP1_TX_WORDSIZE_0(r) FIELD_GET(GENMASK(18, 16), (r))75#define COMP1_RX_ENABLED(r) FIELD_GET(BIT(6), (r))76#define COMP1_TX_ENABLED(r) FIELD_GET(BIT(5), (r))77#define COMP1_MODE_EN(r) FIELD_GET(BIT(4), (r))78#define COMP1_APB_DATA_WIDTH(r) FIELD_GET(GENMASK(1, 0), (r))79#define COMP2_RX_WORDSIZE_3(r) FIELD_GET(GENMASK(12, 10), (r))80#define COMP2_RX_WORDSIZE_2(r) FIELD_GET(GENMASK(9, 7), (r))81#define COMP2_RX_WORDSIZE_1(r) FIELD_GET(GENMASK(5, 3), (r))82#define COMP2_RX_WORDSIZE_0(r) FIELD_GET(GENMASK(2, 0), (r))83 84/* Add 1 to the below registers to indicate the actual size */85#define COMP1_TX_CHANNELS(r) (FIELD_GET(GENMASK(10, 9), (r)) + 1)86#define COMP1_RX_CHANNELS(r) (FIELD_GET(GENMASK(8, 7), (r)) + 1)87#define COMP1_FIFO_DEPTH(r) (FIELD_GET(GENMASK(3, 2), (r)) + 1)88 89/* Number of entries in WORDSIZE and DATA_WIDTH parameter registers */90#define COMP_MAX_WORDSIZE 8 /* 3 bits register width */91 92#define MAX_CHANNEL_NUM 893#define MIN_CHANNEL_NUM 294#define MAX_ISR 495 96#define TWO_CHANNEL_SUPPORT 2 /* up to 2.0 */97#define FOUR_CHANNEL_SUPPORT 4 /* up to 3.1 */98#define SIX_CHANNEL_SUPPORT 6 /* up to 5.1 */99#define EIGHT_CHANNEL_SUPPORT 8 /* up to 7.1 */100 101#define DWC_I2S_PLAY BIT(0)102#define DWC_I2S_RECORD BIT(1)103#define DW_I2S_CONSUMER BIT(2)104#define DW_I2S_PROVIDER BIT(3)105 106#define I2S_RXDMA 0x01C0107#define I2S_RRXDMA 0x01C4108#define I2S_TXDMA 0x01C8109#define I2S_RTXDMA 0x01CC110#define I2S_DMACR 0x0200111#define I2S_DMAEN_RXBLOCK (1 << 16)112#define I2S_DMAEN_TXBLOCK (1 << 17)113 114/*115 * struct i2s_clk_config_data - represent i2s clk configuration data116 * @chan_nr: number of channel117 * @data_width: number of bits per sample (8/16/24/32 bit)118 * @sample_rate: sampling frequency (8Khz, 16Khz, 48Khz)119 */120struct i2s_clk_config_data {121 int chan_nr;122 u32 data_width;123 u32 sample_rate;124};125 126struct kmb_i2s_info {127 void __iomem *i2s_base;128 void __iomem *pss_base;129 struct clk *clk_i2s;130 struct clk *clk_apb;131 int active;132 unsigned int capability;133 unsigned int i2s_reg_comp1;134 unsigned int i2s_reg_comp2;135 struct device *dev;136 u32 ccr;137 u32 xfer_resolution;138 u32 fifo_th;139 bool clock_provider;140 /* data related to DMA transfers b/w i2s and DMAC */141 struct snd_dmaengine_dai_dma_data play_dma_data;142 struct snd_dmaengine_dai_dma_data capture_dma_data;143 144 struct i2s_clk_config_data config;145 int (*i2s_clk_cfg)(struct i2s_clk_config_data *config);146 147 /* data related to PIO transfers */148 bool use_pio;149 struct snd_pcm_substream *tx_substream;150 struct snd_pcm_substream *rx_substream;151 unsigned int tx_ptr;152 unsigned int rx_ptr;153 bool iec958_fmt;154};155 156#endif /* KMB_PLATFORM_H_ */157