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1/* SPDX-License-Identifier: GPL-2.0 */2/*3 * mt2701-reg.h -- Mediatek 2701 audio driver reg definition4 *5 * Copyright (c) 2016 MediaTek Inc.6 * Author: Garlic Tseng <garlic.tseng@mediatek.com>7 */8 9#ifndef _MT2701_REG_H_10#define _MT2701_REG_H_11 12#define AUDIO_TOP_CON0 0x000013#define AUDIO_TOP_CON4 0x001014#define AUDIO_TOP_CON5 0x001415#define AFE_DAIBT_CON0 0x001c16#define AFE_MRGIF_CON 0x003c17#define ASMI_TIMING_CON1 0x010018#define ASMO_TIMING_CON1 0x010419#define PWR1_ASM_CON1 0x010820#define ASYS_TOP_CON 0x060021#define ASYS_I2SIN1_CON 0x060422#define ASYS_I2SIN2_CON 0x060823#define ASYS_I2SIN3_CON 0x060c24#define ASYS_I2SIN4_CON 0x061025#define ASYS_I2SIN5_CON 0x061426#define ASYS_I2SO1_CON 0x061C27#define ASYS_I2SO2_CON 0x062028#define ASYS_I2SO3_CON 0x062429#define ASYS_I2SO4_CON 0x062830#define ASYS_I2SO5_CON 0x062c31#define PWR2_TOP_CON 0x063432#define AFE_CONN0 0x06c033#define AFE_CONN1 0x06c434#define AFE_CONN2 0x06c835#define AFE_CONN3 0x06cc36#define AFE_CONN14 0x06f837#define AFE_CONN15 0x06fc38#define AFE_CONN16 0x070039#define AFE_CONN17 0x070440#define AFE_CONN18 0x070841#define AFE_CONN19 0x070c42#define AFE_CONN20 0x071043#define AFE_CONN21 0x071444#define AFE_CONN22 0x071845#define AFE_CONN23 0x071c46#define AFE_CONN24 0x072047#define AFE_CONN41 0x076448#define ASYS_IRQ1_CON 0x078049#define ASYS_IRQ2_CON 0x078450#define ASYS_IRQ3_CON 0x078851#define ASYS_IRQ_CLR 0x07c052#define ASYS_IRQ_STATUS 0x07c453#define PWR2_ASM_CON1 0x107054#define AFE_DAC_CON0 0x120055#define AFE_DAC_CON1 0x120456#define AFE_DAC_CON2 0x120857#define AFE_DAC_CON3 0x120c58#define AFE_DAC_CON4 0x121059#define AFE_MEMIF_HD_CON1 0x121c60#define AFE_MEMIF_PBUF_SIZE 0x123861#define AFE_MEMIF_HD_CON0 0x123c62#define AFE_DL1_BASE 0x124063#define AFE_DL1_CUR 0x124464#define AFE_DL2_BASE 0x125065#define AFE_DL2_CUR 0x125466#define AFE_DL3_BASE 0x126067#define AFE_DL3_CUR 0x126468#define AFE_DL4_BASE 0x127069#define AFE_DL4_CUR 0x127470#define AFE_DL5_BASE 0x128071#define AFE_DL5_CUR 0x128472#define AFE_DLMCH_BASE 0x12a073#define AFE_DLMCH_CUR 0x12a474#define AFE_ARB1_BASE 0x12b075#define AFE_ARB1_CUR 0x12b476#define AFE_VUL_BASE 0x130077#define AFE_VUL_CUR 0x130c78#define AFE_UL2_BASE 0x131079#define AFE_UL2_END 0x131880#define AFE_UL2_CUR 0x131c81#define AFE_UL3_BASE 0x132082#define AFE_UL3_END 0x132883#define AFE_UL3_CUR 0x132c84#define AFE_UL4_BASE 0x133085#define AFE_UL4_END 0x133886#define AFE_UL4_CUR 0x133c87#define AFE_UL5_BASE 0x134088#define AFE_UL5_END 0x134889#define AFE_UL5_CUR 0x134c90#define AFE_DAI_BASE 0x137091#define AFE_DAI_CUR 0x137c92 93/* AFE_DAIBT_CON0 (0x001c) */94#define AFE_DAIBT_CON0_DAIBT_EN (0x1 << 0)95#define AFE_DAIBT_CON0_BT_FUNC_EN (0x1 << 1)96#define AFE_DAIBT_CON0_BT_FUNC_RDY (0x1 << 3)97#define AFE_DAIBT_CON0_BT_WIDE_MODE_EN (0x1 << 9)98#define AFE_DAIBT_CON0_MRG_USE (0x1 << 12)99 100/* PWR1_ASM_CON1 (0x0108) */101#define PWR1_ASM_CON1_INIT_VAL (0x492)102 103/* AFE_MRGIF_CON (0x003c) */104#define AFE_MRGIF_CON_MRG_EN (0x1 << 0)105#define AFE_MRGIF_CON_MRG_I2S_EN (0x1 << 16)106#define AFE_MRGIF_CON_I2S_MODE_MASK (0xf << 20)107#define AFE_MRGIF_CON_I2S_MODE_32K (0x4 << 20)108 109/* ASYS_TOP_CON (0x0600) */110#define ASYS_TOP_CON_ASYS_TIMING_ON (0x3 << 0)111 112/* PWR2_ASM_CON1 (0x1070) */113#define PWR2_ASM_CON1_INIT_VAL (0x492492)114 115/* AFE_DAC_CON0 (0x1200) */116#define AFE_DAC_CON0_AFE_ON (0x1 << 0)117 118/* AFE_MEMIF_PBUF_SIZE (0x1238) */119#define AFE_MEMIF_PBUF_SIZE_DLM_MASK (0x1 << 29)120#define AFE_MEMIF_PBUF_SIZE_PAIR_INTERLEAVE (0x0 << 29)121#define AFE_MEMIF_PBUF_SIZE_FULL_INTERLEAVE (0x1 << 29)122#define DLMCH_BIT_WIDTH_MASK (0x1 << 28)123#define AFE_MEMIF_PBUF_SIZE_DLM_CH_MASK (0xf << 24)124#define AFE_MEMIF_PBUF_SIZE_DLM_CH(x) ((x) << 24)125#define AFE_MEMIF_PBUF_SIZE_DLM_BYTE_MASK (0x3 << 12)126#define AFE_MEMIF_PBUF_SIZE_DLM_32BYTES (0x1 << 12)127 128/* I2S in/out register bit control */129#define ASYS_I2S_CON_FS (0x1f << 8)130#define ASYS_I2S_CON_FS_SET(x) ((x) << 8)131#define ASYS_I2S_CON_RESET (0x1 << 30)132#define ASYS_I2S_CON_I2S_EN (0x1 << 0)133#define ASYS_I2S_CON_ONE_HEART_MODE (0x1 << 16)134#define ASYS_I2S_CON_I2S_COUPLE_MODE (0x1 << 17)135/* 0:EIAJ 1:I2S */136#define ASYS_I2S_CON_I2S_MODE (0x1 << 3)137#define ASYS_I2S_CON_WIDE_MODE (0x1 << 1)138#define ASYS_I2S_CON_WIDE_MODE_SET(x) ((x) << 1)139#define ASYS_I2S_IN_PHASE_FIX (0x1 << 31)140 141#endif142