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1/* SPDX-License-Identifier: GPL-2.0 */2/*3 * mt6797-reg.h -- Mediatek 6797 audio driver reg definition4 *5 * Copyright (c) 2018 MediaTek Inc.6 * Author: KaiChieh Chuang <kaichieh.chuang@mediatek.com>7 */8 9#ifndef _MT6797_REG_H_10#define _MT6797_REG_H_11 12#define AUDIO_TOP_CON0 0x000013#define AUDIO_TOP_CON1 0x000414#define AUDIO_TOP_CON3 0x000c15#define AFE_DAC_CON0 0x001016#define AFE_DAC_CON1 0x001417#define AFE_I2S_CON 0x001818#define AFE_DAIBT_CON0 0x001c19#define AFE_CONN0 0x002020#define AFE_CONN1 0x002421#define AFE_CONN2 0x002822#define AFE_CONN3 0x002c23#define AFE_CONN4 0x003024#define AFE_I2S_CON1 0x003425#define AFE_I2S_CON2 0x003826#define AFE_MRGIF_CON 0x003c27#define AFE_DL1_BASE 0x004028#define AFE_DL1_CUR 0x004429#define AFE_DL1_END 0x004830#define AFE_I2S_CON3 0x004c31#define AFE_DL2_BASE 0x005032#define AFE_DL2_CUR 0x005433#define AFE_DL2_END 0x005834#define AFE_CONN5 0x005c35#define AFE_CONN_24BIT 0x006c36#define AFE_AWB_BASE 0x007037#define AFE_AWB_END 0x007838#define AFE_AWB_CUR 0x007c39#define AFE_VUL_BASE 0x008040#define AFE_VUL_END 0x008841#define AFE_VUL_CUR 0x008c42#define AFE_DAI_BASE 0x009043#define AFE_DAI_END 0x009844#define AFE_DAI_CUR 0x009c45#define AFE_CONN6 0x00bc46#define AFE_MEMIF_MSB 0x00cc47#define AFE_MEMIF_MON0 0x00d048#define AFE_MEMIF_MON1 0x00d449#define AFE_MEMIF_MON2 0x00d850#define AFE_MEMIF_MON4 0x00e051#define AFE_ADDA_DL_SRC2_CON0 0x010852#define AFE_ADDA_DL_SRC2_CON1 0x010c53#define AFE_ADDA_UL_SRC_CON0 0x011454#define AFE_ADDA_UL_SRC_CON1 0x011855#define AFE_ADDA_TOP_CON0 0x012056#define AFE_ADDA_UL_DL_CON0 0x012457#define AFE_ADDA_SRC_DEBUG 0x012c58#define AFE_ADDA_SRC_DEBUG_MON0 0x013059#define AFE_ADDA_SRC_DEBUG_MON1 0x013460#define AFE_ADDA_NEWIF_CFG0 0x013861#define AFE_ADDA_NEWIF_CFG1 0x013c62#define AFE_ADDA_NEWIF_CFG2 0x014063#define AFE_DMA_CTL 0x015064#define AFE_DMA_MON0 0x015465#define AFE_DMA_MON1 0x015866#define AFE_SIDETONE_DEBUG 0x01d067#define AFE_SIDETONE_MON 0x01d468#define AFE_SIDETONE_CON0 0x01e069#define AFE_SIDETONE_COEFF 0x01e470#define AFE_SIDETONE_CON1 0x01e871#define AFE_SIDETONE_GAIN 0x01ec72#define AFE_SGEN_CON0 0x01f073#define AFE_SINEGEN_CON_TDM 0x01fc74#define AFE_TOP_CON0 0x020075#define AFE_ADDA_PREDIS_CON0 0x026076#define AFE_ADDA_PREDIS_CON1 0x026477#define AFE_MRGIF_MON0 0x027078#define AFE_MRGIF_MON1 0x027479#define AFE_MRGIF_MON2 0x027880#define AFE_I2S_MON 0x027c81#define AFE_MOD_DAI_BASE 0x033082#define AFE_MOD_DAI_END 0x033883#define AFE_MOD_DAI_CUR 0x033c84#define AFE_VUL_D2_BASE 0x035085#define AFE_VUL_D2_END 0x035886#define AFE_VUL_D2_CUR 0x035c87#define AFE_DL3_BASE 0x036088#define AFE_DL3_CUR 0x036489#define AFE_DL3_END 0x036890#define AFE_HDMI_OUT_CON0 0x037091#define AFE_HDMI_BASE 0x037492#define AFE_HDMI_CUR 0x037893#define AFE_HDMI_END 0x037c94#define AFE_HDMI_CONN0 0x039095#define AFE_IRQ3_MCU_CNT_MON 0x039896#define AFE_IRQ4_MCU_CNT_MON 0x039c97#define AFE_IRQ_MCU_CON 0x03a098#define AFE_IRQ_MCU_STATUS 0x03a499#define AFE_IRQ_MCU_CLR 0x03a8100#define AFE_IRQ_MCU_CNT1 0x03ac101#define AFE_IRQ_MCU_CNT2 0x03b0102#define AFE_IRQ_MCU_EN 0x03b4103#define AFE_IRQ_MCU_MON2 0x03b8104#define AFE_IRQ_MCU_CNT5 0x03bc105#define AFE_IRQ1_MCU_CNT_MON 0x03c0106#define AFE_IRQ2_MCU_CNT_MON 0x03c4107#define AFE_IRQ1_MCU_EN_CNT_MON 0x03c8108#define AFE_IRQ5_MCU_CNT_MON 0x03cc109#define AFE_MEMIF_MINLEN 0x03d0110#define AFE_MEMIF_MAXLEN 0x03d4111#define AFE_MEMIF_PBUF_SIZE 0x03d8112#define AFE_IRQ_MCU_CNT7 0x03dc113#define AFE_IRQ7_MCU_CNT_MON 0x03e0114#define AFE_IRQ_MCU_CNT3 0x03e4115#define AFE_IRQ_MCU_CNT4 0x03e8116#define AFE_APLL1_TUNER_CFG 0x03f0117#define AFE_APLL2_TUNER_CFG 0x03f4118#define AFE_MEMIF_HD_MODE 0x03f8119#define AFE_MEMIF_HDALIGN 0x03fc120#define AFE_GAIN1_CON0 0x0410121#define AFE_GAIN1_CON1 0x0414122#define AFE_GAIN1_CON2 0x0418123#define AFE_GAIN1_CON3 0x041c124#define AFE_CONN7 0x0420125#define AFE_GAIN1_CUR 0x0424126#define AFE_GAIN2_CON0 0x0428127#define AFE_GAIN2_CON1 0x042c128#define AFE_GAIN2_CON2 0x0430129#define AFE_GAIN2_CON3 0x0434130#define AFE_CONN8 0x0438131#define AFE_GAIN2_CUR 0x043c132#define AFE_CONN9 0x0440133#define AFE_CONN10 0x0444134#define AFE_CONN11 0x0448135#define AFE_CONN12 0x044c136#define AFE_CONN13 0x0450137#define AFE_CONN14 0x0454138#define AFE_CONN15 0x0458139#define AFE_CONN16 0x045c140#define AFE_CONN17 0x0460141#define AFE_CONN18 0x0464142#define AFE_CONN19 0x0468143#define AFE_CONN20 0x046c144#define AFE_CONN21 0x0470145#define AFE_CONN22 0x0474146#define AFE_CONN23 0x0478147#define AFE_CONN24 0x047c148#define AFE_CONN_RS 0x0494149#define AFE_CONN_DI 0x0498150#define AFE_CONN25 0x04b0151#define AFE_CONN26 0x04b4152#define AFE_CONN27 0x04b8153#define AFE_CONN28 0x04bc154#define AFE_CONN29 0x04c0155#define AFE_SRAM_DELSEL_CON0 0x04f0156#define AFE_SRAM_DELSEL_CON1 0x04f4157#define AFE_ASRC_CON0 0x0500158#define AFE_ASRC_CON1 0x0504159#define AFE_ASRC_CON2 0x0508160#define AFE_ASRC_CON3 0x050c161#define AFE_ASRC_CON4 0x0510162#define AFE_ASRC_CON5 0x0514163#define AFE_ASRC_CON6 0x0518164#define AFE_ASRC_CON7 0x051c165#define AFE_ASRC_CON8 0x0520166#define AFE_ASRC_CON9 0x0524167#define AFE_ASRC_CON10 0x0528168#define AFE_ASRC_CON11 0x052c169#define PCM_INTF_CON1 0x0530170#define PCM_INTF_CON2 0x0538171#define PCM2_INTF_CON 0x053c172#define AFE_TDM_CON1 0x0548173#define AFE_TDM_CON2 0x054c174#define AFE_ASRC_CON13 0x0550175#define AFE_ASRC_CON14 0x0554176#define AFE_ASRC_CON15 0x0558177#define AFE_ASRC_CON16 0x055c178#define AFE_ASRC_CON17 0x0560179#define AFE_ASRC_CON18 0x0564180#define AFE_ASRC_CON19 0x0568181#define AFE_ASRC_CON20 0x056c182#define AFE_ASRC_CON21 0x0570183#define CLK_AUDDIV_0 0x05a0184#define CLK_AUDDIV_1 0x05a4185#define CLK_AUDDIV_2 0x05a8186#define CLK_AUDDIV_3 0x05ac187#define AUDIO_TOP_DBG_CON 0x05c8188#define AUDIO_TOP_DBG_MON0 0x05cc189#define AUDIO_TOP_DBG_MON1 0x05d0190#define AUDIO_TOP_DBG_MON2 0x05d4191#define AFE_ADDA2_TOP_CON0 0x0600192#define AFE_ASRC4_CON0 0x06c0193#define AFE_ASRC4_CON1 0x06c4194#define AFE_ASRC4_CON2 0x06c8195#define AFE_ASRC4_CON3 0x06cc196#define AFE_ASRC4_CON4 0x06d0197#define AFE_ASRC4_CON5 0x06d4198#define AFE_ASRC4_CON6 0x06d8199#define AFE_ASRC4_CON7 0x06dc200#define AFE_ASRC4_CON8 0x06e0201#define AFE_ASRC4_CON9 0x06e4202#define AFE_ASRC4_CON10 0x06e8203#define AFE_ASRC4_CON11 0x06ec204#define AFE_ASRC4_CON12 0x06f0205#define AFE_ASRC4_CON13 0x06f4206#define AFE_ASRC4_CON14 0x06f8207#define AFE_ASRC2_CON0 0x0700208#define AFE_ASRC2_CON1 0x0704209#define AFE_ASRC2_CON2 0x0708210#define AFE_ASRC2_CON3 0x070c211#define AFE_ASRC2_CON4 0x0710212#define AFE_ASRC2_CON5 0x0714213#define AFE_ASRC2_CON6 0x0718214#define AFE_ASRC2_CON7 0x071c215#define AFE_ASRC2_CON8 0x0720216#define AFE_ASRC2_CON9 0x0724217#define AFE_ASRC2_CON10 0x0728218#define AFE_ASRC2_CON11 0x072c219#define AFE_ASRC2_CON12 0x0730220#define AFE_ASRC2_CON13 0x0734221#define AFE_ASRC2_CON14 0x0738222#define AFE_ASRC3_CON0 0x0740223#define AFE_ASRC3_CON1 0x0744224#define AFE_ASRC3_CON2 0x0748225#define AFE_ASRC3_CON3 0x074c226#define AFE_ASRC3_CON4 0x0750227#define AFE_ASRC3_CON5 0x0754228#define AFE_ASRC3_CON6 0x0758229#define AFE_ASRC3_CON7 0x075c230#define AFE_ASRC3_CON8 0x0760231#define AFE_ASRC3_CON9 0x0764232#define AFE_ASRC3_CON10 0x0768233#define AFE_ASRC3_CON11 0x076c234#define AFE_ASRC3_CON12 0x0770235#define AFE_ASRC3_CON13 0x0774236#define AFE_ASRC3_CON14 0x0778237#define AFE_GENERAL_REG0 0x0800238#define AFE_GENERAL_REG1 0x0804239#define AFE_GENERAL_REG2 0x0808240#define AFE_GENERAL_REG3 0x080c241#define AFE_GENERAL_REG4 0x0810242#define AFE_GENERAL_REG5 0x0814243#define AFE_GENERAL_REG6 0x0818244#define AFE_GENERAL_REG7 0x081c245#define AFE_GENERAL_REG8 0x0820246#define AFE_GENERAL_REG9 0x0824247#define AFE_GENERAL_REG10 0x0828248#define AFE_GENERAL_REG11 0x082c249#define AFE_GENERAL_REG12 0x0830250#define AFE_GENERAL_REG13 0x0834251#define AFE_GENERAL_REG14 0x0838252#define AFE_GENERAL_REG15 0x083c253#define AFE_CBIP_CFG0 0x0840254#define AFE_CBIP_MON0 0x0844255#define AFE_CBIP_SLV_MUX_MON0 0x0848256#define AFE_CBIP_SLV_DECODER_MON0 0x084c257 258#define AFE_MAX_REGISTER AFE_CBIP_SLV_DECODER_MON0259#define AFE_IRQ_STATUS_BITS 0x5f260 261/* AUDIO_TOP_CON0 */262#define AHB_IDLE_EN_INT_SFT 30263#define AHB_IDLE_EN_INT_MASK 0x1264#define AHB_IDLE_EN_INT_MASK_SFT (0x1 << 30)265#define AHB_IDLE_EN_EXT_SFT 29266#define AHB_IDLE_EN_EXT_MASK 0x1267#define AHB_IDLE_EN_EXT_MASK_SFT (0x1 << 29)268#define PDN_TML_SFT 27269#define PDN_TML_MASK 0x1270#define PDN_TML_MASK_SFT (0x1 << 27)271#define PDN_DAC_PREDIS_SFT 26272#define PDN_DAC_PREDIS_MASK 0x1273#define PDN_DAC_PREDIS_MASK_SFT (0x1 << 26)274#define PDN_DAC_SFT 25275#define PDN_DAC_MASK 0x1276#define PDN_DAC_MASK_SFT (0x1 << 25)277#define PDN_ADC_SFT 24278#define PDN_ADC_MASK 0x1279#define PDN_ADC_MASK_SFT (0x1 << 24)280#define PDN_TDM_CK_SFT 20281#define PDN_TDM_CK_MASK 0x1282#define PDN_TDM_CK_MASK_SFT (0x1 << 20)283#define PDN_APLL_TUNER_SFT 19284#define PDN_APLL_TUNER_MASK 0x1285#define PDN_APLL_TUNER_MASK_SFT (0x1 << 19)286#define PDN_APLL2_TUNER_SFT 18287#define PDN_APLL2_TUNER_MASK 0x1288#define PDN_APLL2_TUNER_MASK_SFT (0x1 << 18)289#define APB3_SEL_SFT 14290#define APB3_SEL_MASK 0x1291#define APB3_SEL_MASK_SFT (0x1 << 14)292#define APB_R2T_SFT 13293#define APB_R2T_MASK 0x1294#define APB_R2T_MASK_SFT (0x1 << 13)295#define APB_W2T_SFT 12296#define APB_W2T_MASK 0x1297#define APB_W2T_MASK_SFT (0x1 << 12)298#define PDN_24M_SFT 9299#define PDN_24M_MASK 0x1300#define PDN_24M_MASK_SFT (0x1 << 9)301#define PDN_22M_SFT 8302#define PDN_22M_MASK 0x1303#define PDN_22M_MASK_SFT (0x1 << 8)304#define PDN_ADDA4_ADC_SFT 7305#define PDN_ADDA4_ADC_MASK 0x1306#define PDN_ADDA4_ADC_MASK_SFT (0x1 << 7)307#define PDN_I2S_SFT 6308#define PDN_I2S_MASK 0x1309#define PDN_I2S_MASK_SFT (0x1 << 6)310#define PDN_AFE_SFT 2311#define PDN_AFE_MASK 0x1312#define PDN_AFE_MASK_SFT (0x1 << 2)313 314/* AUDIO_TOP_CON1 */315#define PDN_ADC_HIRES_TML_SFT 17316#define PDN_ADC_HIRES_TML_MASK 0x1317#define PDN_ADC_HIRES_TML_MASK_SFT (0x1 << 17)318#define PDN_ADC_HIRES_SFT 16319#define PDN_ADC_HIRES_MASK 0x1320#define PDN_ADC_HIRES_MASK_SFT (0x1 << 16)321#define I2S4_BCLK_SW_CG_SFT 7322#define I2S4_BCLK_SW_CG_MASK 0x1323#define I2S4_BCLK_SW_CG_MASK_SFT (0x1 << 7)324#define I2S3_BCLK_SW_CG_SFT 6325#define I2S3_BCLK_SW_CG_MASK 0x1326#define I2S3_BCLK_SW_CG_MASK_SFT (0x1 << 6)327#define I2S2_BCLK_SW_CG_SFT 5328#define I2S2_BCLK_SW_CG_MASK 0x1329#define I2S2_BCLK_SW_CG_MASK_SFT (0x1 << 5)330#define I2S1_BCLK_SW_CG_SFT 4331#define I2S1_BCLK_SW_CG_MASK 0x1332#define I2S1_BCLK_SW_CG_MASK_SFT (0x1 << 4)333#define I2S_SOFT_RST2_SFT 2334#define I2S_SOFT_RST2_MASK 0x1335#define I2S_SOFT_RST2_MASK_SFT (0x1 << 2)336#define I2S_SOFT_RST_SFT 1337#define I2S_SOFT_RST_MASK 0x1338#define I2S_SOFT_RST_MASK_SFT (0x1 << 1)339 340/* AFE_DAC_CON0 */341#define AFE_AWB_RETM_SFT 31342#define AFE_AWB_RETM_MASK 0x1343#define AFE_AWB_RETM_MASK_SFT (0x1 << 31)344#define AFE_DL1_DATA2_RETM_SFT 30345#define AFE_DL1_DATA2_RETM_MASK 0x1346#define AFE_DL1_DATA2_RETM_MASK_SFT (0x1 << 30)347#define AFE_DL2_RETM_SFT 29348#define AFE_DL2_RETM_MASK 0x1349#define AFE_DL2_RETM_MASK_SFT (0x1 << 29)350#define AFE_DL1_RETM_SFT 28351#define AFE_DL1_RETM_MASK 0x1352#define AFE_DL1_RETM_MASK_SFT (0x1 << 28)353#define AFE_ON_RETM_SFT 27354#define AFE_ON_RETM_MASK 0x1355#define AFE_ON_RETM_MASK_SFT (0x1 << 27)356#define MOD_DAI_DUP_WR_SFT 26357#define MOD_DAI_DUP_WR_MASK 0x1358#define MOD_DAI_DUP_WR_MASK_SFT (0x1 << 26)359#define DAI_MODE_SFT 24360#define DAI_MODE_MASK 0x3361#define DAI_MODE_MASK_SFT (0x3 << 24)362#define VUL_DATA2_MODE_SFT 20363#define VUL_DATA2_MODE_MASK 0xf364#define VUL_DATA2_MODE_MASK_SFT (0xf << 20)365#define DL1_DATA2_MODE_SFT 16366#define DL1_DATA2_MODE_MASK 0xf367#define DL1_DATA2_MODE_MASK_SFT (0xf << 16)368#define DL3_MODE_SFT 12369#define DL3_MODE_MASK 0xf370#define DL3_MODE_MASK_SFT (0xf << 12)371#define VUL_DATA2_R_MONO_SFT 11372#define VUL_DATA2_R_MONO_MASK 0x1373#define VUL_DATA2_R_MONO_MASK_SFT (0x1 << 11)374#define VUL_DATA2_DATA_SFT 10375#define VUL_DATA2_DATA_MASK 0x1376#define VUL_DATA2_DATA_MASK_SFT (0x1 << 10)377#define VUL_DATA2_ON_SFT 9378#define VUL_DATA2_ON_MASK 0x1379#define VUL_DATA2_ON_MASK_SFT (0x1 << 9)380#define DL1_DATA2_ON_SFT 8381#define DL1_DATA2_ON_MASK 0x1382#define DL1_DATA2_ON_MASK_SFT (0x1 << 8)383#define MOD_DAI_ON_SFT 7384#define MOD_DAI_ON_MASK 0x1385#define MOD_DAI_ON_MASK_SFT (0x1 << 7)386#define AWB_ON_SFT 6387#define AWB_ON_MASK 0x1388#define AWB_ON_MASK_SFT (0x1 << 6)389#define DL3_ON_SFT 5390#define DL3_ON_MASK 0x1391#define DL3_ON_MASK_SFT (0x1 << 5)392#define DAI_ON_SFT 4393#define DAI_ON_MASK 0x1394#define DAI_ON_MASK_SFT (0x1 << 4)395#define VUL_ON_SFT 3396#define VUL_ON_MASK 0x1397#define VUL_ON_MASK_SFT (0x1 << 3)398#define DL2_ON_SFT 2399#define DL2_ON_MASK 0x1400#define DL2_ON_MASK_SFT (0x1 << 2)401#define DL1_ON_SFT 1402#define DL1_ON_MASK 0x1403#define DL1_ON_MASK_SFT (0x1 << 1)404#define AFE_ON_SFT 0405#define AFE_ON_MASK 0x1406#define AFE_ON_MASK_SFT (0x1 << 0)407 408/* AFE_DAC_CON1 */409#define MOD_DAI_MODE_SFT 30410#define MOD_DAI_MODE_MASK 0x3411#define MOD_DAI_MODE_MASK_SFT (0x3 << 30)412#define DAI_DUP_WR_SFT 29413#define DAI_DUP_WR_MASK 0x1414#define DAI_DUP_WR_MASK_SFT (0x1 << 29)415#define VUL_R_MONO_SFT 28416#define VUL_R_MONO_MASK 0x1417#define VUL_R_MONO_MASK_SFT (0x1 << 28)418#define VUL_DATA_SFT 27419#define VUL_DATA_MASK 0x1420#define VUL_DATA_MASK_SFT (0x1 << 27)421#define AXI_2X1_CG_DISABLE_SFT 26422#define AXI_2X1_CG_DISABLE_MASK 0x1423#define AXI_2X1_CG_DISABLE_MASK_SFT (0x1 << 26)424#define AWB_R_MONO_SFT 25425#define AWB_R_MONO_MASK 0x1426#define AWB_R_MONO_MASK_SFT (0x1 << 25)427#define AWB_DATA_SFT 24428#define AWB_DATA_MASK 0x1429#define AWB_DATA_MASK_SFT (0x1 << 24)430#define DL3_DATA_SFT 23431#define DL3_DATA_MASK 0x1432#define DL3_DATA_MASK_SFT (0x1 << 23)433#define DL2_DATA_SFT 22434#define DL2_DATA_MASK 0x1435#define DL2_DATA_MASK_SFT (0x1 << 22)436#define DL1_DATA_SFT 21437#define DL1_DATA_MASK 0x1438#define DL1_DATA_MASK_SFT (0x1 << 21)439#define DL1_DATA2_DATA_SFT 20440#define DL1_DATA2_DATA_MASK 0x1441#define DL1_DATA2_DATA_MASK_SFT (0x1 << 20)442#define VUL_MODE_SFT 16443#define VUL_MODE_MASK 0xf444#define VUL_MODE_MASK_SFT (0xf << 16)445#define AWB_MODE_SFT 12446#define AWB_MODE_MASK 0xf447#define AWB_MODE_MASK_SFT (0xf << 12)448#define I2S_MODE_SFT 8449#define I2S_MODE_MASK 0xf450#define I2S_MODE_MASK_SFT (0xf << 8)451#define DL2_MODE_SFT 4452#define DL2_MODE_MASK 0xf453#define DL2_MODE_MASK_SFT (0xf << 4)454#define DL1_MODE_SFT 0455#define DL1_MODE_MASK 0xf456#define DL1_MODE_MASK_SFT (0xf << 0)457 458/* AFE_ADDA_DL_SRC2_CON0 */459#define DL_2_INPUT_MODE_CTL_SFT 28460#define DL_2_INPUT_MODE_CTL_MASK 0xf461#define DL_2_INPUT_MODE_CTL_MASK_SFT (0xf << 28)462#define DL_2_CH1_SATURATION_EN_CTL_SFT 27463#define DL_2_CH1_SATURATION_EN_CTL_MASK 0x1464#define DL_2_CH1_SATURATION_EN_CTL_MASK_SFT (0x1 << 27)465#define DL_2_CH2_SATURATION_EN_CTL_SFT 26466#define DL_2_CH2_SATURATION_EN_CTL_MASK 0x1467#define DL_2_CH2_SATURATION_EN_CTL_MASK_SFT (0x1 << 26)468#define DL_2_OUTPUT_SEL_CTL_SFT 24469#define DL_2_OUTPUT_SEL_CTL_MASK 0x3470#define DL_2_OUTPUT_SEL_CTL_MASK_SFT (0x3 << 24)471#define DL_2_FADEIN_0START_EN_SFT 16472#define DL_2_FADEIN_0START_EN_MASK 0x3473#define DL_2_FADEIN_0START_EN_MASK_SFT (0x3 << 16)474#define DL_DISABLE_HW_CG_CTL_SFT 15475#define DL_DISABLE_HW_CG_CTL_MASK 0x1476#define DL_DISABLE_HW_CG_CTL_MASK_SFT (0x1 << 15)477#define C_DATA_EN_SEL_CTL_PRE_SFT 14478#define C_DATA_EN_SEL_CTL_PRE_MASK 0x1479#define C_DATA_EN_SEL_CTL_PRE_MASK_SFT (0x1 << 14)480#define DL_2_SIDE_TONE_ON_CTL_PRE_SFT 13481#define DL_2_SIDE_TONE_ON_CTL_PRE_MASK 0x1482#define DL_2_SIDE_TONE_ON_CTL_PRE_MASK_SFT (0x1 << 13)483#define DL_2_MUTE_CH1_OFF_CTL_PRE_SFT 12484#define DL_2_MUTE_CH1_OFF_CTL_PRE_MASK 0x1485#define DL_2_MUTE_CH1_OFF_CTL_PRE_MASK_SFT (0x1 << 12)486#define DL_2_MUTE_CH2_OFF_CTL_PRE_SFT 11487#define DL_2_MUTE_CH2_OFF_CTL_PRE_MASK 0x1488#define DL_2_MUTE_CH2_OFF_CTL_PRE_MASK_SFT (0x1 << 11)489#define DL2_ARAMPSP_CTL_PRE_SFT 9490#define DL2_ARAMPSP_CTL_PRE_MASK 0x3491#define DL2_ARAMPSP_CTL_PRE_MASK_SFT (0x3 << 9)492#define DL_2_IIRMODE_CTL_PRE_SFT 6493#define DL_2_IIRMODE_CTL_PRE_MASK 0x7494#define DL_2_IIRMODE_CTL_PRE_MASK_SFT (0x7 << 6)495#define DL_2_VOICE_MODE_CTL_PRE_SFT 5496#define DL_2_VOICE_MODE_CTL_PRE_MASK 0x1497#define DL_2_VOICE_MODE_CTL_PRE_MASK_SFT (0x1 << 5)498#define D2_2_MUTE_CH1_ON_CTL_PRE_SFT 4499#define D2_2_MUTE_CH1_ON_CTL_PRE_MASK 0x1500#define D2_2_MUTE_CH1_ON_CTL_PRE_MASK_SFT (0x1 << 4)501#define D2_2_MUTE_CH2_ON_CTL_PRE_SFT 3502#define D2_2_MUTE_CH2_ON_CTL_PRE_MASK 0x1503#define D2_2_MUTE_CH2_ON_CTL_PRE_MASK_SFT (0x1 << 3)504#define DL_2_IIR_ON_CTL_PRE_SFT 2505#define DL_2_IIR_ON_CTL_PRE_MASK 0x1506#define DL_2_IIR_ON_CTL_PRE_MASK_SFT (0x1 << 2)507#define DL_2_GAIN_ON_CTL_PRE_SFT 1508#define DL_2_GAIN_ON_CTL_PRE_MASK 0x1509#define DL_2_GAIN_ON_CTL_PRE_MASK_SFT (0x1 << 1)510#define DL_2_SRC_ON_TMP_CTL_PRE_SFT 0511#define DL_2_SRC_ON_TMP_CTL_PRE_MASK 0x1512#define DL_2_SRC_ON_TMP_CTL_PRE_MASK_SFT (0x1 << 0)513 514/* AFE_ADDA_DL_SRC2_CON1 */515#define DL_2_GAIN_CTL_PRE_SFT 16516#define DL_2_GAIN_CTL_PRE_MASK 0xffff517#define DL_2_GAIN_CTL_PRE_MASK_SFT (0xffff << 16)518#define DL_2_GAIN_MODE_CTL_SFT 0519#define DL_2_GAIN_MODE_CTL_MASK 0x1520#define DL_2_GAIN_MODE_CTL_MASK_SFT (0x1 << 0)521 522/* AFE_ADDA_UL_SRC_CON0 */523#define C_COMB_OUT_SIN_GEN_CTL_SFT 31524#define C_COMB_OUT_SIN_GEN_CTL_MASK 0x1525#define C_COMB_OUT_SIN_GEN_CTL_MASK_SFT (0x1 << 31)526#define C_BASEBAND_SIN_GEN_CTL_SFT 30527#define C_BASEBAND_SIN_GEN_CTL_MASK 0x1528#define C_BASEBAND_SIN_GEN_CTL_MASK_SFT (0x1 << 30)529#define C_DIGMIC_PHASE_SEL_CH1_CTL_SFT 27530#define C_DIGMIC_PHASE_SEL_CH1_CTL_MASK 0x7531#define C_DIGMIC_PHASE_SEL_CH1_CTL_MASK_SFT (0x7 << 27)532#define C_DIGMIC_PHASE_SEL_CH2_CTL_SFT 24533#define C_DIGMIC_PHASE_SEL_CH2_CTL_MASK 0x7534#define C_DIGMIC_PHASE_SEL_CH2_CTL_MASK_SFT (0x7 << 24)535#define C_TWO_DIGITAL_MIC_CTL_SFT 23536#define C_TWO_DIGITAL_MIC_CTL_MASK 0x1537#define C_TWO_DIGITAL_MIC_CTL_MASK_SFT (0x1 << 23)538#define UL_MODE_3P25M_CH2_CTL_SFT 22539#define UL_MODE_3P25M_CH2_CTL_MASK 0x1540#define UL_MODE_3P25M_CH2_CTL_MASK_SFT (0x1 << 22)541#define UL_MODE_3P25M_CH1_CTL_SFT 21542#define UL_MODE_3P25M_CH1_CTL_MASK 0x1543#define UL_MODE_3P25M_CH1_CTL_MASK_SFT (0x1 << 21)544#define UL_SRC_USE_CIC_OUT_CTL_SFT 20545#define UL_SRC_USE_CIC_OUT_CTL_MASK 0x1546#define UL_SRC_USE_CIC_OUT_CTL_MASK_SFT (0x1 << 20)547#define UL_VOICE_MODE_CH1_CH2_CTL_SFT 17548#define UL_VOICE_MODE_CH1_CH2_CTL_MASK 0x7549#define UL_VOICE_MODE_CH1_CH2_CTL_MASK_SFT (0x7 << 17)550#define DMIC_LOW_POWER_MODE_CTL_SFT 14551#define DMIC_LOW_POWER_MODE_CTL_MASK 0x3552#define DMIC_LOW_POWER_MODE_CTL_MASK_SFT (0x3 << 14)553#define DMIC_48K_SEL_CTL_SFT 13554#define DMIC_48K_SEL_CTL_MASK 0x1555#define DMIC_48K_SEL_CTL_MASK_SFT (0x1 << 13)556#define UL_DISABLE_HW_CG_CTL_SFT 12557#define UL_DISABLE_HW_CG_CTL_MASK 0x1558#define UL_DISABLE_HW_CG_CTL_MASK_SFT (0x1 << 12)559#define UL_IIR_ON_TMP_CTL_SFT 10560#define UL_IIR_ON_TMP_CTL_MASK 0x1561#define UL_IIR_ON_TMP_CTL_MASK_SFT (0x1 << 10)562#define UL_IIRMODE_CTL_SFT 7563#define UL_IIRMODE_CTL_MASK 0x7564#define UL_IIRMODE_CTL_MASK_SFT (0x7 << 7)565#define DIGMIC_3P25M_1P625M_SEL_CTL_SFT 5566#define DIGMIC_3P25M_1P625M_SEL_CTL_MASK 0x1567#define DIGMIC_3P25M_1P625M_SEL_CTL_MASK_SFT (0x1 << 5)568#define AGC_260K_SEL_CH2_CTL_SFT 4569#define AGC_260K_SEL_CH2_CTL_MASK 0x1570#define AGC_260K_SEL_CH2_CTL_MASK_SFT (0x1 << 4)571#define AGC_260K_SEL_CH1_CTL_SFT 3572#define AGC_260K_SEL_CH1_CTL_MASK 0x1573#define AGC_260K_SEL_CH1_CTL_MASK_SFT (0x1 << 3)574#define UL_LOOP_BACK_MODE_CTL_SFT 2575#define UL_LOOP_BACK_MODE_CTL_MASK 0x1576#define UL_LOOP_BACK_MODE_CTL_MASK_SFT (0x1 << 2)577#define UL_SDM_3_LEVEL_CTL_SFT 1578#define UL_SDM_3_LEVEL_CTL_MASK 0x1579#define UL_SDM_3_LEVEL_CTL_MASK_SFT (0x1 << 1)580#define UL_SRC_ON_TMP_CTL_SFT 0581#define UL_SRC_ON_TMP_CTL_MASK 0x1582#define UL_SRC_ON_TMP_CTL_MASK_SFT (0x1 << 0)583 584/* AFE_ADDA_UL_SRC_CON1 */585#define C_SDM_RESET_CTL_SFT 31586#define C_SDM_RESET_CTL_MASK 0x1587#define C_SDM_RESET_CTL_MASK_SFT (0x1 << 31)588#define ADITHON_CTL_SFT 30589#define ADITHON_CTL_MASK 0x1590#define ADITHON_CTL_MASK_SFT (0x1 << 30)591#define ADITHVAL_CTL_SFT 28592#define ADITHVAL_CTL_MASK 0x3593#define ADITHVAL_CTL_MASK_SFT (0x3 << 28)594#define C_DAC_EN_CTL_SFT 27595#define C_DAC_EN_CTL_MASK 0x1596#define C_DAC_EN_CTL_MASK_SFT (0x1 << 27)597#define C_MUTE_SW_CTL_SFT 26598#define C_MUTE_SW_CTL_MASK 0x1599#define C_MUTE_SW_CTL_MASK_SFT (0x1 << 26)600#define ASDM_SRC_SEL_CTL_SFT 25601#define ASDM_SRC_SEL_CTL_MASK 0x1602#define ASDM_SRC_SEL_CTL_MASK_SFT (0x1 << 25)603#define C_AMP_DIV_CH2_CTL_SFT 21604#define C_AMP_DIV_CH2_CTL_MASK 0x7605#define C_AMP_DIV_CH2_CTL_MASK_SFT (0x7 << 21)606#define C_FREQ_DIV_CH2_CTL_SFT 16607#define C_FREQ_DIV_CH2_CTL_MASK 0x1f608#define C_FREQ_DIV_CH2_CTL_MASK_SFT (0x1f << 16)609#define C_SINE_MODE_CH2_CTL_SFT 12610#define C_SINE_MODE_CH2_CTL_MASK 0xf611#define C_SINE_MODE_CH2_CTL_MASK_SFT (0xf << 12)612#define C_AMP_DIV_CH1_CTL_SFT 9613#define C_AMP_DIV_CH1_CTL_MASK 0x7614#define C_AMP_DIV_CH1_CTL_MASK_SFT (0x7 << 9)615#define C_FREQ_DIV_CH1_CTL_SFT 4616#define C_FREQ_DIV_CH1_CTL_MASK 0x1f617#define C_FREQ_DIV_CH1_CTL_MASK_SFT (0x1f << 4)618#define C_SINE_MODE_CH1_CTL_SFT 0619#define C_SINE_MODE_CH1_CTL_MASK 0xf620#define C_SINE_MODE_CH1_CTL_MASK_SFT (0xf << 0)621 622/* AFE_ADDA_TOP_CON0 */623#define C_LOOP_BACK_MODE_CTL_SFT 12624#define C_LOOP_BACK_MODE_CTL_MASK 0xf625#define C_LOOP_BACK_MODE_CTL_MASK_SFT (0xf << 12)626#define C_EXT_ADC_CTL_SFT 0627#define C_EXT_ADC_CTL_MASK 0x1628#define C_EXT_ADC_CTL_MASK_SFT (0x1 << 0)629 630/* AFE_ADDA_UL_DL_CON0 */631#define AFE_UL_DL_CON0_RESERVED_SFT 1632#define AFE_UL_DL_CON0_RESERVED_MASK 0x3fff633#define AFE_UL_DL_CON0_RESERVED_MASK_SFT (0x3fff << 1)634#define ADDA_AFE_ON_SFT 0635#define ADDA_AFE_ON_MASK 0x1636#define ADDA_AFE_ON_MASK_SFT (0x1 << 0)637 638/* AFE_IRQ_MCU_CON */639#define IRQ7_MCU_MODE_SFT 24640#define IRQ7_MCU_MODE_MASK 0xf641#define IRQ7_MCU_MODE_MASK_SFT (0xf << 24)642#define IRQ4_MCU_MODE_SFT 20643#define IRQ4_MCU_MODE_MASK 0xf644#define IRQ4_MCU_MODE_MASK_SFT (0xf << 20)645#define IRQ3_MCU_MODE_SFT 16646#define IRQ3_MCU_MODE_MASK 0xf647#define IRQ3_MCU_MODE_MASK_SFT (0xf << 16)648#define IRQ7_MCU_ON_SFT 14649#define IRQ7_MCU_ON_MASK 0x1650#define IRQ7_MCU_ON_MASK_SFT (0x1 << 14)651#define IRQ5_MCU_ON_SFT 12652#define IRQ5_MCU_ON_MASK 0x1653#define IRQ5_MCU_ON_MASK_SFT (0x1 << 12)654#define IRQ2_MCU_MODE_SFT 8655#define IRQ2_MCU_MODE_MASK 0xf656#define IRQ2_MCU_MODE_MASK_SFT (0xf << 8)657#define IRQ1_MCU_MODE_SFT 4658#define IRQ1_MCU_MODE_MASK 0xf659#define IRQ1_MCU_MODE_MASK_SFT (0xf << 4)660#define IRQ4_MCU_ON_SFT 3661#define IRQ4_MCU_ON_MASK 0x1662#define IRQ4_MCU_ON_MASK_SFT (0x1 << 3)663#define IRQ3_MCU_ON_SFT 2664#define IRQ3_MCU_ON_MASK 0x1665#define IRQ3_MCU_ON_MASK_SFT (0x1 << 2)666#define IRQ2_MCU_ON_SFT 1667#define IRQ2_MCU_ON_MASK 0x1668#define IRQ2_MCU_ON_MASK_SFT (0x1 << 1)669#define IRQ1_MCU_ON_SFT 0670#define IRQ1_MCU_ON_MASK 0x1671#define IRQ1_MCU_ON_MASK_SFT (0x1 << 0)672 673/* AFE_IRQ_MCU_EN */674#define AFE_IRQ_CM4_EN_SFT 16675#define AFE_IRQ_CM4_EN_MASK 0x7f676#define AFE_IRQ_CM4_EN_MASK_SFT (0x7f << 16)677#define AFE_IRQ_MD32_EN_SFT 8678#define AFE_IRQ_MD32_EN_MASK 0x7f679#define AFE_IRQ_MD32_EN_MASK_SFT (0x7f << 8)680#define AFE_IRQ_MCU_EN_SFT 0681#define AFE_IRQ_MCU_EN_MASK 0x7f682#define AFE_IRQ_MCU_EN_MASK_SFT (0x7f << 0)683 684/* AFE_IRQ_MCU_CLR */685#define IRQ7_MCU_CLR_SFT 6686#define IRQ7_MCU_CLR_MASK 0x1687#define IRQ7_MCU_CLR_MASK_SFT (0x1 << 6)688#define IRQ5_MCU_CLR_SFT 4689#define IRQ5_MCU_CLR_MASK 0x1690#define IRQ5_MCU_CLR_MASK_SFT (0x1 << 4)691#define IRQ4_MCU_CLR_SFT 3692#define IRQ4_MCU_CLR_MASK 0x1693#define IRQ4_MCU_CLR_MASK_SFT (0x1 << 3)694#define IRQ3_MCU_CLR_SFT 2695#define IRQ3_MCU_CLR_MASK 0x1696#define IRQ3_MCU_CLR_MASK_SFT (0x1 << 2)697#define IRQ2_MCU_CLR_SFT 1698#define IRQ2_MCU_CLR_MASK 0x1699#define IRQ2_MCU_CLR_MASK_SFT (0x1 << 1)700#define IRQ1_MCU_CLR_SFT 0701#define IRQ1_MCU_CLR_MASK 0x1702#define IRQ1_MCU_CLR_MASK_SFT (0x1 << 0)703 704/* AFE_IRQ_MCU_CNT1 */705#define AFE_IRQ_MCU_CNT1_SFT 0706#define AFE_IRQ_MCU_CNT1_MASK 0x3ffff707#define AFE_IRQ_MCU_CNT1_MASK_SFT (0x3ffff << 0)708 709/* AFE_IRQ_MCU_CNT2 */710#define AFE_IRQ_MCU_CNT2_SFT 0711#define AFE_IRQ_MCU_CNT2_MASK 0x3ffff712#define AFE_IRQ_MCU_CNT2_MASK_SFT (0x3ffff << 0)713 714/* AFE_IRQ_MCU_CNT3 */715#define AFE_IRQ_MCU_CNT3_SFT 0716#define AFE_IRQ_MCU_CNT3_MASK 0x3ffff717#define AFE_IRQ_MCU_CNT3_MASK_SFT (0x3ffff << 0)718 719/* AFE_IRQ_MCU_CNT4 */720#define AFE_IRQ_MCU_CNT4_SFT 0721#define AFE_IRQ_MCU_CNT4_MASK 0x3ffff722#define AFE_IRQ_MCU_CNT4_MASK_SFT (0x3ffff << 0)723 724/* AFE_IRQ_MCU_CNT5 */725#define AFE_IRQ_MCU_CNT5_SFT 0726#define AFE_IRQ_MCU_CNT5_MASK 0x3ffff727#define AFE_IRQ_MCU_CNT5_MASK_SFT (0x3ffff << 0)728 729/* AFE_IRQ_MCU_CNT7 */730#define AFE_IRQ_MCU_CNT7_SFT 0731#define AFE_IRQ_MCU_CNT7_MASK 0x3ffff732#define AFE_IRQ_MCU_CNT7_MASK_SFT (0x3ffff << 0)733 734/* AFE_MEMIF_MSB */735#define CPU_COMPACT_MODE_SFT 23736#define CPU_COMPACT_MODE_MASK 0x1737#define CPU_COMPACT_MODE_MASK_SFT (0x1 << 23)738#define CPU_HD_ALIGN_SFT 22739#define CPU_HD_ALIGN_MASK 0x1740#define CPU_HD_ALIGN_MASK_SFT (0x1 << 22)741 742/* AFE_MEMIF_HD_MODE */743#define HDMI_HD_SFT 20744#define HDMI_HD_MASK 0x3745#define HDMI_HD_MASK_SFT (0x3 << 20)746#define MOD_DAI_HD_SFT 18747#define MOD_DAI_HD_MASK 0x3748#define MOD_DAI_HD_MASK_SFT (0x3 << 18)749#define DAI_HD_SFT 16750#define DAI_HD_MASK 0x3751#define DAI_HD_MASK_SFT (0x3 << 16)752#define VUL_DATA2_HD_SFT 12753#define VUL_DATA2_HD_MASK 0x3754#define VUL_DATA2_HD_MASK_SFT (0x3 << 12)755#define VUL_HD_SFT 10756#define VUL_HD_MASK 0x3757#define VUL_HD_MASK_SFT (0x3 << 10)758#define AWB_HD_SFT 8759#define AWB_HD_MASK 0x3760#define AWB_HD_MASK_SFT (0x3 << 8)761#define DL3_HD_SFT 6762#define DL3_HD_MASK 0x3763#define DL3_HD_MASK_SFT (0x3 << 6)764#define DL2_HD_SFT 4765#define DL2_HD_MASK 0x3766#define DL2_HD_MASK_SFT (0x3 << 4)767#define DL1_DATA2_HD_SFT 2768#define DL1_DATA2_HD_MASK 0x3769#define DL1_DATA2_HD_MASK_SFT (0x3 << 2)770#define DL1_HD_SFT 0771#define DL1_HD_MASK 0x3772#define DL1_HD_MASK_SFT (0x3 << 0)773 774/* AFE_MEMIF_HDALIGN */775#define HDMI_NORMAL_MODE_SFT 26776#define HDMI_NORMAL_MODE_MASK 0x1777#define HDMI_NORMAL_MODE_MASK_SFT (0x1 << 26)778#define MOD_DAI_NORMAL_MODE_SFT 25779#define MOD_DAI_NORMAL_MODE_MASK 0x1780#define MOD_DAI_NORMAL_MODE_MASK_SFT (0x1 << 25)781#define DAI_NORMAL_MODE_SFT 24782#define DAI_NORMAL_MODE_MASK 0x1783#define DAI_NORMAL_MODE_MASK_SFT (0x1 << 24)784#define VUL_DATA2_NORMAL_MODE_SFT 22785#define VUL_DATA2_NORMAL_MODE_MASK 0x1786#define VUL_DATA2_NORMAL_MODE_MASK_SFT (0x1 << 22)787#define VUL_NORMAL_MODE_SFT 21788#define VUL_NORMAL_MODE_MASK 0x1789#define VUL_NORMAL_MODE_MASK_SFT (0x1 << 21)790#define AWB_NORMAL_MODE_SFT 20791#define AWB_NORMAL_MODE_MASK 0x1792#define AWB_NORMAL_MODE_MASK_SFT (0x1 << 20)793#define DL3_NORMAL_MODE_SFT 19794#define DL3_NORMAL_MODE_MASK 0x1795#define DL3_NORMAL_MODE_MASK_SFT (0x1 << 19)796#define DL2_NORMAL_MODE_SFT 18797#define DL2_NORMAL_MODE_MASK 0x1798#define DL2_NORMAL_MODE_MASK_SFT (0x1 << 18)799#define DL1_DATA2_NORMAL_MODE_SFT 17800#define DL1_DATA2_NORMAL_MODE_MASK 0x1801#define DL1_DATA2_NORMAL_MODE_MASK_SFT (0x1 << 17)802#define DL1_NORMAL_MODE_SFT 16803#define DL1_NORMAL_MODE_MASK 0x1804#define DL1_NORMAL_MODE_MASK_SFT (0x1 << 16)805#define HDMI_HD_ALIGN_SFT 10806#define HDMI_HD_ALIGN_MASK 0x1807#define HDMI_HD_ALIGN_MASK_SFT (0x1 << 10)808#define MOD_DAI_HD_ALIGN_SFT 9809#define MOD_DAI_HD_ALIGN_MASK 0x1810#define MOD_DAI_HD_ALIGN_MASK_SFT (0x1 << 9)811#define DAI_ALIGN_SFT 8812#define DAI_ALIGN_MASK 0x1813#define DAI_ALIGN_MASK_SFT (0x1 << 8)814#define VUL2_HD_ALIGN_SFT 7815#define VUL2_HD_ALIGN_MASK 0x1816#define VUL2_HD_ALIGN_MASK_SFT (0x1 << 7)817#define VUL_DATA2_HD_ALIGN_SFT 6818#define VUL_DATA2_HD_ALIGN_MASK 0x1819#define VUL_DATA2_HD_ALIGN_MASK_SFT (0x1 << 6)820#define VUL_HD_ALIGN_SFT 5821#define VUL_HD_ALIGN_MASK 0x1822#define VUL_HD_ALIGN_MASK_SFT (0x1 << 5)823#define AWB_HD_ALIGN_SFT 4824#define AWB_HD_ALIGN_MASK 0x1825#define AWB_HD_ALIGN_MASK_SFT (0x1 << 4)826#define DL3_HD_ALIGN_SFT 3827#define DL3_HD_ALIGN_MASK 0x1828#define DL3_HD_ALIGN_MASK_SFT (0x1 << 3)829#define DL2_HD_ALIGN_SFT 2830#define DL2_HD_ALIGN_MASK 0x1831#define DL2_HD_ALIGN_MASK_SFT (0x1 << 2)832#define DL1_DATA2_HD_ALIGN_SFT 1833#define DL1_DATA2_HD_ALIGN_MASK 0x1834#define DL1_DATA2_HD_ALIGN_MASK_SFT (0x1 << 1)835#define DL1_HD_ALIGN_SFT 0836#define DL1_HD_ALIGN_MASK 0x1837#define DL1_HD_ALIGN_MASK_SFT (0x1 << 0)838 839/* PCM_INTF_CON1 */840#define PCM_FIX_VALUE_SEL_SFT 31841#define PCM_FIX_VALUE_SEL_MASK 0x1842#define PCM_FIX_VALUE_SEL_MASK_SFT (0x1 << 31)843#define PCM_BUFFER_LOOPBACK_SFT 30844#define PCM_BUFFER_LOOPBACK_MASK 0x1845#define PCM_BUFFER_LOOPBACK_MASK_SFT (0x1 << 30)846#define PCM_PARALLEL_LOOPBACK_SFT 29847#define PCM_PARALLEL_LOOPBACK_MASK 0x1848#define PCM_PARALLEL_LOOPBACK_MASK_SFT (0x1 << 29)849#define PCM_SERIAL_LOOPBACK_SFT 28850#define PCM_SERIAL_LOOPBACK_MASK 0x1851#define PCM_SERIAL_LOOPBACK_MASK_SFT (0x1 << 28)852#define PCM_DAI_PCM_LOOPBACK_SFT 27853#define PCM_DAI_PCM_LOOPBACK_MASK 0x1854#define PCM_DAI_PCM_LOOPBACK_MASK_SFT (0x1 << 27)855#define PCM_I2S_PCM_LOOPBACK_SFT 26856#define PCM_I2S_PCM_LOOPBACK_MASK 0x1857#define PCM_I2S_PCM_LOOPBACK_MASK_SFT (0x1 << 26)858#define PCM_SYNC_DELSEL_SFT 25859#define PCM_SYNC_DELSEL_MASK 0x1860#define PCM_SYNC_DELSEL_MASK_SFT (0x1 << 25)861#define PCM_TX_LR_SWAP_SFT 24862#define PCM_TX_LR_SWAP_MASK 0x1863#define PCM_TX_LR_SWAP_MASK_SFT (0x1 << 24)864#define PCM_SYNC_OUT_INV_SFT 23865#define PCM_SYNC_OUT_INV_MASK 0x1866#define PCM_SYNC_OUT_INV_MASK_SFT (0x1 << 23)867#define PCM_BCLK_OUT_INV_SFT 22868#define PCM_BCLK_OUT_INV_MASK 0x1869#define PCM_BCLK_OUT_INV_MASK_SFT (0x1 << 22)870#define PCM_SYNC_IN_INV_SFT 21871#define PCM_SYNC_IN_INV_MASK 0x1872#define PCM_SYNC_IN_INV_MASK_SFT (0x1 << 21)873#define PCM_BCLK_IN_INV_SFT 20874#define PCM_BCLK_IN_INV_MASK 0x1875#define PCM_BCLK_IN_INV_MASK_SFT (0x1 << 20)876#define PCM_TX_LCH_RPT_SFT 19877#define PCM_TX_LCH_RPT_MASK 0x1878#define PCM_TX_LCH_RPT_MASK_SFT (0x1 << 19)879#define PCM_VBT_16K_MODE_SFT 18880#define PCM_VBT_16K_MODE_MASK 0x1881#define PCM_VBT_16K_MODE_MASK_SFT (0x1 << 18)882#define PCM_EXT_MODEM_SFT 17883#define PCM_EXT_MODEM_MASK 0x1884#define PCM_EXT_MODEM_MASK_SFT (0x1 << 17)885#define PCM_24BIT_SFT 16886#define PCM_24BIT_MASK 0x1887#define PCM_24BIT_MASK_SFT (0x1 << 16)888#define PCM_WLEN_SFT 14889#define PCM_WLEN_MASK 0x3890#define PCM_WLEN_MASK_SFT (0x3 << 14)891#define PCM_SYNC_LENGTH_SFT 9892#define PCM_SYNC_LENGTH_MASK 0x1f893#define PCM_SYNC_LENGTH_MASK_SFT (0x1f << 9)894#define PCM_SYNC_TYPE_SFT 8895#define PCM_SYNC_TYPE_MASK 0x1896#define PCM_SYNC_TYPE_MASK_SFT (0x1 << 8)897#define PCM_BT_MODE_SFT 7898#define PCM_BT_MODE_MASK 0x1899#define PCM_BT_MODE_MASK_SFT (0x1 << 7)900#define PCM_BYP_ASRC_SFT 6901#define PCM_BYP_ASRC_MASK 0x1902#define PCM_BYP_ASRC_MASK_SFT (0x1 << 6)903#define PCM_SLAVE_SFT 5904#define PCM_SLAVE_MASK 0x1905#define PCM_SLAVE_MASK_SFT (0x1 << 5)906#define PCM_MODE_SFT 3907#define PCM_MODE_MASK 0x3908#define PCM_MODE_MASK_SFT (0x3 << 3)909#define PCM_FMT_SFT 1910#define PCM_FMT_MASK 0x3911#define PCM_FMT_MASK_SFT (0x3 << 1)912#define PCM_EN_SFT 0913#define PCM_EN_MASK 0x1914#define PCM_EN_MASK_SFT (0x1 << 0)915 916/* PCM_INTF_CON2 */917#define PCM1_TX_FIFO_OV_SFT 31918#define PCM1_TX_FIFO_OV_MASK 0x1919#define PCM1_TX_FIFO_OV_MASK_SFT (0x1 << 31)920#define PCM1_RX_FIFO_OV_SFT 30921#define PCM1_RX_FIFO_OV_MASK 0x1922#define PCM1_RX_FIFO_OV_MASK_SFT (0x1 << 30)923#define PCM2_TX_FIFO_OV_SFT 29924#define PCM2_TX_FIFO_OV_MASK 0x1925#define PCM2_TX_FIFO_OV_MASK_SFT (0x1 << 29)926#define PCM2_RX_FIFO_OV_SFT 28927#define PCM2_RX_FIFO_OV_MASK 0x1928#define PCM2_RX_FIFO_OV_MASK_SFT (0x1 << 28)929#define PCM1_SYNC_GLITCH_SFT 27930#define PCM1_SYNC_GLITCH_MASK 0x1931#define PCM1_SYNC_GLITCH_MASK_SFT (0x1 << 27)932#define PCM2_SYNC_GLITCH_SFT 26933#define PCM2_SYNC_GLITCH_MASK 0x1934#define PCM2_SYNC_GLITCH_MASK_SFT (0x1 << 26)935#define PCM1_PCM2_LOOPBACK_SFT 15936#define PCM1_PCM2_LOOPBACK_MASK 0x1937#define PCM1_PCM2_LOOPBACK_MASK_SFT (0x1 << 15)938#define DAI_PCM_LOOPBACK_CH_SFT 13939#define DAI_PCM_LOOPBACK_CH_MASK 0x1940#define DAI_PCM_LOOPBACK_CH_MASK_SFT (0x1 << 13)941#define I2S_PCM_LOOPBACK_CH_SFT 12942#define I2S_PCM_LOOPBACK_CH_MASK 0x1943#define I2S_PCM_LOOPBACK_CH_MASK_SFT (0x1 << 12)944#define PCM_USE_MD3_SFT 8945#define PCM_USE_MD3_MASK 0x1946#define PCM_USE_MD3_MASK_SFT (0x1 << 8)947#define TX_FIX_VALUE_SFT 0948#define TX_FIX_VALUE_MASK 0xff949#define TX_FIX_VALUE_MASK_SFT (0xff << 0)950 951/* PCM2_INTF_CON */952#define PCM2_TX_FIX_VALUE_SFT 24953#define PCM2_TX_FIX_VALUE_MASK 0xff954#define PCM2_TX_FIX_VALUE_MASK_SFT (0xff << 24)955#define PCM2_FIX_VALUE_SEL_SFT 23956#define PCM2_FIX_VALUE_SEL_MASK 0x1957#define PCM2_FIX_VALUE_SEL_MASK_SFT (0x1 << 23)958#define PCM2_BUFFER_LOOPBACK_SFT 22959#define PCM2_BUFFER_LOOPBACK_MASK 0x1960#define PCM2_BUFFER_LOOPBACK_MASK_SFT (0x1 << 22)961#define PCM2_PARALLEL_LOOPBACK_SFT 21962#define PCM2_PARALLEL_LOOPBACK_MASK 0x1963#define PCM2_PARALLEL_LOOPBACK_MASK_SFT (0x1 << 21)964#define PCM2_SERIAL_LOOPBACK_SFT 20965#define PCM2_SERIAL_LOOPBACK_MASK 0x1966#define PCM2_SERIAL_LOOPBACK_MASK_SFT (0x1 << 20)967#define PCM2_DAI_PCM_LOOPBACK_SFT 19968#define PCM2_DAI_PCM_LOOPBACK_MASK 0x1969#define PCM2_DAI_PCM_LOOPBACK_MASK_SFT (0x1 << 19)970#define PCM2_I2S_PCM_LOOPBACK_SFT 18971#define PCM2_I2S_PCM_LOOPBACK_MASK 0x1972#define PCM2_I2S_PCM_LOOPBACK_MASK_SFT (0x1 << 18)973#define PCM2_SYNC_DELSEL_SFT 17974#define PCM2_SYNC_DELSEL_MASK 0x1975#define PCM2_SYNC_DELSEL_MASK_SFT (0x1 << 17)976#define PCM2_TX_LR_SWAP_SFT 16977#define PCM2_TX_LR_SWAP_MASK 0x1978#define PCM2_TX_LR_SWAP_MASK_SFT (0x1 << 16)979#define PCM2_SYNC_IN_INV_SFT 15980#define PCM2_SYNC_IN_INV_MASK 0x1981#define PCM2_SYNC_IN_INV_MASK_SFT (0x1 << 15)982#define PCM2_BCLK_IN_INV_SFT 14983#define PCM2_BCLK_IN_INV_MASK 0x1984#define PCM2_BCLK_IN_INV_MASK_SFT (0x1 << 14)985#define PCM2_TX_LCH_RPT_SFT 13986#define PCM2_TX_LCH_RPT_MASK 0x1987#define PCM2_TX_LCH_RPT_MASK_SFT (0x1 << 13)988#define PCM2_VBT_16K_MODE_SFT 12989#define PCM2_VBT_16K_MODE_MASK 0x1990#define PCM2_VBT_16K_MODE_MASK_SFT (0x1 << 12)991#define PCM2_LOOPBACK_CH_SEL_SFT 10992#define PCM2_LOOPBACK_CH_SEL_MASK 0x3993#define PCM2_LOOPBACK_CH_SEL_MASK_SFT (0x3 << 10)994#define PCM2_TX2_BT_MODE_SFT 8995#define PCM2_TX2_BT_MODE_MASK 0x1996#define PCM2_TX2_BT_MODE_MASK_SFT (0x1 << 8)997#define PCM2_BT_MODE_SFT 7998#define PCM2_BT_MODE_MASK 0x1999#define PCM2_BT_MODE_MASK_SFT (0x1 << 7)1000#define PCM2_AFIFO_SFT 61001#define PCM2_AFIFO_MASK 0x11002#define PCM2_AFIFO_MASK_SFT (0x1 << 6)1003#define PCM2_WLEN_SFT 51004#define PCM2_WLEN_MASK 0x11005#define PCM2_WLEN_MASK_SFT (0x1 << 5)1006#define PCM2_MODE_SFT 31007#define PCM2_MODE_MASK 0x31008#define PCM2_MODE_MASK_SFT (0x3 << 3)1009#define PCM2_FMT_SFT 11010#define PCM2_FMT_MASK 0x31011#define PCM2_FMT_MASK_SFT (0x3 << 1)1012#define PCM2_EN_SFT 01013#define PCM2_EN_MASK 0x11014#define PCM2_EN_MASK_SFT (0x1 << 0)1015#endif1016