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1/* SPDX-License-Identifier: GPL-2.0 */2/*3 * mt8183-reg.h -- Mediatek 8183 audio driver reg definition4 *5 * Copyright (c) 2018 MediaTek Inc.6 * Author: KaiChieh Chuang <kaichieh.chuang@mediatek.com>7 */8 9#ifndef _MT8183_REG_H_10#define _MT8183_REG_H_11 12#define AUDIO_TOP_CON0 0x000013#define AUDIO_TOP_CON1 0x000414#define AUDIO_TOP_CON3 0x000c15#define AFE_DAC_CON0 0x001016#define AFE_DAC_CON1 0x001417#define AFE_I2S_CON 0x001818#define AFE_DAIBT_CON0 0x001c19#define AFE_CONN0 0x002020#define AFE_CONN1 0x002421#define AFE_CONN2 0x002822#define AFE_CONN3 0x002c23#define AFE_CONN4 0x003024#define AFE_I2S_CON1 0x003425#define AFE_I2S_CON2 0x003826#define AFE_MRGIF_CON 0x003c27#define AFE_DL1_BASE 0x004028#define AFE_DL1_CUR 0x004429#define AFE_DL1_END 0x004830#define AFE_I2S_CON3 0x004c31#define AFE_DL2_BASE 0x005032#define AFE_DL2_CUR 0x005433#define AFE_DL2_END 0x005834#define AFE_CONN5 0x005c35#define AFE_CONN_24BIT 0x006c36#define AFE_AWB_BASE 0x007037#define AFE_AWB_END 0x007838#define AFE_AWB_CUR 0x007c39#define AFE_VUL_BASE 0x008040#define AFE_VUL_END 0x008841#define AFE_VUL_CUR 0x008c42#define AFE_CONN6 0x00bc43#define AFE_MEMIF_MSB 0x00cc44#define AFE_MEMIF_MON0 0x00d045#define AFE_MEMIF_MON1 0x00d446#define AFE_MEMIF_MON2 0x00d847#define AFE_MEMIF_MON3 0x00dc48#define AFE_MEMIF_MON4 0x00e049#define AFE_MEMIF_MON5 0x00e450#define AFE_MEMIF_MON6 0x00e851#define AFE_MEMIF_MON7 0x00ec52#define AFE_MEMIF_MON8 0x00f053#define AFE_MEMIF_MON9 0x00f454#define AFE_ADDA_DL_SRC2_CON0 0x010855#define AFE_ADDA_DL_SRC2_CON1 0x010c56#define AFE_ADDA_UL_SRC_CON0 0x011457#define AFE_ADDA_UL_SRC_CON1 0x011858#define AFE_ADDA_TOP_CON0 0x012059#define AFE_ADDA_UL_DL_CON0 0x012460#define AFE_ADDA_SRC_DEBUG 0x012c61#define AFE_ADDA_SRC_DEBUG_MON0 0x013062#define AFE_ADDA_SRC_DEBUG_MON1 0x013463#define AFE_ADDA_UL_SRC_MON0 0x014864#define AFE_ADDA_UL_SRC_MON1 0x014c65#define AFE_SIDETONE_DEBUG 0x01d066#define AFE_SIDETONE_MON 0x01d467#define AFE_SINEGEN_CON2 0x01dc68#define AFE_SIDETONE_CON0 0x01e069#define AFE_SIDETONE_COEFF 0x01e470#define AFE_SIDETONE_CON1 0x01e871#define AFE_SIDETONE_GAIN 0x01ec72#define AFE_SINEGEN_CON0 0x01f073#define AFE_TOP_CON0 0x020074#define AFE_BUS_CFG 0x024075#define AFE_BUS_MON0 0x024476#define AFE_ADDA_PREDIS_CON0 0x026077#define AFE_ADDA_PREDIS_CON1 0x026478#define AFE_MRGIF_MON0 0x027079#define AFE_MRGIF_MON1 0x027480#define AFE_MRGIF_MON2 0x027881#define AFE_I2S_MON 0x027c82#define AFE_ADDA_IIR_COEF_02_01 0x029083#define AFE_ADDA_IIR_COEF_04_03 0x029484#define AFE_ADDA_IIR_COEF_06_05 0x029885#define AFE_ADDA_IIR_COEF_08_07 0x029c86#define AFE_ADDA_IIR_COEF_10_09 0x02a087#define AFE_DAC_CON2 0x02e088#define AFE_IRQ_MCU_CON1 0x02e489#define AFE_IRQ_MCU_CON2 0x02e890#define AFE_DAC_MON 0x02ec91#define AFE_VUL2_BASE 0x02f092#define AFE_VUL2_END 0x02f893#define AFE_VUL2_CUR 0x02fc94#define AFE_IRQ_MCU_CNT0 0x030095#define AFE_IRQ_MCU_CNT6 0x030496#define AFE_IRQ_MCU_CNT8 0x030897#define AFE_IRQ_MCU_EN1 0x030c98#define AFE_IRQ0_MCU_CNT_MON 0x031099#define AFE_IRQ6_MCU_CNT_MON 0x0314100#define AFE_MOD_DAI_BASE 0x0330101#define AFE_MOD_DAI_END 0x0338102#define AFE_MOD_DAI_CUR 0x033c103#define AFE_VUL_D2_BASE 0x0350104#define AFE_VUL_D2_END 0x0358105#define AFE_VUL_D2_CUR 0x035c106#define AFE_DL3_BASE 0x0360107#define AFE_DL3_CUR 0x0364108#define AFE_DL3_END 0x0368109#define AFE_HDMI_OUT_CON0 0x0370110#define AFE_HDMI_OUT_BASE 0x0374111#define AFE_HDMI_OUT_CUR 0x0378112#define AFE_HDMI_OUT_END 0x037c113#define AFE_HDMI_CONN0 0x0390114#define AFE_IRQ3_MCU_CNT_MON 0x0398115#define AFE_IRQ4_MCU_CNT_MON 0x039c116#define AFE_IRQ_MCU_CON0 0x03a0117#define AFE_IRQ_MCU_STATUS 0x03a4118#define AFE_IRQ_MCU_CLR 0x03a8119#define AFE_IRQ_MCU_CNT1 0x03ac120#define AFE_IRQ_MCU_CNT2 0x03b0121#define AFE_IRQ_MCU_EN 0x03b4122#define AFE_IRQ_MCU_MON2 0x03b8123#define AFE_IRQ_MCU_CNT5 0x03bc124#define AFE_IRQ1_MCU_CNT_MON 0x03c0125#define AFE_IRQ2_MCU_CNT_MON 0x03c4126#define AFE_IRQ1_MCU_EN_CNT_MON 0x03c8127#define AFE_IRQ5_MCU_CNT_MON 0x03cc128#define AFE_MEMIF_MINLEN 0x03d0129#define AFE_MEMIF_MAXLEN 0x03d4130#define AFE_MEMIF_PBUF_SIZE 0x03d8131#define AFE_IRQ_MCU_CNT7 0x03dc132#define AFE_IRQ7_MCU_CNT_MON 0x03e0133#define AFE_IRQ_MCU_CNT3 0x03e4134#define AFE_IRQ_MCU_CNT4 0x03e8135#define AFE_IRQ_MCU_CNT11 0x03ec136#define AFE_APLL1_TUNER_CFG 0x03f0137#define AFE_APLL2_TUNER_CFG 0x03f4138#define AFE_MEMIF_HD_MODE 0x03f8139#define AFE_MEMIF_HDALIGN 0x03fc140#define AFE_CONN33 0x0408141#define AFE_IRQ_MCU_CNT12 0x040c142#define AFE_GAIN1_CON0 0x0410143#define AFE_GAIN1_CON1 0x0414144#define AFE_GAIN1_CON2 0x0418145#define AFE_GAIN1_CON3 0x041c146#define AFE_CONN7 0x0420147#define AFE_GAIN1_CUR 0x0424148#define AFE_GAIN2_CON0 0x0428149#define AFE_GAIN2_CON1 0x042c150#define AFE_GAIN2_CON2 0x0430151#define AFE_GAIN2_CON3 0x0434152#define AFE_CONN8 0x0438153#define AFE_GAIN2_CUR 0x043c154#define AFE_CONN9 0x0440155#define AFE_CONN10 0x0444156#define AFE_CONN11 0x0448157#define AFE_CONN12 0x044c158#define AFE_CONN13 0x0450159#define AFE_CONN14 0x0454160#define AFE_CONN15 0x0458161#define AFE_CONN16 0x045c162#define AFE_CONN17 0x0460163#define AFE_CONN18 0x0464164#define AFE_CONN19 0x0468165#define AFE_CONN20 0x046c166#define AFE_CONN21 0x0470167#define AFE_CONN22 0x0474168#define AFE_CONN23 0x0478169#define AFE_CONN24 0x047c170#define AFE_CONN_RS 0x0494171#define AFE_CONN_DI 0x0498172#define AFE_CONN25 0x04b0173#define AFE_CONN26 0x04b4174#define AFE_CONN27 0x04b8175#define AFE_CONN28 0x04bc176#define AFE_CONN29 0x04c0177#define AFE_CONN30 0x04c4178#define AFE_CONN31 0x04c8179#define AFE_CONN32 0x04cc180#define AFE_SRAM_DELSEL_CON0 0x04f0181#define AFE_SRAM_DELSEL_CON2 0x04f8182#define AFE_SRAM_DELSEL_CON3 0x04fc183#define AFE_ASRC_2CH_CON12 0x0528184#define AFE_ASRC_2CH_CON13 0x052c185#define PCM_INTF_CON1 0x0530186#define PCM_INTF_CON2 0x0538187#define PCM2_INTF_CON 0x053c188#define AFE_TDM_CON1 0x0548189#define AFE_TDM_CON2 0x054c190#define AFE_CONN34 0x0580191#define FPGA_CFG0 0x05b0192#define FPGA_CFG1 0x05b4193#define FPGA_CFG2 0x05c0194#define FPGA_CFG3 0x05c4195#define AUDIO_TOP_DBG_CON 0x05c8196#define AUDIO_TOP_DBG_MON0 0x05cc197#define AUDIO_TOP_DBG_MON1 0x05d0198#define AFE_IRQ8_MCU_CNT_MON 0x05e4199#define AFE_IRQ11_MCU_CNT_MON 0x05e8200#define AFE_IRQ12_MCU_CNT_MON 0x05ec201#define AFE_GENERAL_REG0 0x0800202#define AFE_GENERAL_REG1 0x0804203#define AFE_GENERAL_REG2 0x0808204#define AFE_GENERAL_REG3 0x080c205#define AFE_GENERAL_REG4 0x0810206#define AFE_GENERAL_REG5 0x0814207#define AFE_GENERAL_REG6 0x0818208#define AFE_GENERAL_REG7 0x081c209#define AFE_GENERAL_REG8 0x0820210#define AFE_GENERAL_REG9 0x0824211#define AFE_GENERAL_REG10 0x0828212#define AFE_GENERAL_REG11 0x082c213#define AFE_GENERAL_REG12 0x0830214#define AFE_GENERAL_REG13 0x0834215#define AFE_GENERAL_REG14 0x0838216#define AFE_GENERAL_REG15 0x083c217#define AFE_CBIP_CFG0 0x0840218#define AFE_CBIP_MON0 0x0844219#define AFE_CBIP_SLV_MUX_MON0 0x0848220#define AFE_CBIP_SLV_DECODER_MON0 0x084c221#define AFE_CONN0_1 0x0900222#define AFE_CONN1_1 0x0904223#define AFE_CONN2_1 0x0908224#define AFE_CONN3_1 0x090c225#define AFE_CONN4_1 0x0910226#define AFE_CONN5_1 0x0914227#define AFE_CONN6_1 0x0918228#define AFE_CONN7_1 0x091c229#define AFE_CONN8_1 0x0920230#define AFE_CONN9_1 0x0924231#define AFE_CONN10_1 0x0928232#define AFE_CONN11_1 0x092c233#define AFE_CONN12_1 0x0930234#define AFE_CONN13_1 0x0934235#define AFE_CONN14_1 0x0938236#define AFE_CONN15_1 0x093c237#define AFE_CONN16_1 0x0940238#define AFE_CONN17_1 0x0944239#define AFE_CONN18_1 0x0948240#define AFE_CONN19_1 0x094c241#define AFE_CONN20_1 0x0950242#define AFE_CONN21_1 0x0954243#define AFE_CONN22_1 0x0958244#define AFE_CONN23_1 0x095c245#define AFE_CONN24_1 0x0960246#define AFE_CONN25_1 0x0964247#define AFE_CONN26_1 0x0968248#define AFE_CONN27_1 0x096c249#define AFE_CONN28_1 0x0970250#define AFE_CONN29_1 0x0974251#define AFE_CONN30_1 0x0978252#define AFE_CONN31_1 0x097c253#define AFE_CONN32_1 0x0980254#define AFE_CONN33_1 0x0984255#define AFE_CONN34_1 0x0988256#define AFE_CONN_RS_1 0x098c257#define AFE_CONN_DI_1 0x0990258#define AFE_CONN_24BIT_1 0x0994259#define AFE_CONN_REG 0x0998260#define AFE_CONN35 0x09a0261#define AFE_CONN36 0x09a4262#define AFE_CONN37 0x09a8263#define AFE_CONN38 0x09ac264#define AFE_CONN35_1 0x09b0265#define AFE_CONN36_1 0x09b4266#define AFE_CONN37_1 0x09b8267#define AFE_CONN38_1 0x09bc268#define AFE_CONN39 0x09c0269#define AFE_CONN40 0x09c4270#define AFE_CONN41 0x09c8271#define AFE_CONN42 0x09cc272#define AFE_CONN39_1 0x09e0273#define AFE_CONN40_1 0x09e4274#define AFE_CONN41_1 0x09e8275#define AFE_CONN42_1 0x09ec276#define AFE_I2S_CON4 0x09f8277#define AFE_ADDA6_TOP_CON0 0x0a80278#define AFE_ADDA6_UL_SRC_CON0 0x0a84279#define AFE_ADD6_UL_SRC_CON1 0x0a88280#define AFE_ADDA6_SRC_DEBUG 0x0a8c281#define AFE_ADDA6_SRC_DEBUG_MON0 0x0a90282#define AFE_ADDA6_ULCF_CFG_02_01 0x0aa0283#define AFE_ADDA6_ULCF_CFG_04_03 0x0aa4284#define AFE_ADDA6_ULCF_CFG_06_05 0x0aa8285#define AFE_ADDA6_ULCF_CFG_08_07 0x0aac286#define AFE_ADDA6_ULCF_CFG_10_09 0x0ab0287#define AFE_ADDA6_ULCF_CFG_12_11 0x0ab4288#define AFE_ADDA6_ULCF_CFG_14_13 0x0ab8289#define AFE_ADDA6_ULCF_CFG_16_15 0x0abc290#define AFE_ADDA6_ULCF_CFG_18_17 0x0ac0291#define AFE_ADDA6_ULCF_CFG_20_19 0x0ac4292#define AFE_ADDA6_ULCF_CFG_22_21 0x0ac8293#define AFE_ADDA6_ULCF_CFG_24_23 0x0acc294#define AFE_ADDA6_ULCF_CFG_26_25 0x0ad0295#define AFE_ADDA6_ULCF_CFG_28_27 0x0ad4296#define AFE_ADDA6_ULCF_CFG_30_29 0x0ad8297#define AFE_ADD6A_UL_SRC_MON0 0x0ae4298#define AFE_ADDA6_UL_SRC_MON1 0x0ae8299#define AFE_CONN43 0x0af8300#define AFE_CONN43_1 0x0afc301#define AFE_DL1_BASE_MSB 0x0b00302#define AFE_DL1_CUR_MSB 0x0b04303#define AFE_DL1_END_MSB 0x0b08304#define AFE_DL2_BASE_MSB 0x0b10305#define AFE_DL2_CUR_MSB 0x0b14306#define AFE_DL2_END_MSB 0x0b18307#define AFE_AWB_BASE_MSB 0x0b20308#define AFE_AWB_END_MSB 0x0b28309#define AFE_AWB_CUR_MSB 0x0b2c310#define AFE_VUL_BASE_MSB 0x0b30311#define AFE_VUL_END_MSB 0x0b38312#define AFE_VUL_CUR_MSB 0x0b3c313#define AFE_VUL2_BASE_MSB 0x0b50314#define AFE_VUL2_END_MSB 0x0b58315#define AFE_VUL2_CUR_MSB 0x0b5c316#define AFE_MOD_DAI_BASE_MSB 0x0b60317#define AFE_MOD_DAI_END_MSB 0x0b68318#define AFE_MOD_DAI_CUR_MSB 0x0b6c319#define AFE_VUL_D2_BASE_MSB 0x0b80320#define AFE_VUL_D2_END_MSB 0x0b88321#define AFE_VUL_D2_CUR_MSB 0x0b8c322#define AFE_DL3_BASE_MSB 0x0b90323#define AFE_DL3_CUR_MSB 0x0b94324#define AFE_DL3_END_MSB 0x0b98325#define AFE_HDMI_OUT_BASE_MSB 0x0ba4326#define AFE_HDMI_OUT_CUR_MSB 0x0ba8327#define AFE_HDMI_OUT_END_MSB 0x0bac328#define AFE_AWB2_BASE 0x0bd0329#define AFE_AWB2_END 0x0bd8330#define AFE_AWB2_CUR 0x0bdc331#define AFE_AWB2_BASE_MSB 0x0be0332#define AFE_AWB2_END_MSB 0x0be8333#define AFE_AWB2_CUR_MSB 0x0bec334#define AFE_ADDA_DL_SDM_DCCOMP_CON 0x0c50335#define AFE_ADDA_DL_SDM_TEST 0x0c54336#define AFE_ADDA_DL_DC_COMP_CFG0 0x0c58337#define AFE_ADDA_DL_DC_COMP_CFG1 0x0c5c338#define AFE_ADDA_DL_SDM_FIFO_MON 0x0c60339#define AFE_ADDA_DL_SRC_LCH_MON 0x0c64340#define AFE_ADDA_DL_SRC_RCH_MON 0x0c68341#define AFE_ADDA_DL_SDM_OUT_MON 0x0c6c342#define AFE_CONNSYS_I2S_CON 0x0c78343#define AFE_CONNSYS_I2S_MON 0x0c7c344#define AFE_ASRC_2CH_CON0 0x0c80345#define AFE_ASRC_2CH_CON1 0x0c84346#define AFE_ASRC_2CH_CON2 0x0c88347#define AFE_ASRC_2CH_CON3 0x0c8c348#define AFE_ASRC_2CH_CON4 0x0c90349#define AFE_ASRC_2CH_CON5 0x0c94350#define AFE_ASRC_2CH_CON6 0x0c98351#define AFE_ASRC_2CH_CON7 0x0c9c352#define AFE_ASRC_2CH_CON8 0x0ca0353#define AFE_ASRC_2CH_CON9 0x0ca4354#define AFE_ASRC_2CH_CON10 0x0ca8355#define AFE_ADDA6_IIR_COEF_02_01 0x0ce0356#define AFE_ADDA6_IIR_COEF_04_03 0x0ce4357#define AFE_ADDA6_IIR_COEF_06_05 0x0ce8358#define AFE_ADDA6_IIR_COEF_08_07 0x0cec359#define AFE_ADDA6_IIR_COEF_10_09 0x0cf0360#define AFE_ADDA_PREDIS_CON2 0x0d40361#define AFE_ADDA_PREDIS_CON3 0x0d44362#define AFE_MEMIF_MON12 0x0d70363#define AFE_MEMIF_MON13 0x0d74364#define AFE_MEMIF_MON14 0x0d78365#define AFE_MEMIF_MON15 0x0d7c366#define AFE_MEMIF_MON16 0x0d80367#define AFE_MEMIF_MON17 0x0d84368#define AFE_MEMIF_MON18 0x0d88369#define AFE_MEMIF_MON19 0x0d8c370#define AFE_MEMIF_MON20 0x0d90371#define AFE_MEMIF_MON21 0x0d94372#define AFE_MEMIF_MON22 0x0d98373#define AFE_MEMIF_MON23 0x0d9c374#define AFE_MEMIF_MON24 0x0da0375#define AFE_HD_ENGEN_ENABLE 0x0dd0376#define AFE_ADDA_MTKAIF_CFG0 0x0e00377#define AFE_ADDA_MTKAIF_TX_CFG1 0x0e14378#define AFE_ADDA_MTKAIF_RX_CFG0 0x0e20379#define AFE_ADDA_MTKAIF_RX_CFG1 0x0e24380#define AFE_ADDA_MTKAIF_RX_CFG2 0x0e28381#define AFE_ADDA_MTKAIF_MON0 0x0e34382#define AFE_ADDA_MTKAIF_MON1 0x0e38383#define AFE_AUD_PAD_TOP 0x0e40384#define AFE_GENERAL1_ASRC_2CH_CON0 0x0e80385#define AFE_GENERAL1_ASRC_2CH_CON1 0x0e84386#define AFE_GENERAL1_ASRC_2CH_CON2 0x0e88387#define AFE_GENERAL1_ASRC_2CH_CON3 0x0e8c388#define AFE_GENERAL1_ASRC_2CH_CON4 0x0e90389#define AFE_GENERAL1_ASRC_2CH_CON5 0x0e94390#define AFE_GENERAL1_ASRC_2CH_CON6 0x0e98391#define AFE_GENERAL1_ASRC_2CH_CON7 0x0e9c392#define AFE_GENERAL1_ASRC_2CH_CON8 0x0ea0393#define AFE_GENERAL1_ASRC_2CH_CON9 0x0ea4394#define AFE_GENERAL1_ASRC_2CH_CON10 0x0ea8395#define AFE_GENERAL1_ASRC_2CH_CON12 0x0eb0396#define AFE_GENERAL1_ASRC_2CH_CON13 0x0eb4397#define GENERAL_ASRC_MODE 0x0eb8398#define GENERAL_ASRC_EN_ON 0x0ebc399#define AFE_GENERAL2_ASRC_2CH_CON0 0x0f00400#define AFE_GENERAL2_ASRC_2CH_CON1 0x0f04401#define AFE_GENERAL2_ASRC_2CH_CON2 0x0f08402#define AFE_GENERAL2_ASRC_2CH_CON3 0x0f0c403#define AFE_GENERAL2_ASRC_2CH_CON4 0x0f10404#define AFE_GENERAL2_ASRC_2CH_CON5 0x0f14405#define AFE_GENERAL2_ASRC_2CH_CON6 0x0f18406#define AFE_GENERAL2_ASRC_2CH_CON7 0x0f1c407#define AFE_GENERAL2_ASRC_2CH_CON8 0x0f20408#define AFE_GENERAL2_ASRC_2CH_CON9 0x0f24409#define AFE_GENERAL2_ASRC_2CH_CON10 0x0f28410#define AFE_GENERAL2_ASRC_2CH_CON12 0x0f30411#define AFE_GENERAL2_ASRC_2CH_CON13 0x0f34412 413#define AFE_MAX_REGISTER AFE_GENERAL2_ASRC_2CH_CON13414#define AFE_IRQ_STATUS_BITS 0x1fff415 416/* AUDIO_TOP_CON3 */417#define BCK_INVERSE_SFT 3418#define BCK_INVERSE_MASK 0x1419#define BCK_INVERSE_MASK_SFT (0x1 << 3)420 421/* AFE_DAC_CON0 */422#define AWB2_ON_SFT 29423#define AWB2_ON_MASK 0x1424#define AWB2_ON_MASK_SFT (0x1 << 29)425#define VUL2_ON_SFT 27426#define VUL2_ON_MASK 0x1427#define VUL2_ON_MASK_SFT (0x1 << 27)428#define MOD_DAI_DUP_WR_SFT 26429#define MOD_DAI_DUP_WR_MASK 0x1430#define MOD_DAI_DUP_WR_MASK_SFT (0x1 << 26)431#define VUL12_MODE_SFT 20432#define VUL12_MODE_MASK 0xf433#define VUL12_MODE_MASK_SFT (0xf << 20)434#define VUL12_R_MONO_SFT 11435#define VUL12_R_MONO_MASK 0x1436#define VUL12_R_MONO_MASK_SFT (0x1 << 11)437#define VUL12_MONO_SFT 10438#define VUL12_MONO_MASK 0x1439#define VUL12_MONO_MASK_SFT (0x1 << 10)440#define VUL12_ON_SFT 9441#define VUL12_ON_MASK 0x1442#define VUL12_ON_MASK_SFT (0x1 << 9)443#define MOD_DAI_ON_SFT 7444#define MOD_DAI_ON_MASK 0x1445#define MOD_DAI_ON_MASK_SFT (0x1 << 7)446#define AWB_ON_SFT 6447#define AWB_ON_MASK 0x1448#define AWB_ON_MASK_SFT (0x1 << 6)449#define DL3_ON_SFT 5450#define DL3_ON_MASK 0x1451#define DL3_ON_MASK_SFT (0x1 << 5)452#define VUL_ON_SFT 3453#define VUL_ON_MASK 0x1454#define VUL_ON_MASK_SFT (0x1 << 3)455#define DL2_ON_SFT 2456#define DL2_ON_MASK 0x1457#define DL2_ON_MASK_SFT (0x1 << 2)458#define DL1_ON_SFT 1459#define DL1_ON_MASK 0x1460#define DL1_ON_MASK_SFT (0x1 << 1)461#define AFE_ON_SFT 0462#define AFE_ON_MASK 0x1463#define AFE_ON_MASK_SFT (0x1 << 0)464 465/* AFE_DAC_CON1 */466#define MOD_DAI_MODE_SFT 30467#define MOD_DAI_MODE_MASK 0x3468#define MOD_DAI_MODE_MASK_SFT (0x3 << 30)469#define VUL_R_MONO_SFT 28470#define VUL_R_MONO_MASK 0x1471#define VUL_R_MONO_MASK_SFT (0x1 << 28)472#define VUL_DATA_SFT 27473#define VUL_DATA_MASK 0x1474#define VUL_DATA_MASK_SFT (0x1 << 27)475#define AWB_R_MONO_SFT 25476#define AWB_R_MONO_MASK 0x1477#define AWB_R_MONO_MASK_SFT (0x1 << 25)478#define AWB_DATA_SFT 24479#define AWB_DATA_MASK 0x1480#define AWB_DATA_MASK_SFT (0x1 << 24)481#define DL3_DATA_SFT 23482#define DL3_DATA_MASK 0x1483#define DL3_DATA_MASK_SFT (0x1 << 23)484#define DL2_DATA_SFT 22485#define DL2_DATA_MASK 0x1486#define DL2_DATA_MASK_SFT (0x1 << 22)487#define DL1_DATA_SFT 21488#define DL1_DATA_MASK 0x1489#define DL1_DATA_MASK_SFT (0x1 << 21)490#define VUL_MODE_SFT 16491#define VUL_MODE_MASK 0xf492#define VUL_MODE_MASK_SFT (0xf << 16)493#define AWB_MODE_SFT 12494#define AWB_MODE_MASK 0xf495#define AWB_MODE_MASK_SFT (0xf << 12)496#define I2S_MODE_SFT 8497#define I2S_MODE_MASK 0xf498#define I2S_MODE_MASK_SFT (0xf << 8)499#define DL2_MODE_SFT 4500#define DL2_MODE_MASK 0xf501#define DL2_MODE_MASK_SFT (0xf << 4)502#define DL1_MODE_SFT 0503#define DL1_MODE_MASK 0xf504#define DL1_MODE_MASK_SFT (0xf << 0)505 506/* AFE_DAC_CON2 */507#define AWB2_R_MONO_SFT 21508#define AWB2_R_MONO_MASK 0x1509#define AWB2_R_MONO_MASK_SFT (0x1 << 21)510#define AWB2_DATA_SFT 20511#define AWB2_DATA_MASK 0x1512#define AWB2_DATA_MASK_SFT (0x1 << 20)513#define AWB2_MODE_SFT 16514#define AWB2_MODE_MASK 0xf515#define AWB2_MODE_MASK_SFT (0xf << 16)516#define DL3_MODE_SFT 8517#define DL3_MODE_MASK 0xf518#define DL3_MODE_MASK_SFT (0xf << 8)519#define VUL2_MODE_SFT 4520#define VUL2_MODE_MASK 0xf521#define VUL2_MODE_MASK_SFT (0xf << 4)522#define VUL2_R_MONO_SFT 1523#define VUL2_R_MONO_MASK 0x1524#define VUL2_R_MONO_MASK_SFT (0x1 << 1)525#define VUL2_DATA_SFT 0526#define VUL2_DATA_MASK 0x1527#define VUL2_DATA_MASK_SFT (0x1 << 0)528 529/* AFE_DAC_MON */530#define AFE_ON_RETM_SFT 0531#define AFE_ON_RETM_MASK 0x1532#define AFE_ON_RETM_MASK_SFT (0x1 << 0)533 534/* AFE_I2S_CON */535#define BCK_NEG_EG_LATCH_SFT 30536#define BCK_NEG_EG_LATCH_MASK 0x1537#define BCK_NEG_EG_LATCH_MASK_SFT (0x1 << 30)538#define BCK_INV_SFT 29539#define BCK_INV_MASK 0x1540#define BCK_INV_MASK_SFT (0x1 << 29)541#define I2SIN_PAD_SEL_SFT 28542#define I2SIN_PAD_SEL_MASK 0x1543#define I2SIN_PAD_SEL_MASK_SFT (0x1 << 28)544#define I2S_LOOPBACK_SFT 20545#define I2S_LOOPBACK_MASK 0x1546#define I2S_LOOPBACK_MASK_SFT (0x1 << 20)547#define I2S_ONOFF_NOT_RESET_CK_ENABLE_SFT 17548#define I2S_ONOFF_NOT_RESET_CK_ENABLE_MASK 0x1549#define I2S_ONOFF_NOT_RESET_CK_ENABLE_MASK_SFT (0x1 << 17)550#define I2S1_HD_EN_SFT 12551#define I2S1_HD_EN_MASK 0x1552#define I2S1_HD_EN_MASK_SFT (0x1 << 12)553#define INV_PAD_CTRL_SFT 7554#define INV_PAD_CTRL_MASK 0x1555#define INV_PAD_CTRL_MASK_SFT (0x1 << 7)556#define I2S_BYPSRC_SFT 6557#define I2S_BYPSRC_MASK 0x1558#define I2S_BYPSRC_MASK_SFT (0x1 << 6)559#define INV_LRCK_SFT 5560#define INV_LRCK_MASK 0x1561#define INV_LRCK_MASK_SFT (0x1 << 5)562#define I2S_FMT_SFT 3563#define I2S_FMT_MASK 0x1564#define I2S_FMT_MASK_SFT (0x1 << 3)565#define I2S_SRC_SFT 2566#define I2S_SRC_MASK 0x1567#define I2S_SRC_MASK_SFT (0x1 << 2)568#define I2S_WLEN_SFT 1569#define I2S_WLEN_MASK 0x1570#define I2S_WLEN_MASK_SFT (0x1 << 1)571#define I2S_EN_SFT 0572#define I2S_EN_MASK 0x1573#define I2S_EN_MASK_SFT (0x1 << 0)574 575/* AFE_I2S_CON1 */576#define I2S2_LR_SWAP_SFT 31577#define I2S2_LR_SWAP_MASK 0x1578#define I2S2_LR_SWAP_MASK_SFT (0x1 << 31)579#define I2S2_SEL_O19_O20_SFT 18580#define I2S2_SEL_O19_O20_MASK 0x1581#define I2S2_SEL_O19_O20_MASK_SFT (0x1 << 18)582#define I2S_ONOFF_NOT_RESET_CK_ENABLE_SFT 17583#define I2S_ONOFF_NOT_RESET_CK_ENABLE_MASK 0x1584#define I2S_ONOFF_NOT_RESET_CK_ENABLE_MASK_SFT (0x1 << 17)585#define I2S2_SEL_O03_O04_SFT 16586#define I2S2_SEL_O03_O04_MASK 0x1587#define I2S2_SEL_O03_O04_MASK_SFT (0x1 << 16)588#define I2S2_32BIT_EN_SFT 13589#define I2S2_32BIT_EN_MASK 0x1590#define I2S2_32BIT_EN_MASK_SFT (0x1 << 13)591#define I2S2_HD_EN_SFT 12592#define I2S2_HD_EN_MASK 0x1593#define I2S2_HD_EN_MASK_SFT (0x1 << 12)594#define I2S2_OUT_MODE_SFT 8595#define I2S2_OUT_MODE_MASK 0xf596#define I2S2_OUT_MODE_MASK_SFT (0xf << 8)597#define INV_LRCK_SFT 5598#define INV_LRCK_MASK 0x1599#define INV_LRCK_MASK_SFT (0x1 << 5)600#define I2S2_FMT_SFT 3601#define I2S2_FMT_MASK 0x1602#define I2S2_FMT_MASK_SFT (0x1 << 3)603#define I2S2_WLEN_SFT 1604#define I2S2_WLEN_MASK 0x1605#define I2S2_WLEN_MASK_SFT (0x1 << 1)606#define I2S2_EN_SFT 0607#define I2S2_EN_MASK 0x1608#define I2S2_EN_MASK_SFT (0x1 << 0)609 610/* AFE_I2S_CON2 */611#define I2S3_LR_SWAP_SFT 31612#define I2S3_LR_SWAP_MASK 0x1613#define I2S3_LR_SWAP_MASK_SFT (0x1 << 31)614#define I2S3_UPDATE_WORD_SFT 24615#define I2S3_UPDATE_WORD_MASK 0x1f616#define I2S3_UPDATE_WORD_MASK_SFT (0x1f << 24)617#define I2S3_BCK_INV_SFT 23618#define I2S3_BCK_INV_MASK 0x1619#define I2S3_BCK_INV_MASK_SFT (0x1 << 23)620#define I2S3_FPGA_BIT_TEST_SFT 22621#define I2S3_FPGA_BIT_TEST_MASK 0x1622#define I2S3_FPGA_BIT_TEST_MASK_SFT (0x1 << 22)623#define I2S3_FPGA_BIT_SFT 21624#define I2S3_FPGA_BIT_MASK 0x1625#define I2S3_FPGA_BIT_MASK_SFT (0x1 << 21)626#define I2S3_LOOPBACK_SFT 20627#define I2S3_LOOPBACK_MASK 0x1628#define I2S3_LOOPBACK_MASK_SFT (0x1 << 20)629#define I2S_ONOFF_NOT_RESET_CK_ENABLE_SFT 17630#define I2S_ONOFF_NOT_RESET_CK_ENABLE_MASK 0x1631#define I2S_ONOFF_NOT_RESET_CK_ENABLE_MASK_SFT (0x1 << 17)632#define I2S3_HD_EN_SFT 12633#define I2S3_HD_EN_MASK 0x1634#define I2S3_HD_EN_MASK_SFT (0x1 << 12)635#define I2S3_OUT_MODE_SFT 8636#define I2S3_OUT_MODE_MASK 0xf637#define I2S3_OUT_MODE_MASK_SFT (0xf << 8)638#define I2S3_FMT_SFT 3639#define I2S3_FMT_MASK 0x1640#define I2S3_FMT_MASK_SFT (0x1 << 3)641#define I2S3_WLEN_SFT 1642#define I2S3_WLEN_MASK 0x1643#define I2S3_WLEN_MASK_SFT (0x1 << 1)644#define I2S3_EN_SFT 0645#define I2S3_EN_MASK 0x1646#define I2S3_EN_MASK_SFT (0x1 << 0)647 648/* AFE_I2S_CON3 */649#define I2S4_LR_SWAP_SFT 31650#define I2S4_LR_SWAP_MASK 0x1651#define I2S4_LR_SWAP_MASK_SFT (0x1 << 31)652#define I2S_ONOFF_NOT_RESET_CK_ENABLE_SFT 17653#define I2S_ONOFF_NOT_RESET_CK_ENABLE_MASK 0x1654#define I2S_ONOFF_NOT_RESET_CK_ENABLE_MASK_SFT (0x1 << 17)655#define I2S4_32BIT_EN_SFT 13656#define I2S4_32BIT_EN_MASK 0x1657#define I2S4_32BIT_EN_MASK_SFT (0x1 << 13)658#define I2S4_HD_EN_SFT 12659#define I2S4_HD_EN_MASK 0x1660#define I2S4_HD_EN_MASK_SFT (0x1 << 12)661#define I2S4_OUT_MODE_SFT 8662#define I2S4_OUT_MODE_MASK 0xf663#define I2S4_OUT_MODE_MASK_SFT (0xf << 8)664#define INV_LRCK_SFT 5665#define INV_LRCK_MASK 0x1666#define INV_LRCK_MASK_SFT (0x1 << 5)667#define I2S4_FMT_SFT 3668#define I2S4_FMT_MASK 0x1669#define I2S4_FMT_MASK_SFT (0x1 << 3)670#define I2S4_WLEN_SFT 1671#define I2S4_WLEN_MASK 0x1672#define I2S4_WLEN_MASK_SFT (0x1 << 1)673#define I2S4_EN_SFT 0674#define I2S4_EN_MASK 0x1675#define I2S4_EN_MASK_SFT (0x1 << 0)676 677/* AFE_I2S_CON4 */678#define I2S5_LR_SWAP_SFT 31679#define I2S5_LR_SWAP_MASK 0x1680#define I2S5_LR_SWAP_MASK_SFT (0x1 << 31)681#define I2S_LOOPBACK_SFT 20682#define I2S_LOOPBACK_MASK 0x1683#define I2S_LOOPBACK_MASK_SFT (0x1 << 20)684#define I2S_ONOFF_NOT_RESET_CK_ENABLE_SFT 17685#define I2S_ONOFF_NOT_RESET_CK_ENABLE_MASK 0x1686#define I2S_ONOFF_NOT_RESET_CK_ENABLE_MASK_SFT (0x1 << 17)687#define I2S5_32BIT_EN_SFT 13688#define I2S5_32BIT_EN_MASK 0x1689#define I2S5_32BIT_EN_MASK_SFT (0x1 << 13)690#define I2S5_HD_EN_SFT 12691#define I2S5_HD_EN_MASK 0x1692#define I2S5_HD_EN_MASK_SFT (0x1 << 12)693#define I2S5_OUT_MODE_SFT 8694#define I2S5_OUT_MODE_MASK 0xf695#define I2S5_OUT_MODE_MASK_SFT (0xf << 8)696#define INV_LRCK_SFT 5697#define INV_LRCK_MASK 0x1698#define INV_LRCK_MASK_SFT (0x1 << 5)699#define I2S5_FMT_SFT 3700#define I2S5_FMT_MASK 0x1701#define I2S5_FMT_MASK_SFT (0x1 << 3)702#define I2S5_WLEN_SFT 1703#define I2S5_WLEN_MASK 0x1704#define I2S5_WLEN_MASK_SFT (0x1 << 1)705#define I2S5_EN_SFT 0706#define I2S5_EN_MASK 0x1707#define I2S5_EN_MASK_SFT (0x1 << 0)708 709/* AFE_GAIN1_CON0 */710#define GAIN1_SAMPLE_PER_STEP_SFT 8711#define GAIN1_SAMPLE_PER_STEP_MASK 0xff712#define GAIN1_SAMPLE_PER_STEP_MASK_SFT (0xff << 8)713#define GAIN1_MODE_SFT 4714#define GAIN1_MODE_MASK 0xf715#define GAIN1_MODE_MASK_SFT (0xf << 4)716#define GAIN1_ON_SFT 0717#define GAIN1_ON_MASK 0x1718#define GAIN1_ON_MASK_SFT (0x1 << 0)719 720/* AFE_GAIN1_CON1 */721#define GAIN1_TARGET_SFT 0722#define GAIN1_TARGET_MASK 0xfffff723#define GAIN1_TARGET_MASK_SFT (0xfffff << 0)724 725/* AFE_GAIN2_CON0 */726#define GAIN2_SAMPLE_PER_STEP_SFT 8727#define GAIN2_SAMPLE_PER_STEP_MASK 0xff728#define GAIN2_SAMPLE_PER_STEP_MASK_SFT (0xff << 8)729#define GAIN2_MODE_SFT 4730#define GAIN2_MODE_MASK 0xf731#define GAIN2_MODE_MASK_SFT (0xf << 4)732#define GAIN2_ON_SFT 0733#define GAIN2_ON_MASK 0x1734#define GAIN2_ON_MASK_SFT (0x1 << 0)735 736/* AFE_GAIN2_CON1 */737#define GAIN2_TARGET_SFT 0738#define GAIN2_TARGET_MASK 0xfffff739#define GAIN2_TARGET_MASK_SFT (0xfffff << 0)740 741/* AFE_GAIN1_CUR */742#define AFE_GAIN1_CUR_SFT 0743#define AFE_GAIN1_CUR_MASK 0xfffff744#define AFE_GAIN1_CUR_MASK_SFT (0xfffff << 0)745 746/* AFE_GAIN2_CUR */747#define AFE_GAIN2_CUR_SFT 0748#define AFE_GAIN2_CUR_MASK 0xfffff749#define AFE_GAIN2_CUR_MASK_SFT (0xfffff << 0)750 751/* AFE_MEMIF_HD_MODE */752#define AWB2_HD_SFT 28753#define AWB2_HD_MASK 0x3754#define AWB2_HD_MASK_SFT (0x3 << 28)755#define HDMI_HD_SFT 20756#define HDMI_HD_MASK 0x3757#define HDMI_HD_MASK_SFT (0x3 << 20)758#define MOD_DAI_HD_SFT 18759#define MOD_DAI_HD_MASK 0x3760#define MOD_DAI_HD_MASK_SFT (0x3 << 18)761#define DAI_HD_SFT 16762#define DAI_HD_MASK 0x3763#define DAI_HD_MASK_SFT (0x3 << 16)764#define VUL2_HD_SFT 14765#define VUL2_HD_MASK 0x3766#define VUL2_HD_MASK_SFT (0x3 << 14)767#define VUL12_HD_SFT 12768#define VUL12_HD_MASK 0x3769#define VUL12_HD_MASK_SFT (0x3 << 12)770#define VUL_HD_SFT 10771#define VUL_HD_MASK 0x3772#define VUL_HD_MASK_SFT (0x3 << 10)773#define AWB_HD_SFT 8774#define AWB_HD_MASK 0x3775#define AWB_HD_MASK_SFT (0x3 << 8)776#define DL3_HD_SFT 6777#define DL3_HD_MASK 0x3778#define DL3_HD_MASK_SFT (0x3 << 6)779#define DL2_HD_SFT 4780#define DL2_HD_MASK 0x3781#define DL2_HD_MASK_SFT (0x3 << 4)782#define DL1_HD_SFT 0783#define DL1_HD_MASK 0x3784#define DL1_HD_MASK_SFT (0x3 << 0)785 786/* AFE_MEMIF_HDALIGN */787#define AWB2_NORMAL_MODE_SFT 30788#define AWB2_NORMAL_MODE_MASK 0x1789#define AWB2_NORMAL_MODE_MASK_SFT (0x1 << 30)790#define HDMI_NORMAL_MODE_SFT 26791#define HDMI_NORMAL_MODE_MASK 0x1792#define HDMI_NORMAL_MODE_MASK_SFT (0x1 << 26)793#define MOD_DAI_NORMAL_MODE_SFT 25794#define MOD_DAI_NORMAL_MODE_MASK 0x1795#define MOD_DAI_NORMAL_MODE_MASK_SFT (0x1 << 25)796#define DAI_NORMAL_MODE_SFT 24797#define DAI_NORMAL_MODE_MASK 0x1798#define DAI_NORMAL_MODE_MASK_SFT (0x1 << 24)799#define VUL2_NORMAL_MODE_SFT 23800#define VUL2_NORMAL_MODE_MASK 0x1801#define VUL2_NORMAL_MODE_MASK_SFT (0x1 << 23)802#define VUL12_NORMAL_MODE_SFT 22803#define VUL12_NORMAL_MODE_MASK 0x1804#define VUL12_NORMAL_MODE_MASK_SFT (0x1 << 22)805#define VUL_NORMAL_MODE_SFT 21806#define VUL_NORMAL_MODE_MASK 0x1807#define VUL_NORMAL_MODE_MASK_SFT (0x1 << 21)808#define AWB_NORMAL_MODE_SFT 20809#define AWB_NORMAL_MODE_MASK 0x1810#define AWB_NORMAL_MODE_MASK_SFT (0x1 << 20)811#define DL3_NORMAL_MODE_SFT 19812#define DL3_NORMAL_MODE_MASK 0x1813#define DL3_NORMAL_MODE_MASK_SFT (0x1 << 19)814#define DL2_NORMAL_MODE_SFT 18815#define DL2_NORMAL_MODE_MASK 0x1816#define DL2_NORMAL_MODE_MASK_SFT (0x1 << 18)817#define DL1_NORMAL_MODE_SFT 16818#define DL1_NORMAL_MODE_MASK 0x1819#define DL1_NORMAL_MODE_MASK_SFT (0x1 << 16)820#define RESERVED1_SFT 15821#define RESERVED1_MASK 0x1822#define RESERVED1_MASK_SFT (0x1 << 15)823#define AWB2_ALIGN_SFT 14824#define AWB2_ALIGN_MASK 0x1825#define AWB2_ALIGN_MASK_SFT (0x1 << 14)826#define HDMI_HD_ALIGN_SFT 10827#define HDMI_HD_ALIGN_MASK 0x1828#define HDMI_HD_ALIGN_MASK_SFT (0x1 << 10)829#define MOD_DAI_HD_ALIGN_SFT 9830#define MOD_DAI_HD_ALIGN_MASK 0x1831#define MOD_DAI_HD_ALIGN_MASK_SFT (0x1 << 9)832#define VUL2_HD_ALIGN_SFT 7833#define VUL2_HD_ALIGN_MASK 0x1834#define VUL2_HD_ALIGN_MASK_SFT (0x1 << 7)835#define VUL12_HD_ALIGN_SFT 6836#define VUL12_HD_ALIGN_MASK 0x1837#define VUL12_HD_ALIGN_MASK_SFT (0x1 << 6)838#define VUL_HD_ALIGN_SFT 5839#define VUL_HD_ALIGN_MASK 0x1840#define VUL_HD_ALIGN_MASK_SFT (0x1 << 5)841#define AWB_HD_ALIGN_SFT 4842#define AWB_HD_ALIGN_MASK 0x1843#define AWB_HD_ALIGN_MASK_SFT (0x1 << 4)844#define DL3_HD_ALIGN_SFT 3845#define DL3_HD_ALIGN_MASK 0x1846#define DL3_HD_ALIGN_MASK_SFT (0x1 << 3)847#define DL2_HD_ALIGN_SFT 2848#define DL2_HD_ALIGN_MASK 0x1849#define DL2_HD_ALIGN_MASK_SFT (0x1 << 2)850#define DL1_HD_ALIGN_SFT 0851#define DL1_HD_ALIGN_MASK 0x1852#define DL1_HD_ALIGN_MASK_SFT (0x1 << 0)853 854/* PCM_INTF_CON1 */855#define PCM_FIX_VALUE_SEL_SFT 31856#define PCM_FIX_VALUE_SEL_MASK 0x1857#define PCM_FIX_VALUE_SEL_MASK_SFT (0x1 << 31)858#define PCM_BUFFER_LOOPBACK_SFT 30859#define PCM_BUFFER_LOOPBACK_MASK 0x1860#define PCM_BUFFER_LOOPBACK_MASK_SFT (0x1 << 30)861#define PCM_PARALLEL_LOOPBACK_SFT 29862#define PCM_PARALLEL_LOOPBACK_MASK 0x1863#define PCM_PARALLEL_LOOPBACK_MASK_SFT (0x1 << 29)864#define PCM_SERIAL_LOOPBACK_SFT 28865#define PCM_SERIAL_LOOPBACK_MASK 0x1866#define PCM_SERIAL_LOOPBACK_MASK_SFT (0x1 << 28)867#define PCM_DAI_PCM_LOOPBACK_SFT 27868#define PCM_DAI_PCM_LOOPBACK_MASK 0x1869#define PCM_DAI_PCM_LOOPBACK_MASK_SFT (0x1 << 27)870#define PCM_I2S_PCM_LOOPBACK_SFT 26871#define PCM_I2S_PCM_LOOPBACK_MASK 0x1872#define PCM_I2S_PCM_LOOPBACK_MASK_SFT (0x1 << 26)873#define PCM_SYNC_DELSEL_SFT 25874#define PCM_SYNC_DELSEL_MASK 0x1875#define PCM_SYNC_DELSEL_MASK_SFT (0x1 << 25)876#define PCM_TX_LR_SWAP_SFT 24877#define PCM_TX_LR_SWAP_MASK 0x1878#define PCM_TX_LR_SWAP_MASK_SFT (0x1 << 24)879#define PCM_SYNC_OUT_INV_SFT 23880#define PCM_SYNC_OUT_INV_MASK 0x1881#define PCM_SYNC_OUT_INV_MASK_SFT (0x1 << 23)882#define PCM_BCLK_OUT_INV_SFT 22883#define PCM_BCLK_OUT_INV_MASK 0x1884#define PCM_BCLK_OUT_INV_MASK_SFT (0x1 << 22)885#define PCM_SYNC_IN_INV_SFT 21886#define PCM_SYNC_IN_INV_MASK 0x1887#define PCM_SYNC_IN_INV_MASK_SFT (0x1 << 21)888#define PCM_BCLK_IN_INV_SFT 20889#define PCM_BCLK_IN_INV_MASK 0x1890#define PCM_BCLK_IN_INV_MASK_SFT (0x1 << 20)891#define PCM_TX_LCH_RPT_SFT 19892#define PCM_TX_LCH_RPT_MASK 0x1893#define PCM_TX_LCH_RPT_MASK_SFT (0x1 << 19)894#define PCM_VBT_16K_MODE_SFT 18895#define PCM_VBT_16K_MODE_MASK 0x1896#define PCM_VBT_16K_MODE_MASK_SFT (0x1 << 18)897#define PCM_EXT_MODEM_SFT 17898#define PCM_EXT_MODEM_MASK 0x1899#define PCM_EXT_MODEM_MASK_SFT (0x1 << 17)900#define PCM_24BIT_SFT 16901#define PCM_24BIT_MASK 0x1902#define PCM_24BIT_MASK_SFT (0x1 << 16)903#define PCM_WLEN_SFT 14904#define PCM_WLEN_MASK 0x3905#define PCM_WLEN_MASK_SFT (0x3 << 14)906#define PCM_SYNC_LENGTH_SFT 9907#define PCM_SYNC_LENGTH_MASK 0x1f908#define PCM_SYNC_LENGTH_MASK_SFT (0x1f << 9)909#define PCM_SYNC_TYPE_SFT 8910#define PCM_SYNC_TYPE_MASK 0x1911#define PCM_SYNC_TYPE_MASK_SFT (0x1 << 8)912#define PCM_BT_MODE_SFT 7913#define PCM_BT_MODE_MASK 0x1914#define PCM_BT_MODE_MASK_SFT (0x1 << 7)915#define PCM_BYP_ASRC_SFT 6916#define PCM_BYP_ASRC_MASK 0x1917#define PCM_BYP_ASRC_MASK_SFT (0x1 << 6)918#define PCM_SLAVE_SFT 5919#define PCM_SLAVE_MASK 0x1920#define PCM_SLAVE_MASK_SFT (0x1 << 5)921#define PCM_MODE_SFT 3922#define PCM_MODE_MASK 0x3923#define PCM_MODE_MASK_SFT (0x3 << 3)924#define PCM_FMT_SFT 1925#define PCM_FMT_MASK 0x3926#define PCM_FMT_MASK_SFT (0x3 << 1)927#define PCM_EN_SFT 0928#define PCM_EN_MASK 0x1929#define PCM_EN_MASK_SFT (0x1 << 0)930 931/* PCM_INTF_CON2 */932#define PCM1_TX_FIFO_OV_SFT 31933#define PCM1_TX_FIFO_OV_MASK 0x1934#define PCM1_TX_FIFO_OV_MASK_SFT (0x1 << 31)935#define PCM1_RX_FIFO_OV_SFT 30936#define PCM1_RX_FIFO_OV_MASK 0x1937#define PCM1_RX_FIFO_OV_MASK_SFT (0x1 << 30)938#define PCM2_TX_FIFO_OV_SFT 29939#define PCM2_TX_FIFO_OV_MASK 0x1940#define PCM2_TX_FIFO_OV_MASK_SFT (0x1 << 29)941#define PCM2_RX_FIFO_OV_SFT 28942#define PCM2_RX_FIFO_OV_MASK 0x1943#define PCM2_RX_FIFO_OV_MASK_SFT (0x1 << 28)944#define PCM1_SYNC_GLITCH_SFT 27945#define PCM1_SYNC_GLITCH_MASK 0x1946#define PCM1_SYNC_GLITCH_MASK_SFT (0x1 << 27)947#define PCM2_SYNC_GLITCH_SFT 26948#define PCM2_SYNC_GLITCH_MASK 0x1949#define PCM2_SYNC_GLITCH_MASK_SFT (0x1 << 26)950#define TX3_RCH_DBG_MODE_SFT 17951#define TX3_RCH_DBG_MODE_MASK 0x1952#define TX3_RCH_DBG_MODE_MASK_SFT (0x1 << 17)953#define PCM1_PCM2_LOOPBACK_SFT 16954#define PCM1_PCM2_LOOPBACK_MASK 0x1955#define PCM1_PCM2_LOOPBACK_MASK_SFT (0x1 << 16)956#define DAI_PCM_LOOPBACK_CH_SFT 14957#define DAI_PCM_LOOPBACK_CH_MASK 0x3958#define DAI_PCM_LOOPBACK_CH_MASK_SFT (0x3 << 14)959#define I2S_PCM_LOOPBACK_CH_SFT 12960#define I2S_PCM_LOOPBACK_CH_MASK 0x3961#define I2S_PCM_LOOPBACK_CH_MASK_SFT (0x3 << 12)962#define TX_FIX_VALUE_SFT 0963#define TX_FIX_VALUE_MASK 0xff964#define TX_FIX_VALUE_MASK_SFT (0xff << 0)965 966/* PCM2_INTF_CON */967#define PCM2_TX_FIX_VALUE_SFT 24968#define PCM2_TX_FIX_VALUE_MASK 0xff969#define PCM2_TX_FIX_VALUE_MASK_SFT (0xff << 24)970#define PCM2_FIX_VALUE_SEL_SFT 23971#define PCM2_FIX_VALUE_SEL_MASK 0x1972#define PCM2_FIX_VALUE_SEL_MASK_SFT (0x1 << 23)973#define PCM2_BUFFER_LOOPBACK_SFT 22974#define PCM2_BUFFER_LOOPBACK_MASK 0x1975#define PCM2_BUFFER_LOOPBACK_MASK_SFT (0x1 << 22)976#define PCM2_PARALLEL_LOOPBACK_SFT 21977#define PCM2_PARALLEL_LOOPBACK_MASK 0x1978#define PCM2_PARALLEL_LOOPBACK_MASK_SFT (0x1 << 21)979#define PCM2_SERIAL_LOOPBACK_SFT 20980#define PCM2_SERIAL_LOOPBACK_MASK 0x1981#define PCM2_SERIAL_LOOPBACK_MASK_SFT (0x1 << 20)982#define PCM2_DAI_PCM_LOOPBACK_SFT 19983#define PCM2_DAI_PCM_LOOPBACK_MASK 0x1984#define PCM2_DAI_PCM_LOOPBACK_MASK_SFT (0x1 << 19)985#define PCM2_I2S_PCM_LOOPBACK_SFT 18986#define PCM2_I2S_PCM_LOOPBACK_MASK 0x1987#define PCM2_I2S_PCM_LOOPBACK_MASK_SFT (0x1 << 18)988#define PCM2_SYNC_DELSEL_SFT 17989#define PCM2_SYNC_DELSEL_MASK 0x1990#define PCM2_SYNC_DELSEL_MASK_SFT (0x1 << 17)991#define PCM2_TX_LR_SWAP_SFT 16992#define PCM2_TX_LR_SWAP_MASK 0x1993#define PCM2_TX_LR_SWAP_MASK_SFT (0x1 << 16)994#define PCM2_SYNC_IN_INV_SFT 15995#define PCM2_SYNC_IN_INV_MASK 0x1996#define PCM2_SYNC_IN_INV_MASK_SFT (0x1 << 15)997#define PCM2_BCLK_IN_INV_SFT 14998#define PCM2_BCLK_IN_INV_MASK 0x1999#define PCM2_BCLK_IN_INV_MASK_SFT (0x1 << 14)1000#define PCM2_TX_LCH_RPT_SFT 131001#define PCM2_TX_LCH_RPT_MASK 0x11002#define PCM2_TX_LCH_RPT_MASK_SFT (0x1 << 13)1003#define PCM2_VBT_16K_MODE_SFT 121004#define PCM2_VBT_16K_MODE_MASK 0x11005#define PCM2_VBT_16K_MODE_MASK_SFT (0x1 << 12)1006#define PCM2_LOOPBACK_CH_SEL_SFT 101007#define PCM2_LOOPBACK_CH_SEL_MASK 0x31008#define PCM2_LOOPBACK_CH_SEL_MASK_SFT (0x3 << 10)1009#define PCM2_TX2_BT_MODE_SFT 81010#define PCM2_TX2_BT_MODE_MASK 0x11011#define PCM2_TX2_BT_MODE_MASK_SFT (0x1 << 8)1012#define PCM2_BT_MODE_SFT 71013#define PCM2_BT_MODE_MASK 0x11014#define PCM2_BT_MODE_MASK_SFT (0x1 << 7)1015#define PCM2_AFIFO_SFT 61016#define PCM2_AFIFO_MASK 0x11017#define PCM2_AFIFO_MASK_SFT (0x1 << 6)1018#define PCM2_WLEN_SFT 51019#define PCM2_WLEN_MASK 0x11020#define PCM2_WLEN_MASK_SFT (0x1 << 5)1021#define PCM2_MODE_SFT 31022#define PCM2_MODE_MASK 0x31023#define PCM2_MODE_MASK_SFT (0x3 << 3)1024#define PCM2_FMT_SFT 11025#define PCM2_FMT_MASK 0x31026#define PCM2_FMT_MASK_SFT (0x3 << 1)1027#define PCM2_EN_SFT 01028#define PCM2_EN_MASK 0x11029#define PCM2_EN_MASK_SFT (0x1 << 0)1030 1031/* AFE_ADDA_MTKAIF_CFG0 */1032#define MTKAIF_RXIF_CLKINV_ADC_SFT 311033#define MTKAIF_RXIF_CLKINV_ADC_MASK 0x11034#define MTKAIF_RXIF_CLKINV_ADC_MASK_SFT (0x1 << 31)1035#define MTKAIF_RXIF_BYPASS_SRC_SFT 171036#define MTKAIF_RXIF_BYPASS_SRC_MASK 0x11037#define MTKAIF_RXIF_BYPASS_SRC_MASK_SFT (0x1 << 17)1038#define MTKAIF_RXIF_PROTOCOL2_SFT 161039#define MTKAIF_RXIF_PROTOCOL2_MASK 0x11040#define MTKAIF_RXIF_PROTOCOL2_MASK_SFT (0x1 << 16)1041#define MTKAIF_TXIF_BYPASS_SRC_SFT 51042#define MTKAIF_TXIF_BYPASS_SRC_MASK 0x11043#define MTKAIF_TXIF_BYPASS_SRC_MASK_SFT (0x1 << 5)1044#define MTKAIF_TXIF_PROTOCOL2_SFT 41045#define MTKAIF_TXIF_PROTOCOL2_MASK 0x11046#define MTKAIF_TXIF_PROTOCOL2_MASK_SFT (0x1 << 4)1047#define MTKAIF_TXIF_8TO5_SFT 21048#define MTKAIF_TXIF_8TO5_MASK 0x11049#define MTKAIF_TXIF_8TO5_MASK_SFT (0x1 << 2)1050#define MTKAIF_RXIF_8TO5_SFT 11051#define MTKAIF_RXIF_8TO5_MASK 0x11052#define MTKAIF_RXIF_8TO5_MASK_SFT (0x1 << 1)1053#define MTKAIF_IF_LOOPBACK1_SFT 01054#define MTKAIF_IF_LOOPBACK1_MASK 0x11055#define MTKAIF_IF_LOOPBACK1_MASK_SFT (0x1 << 0)1056 1057/* AFE_ADDA_MTKAIF_RX_CFG2 */1058#define MTKAIF_RXIF_DETECT_ON_PROTOCOL2_SFT 161059#define MTKAIF_RXIF_DETECT_ON_PROTOCOL2_MASK 0x11060#define MTKAIF_RXIF_DETECT_ON_PROTOCOL2_MASK_SFT (0x1 << 16)1061#define MTKAIF_RXIF_DELAY_CYCLE_SFT 121062#define MTKAIF_RXIF_DELAY_CYCLE_MASK 0xf1063#define MTKAIF_RXIF_DELAY_CYCLE_MASK_SFT (0xf << 12)1064#define MTKAIF_RXIF_DELAY_DATA_SFT 81065#define MTKAIF_RXIF_DELAY_DATA_MASK 0x11066#define MTKAIF_RXIF_DELAY_DATA_MASK_SFT (0x1 << 8)1067#define MTKAIF_RXIF_FIFO_RSP_PROTOCOL2_SFT 41068#define MTKAIF_RXIF_FIFO_RSP_PROTOCOL2_MASK 0x71069#define MTKAIF_RXIF_FIFO_RSP_PROTOCOL2_MASK_SFT (0x7 << 4)1070 1071/* AFE_ADDA_DL_SRC2_CON0 */1072#define DL_2_INPUT_MODE_CTL_SFT 281073#define DL_2_INPUT_MODE_CTL_MASK 0xf1074#define DL_2_INPUT_MODE_CTL_MASK_SFT (0xf << 28)1075#define DL_2_CH1_SATURATION_EN_CTL_SFT 271076#define DL_2_CH1_SATURATION_EN_CTL_MASK 0x11077#define DL_2_CH1_SATURATION_EN_CTL_MASK_SFT (0x1 << 27)1078#define DL_2_CH2_SATURATION_EN_CTL_SFT 261079#define DL_2_CH2_SATURATION_EN_CTL_MASK 0x11080#define DL_2_CH2_SATURATION_EN_CTL_MASK_SFT (0x1 << 26)1081#define DL_2_OUTPUT_SEL_CTL_SFT 241082#define DL_2_OUTPUT_SEL_CTL_MASK 0x31083#define DL_2_OUTPUT_SEL_CTL_MASK_SFT (0x3 << 24)1084#define DL_2_FADEIN_0START_EN_SFT 161085#define DL_2_FADEIN_0START_EN_MASK 0x31086#define DL_2_FADEIN_0START_EN_MASK_SFT (0x3 << 16)1087#define DL_DISABLE_HW_CG_CTL_SFT 151088#define DL_DISABLE_HW_CG_CTL_MASK 0x11089#define DL_DISABLE_HW_CG_CTL_MASK_SFT (0x1 << 15)1090#define C_DATA_EN_SEL_CTL_PRE_SFT 141091#define C_DATA_EN_SEL_CTL_PRE_MASK 0x11092#define C_DATA_EN_SEL_CTL_PRE_MASK_SFT (0x1 << 14)1093#define DL_2_SIDE_TONE_ON_CTL_PRE_SFT 131094#define DL_2_SIDE_TONE_ON_CTL_PRE_MASK 0x11095#define DL_2_SIDE_TONE_ON_CTL_PRE_MASK_SFT (0x1 << 13)1096#define DL_2_MUTE_CH1_OFF_CTL_PRE_SFT 121097#define DL_2_MUTE_CH1_OFF_CTL_PRE_MASK 0x11098#define DL_2_MUTE_CH1_OFF_CTL_PRE_MASK_SFT (0x1 << 12)1099#define DL_2_MUTE_CH2_OFF_CTL_PRE_SFT 111100#define DL_2_MUTE_CH2_OFF_CTL_PRE_MASK 0x11101#define DL_2_MUTE_CH2_OFF_CTL_PRE_MASK_SFT (0x1 << 11)1102#define DL2_ARAMPSP_CTL_PRE_SFT 91103#define DL2_ARAMPSP_CTL_PRE_MASK 0x31104#define DL2_ARAMPSP_CTL_PRE_MASK_SFT (0x3 << 9)1105#define DL_2_IIRMODE_CTL_PRE_SFT 61106#define DL_2_IIRMODE_CTL_PRE_MASK 0x71107#define DL_2_IIRMODE_CTL_PRE_MASK_SFT (0x7 << 6)1108#define DL_2_VOICE_MODE_CTL_PRE_SFT 51109#define DL_2_VOICE_MODE_CTL_PRE_MASK 0x11110#define DL_2_VOICE_MODE_CTL_PRE_MASK_SFT (0x1 << 5)1111#define D2_2_MUTE_CH1_ON_CTL_PRE_SFT 41112#define D2_2_MUTE_CH1_ON_CTL_PRE_MASK 0x11113#define D2_2_MUTE_CH1_ON_CTL_PRE_MASK_SFT (0x1 << 4)1114#define D2_2_MUTE_CH2_ON_CTL_PRE_SFT 31115#define D2_2_MUTE_CH2_ON_CTL_PRE_MASK 0x11116#define D2_2_MUTE_CH2_ON_CTL_PRE_MASK_SFT (0x1 << 3)1117#define DL_2_IIR_ON_CTL_PRE_SFT 21118#define DL_2_IIR_ON_CTL_PRE_MASK 0x11119#define DL_2_IIR_ON_CTL_PRE_MASK_SFT (0x1 << 2)1120#define DL_2_GAIN_ON_CTL_PRE_SFT 11121#define DL_2_GAIN_ON_CTL_PRE_MASK 0x11122#define DL_2_GAIN_ON_CTL_PRE_MASK_SFT (0x1 << 1)1123#define DL_2_SRC_ON_TMP_CTL_PRE_SFT 01124#define DL_2_SRC_ON_TMP_CTL_PRE_MASK 0x11125#define DL_2_SRC_ON_TMP_CTL_PRE_MASK_SFT (0x1 << 0)1126 1127/* AFE_ADDA_DL_SRC2_CON1 */1128#define DL_2_GAIN_CTL_PRE_SFT 161129#define DL_2_GAIN_CTL_PRE_MASK 0xffff1130#define DL_2_GAIN_CTL_PRE_MASK_SFT (0xffff << 16)1131#define DL_2_GAIN_MODE_CTL_SFT 01132#define DL_2_GAIN_MODE_CTL_MASK 0x11133#define DL_2_GAIN_MODE_CTL_MASK_SFT (0x1 << 0)1134 1135/* AFE_ADDA_UL_SRC_CON0 */1136#define ULCF_CFG_EN_CTL_SFT 311137#define ULCF_CFG_EN_CTL_MASK 0x11138#define ULCF_CFG_EN_CTL_MASK_SFT (0x1 << 31)1139#define UL_MODE_3P25M_CH2_CTL_SFT 221140#define UL_MODE_3P25M_CH2_CTL_MASK 0x11141#define UL_MODE_3P25M_CH2_CTL_MASK_SFT (0x1 << 22)1142#define UL_MODE_3P25M_CH1_CTL_SFT 211143#define UL_MODE_3P25M_CH1_CTL_MASK 0x11144#define UL_MODE_3P25M_CH1_CTL_MASK_SFT (0x1 << 21)1145#define UL_VOICE_MODE_CH1_CH2_CTL_SFT 171146#define UL_VOICE_MODE_CH1_CH2_CTL_MASK 0x71147#define UL_VOICE_MODE_CH1_CH2_CTL_MASK_SFT (0x7 << 17)1148#define DMIC_LOW_POWER_MODE_CTL_SFT 141149#define DMIC_LOW_POWER_MODE_CTL_MASK 0x31150#define DMIC_LOW_POWER_MODE_CTL_MASK_SFT (0x3 << 14)1151#define UL_DISABLE_HW_CG_CTL_SFT 121152#define UL_DISABLE_HW_CG_CTL_MASK 0x11153#define UL_DISABLE_HW_CG_CTL_MASK_SFT (0x1 << 12)1154#define UL_IIR_ON_TMP_CTL_SFT 101155#define UL_IIR_ON_TMP_CTL_MASK 0x11156#define UL_IIR_ON_TMP_CTL_MASK_SFT (0x1 << 10)1157#define UL_IIRMODE_CTL_SFT 71158#define UL_IIRMODE_CTL_MASK 0x71159#define UL_IIRMODE_CTL_MASK_SFT (0x7 << 7)1160#define DIGMIC_3P25M_1P625M_SEL_CTL_SFT 51161#define DIGMIC_3P25M_1P625M_SEL_CTL_MASK 0x11162#define DIGMIC_3P25M_1P625M_SEL_CTL_MASK_SFT (0x1 << 5)1163#define UL_LOOP_BACK_MODE_CTL_SFT 21164#define UL_LOOP_BACK_MODE_CTL_MASK 0x11165#define UL_LOOP_BACK_MODE_CTL_MASK_SFT (0x1 << 2)1166#define UL_SDM_3_LEVEL_CTL_SFT 11167#define UL_SDM_3_LEVEL_CTL_MASK 0x11168#define UL_SDM_3_LEVEL_CTL_MASK_SFT (0x1 << 1)1169#define UL_SRC_ON_TMP_CTL_SFT 01170#define UL_SRC_ON_TMP_CTL_MASK 0x11171#define UL_SRC_ON_TMP_CTL_MASK_SFT (0x1 << 0)1172 1173/* AFE_ADDA_UL_SRC_CON1 */1174#define C_DAC_EN_CTL_SFT 271175#define C_DAC_EN_CTL_MASK 0x11176#define C_DAC_EN_CTL_MASK_SFT (0x1 << 27)1177#define C_MUTE_SW_CTL_SFT 261178#define C_MUTE_SW_CTL_MASK 0x11179#define C_MUTE_SW_CTL_MASK_SFT (0x1 << 26)1180#define ASDM_SRC_SEL_CTL_SFT 251181#define ASDM_SRC_SEL_CTL_MASK 0x11182#define ASDM_SRC_SEL_CTL_MASK_SFT (0x1 << 25)1183#define C_AMP_DIV_CH2_CTL_SFT 211184#define C_AMP_DIV_CH2_CTL_MASK 0x71185#define C_AMP_DIV_CH2_CTL_MASK_SFT (0x7 << 21)1186#define C_FREQ_DIV_CH2_CTL_SFT 161187#define C_FREQ_DIV_CH2_CTL_MASK 0x1f1188#define C_FREQ_DIV_CH2_CTL_MASK_SFT (0x1f << 16)1189#define C_SINE_MODE_CH2_CTL_SFT 121190#define C_SINE_MODE_CH2_CTL_MASK 0xf1191#define C_SINE_MODE_CH2_CTL_MASK_SFT (0xf << 12)1192#define C_AMP_DIV_CH1_CTL_SFT 91193#define C_AMP_DIV_CH1_CTL_MASK 0x71194#define C_AMP_DIV_CH1_CTL_MASK_SFT (0x7 << 9)1195#define C_FREQ_DIV_CH1_CTL_SFT 41196#define C_FREQ_DIV_CH1_CTL_MASK 0x1f1197#define C_FREQ_DIV_CH1_CTL_MASK_SFT (0x1f << 4)1198#define C_SINE_MODE_CH1_CTL_SFT 01199#define C_SINE_MODE_CH1_CTL_MASK 0xf1200#define C_SINE_MODE_CH1_CTL_MASK_SFT (0xf << 0)1201 1202/* AFE_ADDA_TOP_CON0 */1203#define C_LOOP_BACK_MODE_CTL_SFT 121204#define C_LOOP_BACK_MODE_CTL_MASK 0xf1205#define C_LOOP_BACK_MODE_CTL_MASK_SFT (0xf << 12)1206#define C_EXT_ADC_CTL_SFT 01207#define C_EXT_ADC_CTL_MASK 0x11208#define C_EXT_ADC_CTL_MASK_SFT (0x1 << 0)1209 1210/* AFE_ADDA_UL_DL_CON0 */1211#define AFE_ADDA6_UL_LR_SWAP_SFT 151212#define AFE_ADDA6_UL_LR_SWAP_MASK 0x11213#define AFE_ADDA6_UL_LR_SWAP_MASK_SFT (0x1 << 15)1214#define AFE_ADDA6_CKDIV_RST_SFT 141215#define AFE_ADDA6_CKDIV_RST_MASK 0x11216#define AFE_ADDA6_CKDIV_RST_MASK_SFT (0x1 << 14)1217#define AFE_ADDA6_FIFO_AUTO_RST_SFT 131218#define AFE_ADDA6_FIFO_AUTO_RST_MASK 0x11219#define AFE_ADDA6_FIFO_AUTO_RST_MASK_SFT (0x1 << 13)1220#define UL_FIFO_DIGMIC_TESTIN_SFT 51221#define UL_FIFO_DIGMIC_TESTIN_MASK 0x31222#define UL_FIFO_DIGMIC_TESTIN_MASK_SFT (0x3 << 5)1223#define UL_FIFO_DIGMIC_WDATA_TESTEN_SFT 41224#define UL_FIFO_DIGMIC_WDATA_TESTEN_MASK 0x11225#define UL_FIFO_DIGMIC_WDATA_TESTEN_MASK_SFT (0x1 << 4)1226#define ADDA_AFE_ON_SFT 01227#define ADDA_AFE_ON_MASK 0x11228#define ADDA_AFE_ON_MASK_SFT (0x1 << 0)1229 1230/* AFE_SIDETONE_CON0 */1231#define R_RDY_SFT 301232#define R_RDY_MASK 0x11233#define R_RDY_MASK_SFT (0x1 << 30)1234#define W_RDY_SFT 291235#define W_RDY_MASK 0x11236#define W_RDY_MASK_SFT (0x1 << 29)1237#define R_W_EN_SFT 251238#define R_W_EN_MASK 0x11239#define R_W_EN_MASK_SFT (0x1 << 25)1240#define R_W_SEL_SFT 241241#define R_W_SEL_MASK 0x11242#define R_W_SEL_MASK_SFT (0x1 << 24)1243#define SEL_CH2_SFT 231244#define SEL_CH2_MASK 0x11245#define SEL_CH2_MASK_SFT (0x1 << 23)1246#define SIDE_TONE_COEFFICIENT_ADDR_SFT 161247#define SIDE_TONE_COEFFICIENT_ADDR_MASK 0x1f1248#define SIDE_TONE_COEFFICIENT_ADDR_MASK_SFT (0x1f << 16)1249#define SIDE_TONE_COEFFICIENT_SFT 01250#define SIDE_TONE_COEFFICIENT_MASK 0xffff1251#define SIDE_TONE_COEFFICIENT_MASK_SFT (0xffff << 0)1252 1253/* AFE_SIDETONE_COEFF */1254#define SIDE_TONE_COEFF_SFT 01255#define SIDE_TONE_COEFF_MASK 0xffff1256#define SIDE_TONE_COEFF_MASK_SFT (0xffff << 0)1257 1258/* AFE_SIDETONE_CON1 */1259#define STF_BYPASS_MODE_SFT 311260#define STF_BYPASS_MODE_MASK 0x11261#define STF_BYPASS_MODE_MASK_SFT (0x1 << 31)1262#define STF_BYPASS_MODE_O28_O29_SFT 301263#define STF_BYPASS_MODE_O28_O29_MASK 0x11264#define STF_BYPASS_MODE_O28_O29_MASK_SFT (0x1 << 30)1265#define STF_BYPASS_MODE_I2S4_SFT 291266#define STF_BYPASS_MODE_I2S4_MASK 0x11267#define STF_BYPASS_MODE_I2S4_MASK_SFT (0x1 << 29)1268#define STF_BYPASS_MODE_I2S5_SFT 281269#define STF_BYPASS_MODE_I2S5_MASK 0x11270#define STF_BYPASS_MODE_I2S5_MASK_SFT (0x1 << 28)1271#define STF_INPUT_EN_SEL_SFT 131272#define STF_INPUT_EN_SEL_MASK 0x11273#define STF_INPUT_EN_SEL_MASK_SFT (0x1 << 13)1274#define STF_SOURCE_FROM_O19O20_SFT 121275#define STF_SOURCE_FROM_O19O20_MASK 0x11276#define STF_SOURCE_FROM_O19O20_MASK_SFT (0x1 << 12)1277#define SIDE_TONE_ON_SFT 81278#define SIDE_TONE_ON_MASK 0x11279#define SIDE_TONE_ON_MASK_SFT (0x1 << 8)1280#define SIDE_TONE_HALF_TAP_NUM_SFT 01281#define SIDE_TONE_HALF_TAP_NUM_MASK 0x3f1282#define SIDE_TONE_HALF_TAP_NUM_MASK_SFT (0x3f << 0)1283 1284/* AFE_SIDETONE_GAIN */1285#define POSITIVE_GAIN_SFT 161286#define POSITIVE_GAIN_MASK 0x71287#define POSITIVE_GAIN_MASK_SFT (0x7 << 16)1288#define SIDE_TONE_GAIN_SFT 01289#define SIDE_TONE_GAIN_MASK 0xffff1290#define SIDE_TONE_GAIN_MASK_SFT (0xffff << 0)1291 1292/* AFE_ADDA_DL_SDM_DCCOMP_CON */1293#define AUD_DC_COMP_EN_SFT 81294#define AUD_DC_COMP_EN_MASK 0x11295#define AUD_DC_COMP_EN_MASK_SFT (0x1 << 8)1296#define ATTGAIN_CTL_SFT 01297#define ATTGAIN_CTL_MASK 0x3f1298#define ATTGAIN_CTL_MASK_SFT (0x3f << 0)1299 1300/* AFE_SINEGEN_CON0 */1301#define DAC_EN_SFT 261302#define DAC_EN_MASK 0x11303#define DAC_EN_MASK_SFT (0x1 << 26)1304#define MUTE_SW_CH2_SFT 251305#define MUTE_SW_CH2_MASK 0x11306#define MUTE_SW_CH2_MASK_SFT (0x1 << 25)1307#define MUTE_SW_CH1_SFT 241308#define MUTE_SW_CH1_MASK 0x11309#define MUTE_SW_CH1_MASK_SFT (0x1 << 24)1310#define SINE_MODE_CH2_SFT 201311#define SINE_MODE_CH2_MASK 0xf1312#define SINE_MODE_CH2_MASK_SFT (0xf << 20)1313#define AMP_DIV_CH2_SFT 171314#define AMP_DIV_CH2_MASK 0x71315#define AMP_DIV_CH2_MASK_SFT (0x7 << 17)1316#define FREQ_DIV_CH2_SFT 121317#define FREQ_DIV_CH2_MASK 0x1f1318#define FREQ_DIV_CH2_MASK_SFT (0x1f << 12)1319#define SINE_MODE_CH1_SFT 81320#define SINE_MODE_CH1_MASK 0xf1321#define SINE_MODE_CH1_MASK_SFT (0xf << 8)1322#define AMP_DIV_CH1_SFT 51323#define AMP_DIV_CH1_MASK 0x71324#define AMP_DIV_CH1_MASK_SFT (0x7 << 5)1325#define FREQ_DIV_CH1_SFT 01326#define FREQ_DIV_CH1_MASK 0x1f1327#define FREQ_DIV_CH1_MASK_SFT (0x1f << 0)1328 1329/* AFE_SINEGEN_CON2 */1330#define INNER_LOOP_BACK_MODE_SFT 01331#define INNER_LOOP_BACK_MODE_MASK 0x3f1332#define INNER_LOOP_BACK_MODE_MASK_SFT (0x3f << 0)1333 1334/* AFE_MEMIF_MINLEN */1335#define HDMI_MINLEN_SFT 241336#define HDMI_MINLEN_MASK 0xf1337#define HDMI_MINLEN_MASK_SFT (0xf << 24)1338#define DL3_MINLEN_SFT 121339#define DL3_MINLEN_MASK 0xf1340#define DL3_MINLEN_MASK_SFT (0xf << 12)1341#define DL2_MINLEN_SFT 81342#define DL2_MINLEN_MASK 0xf1343#define DL2_MINLEN_MASK_SFT (0xf << 8)1344#define DL1_DATA2_MINLEN_SFT 41345#define DL1_DATA2_MINLEN_MASK 0xf1346#define DL1_DATA2_MINLEN_MASK_SFT (0xf << 4)1347#define DL1_MINLEN_SFT 01348#define DL1_MINLEN_MASK 0xf1349#define DL1_MINLEN_MASK_SFT (0xf << 0)1350 1351/* AFE_MEMIF_MAXLEN */1352#define HDMI_MAXLEN_SFT 241353#define HDMI_MAXLEN_MASK 0xf1354#define HDMI_MAXLEN_MASK_SFT (0xf << 24)1355#define DL3_MAXLEN_SFT 81356#define DL3_MAXLEN_MASK 0xf1357#define DL3_MAXLEN_MASK_SFT (0xf << 8)1358#define DL2_MAXLEN_SFT 41359#define DL2_MAXLEN_MASK 0xf1360#define DL2_MAXLEN_MASK_SFT (0xf << 4)1361#define DL1_MAXLEN_SFT 01362#define DL1_MAXLEN_MASK 0x31363#define DL1_MAXLEN_MASK_SFT (0x3 << 0)1364 1365/* AFE_MEMIF_PBUF_SIZE */1366#define VUL12_4CH_SFT 171367#define VUL12_4CH_MASK 0x11368#define VUL12_4CH_MASK_SFT (0x1 << 17)1369#define DL3_PBUF_SIZE_SFT 101370#define DL3_PBUF_SIZE_MASK 0x31371#define DL3_PBUF_SIZE_MASK_SFT (0x3 << 10)1372#define HDMI_PBUF_SIZE_SFT 41373#define HDMI_PBUF_SIZE_MASK 0x31374#define HDMI_PBUF_SIZE_MASK_SFT (0x3 << 4)1375#define DL2_PBUF_SIZE_SFT 21376#define DL2_PBUF_SIZE_MASK 0x31377#define DL2_PBUF_SIZE_MASK_SFT (0x3 << 2)1378#define DL1_PBUF_SIZE_SFT 01379#define DL1_PBUF_SIZE_MASK 0x31380#define DL1_PBUF_SIZE_MASK_SFT (0x3 << 0)1381 1382/* AFE_HD_ENGEN_ENABLE */1383#define AFE_24M_ON_SFT 11384#define AFE_24M_ON_MASK 0x11385#define AFE_24M_ON_MASK_SFT (0x1 << 1)1386#define AFE_22M_ON_SFT 01387#define AFE_22M_ON_MASK 0x11388#define AFE_22M_ON_MASK_SFT (0x1 << 0)1389 1390/* AFE_IRQ_MCU_CON0 */1391#define IRQ12_MCU_ON_SFT 121392#define IRQ12_MCU_ON_MASK 0x11393#define IRQ12_MCU_ON_MASK_SFT (0x1 << 12)1394#define IRQ11_MCU_ON_SFT 111395#define IRQ11_MCU_ON_MASK 0x11396#define IRQ11_MCU_ON_MASK_SFT (0x1 << 11)1397#define IRQ10_MCU_ON_SFT 101398#define IRQ10_MCU_ON_MASK 0x11399#define IRQ10_MCU_ON_MASK_SFT (0x1 << 10)1400#define IRQ9_MCU_ON_SFT 91401#define IRQ9_MCU_ON_MASK 0x11402#define IRQ9_MCU_ON_MASK_SFT (0x1 << 9)1403#define IRQ8_MCU_ON_SFT 81404#define IRQ8_MCU_ON_MASK 0x11405#define IRQ8_MCU_ON_MASK_SFT (0x1 << 8)1406#define IRQ7_MCU_ON_SFT 71407#define IRQ7_MCU_ON_MASK 0x11408#define IRQ7_MCU_ON_MASK_SFT (0x1 << 7)1409#define IRQ6_MCU_ON_SFT 61410#define IRQ6_MCU_ON_MASK 0x11411#define IRQ6_MCU_ON_MASK_SFT (0x1 << 6)1412#define IRQ5_MCU_ON_SFT 51413#define IRQ5_MCU_ON_MASK 0x11414#define IRQ5_MCU_ON_MASK_SFT (0x1 << 5)1415#define IRQ4_MCU_ON_SFT 41416#define IRQ4_MCU_ON_MASK 0x11417#define IRQ4_MCU_ON_MASK_SFT (0x1 << 4)1418#define IRQ3_MCU_ON_SFT 31419#define IRQ3_MCU_ON_MASK 0x11420#define IRQ3_MCU_ON_MASK_SFT (0x1 << 3)1421#define IRQ2_MCU_ON_SFT 21422#define IRQ2_MCU_ON_MASK 0x11423#define IRQ2_MCU_ON_MASK_SFT (0x1 << 2)1424#define IRQ1_MCU_ON_SFT 11425#define IRQ1_MCU_ON_MASK 0x11426#define IRQ1_MCU_ON_MASK_SFT (0x1 << 1)1427#define IRQ0_MCU_ON_SFT 01428#define IRQ0_MCU_ON_MASK 0x11429#define IRQ0_MCU_ON_MASK_SFT (0x1 << 0)1430 1431/* AFE_IRQ_MCU_CON1 */1432#define IRQ7_MCU_MODE_SFT 281433#define IRQ7_MCU_MODE_MASK 0xf1434#define IRQ7_MCU_MODE_MASK_SFT (0xf << 28)1435#define IRQ6_MCU_MODE_SFT 241436#define IRQ6_MCU_MODE_MASK 0xf1437#define IRQ6_MCU_MODE_MASK_SFT (0xf << 24)1438#define IRQ5_MCU_MODE_SFT 201439#define IRQ5_MCU_MODE_MASK 0xf1440#define IRQ5_MCU_MODE_MASK_SFT (0xf << 20)1441#define IRQ4_MCU_MODE_SFT 161442#define IRQ4_MCU_MODE_MASK 0xf1443#define IRQ4_MCU_MODE_MASK_SFT (0xf << 16)1444#define IRQ3_MCU_MODE_SFT 121445#define IRQ3_MCU_MODE_MASK 0xf1446#define IRQ3_MCU_MODE_MASK_SFT (0xf << 12)1447#define IRQ2_MCU_MODE_SFT 81448#define IRQ2_MCU_MODE_MASK 0xf1449#define IRQ2_MCU_MODE_MASK_SFT (0xf << 8)1450#define IRQ1_MCU_MODE_SFT 41451#define IRQ1_MCU_MODE_MASK 0xf1452#define IRQ1_MCU_MODE_MASK_SFT (0xf << 4)1453#define IRQ0_MCU_MODE_SFT 01454#define IRQ0_MCU_MODE_MASK 0xf1455#define IRQ0_MCU_MODE_MASK_SFT (0xf << 0)1456 1457/* AFE_IRQ_MCU_CON2 */1458#define IRQ12_MCU_MODE_SFT 41459#define IRQ12_MCU_MODE_MASK 0xf1460#define IRQ12_MCU_MODE_MASK_SFT (0xf << 4)1461#define IRQ11_MCU_MODE_SFT 01462#define IRQ11_MCU_MODE_MASK 0xf1463#define IRQ11_MCU_MODE_MASK_SFT (0xf << 0)1464 1465/* AFE_IRQ_MCU_CLR */1466#define IRQ12_MCU_MISS_CNT_CLR_SFT 281467#define IRQ12_MCU_MISS_CNT_CLR_MASK 0x11468#define IRQ12_MCU_MISS_CNT_CLR_MASK_SFT (0x1 << 28)1469#define IRQ11_MCU_MISS_CNT_CLR_SFT 271470#define IRQ11_MCU_MISS_CNT_CLR_MASK 0x11471#define IRQ11_MCU_MISS_CNT_CLR_MASK_SFT (0x1 << 27)1472#define IRQ10_MCU_MISS_CLR_SFT 261473#define IRQ10_MCU_MISS_CLR_MASK 0x11474#define IRQ10_MCU_MISS_CLR_MASK_SFT (0x1 << 26)1475#define IRQ9_MCU_MISS_CLR_SFT 251476#define IRQ9_MCU_MISS_CLR_MASK 0x11477#define IRQ9_MCU_MISS_CLR_MASK_SFT (0x1 << 25)1478#define IRQ8_MCU_MISS_CLR_SFT 241479#define IRQ8_MCU_MISS_CLR_MASK 0x11480#define IRQ8_MCU_MISS_CLR_MASK_SFT (0x1 << 24)1481#define IRQ7_MCU_MISS_CLR_SFT 231482#define IRQ7_MCU_MISS_CLR_MASK 0x11483#define IRQ7_MCU_MISS_CLR_MASK_SFT (0x1 << 23)1484#define IRQ6_MCU_MISS_CLR_SFT 221485#define IRQ6_MCU_MISS_CLR_MASK 0x11486#define IRQ6_MCU_MISS_CLR_MASK_SFT (0x1 << 22)1487#define IRQ5_MCU_MISS_CLR_SFT 211488#define IRQ5_MCU_MISS_CLR_MASK 0x11489#define IRQ5_MCU_MISS_CLR_MASK_SFT (0x1 << 21)1490#define IRQ4_MCU_MISS_CLR_SFT 201491#define IRQ4_MCU_MISS_CLR_MASK 0x11492#define IRQ4_MCU_MISS_CLR_MASK_SFT (0x1 << 20)1493#define IRQ3_MCU_MISS_CLR_SFT 191494#define IRQ3_MCU_MISS_CLR_MASK 0x11495#define IRQ3_MCU_MISS_CLR_MASK_SFT (0x1 << 19)1496#define IRQ2_MCU_MISS_CLR_SFT 181497#define IRQ2_MCU_MISS_CLR_MASK 0x11498#define IRQ2_MCU_MISS_CLR_MASK_SFT (0x1 << 18)1499#define IRQ1_MCU_MISS_CLR_SFT 171500#define IRQ1_MCU_MISS_CLR_MASK 0x11501#define IRQ1_MCU_MISS_CLR_MASK_SFT (0x1 << 17)1502#define IRQ0_MCU_MISS_CLR_SFT 161503#define IRQ0_MCU_MISS_CLR_MASK 0x11504#define IRQ0_MCU_MISS_CLR_MASK_SFT (0x1 << 16)1505#define IRQ12_MCU_CLR_SFT 121506#define IRQ12_MCU_CLR_MASK 0x11507#define IRQ12_MCU_CLR_MASK_SFT (0x1 << 12)1508#define IRQ11_MCU_CLR_SFT 111509#define IRQ11_MCU_CLR_MASK 0x11510#define IRQ11_MCU_CLR_MASK_SFT (0x1 << 11)1511#define IRQ10_MCU_CLR_SFT 101512#define IRQ10_MCU_CLR_MASK 0x11513#define IRQ10_MCU_CLR_MASK_SFT (0x1 << 10)1514#define IRQ9_MCU_CLR_SFT 91515#define IRQ9_MCU_CLR_MASK 0x11516#define IRQ9_MCU_CLR_MASK_SFT (0x1 << 9)1517#define IRQ8_MCU_CLR_SFT 81518#define IRQ8_MCU_CLR_MASK 0x11519#define IRQ8_MCU_CLR_MASK_SFT (0x1 << 8)1520#define IRQ7_MCU_CLR_SFT 71521#define IRQ7_MCU_CLR_MASK 0x11522#define IRQ7_MCU_CLR_MASK_SFT (0x1 << 7)1523#define IRQ6_MCU_CLR_SFT 61524#define IRQ6_MCU_CLR_MASK 0x11525#define IRQ6_MCU_CLR_MASK_SFT (0x1 << 6)1526#define IRQ5_MCU_CLR_SFT 51527#define IRQ5_MCU_CLR_MASK 0x11528#define IRQ5_MCU_CLR_MASK_SFT (0x1 << 5)1529#define IRQ4_MCU_CLR_SFT 41530#define IRQ4_MCU_CLR_MASK 0x11531#define IRQ4_MCU_CLR_MASK_SFT (0x1 << 4)1532#define IRQ3_MCU_CLR_SFT 31533#define IRQ3_MCU_CLR_MASK 0x11534#define IRQ3_MCU_CLR_MASK_SFT (0x1 << 3)1535#define IRQ2_MCU_CLR_SFT 21536#define IRQ2_MCU_CLR_MASK 0x11537#define IRQ2_MCU_CLR_MASK_SFT (0x1 << 2)1538#define IRQ1_MCU_CLR_SFT 11539#define IRQ1_MCU_CLR_MASK 0x11540#define IRQ1_MCU_CLR_MASK_SFT (0x1 << 1)1541#define IRQ0_MCU_CLR_SFT 01542#define IRQ0_MCU_CLR_MASK 0x11543#define IRQ0_MCU_CLR_MASK_SFT (0x1 << 0)1544 1545/* AFE_MEMIF_MSB */1546#define CPU_COMPACT_MODE_SFT 291547#define CPU_COMPACT_MODE_MASK 0x11548#define CPU_COMPACT_MODE_MASK_SFT (0x1 << 29)1549#define CPU_HD_ALIGN_SFT 281550#define CPU_HD_ALIGN_MASK 0x11551#define CPU_HD_ALIGN_MASK_SFT (0x1 << 28)1552#define AWB2_AXI_WR_SIGN_SFT 241553#define AWB2_AXI_WR_SIGN_MASK 0x11554#define AWB2_AXI_WR_SIGN_MASK_SFT (0x1 << 24)1555#define VUL2_AXI_WR_SIGN_SFT 221556#define VUL2_AXI_WR_SIGN_MASK 0x11557#define VUL2_AXI_WR_SIGN_MASK_SFT (0x1 << 22)1558#define VUL12_AXI_WR_SIGN_SFT 211559#define VUL12_AXI_WR_SIGN_MASK 0x11560#define VUL12_AXI_WR_SIGN_MASK_SFT (0x1 << 21)1561#define VUL_AXI_WR_SIGN_SFT 201562#define VUL_AXI_WR_SIGN_MASK 0x11563#define VUL_AXI_WR_SIGN_MASK_SFT (0x1 << 20)1564#define MOD_DAI_AXI_WR_SIGN_SFT 181565#define MOD_DAI_AXI_WR_SIGN_MASK 0x11566#define MOD_DAI_AXI_WR_SIGN_MASK_SFT (0x1 << 18)1567#define AWB_MSTR_SIGN_SFT 171568#define AWB_MSTR_SIGN_MASK 0x11569#define AWB_MSTR_SIGN_MASK_SFT (0x1 << 17)1570#define SYSRAM_SIGN_SFT 161571#define SYSRAM_SIGN_MASK 0x11572#define SYSRAM_SIGN_MASK_SFT (0x1 << 16)1573 1574/* AFE_HDMI_CONN0 */1575#define HDMI_O_7_SFT 211576#define HDMI_O_7_MASK 0x71577#define HDMI_O_7_MASK_SFT (0x7 << 21)1578#define HDMI_O_6_SFT 181579#define HDMI_O_6_MASK 0x71580#define HDMI_O_6_MASK_SFT (0x7 << 18)1581#define HDMI_O_5_SFT 151582#define HDMI_O_5_MASK 0x71583#define HDMI_O_5_MASK_SFT (0x7 << 15)1584#define HDMI_O_4_SFT 121585#define HDMI_O_4_MASK 0x71586#define HDMI_O_4_MASK_SFT (0x7 << 12)1587#define HDMI_O_3_SFT 91588#define HDMI_O_3_MASK 0x71589#define HDMI_O_3_MASK_SFT (0x7 << 9)1590#define HDMI_O_2_SFT 61591#define HDMI_O_2_MASK 0x71592#define HDMI_O_2_MASK_SFT (0x7 << 6)1593#define HDMI_O_1_SFT 31594#define HDMI_O_1_MASK 0x71595#define HDMI_O_1_MASK_SFT (0x7 << 3)1596#define HDMI_O_0_SFT 01597#define HDMI_O_0_MASK 0x71598#define HDMI_O_0_MASK_SFT (0x7 << 0)1599 1600/* AFE_TDM_CON1 */1601#define TDM_EN_SFT 01602#define TDM_EN_MASK 0x11603#define TDM_EN_MASK_SFT (0x1 << 0)1604#define LRCK_INVERSE_SFT 21605#define LRCK_INVERSE_MASK 0x11606#define LRCK_INVERSE_MASK_SFT (0x1 << 2)1607#define DELAY_DATA_SFT 31608#define DELAY_DATA_MASK 0x11609#define DELAY_DATA_MASK_SFT (0x1 << 3)1610#define LEFT_ALIGN_SFT 41611#define LEFT_ALIGN_MASK 0x11612#define LEFT_ALIGN_MASK_SFT (0x1 << 4)1613#define WLEN_SFT 81614#define WLEN_MASK 0x31615#define WLEN_MASK_SFT (0x3 << 8)1616#define CHANNEL_NUM_SFT 101617#define CHANNEL_NUM_MASK 0x31618#define CHANNEL_NUM_MASK_SFT (0x3 << 10)1619#define CHANNEL_BCK_CYCLES_SFT 121620#define CHANNEL_BCK_CYCLES_MASK 0x31621#define CHANNEL_BCK_CYCLES_MASK_SFT (0x3 << 12)1622#define DAC_BIT_NUM_SFT 161623#define DAC_BIT_NUM_MASK 0x1f1624#define DAC_BIT_NUM_MASK_SFT (0x1f << 16)1625#define LRCK_TDM_WIDTH_SFT 241626#define LRCK_TDM_WIDTH_MASK 0xff1627#define LRCK_TDM_WIDTH_MASK_SFT (0xff << 24)1628 1629/* AFE_TDM_CON2 */1630#define ST_CH_PAIR_SOUT0_SFT 01631#define ST_CH_PAIR_SOUT0_MASK 0x71632#define ST_CH_PAIR_SOUT0_MASK_SFT (0x7 << 0)1633#define ST_CH_PAIR_SOUT1_SFT 41634#define ST_CH_PAIR_SOUT1_MASK 0x71635#define ST_CH_PAIR_SOUT1_MASK_SFT (0x7 << 4)1636#define ST_CH_PAIR_SOUT2_SFT 81637#define ST_CH_PAIR_SOUT2_MASK 0x71638#define ST_CH_PAIR_SOUT2_MASK_SFT (0x7 << 8)1639#define ST_CH_PAIR_SOUT3_SFT 121640#define ST_CH_PAIR_SOUT3_MASK 0x71641#define ST_CH_PAIR_SOUT3_MASK_SFT (0x7 << 12)1642#define TDM_FIX_VALUE_SEL_SFT 161643#define TDM_FIX_VALUE_SEL_MASK 0x11644#define TDM_FIX_VALUE_SEL_MASK_SFT (0x1 << 16)1645#define TDM_I2S_LOOPBACK_SFT 201646#define TDM_I2S_LOOPBACK_MASK 0x11647#define TDM_I2S_LOOPBACK_MASK_SFT (0x1 << 20)1648#define TDM_I2S_LOOPBACK_CH_SFT 211649#define TDM_I2S_LOOPBACK_CH_MASK 0x31650#define TDM_I2S_LOOPBACK_CH_MASK_SFT (0x3 << 21)1651#define TDM_FIX_VALUE_SFT 241652#define TDM_FIX_VALUE_MASK 0xff1653#define TDM_FIX_VALUE_MASK_SFT (0xff << 24)1654 1655/* AFE_HDMI_OUT_CON0 */1656#define AFE_HDMI_OUT_ON_RETM_SFT 81657#define AFE_HDMI_OUT_ON_RETM_MASK 0x11658#define AFE_HDMI_OUT_ON_RETM_MASK_SFT (0x1 << 8)1659#define AFE_HDMI_OUT_CH_NUM_SFT 41660#define AFE_HDMI_OUT_CH_NUM_MASK 0xf1661#define AFE_HDMI_OUT_CH_NUM_MASK_SFT (0xf << 4)1662#define AFE_HDMI_OUT_BIT_WIDTH_SFT 11663#define AFE_HDMI_OUT_BIT_WIDTH_MASK 0x11664#define AFE_HDMI_OUT_BIT_WIDTH_MASK_SFT (0x1 << 1)1665#define AFE_HDMI_OUT_ON_SFT 01666#define AFE_HDMI_OUT_ON_MASK 0x11667#define AFE_HDMI_OUT_ON_MASK_SFT (0x1 << 0)1668#endif1669