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1// SPDX-License-Identifier: GPL-2.02//3// Mediatek ALSA SoC AFE platform driver for 81864//5// Copyright (c) 2022 MediaTek Inc.6// Author: Jiaxin Yu <jiaxin.yu@mediatek.com>7 8#include <linux/delay.h>9#include <linux/dma-mapping.h>10#include <linux/module.h>11#include <linux/of.h>12#include <linux/of_address.h>13#include <linux/pm_runtime.h>14#include <linux/reset.h>15#include <sound/soc.h>16 17#include "../common/mtk-afe-platform-driver.h"18#include "../common/mtk-afe-fe-dai.h"19 20#include "mt8186-afe-common.h"21#include "mt8186-afe-clk.h"22#include "mt8186-afe-gpio.h"23#include "mt8186-interconnection.h"24 25static const struct snd_pcm_hardware mt8186_afe_hardware = {26	.info = (SNDRV_PCM_INFO_MMAP |27		 SNDRV_PCM_INFO_INTERLEAVED |28		 SNDRV_PCM_INFO_MMAP_VALID),29	.formats = (SNDRV_PCM_FMTBIT_S16_LE |30		    SNDRV_PCM_FMTBIT_S24_LE |31		    SNDRV_PCM_FMTBIT_S32_LE),32	.period_bytes_min = 96,33	.period_bytes_max = 4 * 48 * 1024,34	.periods_min = 2,35	.periods_max = 256,36	.buffer_bytes_max = 4 * 48 * 1024,37	.fifo_size = 0,38};39 40static int mt8186_fe_startup(struct snd_pcm_substream *substream,41			     struct snd_soc_dai *dai)42{43	struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream);44	struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);45	struct snd_pcm_runtime *runtime = substream->runtime;46	int id = snd_soc_rtd_to_cpu(rtd, 0)->id;47	struct mtk_base_afe_memif *memif = &afe->memif[id];48	const struct snd_pcm_hardware *mtk_afe_hardware = afe->mtk_afe_hardware;49	int ret;50 51	memif->substream = substream;52 53	snd_pcm_hw_constraint_step(substream->runtime, 0,54				   SNDRV_PCM_HW_PARAM_BUFFER_BYTES, 16);55 56	snd_soc_set_runtime_hwparams(substream, mtk_afe_hardware);57 58	ret = snd_pcm_hw_constraint_integer(runtime,59					    SNDRV_PCM_HW_PARAM_PERIODS);60	if (ret < 0) {61		dev_err(afe->dev, "snd_pcm_hw_constraint_integer failed\n");62		return ret;63	}64 65	/* dynamic allocate irq to memif */66	if (memif->irq_usage < 0) {67		int irq_id = mtk_dynamic_irq_acquire(afe);68 69		if (irq_id != afe->irqs_size) {70			/* link */71			memif->irq_usage = irq_id;72		} else {73			dev_err(afe->dev, "%s() error: no more asys irq\n",74				__func__);75			return -EBUSY;76		}77	}78 79	return 0;80}81 82static void mt8186_fe_shutdown(struct snd_pcm_substream *substream,83			       struct snd_soc_dai *dai)84{85	struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream);86	struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);87	struct mt8186_afe_private *afe_priv = afe->platform_priv;88	int id = snd_soc_rtd_to_cpu(rtd, 0)->id;89	struct mtk_base_afe_memif *memif = &afe->memif[id];90	int irq_id = memif->irq_usage;91 92	memif->substream = NULL;93	afe_priv->irq_cnt[id] = 0;94	afe_priv->xrun_assert[id] = 0;95 96	if (!memif->const_irq) {97		mtk_dynamic_irq_release(afe, irq_id);98		memif->irq_usage = -1;99		memif->substream = NULL;100	}101}102 103static int mt8186_fe_hw_params(struct snd_pcm_substream *substream,104			       struct snd_pcm_hw_params *params,105			       struct snd_soc_dai *dai)106{107	struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream);108	struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);109	int id = snd_soc_rtd_to_cpu(rtd, 0)->id;110	unsigned int channels = params_channels(params);111	unsigned int rate = params_rate(params);112	int ret;113 114	ret = mtk_afe_fe_hw_params(substream, params, dai);115	if (ret)116		return ret;117 118	/* channel merge configuration, enable control is in UL5_IN_MUX */119	if (id == MT8186_MEMIF_VUL3) {120		int update_cnt = 8;121		unsigned int val = 0;122		unsigned int mask = 0;123		int fs_mode = mt8186_rate_transform(afe->dev, rate, id);124 125		/* set rate, channel, update cnt, disable sgen */126		val = fs_mode << CM1_FS_SELECT_SFT |127			(channels - 1) << CHANNEL_MERGE0_CHNUM_SFT |128			update_cnt << CHANNEL_MERGE0_UPDATE_CNT_SFT;129		mask = CM1_FS_SELECT_MASK_SFT |130			CHANNEL_MERGE0_CHNUM_MASK_SFT |131			CHANNEL_MERGE0_UPDATE_CNT_MASK_SFT;132		regmap_update_bits(afe->regmap, AFE_CM1_CON, mask, val);133	}134 135	return 0;136}137 138static int mt8186_fe_hw_free(struct snd_pcm_substream *substream,139			     struct snd_soc_dai *dai)140{141	struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);142	int ret;143 144	ret = mtk_afe_fe_hw_free(substream, dai);145	if (ret) {146		dev_err(afe->dev, "%s failed\n", __func__);147		return ret;148	}149 150	return 0;151}152 153static int mt8186_fe_trigger(struct snd_pcm_substream *substream, int cmd,154			     struct snd_soc_dai *dai)155{156	struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream);157	struct snd_pcm_runtime * const runtime = substream->runtime;158	struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);159	struct mt8186_afe_private *afe_priv = afe->platform_priv;160	int id = snd_soc_rtd_to_cpu(rtd, 0)->id;161	struct mtk_base_afe_memif *memif = &afe->memif[id];162	int irq_id = memif->irq_usage;163	struct mtk_base_afe_irq *irqs = &afe->irqs[irq_id];164	const struct mtk_base_irq_data *irq_data = irqs->irq_data;165	unsigned int rate = runtime->rate;166	unsigned int counter;167	int fs;168	int ret;169 170	dev_dbg(afe->dev, "%s(), %s cmd %d, irq_id %d\n",171		__func__, memif->data->name, cmd, irq_id);172 173	switch (cmd) {174	case SNDRV_PCM_TRIGGER_START:175	case SNDRV_PCM_TRIGGER_RESUME:176		ret = mtk_memif_set_enable(afe, id);177		if (ret) {178			dev_err(afe->dev, "%s(), error, id %d, memif enable, ret %d\n",179				__func__, id, ret);180			return ret;181		}182 183		/*184		 * for small latency record185		 * ul memif need read some data before irq enable186		 */187		if (substream->stream == SNDRV_PCM_STREAM_CAPTURE &&188		    ((runtime->period_size * 1000) / rate <= 10))189			udelay(300);190 191		/* set irq counter */192		if (afe_priv->irq_cnt[id] > 0)193			counter = afe_priv->irq_cnt[id];194		else195			counter = runtime->period_size;196 197		regmap_update_bits(afe->regmap, irq_data->irq_cnt_reg,198				   irq_data->irq_cnt_maskbit199				   << irq_data->irq_cnt_shift,200				   counter << irq_data->irq_cnt_shift);201 202		/* set irq fs */203		fs = afe->irq_fs(substream, runtime->rate);204		if (fs < 0)205			return -EINVAL;206 207		regmap_update_bits(afe->regmap, irq_data->irq_fs_reg,208				   irq_data->irq_fs_maskbit209				   << irq_data->irq_fs_shift,210				   fs << irq_data->irq_fs_shift);211 212		/* enable interrupt */213		if (runtime->stop_threshold != ~(0U))214			regmap_update_bits(afe->regmap,215					   irq_data->irq_en_reg,216					   1 << irq_data->irq_en_shift,217					   1 << irq_data->irq_en_shift);218		return 0;219	case SNDRV_PCM_TRIGGER_STOP:220	case SNDRV_PCM_TRIGGER_SUSPEND:221		if (afe_priv->xrun_assert[id] > 0) {222			if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {223				int avail = snd_pcm_capture_avail(runtime);224				/* alsa can trigger stop/start when occur xrun */225				if (avail >= runtime->buffer_size)226					dev_dbg(afe->dev, "%s(), id %d, xrun assert\n",227						__func__, id);228			}229		}230 231		ret = mtk_memif_set_disable(afe, id);232		if (ret)233			dev_err(afe->dev, "%s(), error, id %d, memif enable, ret %d\n",234				__func__, id, ret);235 236		/* disable interrupt */237		if (runtime->stop_threshold != ~(0U))238			regmap_update_bits(afe->regmap,239					   irq_data->irq_en_reg,240					   1 << irq_data->irq_en_shift,241					   0 << irq_data->irq_en_shift);242 243		/* clear pending IRQ */244		regmap_write(afe->regmap, irq_data->irq_clr_reg,245			     1 << irq_data->irq_clr_shift);246		return ret;247	default:248		return -EINVAL;249	}250}251 252static int mt8186_memif_fs(struct snd_pcm_substream *substream,253			   unsigned int rate)254{255	struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream);256	struct snd_soc_component *component =257		snd_soc_rtdcom_lookup(rtd, AFE_PCM_NAME);258	struct mtk_base_afe *afe = snd_soc_component_get_drvdata(component);259	int id = snd_soc_rtd_to_cpu(rtd, 0)->id;260 261	return mt8186_rate_transform(afe->dev, rate, id);262}263 264static int mt8186_get_dai_fs(struct mtk_base_afe *afe,265			     int dai_id, unsigned int rate)266{267	return mt8186_rate_transform(afe->dev, rate, dai_id);268}269 270static int mt8186_irq_fs(struct snd_pcm_substream *substream, unsigned int rate)271{272	struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream);273	struct snd_soc_component *component =274		snd_soc_rtdcom_lookup(rtd, AFE_PCM_NAME);275	struct mtk_base_afe *afe = snd_soc_component_get_drvdata(component);276 277	return mt8186_general_rate_transform(afe->dev, rate);278}279 280static int mt8186_get_memif_pbuf_size(struct snd_pcm_substream *substream)281{282	struct snd_pcm_runtime *runtime = substream->runtime;283 284	if ((runtime->period_size * 1000) / runtime->rate > 10)285		return MT8186_MEMIF_PBUF_SIZE_256_BYTES;286 287	return MT8186_MEMIF_PBUF_SIZE_32_BYTES;288}289 290static int mt8186_fe_prepare(struct snd_pcm_substream *substream,291			     struct snd_soc_dai *dai)292{293	struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream);294	struct snd_pcm_runtime * const runtime = substream->runtime;295	struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);296	int id = snd_soc_rtd_to_cpu(rtd, 0)->id;297	struct mtk_base_afe_memif *memif = &afe->memif[id];298	int irq_id = memif->irq_usage;299	struct mtk_base_afe_irq *irqs = &afe->irqs[irq_id];300	const struct mtk_base_irq_data *irq_data = irqs->irq_data;301	unsigned int counter = runtime->period_size;302	int fs;303	int ret;304 305	ret = mtk_afe_fe_prepare(substream, dai);306	if (ret)307		return ret;308 309	/* set irq counter */310	regmap_update_bits(afe->regmap, irq_data->irq_cnt_reg,311			   irq_data->irq_cnt_maskbit312			   << irq_data->irq_cnt_shift,313			   counter << irq_data->irq_cnt_shift);314 315	/* set irq fs */316	fs = afe->irq_fs(substream, runtime->rate);317 318	if (fs < 0)319		return -EINVAL;320 321	regmap_update_bits(afe->regmap, irq_data->irq_fs_reg,322			   irq_data->irq_fs_maskbit323			   << irq_data->irq_fs_shift,324			   fs << irq_data->irq_fs_shift);325 326	return 0;327}328 329/* FE DAIs */330static const struct snd_soc_dai_ops mt8186_memif_dai_ops = {331	.startup	= mt8186_fe_startup,332	.shutdown	= mt8186_fe_shutdown,333	.hw_params	= mt8186_fe_hw_params,334	.hw_free	= mt8186_fe_hw_free,335	.prepare	= mt8186_fe_prepare,336	.trigger	= mt8186_fe_trigger,337};338 339#define MTK_PCM_RATES (SNDRV_PCM_RATE_8000_48000 |\340		       SNDRV_PCM_RATE_88200 |\341		       SNDRV_PCM_RATE_96000 |\342		       SNDRV_PCM_RATE_176400 |\343		       SNDRV_PCM_RATE_192000)344 345#define MTK_PCM_DAI_RATES (SNDRV_PCM_RATE_8000 |\346			   SNDRV_PCM_RATE_16000 |\347			   SNDRV_PCM_RATE_32000 |\348			   SNDRV_PCM_RATE_48000)349 350#define MTK_PCM_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\351			 SNDRV_PCM_FMTBIT_S24_LE |\352			 SNDRV_PCM_FMTBIT_S32_LE)353 354static struct snd_soc_dai_driver mt8186_memif_dai_driver[] = {355	/* FE DAIs: memory intefaces to CPU */356	{357		.name = "DL1",358		.id = MT8186_MEMIF_DL1,359		.playback = {360			.stream_name = "DL1",361			.channels_min = 1,362			.channels_max = 2,363			.rates = MTK_PCM_RATES,364			.formats = MTK_PCM_FORMATS,365		},366		.ops = &mt8186_memif_dai_ops,367	},368	{369		.name = "DL12",370		.id = MT8186_MEMIF_DL12,371		.playback = {372			.stream_name = "DL12",373			.channels_min = 1,374			.channels_max = 4,375			.rates = MTK_PCM_RATES,376			.formats = MTK_PCM_FORMATS,377		},378		.ops = &mt8186_memif_dai_ops,379	},380	{381		.name = "DL2",382		.id = MT8186_MEMIF_DL2,383		.playback = {384			.stream_name = "DL2",385			.channels_min = 1,386			.channels_max = 2,387			.rates = MTK_PCM_RATES,388			.formats = MTK_PCM_FORMATS,389		},390		.ops = &mt8186_memif_dai_ops,391	},392	{393		.name = "DL3",394		.id = MT8186_MEMIF_DL3,395		.playback = {396			.stream_name = "DL3",397			.channels_min = 1,398			.channels_max = 2,399			.rates = MTK_PCM_RATES,400			.formats = MTK_PCM_FORMATS,401		},402		.ops = &mt8186_memif_dai_ops,403	},404	{405		.name = "DL4",406		.id = MT8186_MEMIF_DL4,407		.playback = {408			.stream_name = "DL4",409			.channels_min = 1,410			.channels_max = 2,411			.rates = MTK_PCM_RATES,412			.formats = MTK_PCM_FORMATS,413		},414		.ops = &mt8186_memif_dai_ops,415	},416	{417		.name = "DL5",418		.id = MT8186_MEMIF_DL5,419		.playback = {420			.stream_name = "DL5",421			.channels_min = 1,422			.channels_max = 2,423			.rates = MTK_PCM_RATES,424			.formats = MTK_PCM_FORMATS,425		},426		.ops = &mt8186_memif_dai_ops,427	},428	{429		.name = "DL6",430		.id = MT8186_MEMIF_DL6,431		.playback = {432			.stream_name = "DL6",433			.channels_min = 1,434			.channels_max = 2,435			.rates = MTK_PCM_RATES,436			.formats = MTK_PCM_FORMATS,437		},438		.ops = &mt8186_memif_dai_ops,439	},440	{441		.name = "DL7",442		.id = MT8186_MEMIF_DL7,443		.playback = {444			.stream_name = "DL7",445			.channels_min = 1,446			.channels_max = 2,447			.rates = MTK_PCM_RATES,448			.formats = MTK_PCM_FORMATS,449		},450		.ops = &mt8186_memif_dai_ops,451	},452	{453		.name = "DL8",454		.id = MT8186_MEMIF_DL8,455		.playback = {456			.stream_name = "DL8",457			.channels_min = 1,458			.channels_max = 2,459			.rates = MTK_PCM_RATES,460			.formats = MTK_PCM_FORMATS,461		},462		.ops = &mt8186_memif_dai_ops,463	},464	{465		.name = "UL1",466		.id = MT8186_MEMIF_VUL12,467		.capture = {468			.stream_name = "UL1",469			.channels_min = 1,470			.channels_max = 4,471			.rates = MTK_PCM_RATES,472			.formats = MTK_PCM_FORMATS,473		},474		.ops = &mt8186_memif_dai_ops,475	},476	{477		.name = "UL2",478		.id = MT8186_MEMIF_AWB,479		.capture = {480			.stream_name = "UL2",481			.channels_min = 1,482			.channels_max = 2,483			.rates = MTK_PCM_RATES,484			.formats = MTK_PCM_FORMATS,485		},486		.ops = &mt8186_memif_dai_ops,487	},488	{489		.name = "UL3",490		.id = MT8186_MEMIF_VUL2,491		.capture = {492			.stream_name = "UL3",493			.channels_min = 1,494			.channels_max = 2,495			.rates = MTK_PCM_RATES,496			.formats = MTK_PCM_FORMATS,497		},498		.ops = &mt8186_memif_dai_ops,499	},500	{501		.name = "UL4",502		.id = MT8186_MEMIF_AWB2,503		.capture = {504			.stream_name = "UL4",505			.channels_min = 1,506			.channels_max = 2,507			.rates = MTK_PCM_RATES,508			.formats = MTK_PCM_FORMATS,509		},510		.ops = &mt8186_memif_dai_ops,511	},512	{513		.name = "UL5",514		.id = MT8186_MEMIF_VUL3,515		.capture = {516			.stream_name = "UL5",517			.channels_min = 1,518			.channels_max = 12,519			.rates = MTK_PCM_RATES,520			.formats = MTK_PCM_FORMATS,521		},522		.ops = &mt8186_memif_dai_ops,523	},524	{525		.name = "UL6",526		.id = MT8186_MEMIF_VUL4,527		.capture = {528			.stream_name = "UL6",529			.channels_min = 1,530			.channels_max = 2,531			.rates = MTK_PCM_RATES,532			.formats = MTK_PCM_FORMATS,533		},534		.ops = &mt8186_memif_dai_ops,535	},536	{537		.name = "UL7",538		.id = MT8186_MEMIF_VUL5,539		.capture = {540			.stream_name = "UL7",541			.channels_min = 1,542			.channels_max = 2,543			.rates = MTK_PCM_RATES,544			.formats = MTK_PCM_FORMATS,545		},546		.ops = &mt8186_memif_dai_ops,547	},548	{549		.name = "UL8",550		.id = MT8186_MEMIF_VUL6,551		.capture = {552			.stream_name = "UL8",553			.channels_min = 1,554			.channels_max = 2,555			.rates = MTK_PCM_RATES,556			.formats = MTK_PCM_FORMATS,557		},558		.ops = &mt8186_memif_dai_ops,559	}560};561 562/* kcontrol */563static int mt8186_irq_cnt1_get(struct snd_kcontrol *kcontrol,564			       struct snd_ctl_elem_value *ucontrol)565{566	struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);567	struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);568	struct mt8186_afe_private *afe_priv = afe->platform_priv;569 570	ucontrol->value.integer.value[0] =571		afe_priv->irq_cnt[MT8186_PRIMARY_MEMIF];572 573	return 0;574}575 576static int mt8186_irq_cnt1_set(struct snd_kcontrol *kcontrol,577			       struct snd_ctl_elem_value *ucontrol)578{579	struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);580	struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);581	struct mt8186_afe_private *afe_priv = afe->platform_priv;582	int memif_num = MT8186_PRIMARY_MEMIF;583	struct mtk_base_afe_memif *memif = &afe->memif[memif_num];584	int irq_id = memif->irq_usage;585	int irq_cnt = afe_priv->irq_cnt[memif_num];586 587	dev_dbg(afe->dev, "%s(), irq_id %d, irq_cnt = %d, value = %ld\n",588		__func__, irq_id, irq_cnt, ucontrol->value.integer.value[0]);589 590	if (irq_cnt == ucontrol->value.integer.value[0])591		return 0;592 593	irq_cnt = ucontrol->value.integer.value[0];594	afe_priv->irq_cnt[memif_num] = irq_cnt;595 596	if (!pm_runtime_status_suspended(afe->dev) && irq_id >= 0) {597		struct mtk_base_afe_irq *irqs = &afe->irqs[irq_id];598		const struct mtk_base_irq_data *irq_data = irqs->irq_data;599 600		regmap_update_bits(afe->regmap, irq_data->irq_cnt_reg,601				   irq_data->irq_cnt_maskbit602				   << irq_data->irq_cnt_shift,603				   irq_cnt << irq_data->irq_cnt_shift);604	} else {605		dev_dbg(afe->dev, "%s(), suspended || irq_id %d, not set\n",606			__func__, irq_id);607	}608 609	return 1;610}611 612static int mt8186_irq_cnt2_get(struct snd_kcontrol *kcontrol,613			       struct snd_ctl_elem_value *ucontrol)614{615	struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);616	struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);617	struct mt8186_afe_private *afe_priv = afe->platform_priv;618 619	ucontrol->value.integer.value[0] =620		afe_priv->irq_cnt[MT8186_RECORD_MEMIF];621 622	return 0;623}624 625static int mt8186_irq_cnt2_set(struct snd_kcontrol *kcontrol,626			       struct snd_ctl_elem_value *ucontrol)627{628	struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);629	struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);630	struct mt8186_afe_private *afe_priv = afe->platform_priv;631	int memif_num = MT8186_RECORD_MEMIF;632	struct mtk_base_afe_memif *memif = &afe->memif[memif_num];633	int irq_id = memif->irq_usage;634	int irq_cnt = afe_priv->irq_cnt[memif_num];635 636	dev_dbg(afe->dev, "%s(), irq_id %d, irq_cnt = %d, value = %ld\n",637		__func__, irq_id, irq_cnt, ucontrol->value.integer.value[0]);638 639	if (irq_cnt == ucontrol->value.integer.value[0])640		return 0;641 642	irq_cnt = ucontrol->value.integer.value[0];643	afe_priv->irq_cnt[memif_num] = irq_cnt;644 645	if (!pm_runtime_status_suspended(afe->dev) && irq_id >= 0) {646		struct mtk_base_afe_irq *irqs = &afe->irqs[irq_id];647		const struct mtk_base_irq_data *irq_data = irqs->irq_data;648 649		regmap_update_bits(afe->regmap, irq_data->irq_cnt_reg,650				   irq_data->irq_cnt_maskbit651				   << irq_data->irq_cnt_shift,652				   irq_cnt << irq_data->irq_cnt_shift);653	} else {654		dev_dbg(afe->dev, "%s(), suspended || irq_id %d, not set\n",655			__func__, irq_id);656	}657 658	return 1;659}660 661static int mt8186_record_xrun_assert_get(struct snd_kcontrol *kcontrol,662					 struct snd_ctl_elem_value *ucontrol)663{664	struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);665	struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);666	struct mt8186_afe_private *afe_priv = afe->platform_priv;667	int xrun_assert = afe_priv->xrun_assert[MT8186_RECORD_MEMIF];668 669	ucontrol->value.integer.value[0] = xrun_assert;670 671	return 0;672}673 674static int mt8186_record_xrun_assert_set(struct snd_kcontrol *kcontrol,675					 struct snd_ctl_elem_value *ucontrol)676{677	struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);678	struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);679	struct mt8186_afe_private *afe_priv = afe->platform_priv;680	int xrun_assert = ucontrol->value.integer.value[0];681 682	dev_dbg(afe->dev, "%s(), xrun_assert %d\n", __func__, xrun_assert);683 684	if (xrun_assert == afe_priv->xrun_assert[MT8186_RECORD_MEMIF])685		return 0;686 687	afe_priv->xrun_assert[MT8186_RECORD_MEMIF] = xrun_assert;688 689	return 1;690}691 692static const struct snd_kcontrol_new mt8186_pcm_kcontrols[] = {693	SOC_SINGLE_EXT("Audio IRQ1 CNT", SND_SOC_NOPM, 0, 0x3ffff, 0,694		       mt8186_irq_cnt1_get, mt8186_irq_cnt1_set),695	SOC_SINGLE_EXT("Audio IRQ2 CNT", SND_SOC_NOPM, 0, 0x3ffff, 0,696		       mt8186_irq_cnt2_get, mt8186_irq_cnt2_set),697	SOC_SINGLE_EXT("record_xrun_assert", SND_SOC_NOPM, 0, 0x1, 0,698		       mt8186_record_xrun_assert_get,699		       mt8186_record_xrun_assert_set),700};701 702/* dma widget & routes*/703static const struct snd_kcontrol_new memif_ul1_ch1_mix[] = {704	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1 Switch", AFE_CONN21,705				    I_ADDA_UL_CH1, 1, 0),706	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2 Switch", AFE_CONN21,707				    I_ADDA_UL_CH2, 1, 0),708	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3 Switch", AFE_CONN21,709				    I_ADDA_UL_CH3, 1, 0),710	SOC_DAPM_SINGLE_AUTODISABLE("TDM_IN_CH1 Switch", AFE_CONN21_1,711				    I_TDM_IN_CH1, 1, 0),712};713 714static const struct snd_kcontrol_new memif_ul1_ch2_mix[] = {715	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1 Switch", AFE_CONN22,716				    I_ADDA_UL_CH1, 1, 0),717	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2 Switch", AFE_CONN22,718				    I_ADDA_UL_CH2, 1, 0),719	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3 Switch", AFE_CONN22,720				    I_ADDA_UL_CH3, 1, 0),721	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4 Switch", AFE_CONN22,722				    I_ADDA_UL_CH4, 1, 0),723	SOC_DAPM_SINGLE_AUTODISABLE("TDM_IN_CH2 Switch", AFE_CONN22_1,724				    I_TDM_IN_CH2, 1, 0),725};726 727static const struct snd_kcontrol_new memif_ul1_ch3_mix[] = {728	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1 Switch", AFE_CONN9,729				    I_ADDA_UL_CH1, 1, 0),730	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2 Switch", AFE_CONN9,731				    I_ADDA_UL_CH2, 1, 0),732	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3 Switch", AFE_CONN9,733				    I_ADDA_UL_CH3, 1, 0),734	SOC_DAPM_SINGLE_AUTODISABLE("TDM_IN_CH3 Switch", AFE_CONN9_1,735				    I_TDM_IN_CH3, 1, 0),736};737 738static const struct snd_kcontrol_new memif_ul1_ch4_mix[] = {739	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1 Switch", AFE_CONN10,740				    I_ADDA_UL_CH1, 1, 0),741	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2 Switch", AFE_CONN10,742				    I_ADDA_UL_CH2, 1, 0),743	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3 Switch", AFE_CONN10,744				    I_ADDA_UL_CH3, 1, 0),745	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4 Switch", AFE_CONN10,746				    I_ADDA_UL_CH4, 1, 0),747	SOC_DAPM_SINGLE_AUTODISABLE("TDM_IN_CH4 Switch", AFE_CONN10_1,748				    I_TDM_IN_CH4, 1, 0),749};750 751static const struct snd_kcontrol_new memif_ul2_ch1_mix[] = {752	SOC_DAPM_SINGLE_AUTODISABLE("I2S0_CH1 Switch", AFE_CONN5,753				    I_I2S0_CH1, 1, 0),754	SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH1 Switch", AFE_CONN5,755				    I_DL1_CH1, 1, 0),756	SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH1 Switch", AFE_CONN5,757				    I_DL12_CH1, 1, 0),758	SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1 Switch", AFE_CONN5,759				    I_DL2_CH1, 1, 0),760	SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH1 Switch", AFE_CONN5,761				    I_DL3_CH1, 1, 0),762	SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH1 Switch", AFE_CONN5_1,763				    I_DL4_CH1, 1, 0),764	SOC_DAPM_SINGLE_AUTODISABLE("DL5_CH1 Switch", AFE_CONN5_1,765				    I_DL5_CH1, 1, 0),766	SOC_DAPM_SINGLE_AUTODISABLE("DL6_CH1 Switch", AFE_CONN5_1,767				    I_DL6_CH1, 1, 0),768	SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH1 Switch", AFE_CONN5,769				    I_PCM_1_CAP_CH1, 1, 0),770	SOC_DAPM_SINGLE_AUTODISABLE("I2S2_CH1 Switch", AFE_CONN5,771				    I_I2S2_CH1, 1, 0),772	SOC_DAPM_SINGLE_AUTODISABLE("CONNSYS_I2S_CH1 Switch", AFE_CONN5_1,773				    I_CONNSYS_I2S_CH1, 1, 0),774	SOC_DAPM_SINGLE_AUTODISABLE("SRC_1_OUT_CH1 Switch", AFE_CONN5_1,775				    I_SRC_1_OUT_CH1, 1, 0),776};777 778static const struct snd_kcontrol_new memif_ul2_ch2_mix[] = {779	SOC_DAPM_SINGLE_AUTODISABLE("I2S0_CH2 Switch", AFE_CONN6,780				    I_I2S0_CH2, 1, 0),781	SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH2 Switch", AFE_CONN6,782				    I_DL1_CH2, 1, 0),783	SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH2 Switch", AFE_CONN6,784				    I_DL12_CH2, 1, 0),785	SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH2 Switch", AFE_CONN6,786				    I_DL2_CH2, 1, 0),787	SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH2 Switch", AFE_CONN6,788				    I_DL3_CH2, 1, 0),789	SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH2 Switch", AFE_CONN6_1,790				    I_DL4_CH2, 1, 0),791	SOC_DAPM_SINGLE_AUTODISABLE("DL5_CH2 Switch", AFE_CONN6_1,792				    I_DL5_CH2, 1, 0),793	SOC_DAPM_SINGLE_AUTODISABLE("DL6_CH2 Switch", AFE_CONN6_1,794				    I_DL6_CH2, 1, 0),795	SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH2 Switch", AFE_CONN6,796				    I_PCM_1_CAP_CH2, 1, 0),797	SOC_DAPM_SINGLE_AUTODISABLE("I2S2_CH2 Switch", AFE_CONN6,798				    I_I2S2_CH2, 1, 0),799	SOC_DAPM_SINGLE_AUTODISABLE("CONNSYS_I2S_CH2 Switch", AFE_CONN6_1,800				    I_CONNSYS_I2S_CH2, 1, 0),801	SOC_DAPM_SINGLE_AUTODISABLE("SRC_1_OUT_CH2 Switch", AFE_CONN6_1,802				    I_SRC_1_OUT_CH2, 1, 0),803};804 805static const struct snd_kcontrol_new memif_ul3_ch1_mix[] = {806	SOC_DAPM_SINGLE_AUTODISABLE("CONNSYS_I2S_CH1 Switch", AFE_CONN32_1,807				    I_CONNSYS_I2S_CH1, 1, 0),808	SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH1 Switch", AFE_CONN32,809				    I_DL1_CH1, 1, 0),810	SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1 Switch", AFE_CONN32,811				    I_DL2_CH1, 1, 0),812};813 814static const struct snd_kcontrol_new memif_ul3_ch2_mix[] = {815	SOC_DAPM_SINGLE_AUTODISABLE("CONNSYS_I2S_CH2 Switch", AFE_CONN33_1,816				    I_CONNSYS_I2S_CH2, 1, 0),817};818 819static const struct snd_kcontrol_new memif_ul4_ch1_mix[] = {820	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1 Switch", AFE_CONN38,821				    I_ADDA_UL_CH1, 1, 0),822	SOC_DAPM_SINGLE_AUTODISABLE("I2S0_CH1 Switch", AFE_CONN38,823				    I_I2S0_CH1, 1, 0),824};825 826static const struct snd_kcontrol_new memif_ul4_ch2_mix[] = {827	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2 Switch", AFE_CONN39,828				    I_ADDA_UL_CH2, 1, 0),829	SOC_DAPM_SINGLE_AUTODISABLE("I2S0_CH2 Switch", AFE_CONN39,830				    I_I2S0_CH2, 1, 0),831};832 833static const struct snd_kcontrol_new memif_ul5_ch1_mix[] = {834	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1 Switch", AFE_CONN44,835				    I_ADDA_UL_CH1, 1, 0),836};837 838static const struct snd_kcontrol_new memif_ul5_ch2_mix[] = {839	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2 Switch", AFE_CONN45,840				    I_ADDA_UL_CH2, 1, 0),841};842 843static const struct snd_kcontrol_new memif_ul6_ch1_mix[] = {844	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1 Switch", AFE_CONN46,845				    I_ADDA_UL_CH1, 1, 0),846	SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH1 Switch", AFE_CONN46,847				    I_DL1_CH1, 1, 0),848	SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH1 Switch", AFE_CONN46,849				    I_DL12_CH1, 1, 0),850	SOC_DAPM_SINGLE_AUTODISABLE("DL6_CH1 Switch", AFE_CONN46_1,851				    I_DL6_CH1, 1, 0),852	SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1 Switch", AFE_CONN46,853				    I_DL2_CH1, 1, 0),854	SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH1 Switch", AFE_CONN46,855				    I_DL3_CH1, 1, 0),856	SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH1 Switch", AFE_CONN46_1,857				    I_DL4_CH1, 1, 0),858	SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH1 Switch", AFE_CONN46,859				    I_PCM_1_CAP_CH1, 1, 0),860	SOC_DAPM_SINGLE_AUTODISABLE("GAIN1_OUT_CH1 Switch", AFE_CONN46,861				    I_GAIN1_OUT_CH1, 1, 0),862};863 864static const struct snd_kcontrol_new memif_ul6_ch2_mix[] = {865	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2 Switch", AFE_CONN47,866				    I_ADDA_UL_CH2, 1, 0),867	SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH2 Switch", AFE_CONN47,868				    I_DL1_CH2, 1, 0),869	SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH2 Switch", AFE_CONN47,870				    I_DL12_CH2, 1, 0),871	SOC_DAPM_SINGLE_AUTODISABLE("DL6_CH2 Switch", AFE_CONN47_1,872				    I_DL6_CH2, 1, 0),873	SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH2 Switch", AFE_CONN47,874				    I_DL2_CH2, 1, 0),875	SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH2 Switch", AFE_CONN47,876				    I_DL3_CH2, 1, 0),877	SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH2 Switch", AFE_CONN47_1,878				    I_DL4_CH2, 1, 0),879	SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH2 Switch", AFE_CONN47,880				    I_PCM_1_CAP_CH2, 1, 0),881	SOC_DAPM_SINGLE_AUTODISABLE("GAIN1_OUT_CH2 Switch", AFE_CONN47,882				    I_GAIN1_OUT_CH2, 1, 0),883};884 885static const struct snd_kcontrol_new memif_ul7_ch1_mix[] = {886	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1 Switch", AFE_CONN48,887				    I_ADDA_UL_CH1, 1, 0),888	SOC_DAPM_SINGLE_AUTODISABLE("HW_GAIN2_OUT_CH1 Switch", AFE_CONN48,889				    I_GAIN2_OUT_CH1, 1, 0),890	SOC_DAPM_SINGLE_AUTODISABLE("HW_SRC_2_OUT_CH1 Switch", AFE_CONN48_1,891				    I_SRC_2_OUT_CH1, 1, 0),892};893 894static const struct snd_kcontrol_new memif_ul7_ch2_mix[] = {895	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2 Switch", AFE_CONN49,896				    I_ADDA_UL_CH2, 1, 0),897	SOC_DAPM_SINGLE_AUTODISABLE("HW_GAIN2_OUT_CH2 Switch", AFE_CONN49,898				    I_GAIN2_OUT_CH2, 1, 0),899	SOC_DAPM_SINGLE_AUTODISABLE("HW_SRC_2_OUT_CH2 Switch", AFE_CONN49_1,900				    I_SRC_2_OUT_CH2, 1, 0),901};902 903static const struct snd_kcontrol_new memif_ul8_ch1_mix[] = {904	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1 Switch", AFE_CONN50,905				    I_ADDA_UL_CH1, 1, 0),906};907 908static const struct snd_kcontrol_new memif_ul8_ch2_mix[] = {909	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2 Switch", AFE_CONN51,910				    I_ADDA_UL_CH2, 1, 0),911};912 913static const struct snd_kcontrol_new hw_cm1_ch1_mix[] = {914	SOC_DAPM_SINGLE_AUTODISABLE("TDM_IN_CH1 Switch", AFE_CONN58_1,915				    I_TDM_IN_CH1, 1, 0),916	SOC_DAPM_SINGLE_AUTODISABLE("I2S0_CH1 Switch", AFE_CONN58,917				    I_I2S0_CH1, 1, 0),918	SOC_DAPM_SINGLE_AUTODISABLE("I2S2_CH1 Switch", AFE_CONN58,919				    I_I2S2_CH1, 1, 0),920	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1 Switch", AFE_CONN58,921				    I_ADDA_UL_CH1, 1, 0),922	SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH1 Switch", AFE_CONN58,923				    I_DL1_CH1, 1, 0),924	SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH1 Switch", AFE_CONN58,925				    I_DL12_CH1, 1, 0),926	SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH3 Switch", AFE_CONN58,927				    I_DL12_CH3, 1, 0),928	SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1 Switch", AFE_CONN58,929				    I_DL2_CH1, 1, 0),930	SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH1 Switch", AFE_CONN58,931				    I_DL3_CH1, 1, 0),932	SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH1 Switch", AFE_CONN58_1,933				    I_DL4_CH1, 1, 0),934	SOC_DAPM_SINGLE_AUTODISABLE("DL5_CH1 Switch", AFE_CONN58_1,935				    I_DL5_CH1, 1, 0),936	SOC_DAPM_SINGLE_AUTODISABLE("HW_SRC1_OUT_CH1 Switch", AFE_CONN58_1,937				    I_SRC_1_OUT_CH1, 1, 0),938	SOC_DAPM_SINGLE_AUTODISABLE("HW_SRC2_OUT_CH1 Switch", AFE_CONN58_1,939				    I_SRC_2_OUT_CH1, 1, 0),940};941 942static const struct snd_kcontrol_new hw_cm1_ch2_mix[] = {943	SOC_DAPM_SINGLE_AUTODISABLE("TDM_IN_CH2 Switch", AFE_CONN59_1,944				    I_TDM_IN_CH2, 1, 0),945	SOC_DAPM_SINGLE_AUTODISABLE("I2S0_CH2 Switch", AFE_CONN59,946				    I_I2S0_CH2, 1, 0),947	SOC_DAPM_SINGLE_AUTODISABLE("I2S2_CH2 Switch", AFE_CONN59,948				    I_I2S2_CH2, 1, 0),949	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2 Switch", AFE_CONN59,950				    I_ADDA_UL_CH2, 1, 0),951	SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH2 Switch", AFE_CONN59,952				    I_DL1_CH2, 1, 0),953	SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH2 Switch", AFE_CONN59,954				    I_DL12_CH2, 1, 0),955	SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH4 Switch", AFE_CONN59,956				    I_DL12_CH4, 1, 0),957	SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH2 Switch", AFE_CONN59,958				    I_DL2_CH2, 1, 0),959	SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH2 Switch", AFE_CONN59,960				    I_DL3_CH2, 1, 0),961	SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH2 Switch", AFE_CONN59_1,962				    I_DL4_CH2, 1, 0),963	SOC_DAPM_SINGLE_AUTODISABLE("DL5_CH2 Switch", AFE_CONN59_1,964				    I_DL5_CH2, 1, 0),965	SOC_DAPM_SINGLE_AUTODISABLE("HW_SRC1_OUT_CH2 Switch", AFE_CONN59_1,966				    I_SRC_1_OUT_CH2, 1, 0),967	SOC_DAPM_SINGLE_AUTODISABLE("HW_SRC2_OUT_CH2 Switch", AFE_CONN59_1,968				    I_SRC_2_OUT_CH2, 1, 0),969};970 971static const struct snd_kcontrol_new hw_cm1_ch3_mix[] = {972	SOC_DAPM_SINGLE_AUTODISABLE("TDM_IN_CH3 Switch", AFE_CONN60_1,973				    I_TDM_IN_CH3, 1, 0),974	SOC_DAPM_SINGLE_AUTODISABLE("I2S0_CH1 Switch", AFE_CONN60,975				    I_I2S0_CH1, 1, 0),976	SOC_DAPM_SINGLE_AUTODISABLE("I2S2_CH1 Switch", AFE_CONN60,977				    I_I2S2_CH1, 1, 0),978	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1 Switch", AFE_CONN60,979				    I_ADDA_UL_CH1, 1, 0),980	SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH1 Switch", AFE_CONN60,981				    I_DL1_CH1, 1, 0),982	SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH1 Switch", AFE_CONN60,983				    I_DL12_CH1, 1, 0),984	SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH3 Switch", AFE_CONN60,985				    I_DL12_CH3, 1, 0),986	SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1 Switch", AFE_CONN60,987				    I_DL2_CH1, 1, 0),988	SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH1 Switch", AFE_CONN60,989				    I_DL3_CH1, 1, 0),990	SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH1 Switch", AFE_CONN60_1,991				    I_DL4_CH1, 1, 0),992	SOC_DAPM_SINGLE_AUTODISABLE("DL5_CH1 Switch", AFE_CONN60_1,993				    I_DL5_CH1, 1, 0),994	SOC_DAPM_SINGLE_AUTODISABLE("HW_SRC1_OUT_CH1 Switch", AFE_CONN60_1,995				    I_SRC_1_OUT_CH1, 1, 0),996	SOC_DAPM_SINGLE_AUTODISABLE("HW_SRC2_OUT_CH1 Switch", AFE_CONN60_1,997				    I_SRC_2_OUT_CH1, 1, 0),998};999 1000static const struct snd_kcontrol_new hw_cm1_ch4_mix[] = {1001	SOC_DAPM_SINGLE_AUTODISABLE("TDM_IN_CH4 Switch", AFE_CONN61_1,1002				    I_TDM_IN_CH4, 1, 0),1003	SOC_DAPM_SINGLE_AUTODISABLE("I2S0_CH2 Switch", AFE_CONN61,1004				    I_I2S0_CH2, 1, 0),1005	SOC_DAPM_SINGLE_AUTODISABLE("I2S2_CH2 Switch", AFE_CONN61,1006				    I_I2S2_CH2, 1, 0),1007	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2 Switch", AFE_CONN61,1008				    I_ADDA_UL_CH2, 1, 0),1009	SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH2 Switch", AFE_CONN61,1010				    I_DL1_CH2, 1, 0),1011	SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH2 Switch", AFE_CONN61,1012				    I_DL12_CH2, 1, 0),1013	SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH4 Switch", AFE_CONN61,1014				    I_DL12_CH4, 1, 0),1015	SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH2 Switch", AFE_CONN61,1016				    I_DL2_CH2, 1, 0),1017	SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH2 Switch", AFE_CONN61,1018				    I_DL3_CH2, 1, 0),1019	SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH2 Switch", AFE_CONN61_1,1020				    I_DL4_CH2, 1, 0),1021	SOC_DAPM_SINGLE_AUTODISABLE("DL5_CH2 Switch", AFE_CONN61_1,1022				    I_DL5_CH2, 1, 0),1023	SOC_DAPM_SINGLE_AUTODISABLE("HW_SRC1_OUT_CH2 Switch", AFE_CONN61_1,1024				    I_SRC_1_OUT_CH2, 1, 0),1025	SOC_DAPM_SINGLE_AUTODISABLE("HW_SRC2_OUT_CH2 Switch", AFE_CONN61_1,1026				    I_SRC_2_OUT_CH2, 1, 0),1027};1028 1029static const struct snd_kcontrol_new hw_cm1_ch5_mix[] = {1030	SOC_DAPM_SINGLE_AUTODISABLE("TDM_IN_CH5 Switch", AFE_CONN62_1,1031				    I_TDM_IN_CH5, 1, 0),1032	SOC_DAPM_SINGLE_AUTODISABLE("I2S0_CH1 Switch", AFE_CONN62,1033				    I_I2S0_CH1, 1, 0),1034	SOC_DAPM_SINGLE_AUTODISABLE("I2S2_CH1 Switch", AFE_CONN62,1035				    I_I2S2_CH1, 1, 0),1036	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1 Switch", AFE_CONN62,1037				    I_ADDA_UL_CH1, 1, 0),1038	SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH1 Switch", AFE_CONN62,1039				    I_DL1_CH1, 1, 0),1040	SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH1 Switch", AFE_CONN62,1041				    I_DL12_CH1, 1, 0),1042	SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH3 Switch", AFE_CONN62,1043				    I_DL12_CH3, 1, 0),1044	SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1 Switch", AFE_CONN62,1045				    I_DL2_CH1, 1, 0),1046	SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH1 Switch", AFE_CONN62,1047				    I_DL3_CH1, 1, 0),1048	SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH1 Switch", AFE_CONN62_1,1049				    I_DL4_CH1, 1, 0),1050	SOC_DAPM_SINGLE_AUTODISABLE("DL5_CH1 Switch", AFE_CONN62_1,1051				    I_DL5_CH1, 1, 0),1052	SOC_DAPM_SINGLE_AUTODISABLE("HW_SRC1_OUT_CH1 Switch", AFE_CONN62_1,1053				    I_SRC_1_OUT_CH1, 1, 0),1054	SOC_DAPM_SINGLE_AUTODISABLE("HW_SRC2_OUT_CH1 Switch", AFE_CONN62_1,1055				    I_SRC_2_OUT_CH1, 1, 0),1056};1057 1058static const struct snd_kcontrol_new hw_cm1_ch6_mix[] = {1059	SOC_DAPM_SINGLE_AUTODISABLE("TDM_IN_CH6 Switch", AFE_CONN63_1,1060				    I_TDM_IN_CH6, 1, 0),1061	SOC_DAPM_SINGLE_AUTODISABLE("I2S0_CH2 Switch", AFE_CONN63,1062				    I_I2S0_CH2, 1, 0),1063	SOC_DAPM_SINGLE_AUTODISABLE("I2S2_CH2 Switch", AFE_CONN63,1064				    I_I2S2_CH2, 1, 0),1065	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2 Switch", AFE_CONN63,1066				    I_ADDA_UL_CH2, 1, 0),1067	SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH2 Switch", AFE_CONN63,1068				    I_DL1_CH2, 1, 0),1069	SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH2 Switch", AFE_CONN63,1070				    I_DL12_CH2, 1, 0),1071	SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH4 Switch", AFE_CONN63,1072				    I_DL12_CH4, 1, 0),1073	SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH2 Switch", AFE_CONN63,1074				    I_DL2_CH2, 1, 0),1075	SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH2 Switch", AFE_CONN63,1076				    I_DL3_CH2, 1, 0),1077	SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH2 Switch", AFE_CONN63_1,1078				    I_DL4_CH2, 1, 0),1079	SOC_DAPM_SINGLE_AUTODISABLE("DL5_CH2 Switch", AFE_CONN63_1,1080				    I_DL5_CH2, 1, 0),1081	SOC_DAPM_SINGLE_AUTODISABLE("HW_SRC1_OUT_CH2 Switch", AFE_CONN63_1,1082				    I_SRC_1_OUT_CH2, 1, 0),1083	SOC_DAPM_SINGLE_AUTODISABLE("HW_SRC2_OUT_CH2 Switch", AFE_CONN63_1,1084				    I_SRC_2_OUT_CH2, 1, 0),1085};1086 1087static const struct snd_kcontrol_new hw_cm1_ch7_mix[] = {1088	SOC_DAPM_SINGLE_AUTODISABLE("TDM_IN_CH7 Switch", AFE_CONN64_1,1089				    I_TDM_IN_CH7, 1, 0),1090	SOC_DAPM_SINGLE_AUTODISABLE("I2S0_CH1 Switch", AFE_CONN64,1091				    I_I2S0_CH1, 1, 0),1092	SOC_DAPM_SINGLE_AUTODISABLE("I2S2_CH1 Switch", AFE_CONN64,1093				    I_I2S2_CH1, 1, 0),1094	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1 Switch", AFE_CONN64,1095				    I_ADDA_UL_CH1, 1, 0),1096	SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH1 Switch", AFE_CONN64,1097				    I_DL1_CH1, 1, 0),1098	SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH1v", AFE_CONN64,1099				    I_DL12_CH1, 1, 0),1100	SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH3 Switch", AFE_CONN64,1101				    I_DL12_CH3, 1, 0),1102	SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1 Switch", AFE_CONN64,1103				    I_DL2_CH1, 1, 0),1104	SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH1 Switch", AFE_CONN64,1105				    I_DL3_CH1, 1, 0),1106	SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH1 Switch", AFE_CONN64_1,1107				    I_DL4_CH1, 1, 0),1108	SOC_DAPM_SINGLE_AUTODISABLE("DL5_CH1 Switch", AFE_CONN64_1,1109				    I_DL5_CH1, 1, 0),1110	SOC_DAPM_SINGLE_AUTODISABLE("HW_SRC1_OUT_CH1 Switch", AFE_CONN64_1,1111				    I_SRC_1_OUT_CH1, 1, 0),1112	SOC_DAPM_SINGLE_AUTODISABLE("HW_SRC2_OUT_CH1 Switch", AFE_CONN64_1,1113				    I_SRC_2_OUT_CH1, 1, 0),1114};1115 1116static const struct snd_kcontrol_new hw_cm1_ch8_mix[] = {1117	SOC_DAPM_SINGLE_AUTODISABLE("TDM_IN_CH8 Switch", AFE_CONN65_1,1118				    I_TDM_IN_CH8, 1, 0),1119	SOC_DAPM_SINGLE_AUTODISABLE("I2S0_CH2 Switch", AFE_CONN65,1120				    I_I2S0_CH2, 1, 0),1121	SOC_DAPM_SINGLE_AUTODISABLE("I2S2_CH2 Switch", AFE_CONN65,1122				    I_I2S2_CH2, 1, 0),1123	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2 Switch", AFE_CONN65,1124				    I_ADDA_UL_CH2, 1, 0),1125	SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH2 Switch", AFE_CONN65,1126				    I_DL1_CH2, 1, 0),1127	SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH2 Switch", AFE_CONN65,1128				    I_DL12_CH2, 1, 0),1129	SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH4 Switch", AFE_CONN65,1130				    I_DL12_CH4, 1, 0),1131	SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH2 Switch", AFE_CONN65,1132				    I_DL2_CH2, 1, 0),1133	SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH2 Switch", AFE_CONN65,1134				    I_DL3_CH2, 1, 0),1135	SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH2 Switch", AFE_CONN65_1,1136				    I_DL4_CH2, 1, 0),1137	SOC_DAPM_SINGLE_AUTODISABLE("DL5_CH2 Switch", AFE_CONN65_1,1138				    I_DL5_CH2, 1, 0),1139	SOC_DAPM_SINGLE_AUTODISABLE("HW_SRC1_OUT_CH2 Switch", AFE_CONN65_1,1140				    I_SRC_1_OUT_CH2, 1, 0),1141	SOC_DAPM_SINGLE_AUTODISABLE("HW_SRC2_OUT_CH2 Switch", AFE_CONN65_1,1142				    I_SRC_2_OUT_CH2, 1, 0),1143};1144 1145static const struct snd_kcontrol_new hw_cm1_ch9_mix[] = {1146	SOC_DAPM_SINGLE_AUTODISABLE("I2S0_CH1 Switch", AFE_CONN66,1147				    I_I2S0_CH1, 1, 0),1148	SOC_DAPM_SINGLE_AUTODISABLE("I2S2_CH1 Switch", AFE_CONN66,1149				    I_I2S2_CH1, 1, 0),1150	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1 Switch", AFE_CONN66,1151				    I_ADDA_UL_CH1, 1, 0),1152	SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH1 Switch", AFE_CONN66,1153				    I_DL1_CH1, 1, 0),1154	SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH1 Switch", AFE_CONN66,1155				    I_DL12_CH1, 1, 0),1156	SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH3 Switch", AFE_CONN66,1157				    I_DL12_CH3, 1, 0),1158	SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1 Switch", AFE_CONN66,1159				    I_DL2_CH1, 1, 0),1160	SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH1 Switch", AFE_CONN66,1161				    I_DL3_CH1, 1, 0),1162	SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH1 Switch", AFE_CONN66_1,1163				    I_DL4_CH1, 1, 0),1164	SOC_DAPM_SINGLE_AUTODISABLE("DL5_CH1 Switch", AFE_CONN66_1,1165				    I_DL5_CH1, 1, 0),1166	SOC_DAPM_SINGLE_AUTODISABLE("HW_SRC1_OUT_CH1 Switch", AFE_CONN66_1,1167				    I_SRC_1_OUT_CH1, 1, 0),1168	SOC_DAPM_SINGLE_AUTODISABLE("HW_SRC2_OUT_CH1 Switch", AFE_CONN66_1,1169				    I_SRC_2_OUT_CH1, 1, 0),1170};1171 1172static const struct snd_kcontrol_new hw_cm1_ch10_mix[] = {1173	SOC_DAPM_SINGLE_AUTODISABLE("I2S0_CH2 Switch", AFE_CONN67,1174				    I_I2S0_CH2, 1, 0),1175	SOC_DAPM_SINGLE_AUTODISABLE("I2S2_CH2 Switch", AFE_CONN67,1176				    I_I2S2_CH2, 1, 0),1177	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2 Switch", AFE_CONN67,1178				    I_ADDA_UL_CH2, 1, 0),1179	SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH2 Switch", AFE_CONN67,1180				    I_DL1_CH2, 1, 0),1181	SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH2 Switch", AFE_CONN67,1182				    I_DL12_CH2, 1, 0),1183	SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH4 Switch", AFE_CONN67,1184				    I_DL12_CH4, 1, 0),1185	SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH2 Switch", AFE_CONN67,1186				    I_DL2_CH2, 1, 0),1187	SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH2 Switch", AFE_CONN67,1188				    I_DL3_CH2, 1, 0),1189	SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH2 Switch", AFE_CONN67_1,1190				    I_DL4_CH2, 1, 0),1191	SOC_DAPM_SINGLE_AUTODISABLE("DL5_CH2 Switch", AFE_CONN67_1,1192				    I_DL5_CH2, 1, 0),1193	SOC_DAPM_SINGLE_AUTODISABLE("HW_SRC1_OUT_CH2 Switch", AFE_CONN67_1,1194				    I_SRC_1_OUT_CH2, 1, 0),1195	SOC_DAPM_SINGLE_AUTODISABLE("HW_SRC2_OUT_CH2 Switch", AFE_CONN67_1,1196				    I_SRC_2_OUT_CH2, 1, 0),1197};1198 1199static const struct snd_kcontrol_new hw_cm1_ch11_mix[] = {1200	SOC_DAPM_SINGLE_AUTODISABLE("I2S0_CH1 Switch", AFE_CONN68,1201				    I_I2S0_CH1, 1, 0),1202	SOC_DAPM_SINGLE_AUTODISABLE("I2S2_CH1 Switch", AFE_CONN68,1203				    I_I2S2_CH1, 1, 0),1204	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1 Switch", AFE_CONN68,1205				    I_ADDA_UL_CH1, 1, 0),1206	SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH1 Switch", AFE_CONN68,1207				    I_DL1_CH1, 1, 0),1208	SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH1 Switch", AFE_CONN68,1209				    I_DL12_CH1, 1, 0),1210	SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH3 Switch", AFE_CONN68,1211				    I_DL12_CH3, 1, 0),1212	SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1 Switch", AFE_CONN68,1213				    I_DL2_CH1, 1, 0),1214	SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH1 Switch", AFE_CONN68,1215				    I_DL3_CH1, 1, 0),1216	SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH1 Switch", AFE_CONN68_1,1217				    I_DL4_CH1, 1, 0),1218	SOC_DAPM_SINGLE_AUTODISABLE("DL5_CH1 Switch", AFE_CONN68_1,1219				    I_DL5_CH1, 1, 0),1220	SOC_DAPM_SINGLE_AUTODISABLE("HW_SRC1_OUT_CH1 Switch", AFE_CONN68_1,1221				    I_SRC_1_OUT_CH1, 1, 0),1222	SOC_DAPM_SINGLE_AUTODISABLE("HW_SRC2_OUT_CH1 Switch", AFE_CONN68_1,1223				    I_SRC_2_OUT_CH1, 1, 0),1224};1225 1226static const struct snd_kcontrol_new hw_cm1_ch12_mix[] = {1227	SOC_DAPM_SINGLE_AUTODISABLE("I2S0_CH2 Switch", AFE_CONN69,1228				    I_I2S0_CH2, 1, 0),1229	SOC_DAPM_SINGLE_AUTODISABLE("I2S2_CH2 Switch", AFE_CONN69,1230				    I_I2S2_CH2, 1, 0),1231	SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2 Switch", AFE_CONN69,1232				    I_ADDA_UL_CH2, 1, 0),1233	SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH2 Switch", AFE_CONN69,1234				    I_DL1_CH2, 1, 0),1235	SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH2 Switch", AFE_CONN69,1236				    I_DL12_CH2, 1, 0),1237	SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH4 Switch", AFE_CONN69,1238				    I_DL12_CH4, 1, 0),1239	SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH2 Switch", AFE_CONN69,1240				    I_DL2_CH2, 1, 0),1241	SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH2 Switch", AFE_CONN69,1242				    I_DL3_CH2, 1, 0),1243	SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH2 Switch", AFE_CONN69_1,1244				    I_DL4_CH2, 1, 0),1245	SOC_DAPM_SINGLE_AUTODISABLE("DL5_CH2 Switch", AFE_CONN69_1,1246				    I_DL5_CH2, 1, 0),1247	SOC_DAPM_SINGLE_AUTODISABLE("HW_SRC1_OUT_CH2 Switch", AFE_CONN69_1,1248				    I_SRC_1_OUT_CH2, 1, 0),1249	SOC_DAPM_SINGLE_AUTODISABLE("HW_SRC2_OUT_CH2 Switch", AFE_CONN69_1,1250				    I_SRC_2_OUT_CH2, 1, 0),1251};1252 1253/* ADDA UL MUX */1254enum {1255	UL5_IN_MUX_CM1 = 0,1256	UL5_IN_MUX_NORMAL,1257	UL5_IN_MUX_MASK = 0x1,1258};1259 1260static const char * const ul5_in_mux_map[] = {1261	"UL5_IN_FROM_CM1", "UL5_IN_FROM_Normal"1262};1263 1264static int ul5_in_map_value[] = {1265	UL5_IN_MUX_CM1,1266	UL5_IN_MUX_NORMAL,1267};1268 1269static SOC_VALUE_ENUM_SINGLE_DECL(ul5_in_mux_map_enum,1270				  AFE_CM1_CON,1271				  VUL3_BYPASS_CM_SFT,1272				  VUL3_BYPASS_CM_MASK,1273				  ul5_in_mux_map,1274				  ul5_in_map_value);1275 1276static const struct snd_kcontrol_new ul5_in_mux_control =1277	SOC_DAPM_ENUM("UL5_IN_MUX Select", ul5_in_mux_map_enum);1278 1279static const struct snd_soc_dapm_widget mt8186_memif_widgets[] = {1280	/* inter-connections */1281	SND_SOC_DAPM_MIXER("UL1_CH1", SND_SOC_NOPM, 0, 0,1282			   memif_ul1_ch1_mix, ARRAY_SIZE(memif_ul1_ch1_mix)),1283	SND_SOC_DAPM_MIXER("UL1_CH2", SND_SOC_NOPM, 0, 0,1284			   memif_ul1_ch2_mix, ARRAY_SIZE(memif_ul1_ch2_mix)),1285	SND_SOC_DAPM_MIXER("UL1_CH3", SND_SOC_NOPM, 0, 0,1286			   memif_ul1_ch3_mix, ARRAY_SIZE(memif_ul1_ch3_mix)),1287	SND_SOC_DAPM_MIXER("UL1_CH4", SND_SOC_NOPM, 0, 0,1288			   memif_ul1_ch4_mix, ARRAY_SIZE(memif_ul1_ch4_mix)),1289 1290	SND_SOC_DAPM_MIXER("UL2_CH1", SND_SOC_NOPM, 0, 0,1291			   memif_ul2_ch1_mix, ARRAY_SIZE(memif_ul2_ch1_mix)),1292	SND_SOC_DAPM_MIXER("UL2_CH2", SND_SOC_NOPM, 0, 0,1293			   memif_ul2_ch2_mix, ARRAY_SIZE(memif_ul2_ch2_mix)),1294 1295	SND_SOC_DAPM_MIXER("UL3_CH1", SND_SOC_NOPM, 0, 0,1296			   memif_ul3_ch1_mix, ARRAY_SIZE(memif_ul3_ch1_mix)),1297	SND_SOC_DAPM_MIXER("UL3_CH2", SND_SOC_NOPM, 0, 0,1298			   memif_ul3_ch2_mix, ARRAY_SIZE(memif_ul3_ch2_mix)),1299 1300	SND_SOC_DAPM_MIXER("UL4_CH1", SND_SOC_NOPM, 0, 0,1301			   memif_ul4_ch1_mix, ARRAY_SIZE(memif_ul4_ch1_mix)),1302	SND_SOC_DAPM_MIXER("UL4_CH2", SND_SOC_NOPM, 0, 0,1303			   memif_ul4_ch2_mix, ARRAY_SIZE(memif_ul4_ch2_mix)),1304 1305	SND_SOC_DAPM_MIXER("UL5_CH1", SND_SOC_NOPM, 0, 0,1306			   memif_ul5_ch1_mix, ARRAY_SIZE(memif_ul5_ch1_mix)),1307	SND_SOC_DAPM_MIXER("UL5_CH2", SND_SOC_NOPM, 0, 0,1308			   memif_ul5_ch2_mix, ARRAY_SIZE(memif_ul5_ch2_mix)),1309 1310	SND_SOC_DAPM_MIXER("UL6_CH1", SND_SOC_NOPM, 0, 0,1311			   memif_ul6_ch1_mix, ARRAY_SIZE(memif_ul6_ch1_mix)),1312	SND_SOC_DAPM_MIXER("UL6_CH2", SND_SOC_NOPM, 0, 0,1313			   memif_ul6_ch2_mix, ARRAY_SIZE(memif_ul6_ch2_mix)),1314 1315	SND_SOC_DAPM_MIXER("UL7_CH1", SND_SOC_NOPM, 0, 0,1316			   memif_ul7_ch1_mix, ARRAY_SIZE(memif_ul7_ch1_mix)),1317	SND_SOC_DAPM_MIXER("UL7_CH2", SND_SOC_NOPM, 0, 0,1318			   memif_ul7_ch2_mix, ARRAY_SIZE(memif_ul7_ch2_mix)),1319 1320	SND_SOC_DAPM_MIXER("UL8_CH1", SND_SOC_NOPM, 0, 0,1321			   memif_ul8_ch1_mix, ARRAY_SIZE(memif_ul8_ch1_mix)),1322	SND_SOC_DAPM_MIXER("UL8_CH2", SND_SOC_NOPM, 0, 0,1323			   memif_ul8_ch2_mix, ARRAY_SIZE(memif_ul8_ch2_mix)),1324 1325	SND_SOC_DAPM_MIXER("UL5_2CH", SND_SOC_NOPM, 0, 0, NULL, 0),1326 1327	SND_SOC_DAPM_MIXER("HW_CM1", SND_SOC_NOPM, 0, 0, NULL, 0),1328 1329	/* CM1 en*/1330	SND_SOC_DAPM_SUPPLY_S("CM1_EN", 0, AFE_CM1_CON,1331			      CHANNEL_MERGE0_EN_SFT, 0, NULL,1332			      SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),1333 1334	SND_SOC_DAPM_MIXER("HW_CM1_CH1", SND_SOC_NOPM, 0, 0,1335			   hw_cm1_ch1_mix, ARRAY_SIZE(hw_cm1_ch1_mix)),1336	SND_SOC_DAPM_MIXER("HW_CM1_CH2", SND_SOC_NOPM, 0, 0,1337			   hw_cm1_ch2_mix, ARRAY_SIZE(hw_cm1_ch2_mix)),1338	SND_SOC_DAPM_MIXER("HW_CM1_CH3", SND_SOC_NOPM, 0, 0,1339			   hw_cm1_ch3_mix, ARRAY_SIZE(hw_cm1_ch3_mix)),1340	SND_SOC_DAPM_MIXER("HW_CM1_CH4", SND_SOC_NOPM, 0, 0,1341			   hw_cm1_ch4_mix, ARRAY_SIZE(hw_cm1_ch4_mix)),1342	SND_SOC_DAPM_MIXER("HW_CM1_CH5", SND_SOC_NOPM, 0, 0,1343			   hw_cm1_ch5_mix, ARRAY_SIZE(hw_cm1_ch5_mix)),1344	SND_SOC_DAPM_MIXER("HW_CM1_CH6", SND_SOC_NOPM, 0, 0,1345			   hw_cm1_ch6_mix, ARRAY_SIZE(hw_cm1_ch6_mix)),1346	SND_SOC_DAPM_MIXER("HW_CM1_CH7", SND_SOC_NOPM, 0, 0,1347			   hw_cm1_ch7_mix, ARRAY_SIZE(hw_cm1_ch7_mix)),1348	SND_SOC_DAPM_MIXER("HW_CM1_CH8", SND_SOC_NOPM, 0, 0,1349			   hw_cm1_ch8_mix, ARRAY_SIZE(hw_cm1_ch8_mix)),1350	SND_SOC_DAPM_MIXER("HW_CM1_CH9", SND_SOC_NOPM, 0, 0,1351			   hw_cm1_ch9_mix, ARRAY_SIZE(hw_cm1_ch9_mix)),1352	SND_SOC_DAPM_MIXER("HW_CM1_CH10", SND_SOC_NOPM, 0, 0,1353			   hw_cm1_ch10_mix, ARRAY_SIZE(hw_cm1_ch10_mix)),1354	SND_SOC_DAPM_MIXER("HW_CM1_CH11", SND_SOC_NOPM, 0, 0,1355			   hw_cm1_ch11_mix, ARRAY_SIZE(hw_cm1_ch11_mix)),1356	SND_SOC_DAPM_MIXER("HW_CM1_CH12", SND_SOC_NOPM, 0, 0,1357			   hw_cm1_ch12_mix, ARRAY_SIZE(hw_cm1_ch12_mix)),1358 1359	SND_SOC_DAPM_MUX("UL5_IN_MUX", SND_SOC_NOPM, 0, 0,1360			 &ul5_in_mux_control),1361 1362	SND_SOC_DAPM_MIXER("DSP_DL1_VIRT", SND_SOC_NOPM, 0, 0, NULL, 0),1363	SND_SOC_DAPM_MIXER("DSP_DL2_VIRT", SND_SOC_NOPM, 0, 0, NULL, 0),1364 1365	SND_SOC_DAPM_INPUT("UL1_VIRTUAL_INPUT"),1366	SND_SOC_DAPM_INPUT("UL2_VIRTUAL_INPUT"),1367	SND_SOC_DAPM_INPUT("UL3_VIRTUAL_INPUT"),1368	SND_SOC_DAPM_INPUT("UL4_VIRTUAL_INPUT"),1369	SND_SOC_DAPM_INPUT("UL5_VIRTUAL_INPUT"),1370	SND_SOC_DAPM_INPUT("UL6_VIRTUAL_INPUT"),1371};1372 1373static const struct snd_soc_dapm_route mt8186_memif_routes[] = {1374	{"UL1", NULL, "UL1_CH1"},1375	{"UL1", NULL, "UL1_CH2"},1376	{"UL1", NULL, "UL1_CH3"},1377	{"UL1", NULL, "UL1_CH4"},1378	{"UL1_CH1", "ADDA_UL_CH1 Switch", "ADDA_UL_Mux"},1379	{"UL1_CH1", "ADDA_UL_CH2 Switch", "ADDA_UL_Mux"},1380	{"UL1_CH2", "ADDA_UL_CH1 Switch", "ADDA_UL_Mux"},1381	{"UL1_CH2", "ADDA_UL_CH2 Switch", "ADDA_UL_Mux"},1382	{"UL1_CH3", "ADDA_UL_CH1 Switch", "ADDA_UL_Mux"},1383	{"UL1_CH3", "ADDA_UL_CH2 Switch", "ADDA_UL_Mux"},1384	{"UL1_CH4", "ADDA_UL_CH1 Switch", "ADDA_UL_Mux"},1385	{"UL1_CH4", "ADDA_UL_CH2 Switch", "ADDA_UL_Mux"},1386	{"UL1_CH1", "TDM_IN_CH1 Switch", "TDM IN"},1387	{"UL1_CH2", "TDM_IN_CH2 Switch", "TDM IN"},1388	{"UL1_CH3", "TDM_IN_CH3 Switch", "TDM IN"},1389	{"UL1_CH4", "TDM_IN_CH4 Switch", "TDM IN"},1390 1391	{"UL2", NULL, "UL2_CH1"},1392	{"UL2", NULL, "UL2_CH2"},1393 1394	/* cannot connect FE to FE directly */1395	{"UL2_CH1", "DL1_CH1 Switch", "Hostless_UL2 UL"},1396	{"UL2_CH2", "DL1_CH2 Switch", "Hostless_UL2 UL"},1397	{"UL2_CH1", "DL12_CH1 Switch", "Hostless_UL2 UL"},1398	{"UL2_CH2", "DL12_CH2 Switch", "Hostless_UL2 UL"},1399	{"UL2_CH1", "DL6_CH1 Switch", "Hostless_UL2 UL"},1400	{"UL2_CH2", "DL6_CH2 Switch", "Hostless_UL2 UL"},1401	{"UL2_CH1", "DL2_CH1 Switch", "Hostless_UL2 UL"},1402	{"UL2_CH2", "DL2_CH2 Switch", "Hostless_UL2 UL"},1403	{"UL2_CH1", "DL3_CH1 Switch", "Hostless_UL2 UL"},1404	{"UL2_CH2", "DL3_CH2 Switch", "Hostless_UL2 UL"},1405	{"UL2_CH1", "DL4_CH1 Switch", "Hostless_UL2 UL"},1406	{"UL2_CH2", "DL4_CH2 Switch", "Hostless_UL2 UL"},1407	{"UL2_CH1", "DL5_CH1 Switch", "Hostless_UL2 UL"},1408	{"UL2_CH2", "DL5_CH2 Switch", "Hostless_UL2 UL"},1409 1410	{"Hostless_UL2 UL", NULL, "UL2_VIRTUAL_INPUT"},1411 1412	{"UL2_CH1", "I2S0_CH1 Switch", "I2S0"},1413	{"UL2_CH2", "I2S0_CH2 Switch", "I2S0"},1414	{"UL2_CH1", "I2S2_CH1 Switch", "I2S2"},1415	{"UL2_CH2", "I2S2_CH2 Switch", "I2S2"},1416 1417	{"UL2_CH1", "PCM_1_CAP_CH1 Switch", "PCM 1 Capture"},1418	{"UL2_CH2", "PCM_1_CAP_CH2 Switch", "PCM 1 Capture"},1419 1420	{"UL2_CH1", "CONNSYS_I2S_CH1 Switch", "Connsys I2S"},1421	{"UL2_CH2", "CONNSYS_I2S_CH2 Switch", "Connsys I2S"},1422 1423	{"UL2_CH1", "SRC_1_OUT_CH1 Switch", "HW_SRC_1_Out"},1424	{"UL2_CH2", "SRC_1_OUT_CH2 Switch", "HW_SRC_1_Out"},1425 1426	{"UL3", NULL, "UL3_CH1"},1427	{"UL3", NULL, "UL3_CH2"},1428	{"UL3_CH1", "CONNSYS_I2S_CH1 Switch", "Connsys I2S"},1429	{"UL3_CH2", "CONNSYS_I2S_CH2 Switch", "Connsys I2S"},1430 1431	{"UL4", NULL, "UL4_CH1"},1432	{"UL4", NULL, "UL4_CH2"},1433	{"UL4_CH1", "ADDA_UL_CH1 Switch", "ADDA_UL_Mux"},1434	{"UL4_CH2", "ADDA_UL_CH2 Switch", "ADDA_UL_Mux"},1435	{"UL4_CH1", "I2S0_CH1 Switch", "I2S0"},1436	{"UL4_CH2", "I2S0_CH2 Switch", "I2S0"},1437 1438	{"UL5", NULL, "UL5_IN_MUX"},1439	{"UL5_IN_MUX", "UL5_IN_FROM_Normal", "UL5_2CH"},1440	{"UL5_IN_MUX", "UL5_IN_FROM_CM1", "HW_CM1"},1441	{"UL5_2CH", NULL, "UL5_CH1"},1442	{"UL5_2CH", NULL, "UL5_CH2"},1443	{"UL5_CH1", "ADDA_UL_CH1 Switch", "ADDA_UL_Mux"},1444	{"UL5_CH2", "ADDA_UL_CH2 Switch", "ADDA_UL_Mux"},1445	{"HW_CM1", NULL, "CM1_EN"},1446	{"HW_CM1", NULL, "HW_CM1_CH1"},1447	{"HW_CM1", NULL, "HW_CM1_CH2"},1448	{"HW_CM1", NULL, "HW_CM1_CH3"},1449	{"HW_CM1", NULL, "HW_CM1_CH4"},1450	{"HW_CM1", NULL, "HW_CM1_CH5"},1451	{"HW_CM1", NULL, "HW_CM1_CH6"},1452	{"HW_CM1", NULL, "HW_CM1_CH7"},1453	{"HW_CM1", NULL, "HW_CM1_CH8"},1454	{"HW_CM1", NULL, "HW_CM1_CH9"},1455	{"HW_CM1", NULL, "HW_CM1_CH10"},1456	{"HW_CM1", NULL, "HW_CM1_CH11"},1457	{"HW_CM1", NULL, "HW_CM1_CH12"},1458	{"HW_CM1_CH1", "TDM_IN_CH1 Switch", "TDM IN"},1459	{"HW_CM1_CH2", "TDM_IN_CH2 Switch", "TDM IN"},1460	{"HW_CM1_CH3", "TDM_IN_CH3 Switch", "TDM IN"},1461	{"HW_CM1_CH4", "TDM_IN_CH4 Switch", "TDM IN"},1462	{"HW_CM1_CH5", "TDM_IN_CH5 Switch", "TDM IN"},1463	{"HW_CM1_CH6", "TDM_IN_CH6 Switch", "TDM IN"},1464	{"HW_CM1_CH7", "TDM_IN_CH7 Switch", "TDM IN"},1465	{"HW_CM1_CH8", "TDM_IN_CH8 Switch", "TDM IN"},1466	{"HW_CM1_CH9", "DL1_CH1 Switch", "Hostless_UL5 UL"},1467	{"HW_CM1_CH10", "DL1_CH2 Switch", "Hostless_UL5 UL"},1468 1469	{"HW_CM1_CH3", "DL1_CH1 Switch", "Hostless_UL5 UL"},1470	{"HW_CM1_CH4", "DL1_CH2 Switch", "Hostless_UL5 UL"},1471 1472	{"HW_CM1_CH3", "DL3_CH1 Switch", "Hostless_UL5 UL"},1473	{"HW_CM1_CH4", "DL3_CH2 Switch", "Hostless_UL5 UL"},1474 1475	{"HW_CM1_CH5", "HW_SRC1_OUT_CH1 Switch", "HW_SRC_1_Out"},1476	{"HW_CM1_CH6", "HW_SRC1_OUT_CH2 Switch", "HW_SRC_1_Out"},1477 1478	{"HW_CM1_CH9", "DL12_CH1 Switch", "Hostless_UL5 UL"},1479	{"HW_CM1_CH10", "DL12_CH2 Switch", "Hostless_UL5 UL"},1480	{"HW_CM1_CH11", "DL12_CH3 Switch", "Hostless_UL5 UL"},1481	{"HW_CM1_CH12", "DL12_CH4 Switch", "Hostless_UL5 UL"},1482 1483	{"Hostless_UL5 UL", NULL, "UL5_VIRTUAL_INPUT"},1484 1485	{"UL6", NULL, "UL6_CH1"},1486	{"UL6", NULL, "UL6_CH2"},1487 1488	{"UL6_CH1", "ADDA_UL_CH1 Switch", "ADDA_UL_Mux"},1489	{"UL6_CH2", "ADDA_UL_CH2 Switch", "ADDA_UL_Mux"},1490	{"UL6_CH1", "DL1_CH1 Switch", "Hostless_UL6 UL"},1491	{"UL6_CH2", "DL1_CH2 Switch", "Hostless_UL6 UL"},1492	{"UL6_CH1", "DL2_CH1 Switch", "Hostless_UL6 UL"},1493	{"UL6_CH2", "DL2_CH2 Switch", "Hostless_UL6 UL"},1494	{"UL6_CH1", "DL12_CH1 Switch", "Hostless_UL6 UL"},1495	{"UL6_CH2", "DL12_CH2 Switch", "Hostless_UL6 UL"},1496	{"UL6_CH1", "DL6_CH1 Switch", "Hostless_UL6 UL"},1497	{"UL6_CH2", "DL6_CH2 Switch", "Hostless_UL6 UL"},1498	{"UL6_CH1", "DL3_CH1 Switch", "Hostless_UL6 UL"},1499	{"UL6_CH2", "DL3_CH2 Switch", "Hostless_UL6 UL"},1500	{"UL6_CH1", "DL4_CH1 Switch", "Hostless_UL6 UL"},1501	{"UL6_CH2", "DL4_CH2 Switch", "Hostless_UL6 UL"},1502	{"Hostless_UL6 UL", NULL, "UL6_VIRTUAL_INPUT"},1503	{"UL6_CH1", "PCM_1_CAP_CH1 Switch", "PCM 1 Capture"},1504	{"UL6_CH2", "PCM_1_CAP_CH2 Switch", "PCM 1 Capture"},1505	{"UL6_CH1", "GAIN1_OUT_CH1 Switch", "HW Gain 1 Out"},1506	{"UL6_CH2", "GAIN1_OUT_CH2 Switch", "HW Gain 1 Out"},1507 1508	{"UL7", NULL, "UL7_CH1"},1509	{"UL7", NULL, "UL7_CH2"},1510	{"UL7_CH1", "ADDA_UL_CH1 Switch", "ADDA_UL_Mux"},1511	{"UL7_CH2", "ADDA_UL_CH2 Switch", "ADDA_UL_Mux"},1512	{"UL7_CH1", "HW_GAIN2_OUT_CH1 Switch", "HW Gain 2 Out"},1513	{"UL7_CH2", "HW_GAIN2_OUT_CH2 Switch", "HW Gain 2 Out"},1514	{"UL7_CH1", "HW_SRC_2_OUT_CH1 Switch", "HW_SRC_2_Out"},1515	{"UL7_CH2", "HW_SRC_2_OUT_CH2 Switch", "HW_SRC_2_Out"},1516 1517	{"UL8", NULL, "UL8_CH1"},1518	{"UL8", NULL, "UL8_CH2"},1519	{"UL8_CH1", "ADDA_UL_CH1 Switch", "ADDA_UL_Mux"},1520	{"UL8_CH2", "ADDA_UL_CH2 Switch", "ADDA_UL_Mux"},1521 1522	{"HW_GAIN2_IN_CH1", "ADDA_UL_CH1 Switch", "ADDA_UL_Mux"},1523	{"HW_GAIN2_IN_CH2", "ADDA_UL_CH2 Switch", "ADDA_UL_Mux"},1524};1525 1526static const struct mtk_base_memif_data memif_data[MT8186_MEMIF_NUM] = {1527	[MT8186_MEMIF_DL1] = {1528		.name = "DL1",1529		.id = MT8186_MEMIF_DL1,1530		.reg_ofs_base = AFE_DL1_BASE,1531		.reg_ofs_cur = AFE_DL1_CUR,1532		.reg_ofs_end = AFE_DL1_END,1533		.reg_ofs_base_msb = AFE_DL1_BASE_MSB,1534		.reg_ofs_cur_msb = AFE_DL1_CUR_MSB,1535		.reg_ofs_end_msb = AFE_DL1_END_MSB,1536		.fs_reg = AFE_DL1_CON0,1537		.fs_shift = DL1_MODE_SFT,1538		.fs_maskbit = DL1_MODE_MASK,1539		.mono_reg = AFE_DL1_CON0,1540		.mono_shift = DL1_MONO_SFT,1541		.enable_reg = AFE_DAC_CON0,1542		.enable_shift = DL1_ON_SFT,1543		.hd_reg = AFE_DL1_CON0,1544		.hd_shift = DL1_HD_MODE_SFT,1545		.hd_align_reg = AFE_DL1_CON0,1546		.hd_align_mshift = DL1_HALIGN_SFT,1547		.agent_disable_reg = -1,1548		.agent_disable_shift = -1,1549		.msb_reg = -1,1550		.msb_shift = -1,1551		.pbuf_reg = AFE_DL1_CON0,1552		.pbuf_mask = DL1_PBUF_SIZE_MASK,1553		.pbuf_shift = DL1_PBUF_SIZE_SFT,1554		.minlen_reg = AFE_DL1_CON0,1555		.minlen_mask = DL1_MINLEN_MASK,1556		.minlen_shift = DL1_MINLEN_SFT,1557	},1558	[MT8186_MEMIF_DL12] = {1559		.name = "DL12",1560		.id = MT8186_MEMIF_DL12,1561		.reg_ofs_base = AFE_DL12_BASE,1562		.reg_ofs_cur = AFE_DL12_CUR,1563		.reg_ofs_end = AFE_DL12_END,1564		.reg_ofs_base_msb = AFE_DL12_BASE_MSB,1565		.reg_ofs_cur_msb = AFE_DL12_CUR_MSB,1566		.reg_ofs_end_msb = AFE_DL12_END_MSB,1567		.fs_reg = AFE_DL12_CON0,1568		.fs_shift = DL12_MODE_SFT,1569		.fs_maskbit = DL12_MODE_MASK,1570		.mono_reg = AFE_DL12_CON0,1571		.mono_shift = DL12_MONO_SFT,1572		.quad_ch_reg = AFE_DL12_CON0,1573		.quad_ch_mask = DL12_4CH_EN_MASK,1574		.quad_ch_shift = DL12_4CH_EN_SFT,1575		.enable_reg = AFE_DAC_CON0,1576		.enable_shift = DL12_ON_SFT,1577		.hd_reg = AFE_DL12_CON0,1578		.hd_shift = DL12_HD_MODE_SFT,1579		.hd_align_reg = AFE_DL12_CON0,1580		.hd_align_mshift = DL12_HALIGN_SFT,1581		.agent_disable_reg = -1,1582		.agent_disable_shift = -1,1583		.msb_reg = -1,1584		.msb_shift = -1,1585		.pbuf_reg = AFE_DL12_CON0,1586		.pbuf_mask = DL12_PBUF_SIZE_MASK,1587		.pbuf_shift = DL12_PBUF_SIZE_SFT,1588		.minlen_reg = AFE_DL12_CON0,1589		.minlen_mask = DL12_MINLEN_MASK,1590		.minlen_shift = DL12_MINLEN_SFT,1591	},1592	[MT8186_MEMIF_DL2] = {1593		.name = "DL2",1594		.id = MT8186_MEMIF_DL2,1595		.reg_ofs_base = AFE_DL2_BASE,1596		.reg_ofs_cur = AFE_DL2_CUR,1597		.reg_ofs_end = AFE_DL2_END,1598		.reg_ofs_base_msb = AFE_DL2_BASE_MSB,1599		.reg_ofs_cur_msb = AFE_DL2_CUR_MSB,1600		.reg_ofs_end_msb = AFE_DL2_END_MSB,1601		.fs_reg = AFE_DL2_CON0,1602		.fs_shift = DL2_MODE_SFT,1603		.fs_maskbit = DL2_MODE_MASK,1604		.mono_reg = AFE_DL2_CON0,1605		.mono_shift = DL2_MONO_SFT,1606		.enable_reg = AFE_DAC_CON0,1607		.enable_shift = DL2_ON_SFT,1608		.hd_reg = AFE_DL2_CON0,1609		.hd_shift = DL2_HD_MODE_SFT,1610		.hd_align_reg = AFE_DL2_CON0,1611		.hd_align_mshift = DL2_HALIGN_SFT,1612		.agent_disable_reg = -1,1613		.agent_disable_shift = -1,1614		.msb_reg = -1,1615		.msb_shift = -1,1616		.pbuf_reg = AFE_DL2_CON0,1617		.pbuf_mask = DL2_PBUF_SIZE_MASK,1618		.pbuf_shift = DL2_PBUF_SIZE_SFT,1619		.minlen_reg = AFE_DL2_CON0,1620		.minlen_mask = DL2_MINLEN_MASK,1621		.minlen_shift = DL2_MINLEN_SFT,1622	},1623	[MT8186_MEMIF_DL3] = {1624		.name = "DL3",1625		.id = MT8186_MEMIF_DL3,1626		.reg_ofs_base = AFE_DL3_BASE,1627		.reg_ofs_cur = AFE_DL3_CUR,1628		.reg_ofs_end = AFE_DL3_END,1629		.reg_ofs_base_msb = AFE_DL3_BASE_MSB,1630		.reg_ofs_cur_msb = AFE_DL3_CUR_MSB,1631		.reg_ofs_end_msb = AFE_DL3_END_MSB,1632		.fs_reg = AFE_DL3_CON0,1633		.fs_shift = DL3_MODE_SFT,1634		.fs_maskbit = DL3_MODE_MASK,1635		.mono_reg = AFE_DL3_CON0,1636		.mono_shift = DL3_MONO_SFT,1637		.enable_reg = AFE_DAC_CON0,1638		.enable_shift = DL3_ON_SFT,1639		.hd_reg = AFE_DL3_CON0,1640		.hd_shift = DL3_HD_MODE_SFT,1641		.hd_align_reg = AFE_DL3_CON0,1642		.hd_align_mshift = DL3_HALIGN_SFT,1643		.agent_disable_reg = -1,1644		.agent_disable_shift = -1,1645		.msb_reg = -1,1646		.msb_shift = -1,1647		.pbuf_reg = AFE_DL3_CON0,1648		.pbuf_mask = DL3_PBUF_SIZE_MASK,1649		.pbuf_shift = DL3_PBUF_SIZE_SFT,1650		.minlen_reg = AFE_DL3_CON0,1651		.minlen_mask = DL3_MINLEN_MASK,1652		.minlen_shift = DL3_MINLEN_SFT,1653	},1654	[MT8186_MEMIF_DL4] = {1655		.name = "DL4",1656		.id = MT8186_MEMIF_DL4,1657		.reg_ofs_base = AFE_DL4_BASE,1658		.reg_ofs_cur = AFE_DL4_CUR,1659		.reg_ofs_end = AFE_DL4_END,1660		.reg_ofs_base_msb = AFE_DL4_BASE_MSB,1661		.reg_ofs_cur_msb = AFE_DL4_CUR_MSB,1662		.reg_ofs_end_msb = AFE_DL4_END_MSB,1663		.fs_reg = AFE_DL4_CON0,1664		.fs_shift = DL4_MODE_SFT,1665		.fs_maskbit = DL4_MODE_MASK,1666		.mono_reg = AFE_DL4_CON0,1667		.mono_shift = DL4_MONO_SFT,1668		.enable_reg = AFE_DAC_CON0,1669		.enable_shift = DL4_ON_SFT,1670		.hd_reg = AFE_DL4_CON0,1671		.hd_shift = DL4_HD_MODE_SFT,1672		.hd_align_reg = AFE_DL4_CON0,1673		.hd_align_mshift = DL4_HALIGN_SFT,1674		.agent_disable_reg = -1,1675		.agent_disable_shift = -1,1676		.msb_reg = -1,1677		.msb_shift = -1,1678		.pbuf_reg = AFE_DL4_CON0,1679		.pbuf_mask = DL4_PBUF_SIZE_MASK,1680		.pbuf_shift = DL4_PBUF_SIZE_SFT,1681		.minlen_reg = AFE_DL4_CON0,1682		.minlen_mask = DL4_MINLEN_MASK,1683		.minlen_shift = DL4_MINLEN_SFT,1684	},1685	[MT8186_MEMIF_DL5] = {1686		.name = "DL5",1687		.id = MT8186_MEMIF_DL5,1688		.reg_ofs_base = AFE_DL5_BASE,1689		.reg_ofs_cur = AFE_DL5_CUR,1690		.reg_ofs_end = AFE_DL5_END,1691		.reg_ofs_base_msb = AFE_DL5_BASE_MSB,1692		.reg_ofs_cur_msb = AFE_DL5_CUR_MSB,1693		.reg_ofs_end_msb = AFE_DL5_END_MSB,1694		.fs_reg = AFE_DL5_CON0,1695		.fs_shift = DL5_MODE_SFT,1696		.fs_maskbit = DL5_MODE_MASK,1697		.mono_reg = AFE_DL5_CON0,1698		.mono_shift = DL5_MONO_SFT,1699		.enable_reg = AFE_DAC_CON0,1700		.enable_shift = DL5_ON_SFT,1701		.hd_reg = AFE_DL5_CON0,1702		.hd_shift = DL5_HD_MODE_SFT,1703		.hd_align_reg = AFE_DL5_CON0,1704		.hd_align_mshift = DL5_HALIGN_SFT,1705		.agent_disable_reg = -1,1706		.agent_disable_shift = -1,1707		.msb_reg = -1,1708		.msb_shift = -1,1709		.pbuf_reg = AFE_DL5_CON0,1710		.pbuf_mask = DL5_PBUF_SIZE_MASK,1711		.pbuf_shift = DL5_PBUF_SIZE_SFT,1712		.minlen_reg = AFE_DL5_CON0,1713		.minlen_mask = DL5_MINLEN_MASK,1714		.minlen_shift = DL5_MINLEN_SFT,1715	},1716	[MT8186_MEMIF_DL6] = {1717		.name = "DL6",1718		.id = MT8186_MEMIF_DL6,1719		.reg_ofs_base = AFE_DL6_BASE,1720		.reg_ofs_cur = AFE_DL6_CUR,1721		.reg_ofs_end = AFE_DL6_END,1722		.reg_ofs_base_msb = AFE_DL6_BASE_MSB,1723		.reg_ofs_cur_msb = AFE_DL6_CUR_MSB,1724		.reg_ofs_end_msb = AFE_DL6_END_MSB,1725		.fs_reg = AFE_DL6_CON0,1726		.fs_shift = DL6_MODE_SFT,1727		.fs_maskbit = DL6_MODE_MASK,1728		.mono_reg = AFE_DL6_CON0,1729		.mono_shift = DL6_MONO_SFT,1730		.enable_reg = AFE_DAC_CON0,1731		.enable_shift = DL6_ON_SFT,1732		.hd_reg = AFE_DL6_CON0,1733		.hd_shift = DL6_HD_MODE_SFT,1734		.hd_align_reg = AFE_DL6_CON0,1735		.hd_align_mshift = DL6_HALIGN_SFT,1736		.agent_disable_reg = -1,1737		.agent_disable_shift = -1,1738		.msb_reg = -1,1739		.msb_shift = -1,1740		.pbuf_reg = AFE_DL6_CON0,1741		.pbuf_mask = DL6_PBUF_SIZE_MASK,1742		.pbuf_shift = DL6_PBUF_SIZE_SFT,1743		.minlen_reg = AFE_DL6_CON0,1744		.minlen_mask = DL6_MINLEN_MASK,1745		.minlen_shift = DL6_MINLEN_SFT,1746	},1747	[MT8186_MEMIF_DL7] = {1748		.name = "DL7",1749		.id = MT8186_MEMIF_DL7,1750		.reg_ofs_base = AFE_DL7_BASE,1751		.reg_ofs_cur = AFE_DL7_CUR,1752		.reg_ofs_end = AFE_DL7_END,1753		.reg_ofs_base_msb = AFE_DL7_BASE_MSB,1754		.reg_ofs_cur_msb = AFE_DL7_CUR_MSB,1755		.reg_ofs_end_msb = AFE_DL7_END_MSB,1756		.fs_reg = AFE_DL7_CON0,1757		.fs_shift = DL7_MODE_SFT,1758		.fs_maskbit = DL7_MODE_MASK,1759		.mono_reg = AFE_DL7_CON0,1760		.mono_shift = DL7_MONO_SFT,1761		.enable_reg = AFE_DAC_CON0,1762		.enable_shift = DL7_ON_SFT,1763		.hd_reg = AFE_DL7_CON0,1764		.hd_shift = DL7_HD_MODE_SFT,1765		.hd_align_reg = AFE_DL7_CON0,1766		.hd_align_mshift = DL7_HALIGN_SFT,1767		.agent_disable_reg = -1,1768		.agent_disable_shift = -1,1769		.msb_reg = -1,1770		.msb_shift = -1,1771		.pbuf_reg = AFE_DL7_CON0,1772		.pbuf_mask = DL7_PBUF_SIZE_MASK,1773		.pbuf_shift = DL7_PBUF_SIZE_SFT,1774		.minlen_reg = AFE_DL7_CON0,1775		.minlen_mask = DL7_MINLEN_MASK,1776		.minlen_shift = DL7_MINLEN_SFT,1777	},1778	[MT8186_MEMIF_DL8] = {1779		.name = "DL8",1780		.id = MT8186_MEMIF_DL8,1781		.reg_ofs_base = AFE_DL8_BASE,1782		.reg_ofs_cur = AFE_DL8_CUR,1783		.reg_ofs_end = AFE_DL8_END,1784		.reg_ofs_base_msb = AFE_DL8_BASE_MSB,1785		.reg_ofs_cur_msb = AFE_DL8_CUR_MSB,1786		.reg_ofs_end_msb = AFE_DL8_END_MSB,1787		.fs_reg = AFE_DL8_CON0,1788		.fs_shift = DL8_MODE_SFT,1789		.fs_maskbit = DL8_MODE_MASK,1790		.mono_reg = AFE_DL8_CON0,1791		.mono_shift = DL8_MONO_SFT,1792		.enable_reg = AFE_DAC_CON0,1793		.enable_shift = DL8_ON_SFT,1794		.hd_reg = AFE_DL8_CON0,1795		.hd_shift = DL8_HD_MODE_SFT,1796		.hd_align_reg = AFE_DL8_CON0,1797		.hd_align_mshift = DL8_HALIGN_SFT,1798		.agent_disable_reg = -1,1799		.agent_disable_shift = -1,1800		.msb_reg = -1,1801		.msb_shift = -1,1802		.pbuf_reg = AFE_DL8_CON0,1803		.pbuf_mask = DL8_PBUF_SIZE_MASK,1804		.pbuf_shift = DL8_PBUF_SIZE_SFT,1805		.minlen_reg = AFE_DL8_CON0,1806		.minlen_mask = DL8_MINLEN_MASK,1807		.minlen_shift = DL8_MINLEN_SFT,1808	},1809	[MT8186_MEMIF_VUL12] = {1810		.name = "VUL12",1811		.id = MT8186_MEMIF_VUL12,1812		.reg_ofs_base = AFE_VUL12_BASE,1813		.reg_ofs_cur = AFE_VUL12_CUR,1814		.reg_ofs_end = AFE_VUL12_END,1815		.reg_ofs_base_msb = AFE_VUL12_BASE_MSB,1816		.reg_ofs_cur_msb = AFE_VUL12_CUR_MSB,1817		.reg_ofs_end_msb = AFE_VUL12_END_MSB,1818		.fs_reg = AFE_VUL12_CON0,1819		.fs_shift = VUL12_MODE_SFT,1820		.fs_maskbit = VUL12_MODE_MASK,1821		.mono_reg = AFE_VUL12_CON0,1822		.mono_shift = VUL12_MONO_SFT,1823		.quad_ch_reg = AFE_VUL12_CON0,1824		.quad_ch_mask = VUL12_4CH_EN_MASK,1825		.quad_ch_shift = VUL12_4CH_EN_SFT,1826		.enable_reg = AFE_DAC_CON0,1827		.enable_shift = VUL12_ON_SFT,1828		.hd_reg = AFE_VUL12_CON0,1829		.hd_shift = VUL12_HD_MODE_SFT,1830		.hd_align_reg = AFE_VUL12_CON0,1831		.hd_align_mshift = VUL12_HALIGN_SFT,1832		.agent_disable_reg = -1,1833		.agent_disable_shift = -1,1834		.msb_reg = -1,1835		.msb_shift = -1,1836	},1837	[MT8186_MEMIF_VUL2] = {1838		.name = "VUL2",1839		.id = MT8186_MEMIF_VUL2,1840		.reg_ofs_base = AFE_VUL2_BASE,1841		.reg_ofs_cur = AFE_VUL2_CUR,1842		.reg_ofs_end = AFE_VUL2_END,1843		.reg_ofs_base_msb = AFE_VUL2_BASE_MSB,1844		.reg_ofs_cur_msb = AFE_VUL2_CUR_MSB,1845		.reg_ofs_end_msb = AFE_VUL2_END_MSB,1846		.fs_reg = AFE_VUL2_CON0,1847		.fs_shift = VUL2_MODE_SFT,1848		.fs_maskbit = VUL2_MODE_MASK,1849		.mono_reg = AFE_VUL2_CON0,1850		.mono_shift = VUL2_MONO_SFT,1851		.enable_reg = AFE_DAC_CON0,1852		.enable_shift = VUL2_ON_SFT,1853		.hd_reg = AFE_VUL2_CON0,1854		.hd_shift = VUL2_HD_MODE_SFT,1855		.hd_align_reg = AFE_VUL2_CON0,1856		.hd_align_mshift = VUL2_HALIGN_SFT,1857		.agent_disable_reg = -1,1858		.agent_disable_shift = -1,1859		.msb_reg = -1,1860		.msb_shift = -1,1861	},1862	[MT8186_MEMIF_AWB] = {1863		.name = "AWB",1864		.id = MT8186_MEMIF_AWB,1865		.reg_ofs_base = AFE_AWB_BASE,1866		.reg_ofs_cur = AFE_AWB_CUR,1867		.reg_ofs_end = AFE_AWB_END,1868		.reg_ofs_base_msb = AFE_AWB_BASE_MSB,1869		.reg_ofs_cur_msb = AFE_AWB_CUR_MSB,1870		.reg_ofs_end_msb = AFE_AWB_END_MSB,1871		.fs_reg = AFE_AWB_CON0,1872		.fs_shift = AWB_MODE_SFT,1873		.fs_maskbit = AWB_MODE_MASK,1874		.mono_reg = AFE_AWB_CON0,1875		.mono_shift = AWB_MONO_SFT,1876		.enable_reg = AFE_DAC_CON0,1877		.enable_shift = AWB_ON_SFT,1878		.hd_reg = AFE_AWB_CON0,1879		.hd_shift = AWB_HD_MODE_SFT,1880		.hd_align_reg = AFE_AWB_CON0,1881		.hd_align_mshift = AWB_HALIGN_SFT,1882		.agent_disable_reg = -1,1883		.agent_disable_shift = -1,1884		.msb_reg = -1,1885		.msb_shift = -1,1886	},1887	[MT8186_MEMIF_AWB2] = {1888		.name = "AWB2",1889		.id = MT8186_MEMIF_AWB2,1890		.reg_ofs_base = AFE_AWB2_BASE,1891		.reg_ofs_cur = AFE_AWB2_CUR,1892		.reg_ofs_end = AFE_AWB2_END,1893		.reg_ofs_base_msb = AFE_AWB2_BASE_MSB,1894		.reg_ofs_cur_msb = AFE_AWB2_CUR_MSB,1895		.reg_ofs_end_msb = AFE_AWB2_END_MSB,1896		.fs_reg = AFE_AWB2_CON0,1897		.fs_shift = AWB2_MODE_SFT,1898		.fs_maskbit = AWB2_MODE_MASK,1899		.mono_reg = AFE_AWB2_CON0,1900		.mono_shift = AWB2_MONO_SFT,1901		.enable_reg = AFE_DAC_CON0,1902		.enable_shift = AWB2_ON_SFT,1903		.hd_reg = AFE_AWB2_CON0,1904		.hd_shift = AWB2_HD_MODE_SFT,1905		.hd_align_reg = AFE_AWB2_CON0,1906		.hd_align_mshift = AWB2_HALIGN_SFT,1907		.agent_disable_reg = -1,1908		.agent_disable_shift = -1,1909		.msb_reg = -1,1910		.msb_shift = -1,1911	},1912	[MT8186_MEMIF_VUL3] = {1913		.name = "VUL3",1914		.id = MT8186_MEMIF_VUL3,1915		.reg_ofs_base = AFE_VUL3_BASE,1916		.reg_ofs_cur = AFE_VUL3_CUR,1917		.reg_ofs_end = AFE_VUL3_END,1918		.reg_ofs_base_msb = AFE_VUL3_BASE_MSB,1919		.reg_ofs_cur_msb = AFE_VUL3_CUR_MSB,1920		.reg_ofs_end_msb = AFE_VUL3_END_MSB,1921		.fs_reg = AFE_VUL3_CON0,1922		.fs_shift = VUL3_MODE_SFT,1923		.fs_maskbit = VUL3_MODE_MASK,1924		.mono_reg = AFE_VUL3_CON0,1925		.mono_shift = VUL3_MONO_SFT,1926		.enable_reg = AFE_DAC_CON0,1927		.enable_shift = VUL3_ON_SFT,1928		.hd_reg = AFE_VUL3_CON0,1929		.hd_shift = VUL3_HD_MODE_SFT,1930		.hd_align_reg = AFE_VUL3_CON0,1931		.hd_align_mshift = VUL3_HALIGN_SFT,1932		.agent_disable_reg = -1,1933		.agent_disable_shift = -1,1934		.msb_reg = -1,1935		.msb_shift = -1,1936	},1937	[MT8186_MEMIF_VUL4] = {1938		.name = "VUL4",1939		.id = MT8186_MEMIF_VUL4,1940		.reg_ofs_base = AFE_VUL4_BASE,1941		.reg_ofs_cur = AFE_VUL4_CUR,1942		.reg_ofs_end = AFE_VUL4_END,1943		.reg_ofs_base_msb = AFE_VUL4_BASE_MSB,1944		.reg_ofs_cur_msb = AFE_VUL4_CUR_MSB,1945		.reg_ofs_end_msb = AFE_VUL4_END_MSB,1946		.fs_reg = AFE_VUL4_CON0,1947		.fs_shift = VUL4_MODE_SFT,1948		.fs_maskbit = VUL4_MODE_MASK,1949		.mono_reg = AFE_VUL4_CON0,1950		.mono_shift = VUL4_MONO_SFT,1951		.enable_reg = AFE_DAC_CON0,1952		.enable_shift = VUL4_ON_SFT,1953		.hd_reg = AFE_VUL4_CON0,1954		.hd_shift = VUL4_HD_MODE_SFT,1955		.hd_align_reg = AFE_VUL4_CON0,1956		.hd_align_mshift = VUL4_HALIGN_SFT,1957		.agent_disable_reg = -1,1958		.agent_disable_shift = -1,1959		.msb_reg = -1,1960		.msb_shift = -1,1961	},1962	[MT8186_MEMIF_VUL5] = {1963		.name = "VUL5",1964		.id = MT8186_MEMIF_VUL5,1965		.reg_ofs_base = AFE_VUL5_BASE,1966		.reg_ofs_cur = AFE_VUL5_CUR,1967		.reg_ofs_end = AFE_VUL5_END,1968		.reg_ofs_base_msb = AFE_VUL5_BASE_MSB,1969		.reg_ofs_cur_msb = AFE_VUL5_CUR_MSB,1970		.reg_ofs_end_msb = AFE_VUL5_END_MSB,1971		.fs_reg = AFE_VUL5_CON0,1972		.fs_shift = VUL5_MODE_SFT,1973		.fs_maskbit = VUL5_MODE_MASK,1974		.mono_reg = AFE_VUL5_CON0,1975		.mono_shift = VUL5_MONO_SFT,1976		.enable_reg = AFE_DAC_CON0,1977		.enable_shift = VUL5_ON_SFT,1978		.hd_reg = AFE_VUL5_CON0,1979		.hd_shift = VUL5_HD_MODE_SFT,1980		.hd_align_reg = AFE_VUL5_CON0,1981		.hd_align_mshift = VUL5_HALIGN_SFT,1982		.agent_disable_reg = -1,1983		.agent_disable_shift = -1,1984		.msb_reg = -1,1985		.msb_shift = -1,1986	},1987	[MT8186_MEMIF_VUL6] = {1988		.name = "VUL6",1989		.id = MT8186_MEMIF_VUL6,1990		.reg_ofs_base = AFE_VUL6_BASE,1991		.reg_ofs_cur = AFE_VUL6_CUR,1992		.reg_ofs_end = AFE_VUL6_END,1993		.reg_ofs_base_msb = AFE_VUL6_BASE_MSB,1994		.reg_ofs_cur_msb = AFE_VUL6_CUR_MSB,1995		.reg_ofs_end_msb = AFE_VUL6_END_MSB,1996		.fs_reg = AFE_VUL6_CON0,1997		.fs_shift = VUL6_MODE_SFT,1998		.fs_maskbit = VUL6_MODE_MASK,1999		.mono_reg = AFE_VUL6_CON0,2000		.mono_shift = VUL6_MONO_SFT,2001		.enable_reg = AFE_DAC_CON0,2002		.enable_shift = VUL6_ON_SFT,2003		.hd_reg = AFE_VUL6_CON0,2004		.hd_shift = VUL6_HD_MODE_SFT,2005		.hd_align_reg = AFE_VUL6_CON0,2006		.hd_align_mshift = VUL6_HALIGN_SFT,2007		.agent_disable_reg = -1,2008		.agent_disable_shift = -1,2009		.msb_reg = -1,2010		.msb_shift = -1,2011	},2012};2013 2014static const struct mtk_base_irq_data irq_data[MT8186_IRQ_NUM] = {2015	[MT8186_IRQ_0] = {2016		.id = MT8186_IRQ_0,2017		.irq_cnt_reg = AFE_IRQ_MCU_CNT0,2018		.irq_cnt_shift = AFE_IRQ_CNT_SHIFT,2019		.irq_cnt_maskbit = AFE_IRQ_CNT_MASK,2020		.irq_fs_reg = AFE_IRQ_MCU_CON1,2021		.irq_fs_shift = IRQ0_MCU_MODE_SFT,2022		.irq_fs_maskbit = IRQ0_MCU_MODE_MASK,2023		.irq_en_reg = AFE_IRQ_MCU_CON0,2024		.irq_en_shift = IRQ0_MCU_ON_SFT,2025		.irq_clr_reg = AFE_IRQ_MCU_CLR,2026		.irq_clr_shift = IRQ0_MCU_CLR_SFT,2027	},2028	[MT8186_IRQ_1] = {2029		.id = MT8186_IRQ_1,2030		.irq_cnt_reg = AFE_IRQ_MCU_CNT1,2031		.irq_cnt_shift = AFE_IRQ_CNT_SHIFT,2032		.irq_cnt_maskbit = AFE_IRQ_CNT_MASK,2033		.irq_fs_reg = AFE_IRQ_MCU_CON1,2034		.irq_fs_shift = IRQ1_MCU_MODE_SFT,2035		.irq_fs_maskbit = IRQ1_MCU_MODE_MASK,2036		.irq_en_reg = AFE_IRQ_MCU_CON0,2037		.irq_en_shift = IRQ1_MCU_ON_SFT,2038		.irq_clr_reg = AFE_IRQ_MCU_CLR,2039		.irq_clr_shift = IRQ1_MCU_CLR_SFT,2040	},2041	[MT8186_IRQ_2] = {2042		.id = MT8186_IRQ_2,2043		.irq_cnt_reg = AFE_IRQ_MCU_CNT2,2044		.irq_cnt_shift = AFE_IRQ_CNT_SHIFT,2045		.irq_cnt_maskbit = AFE_IRQ_CNT_MASK,2046		.irq_fs_reg = AFE_IRQ_MCU_CON1,2047		.irq_fs_shift = IRQ2_MCU_MODE_SFT,2048		.irq_fs_maskbit = IRQ2_MCU_MODE_MASK,2049		.irq_en_reg = AFE_IRQ_MCU_CON0,2050		.irq_en_shift = IRQ2_MCU_ON_SFT,2051		.irq_clr_reg = AFE_IRQ_MCU_CLR,2052		.irq_clr_shift = IRQ2_MCU_CLR_SFT,2053	},2054	[MT8186_IRQ_3] = {2055		.id = MT8186_IRQ_3,2056		.irq_cnt_reg = AFE_IRQ_MCU_CNT3,2057		.irq_cnt_shift = AFE_IRQ_CNT_SHIFT,2058		.irq_cnt_maskbit = AFE_IRQ_CNT_MASK,2059		.irq_fs_reg = AFE_IRQ_MCU_CON1,2060		.irq_fs_shift = IRQ3_MCU_MODE_SFT,2061		.irq_fs_maskbit = IRQ3_MCU_MODE_MASK,2062		.irq_en_reg = AFE_IRQ_MCU_CON0,2063		.irq_en_shift = IRQ3_MCU_ON_SFT,2064		.irq_clr_reg = AFE_IRQ_MCU_CLR,2065		.irq_clr_shift = IRQ3_MCU_CLR_SFT,2066	},2067	[MT8186_IRQ_4] = {2068		.id = MT8186_IRQ_4,2069		.irq_cnt_reg = AFE_IRQ_MCU_CNT4,2070		.irq_cnt_shift = AFE_IRQ_CNT_SHIFT,2071		.irq_cnt_maskbit = AFE_IRQ_CNT_MASK,2072		.irq_fs_reg = AFE_IRQ_MCU_CON1,2073		.irq_fs_shift = IRQ4_MCU_MODE_SFT,2074		.irq_fs_maskbit = IRQ4_MCU_MODE_MASK,2075		.irq_en_reg = AFE_IRQ_MCU_CON0,2076		.irq_en_shift = IRQ4_MCU_ON_SFT,2077		.irq_clr_reg = AFE_IRQ_MCU_CLR,2078		.irq_clr_shift = IRQ4_MCU_CLR_SFT,2079	},2080	[MT8186_IRQ_5] = {2081		.id = MT8186_IRQ_5,2082		.irq_cnt_reg = AFE_IRQ_MCU_CNT5,2083		.irq_cnt_shift = AFE_IRQ_CNT_SHIFT,2084		.irq_cnt_maskbit = AFE_IRQ_CNT_MASK,2085		.irq_fs_reg = AFE_IRQ_MCU_CON1,2086		.irq_fs_shift = IRQ5_MCU_MODE_SFT,2087		.irq_fs_maskbit = IRQ5_MCU_MODE_MASK,2088		.irq_en_reg = AFE_IRQ_MCU_CON0,2089		.irq_en_shift = IRQ5_MCU_ON_SFT,2090		.irq_clr_reg = AFE_IRQ_MCU_CLR,2091		.irq_clr_shift = IRQ5_MCU_CLR_SFT,2092	},2093	[MT8186_IRQ_6] = {2094		.id = MT8186_IRQ_6,2095		.irq_cnt_reg = AFE_IRQ_MCU_CNT6,2096		.irq_cnt_shift = AFE_IRQ_CNT_SHIFT,2097		.irq_cnt_maskbit = AFE_IRQ_CNT_MASK,2098		.irq_fs_reg = AFE_IRQ_MCU_CON1,2099		.irq_fs_shift = IRQ6_MCU_MODE_SFT,2100		.irq_fs_maskbit = IRQ6_MCU_MODE_MASK,2101		.irq_en_reg = AFE_IRQ_MCU_CON0,2102		.irq_en_shift = IRQ6_MCU_ON_SFT,2103		.irq_clr_reg = AFE_IRQ_MCU_CLR,2104		.irq_clr_shift = IRQ6_MCU_CLR_SFT,2105	},2106	[MT8186_IRQ_7] = {2107		.id = MT8186_IRQ_7,2108		.irq_cnt_reg = AFE_IRQ_MCU_CNT7,2109		.irq_cnt_shift = AFE_IRQ_CNT_SHIFT,2110		.irq_cnt_maskbit = AFE_IRQ_CNT_MASK,2111		.irq_fs_reg = AFE_IRQ_MCU_CON1,2112		.irq_fs_shift = IRQ7_MCU_MODE_SFT,2113		.irq_fs_maskbit = IRQ7_MCU_MODE_MASK,2114		.irq_en_reg = AFE_IRQ_MCU_CON0,2115		.irq_en_shift = IRQ7_MCU_ON_SFT,2116		.irq_clr_reg = AFE_IRQ_MCU_CLR,2117		.irq_clr_shift = IRQ7_MCU_CLR_SFT,2118	},2119	[MT8186_IRQ_8] = {2120		.id = MT8186_IRQ_8,2121		.irq_cnt_reg = AFE_IRQ_MCU_CNT8,2122		.irq_cnt_shift = AFE_IRQ_CNT_SHIFT,2123		.irq_cnt_maskbit = AFE_IRQ_CNT_MASK,2124		.irq_fs_reg = AFE_IRQ_MCU_CON2,2125		.irq_fs_shift = IRQ8_MCU_MODE_SFT,2126		.irq_fs_maskbit = IRQ8_MCU_MODE_MASK,2127		.irq_en_reg = AFE_IRQ_MCU_CON0,2128		.irq_en_shift = IRQ8_MCU_ON_SFT,2129		.irq_clr_reg = AFE_IRQ_MCU_CLR,2130		.irq_clr_shift = IRQ8_MCU_CLR_SFT,2131	},2132	[MT8186_IRQ_9] = {2133		.id = MT8186_IRQ_9,2134		.irq_cnt_reg = AFE_IRQ_MCU_CNT9,2135		.irq_cnt_shift = AFE_IRQ_CNT_SHIFT,2136		.irq_cnt_maskbit = AFE_IRQ_CNT_MASK,2137		.irq_fs_reg = AFE_IRQ_MCU_CON2,2138		.irq_fs_shift = IRQ9_MCU_MODE_SFT,2139		.irq_fs_maskbit = IRQ9_MCU_MODE_MASK,2140		.irq_en_reg = AFE_IRQ_MCU_CON0,2141		.irq_en_shift = IRQ9_MCU_ON_SFT,2142		.irq_clr_reg = AFE_IRQ_MCU_CLR,2143		.irq_clr_shift = IRQ9_MCU_CLR_SFT,2144	},2145	[MT8186_IRQ_10] = {2146		.id = MT8186_IRQ_10,2147		.irq_cnt_reg = AFE_IRQ_MCU_CNT10,2148		.irq_cnt_shift = AFE_IRQ_CNT_SHIFT,2149		.irq_cnt_maskbit = AFE_IRQ_CNT_MASK,2150		.irq_fs_reg = AFE_IRQ_MCU_CON2,2151		.irq_fs_shift = IRQ10_MCU_MODE_SFT,2152		.irq_fs_maskbit = IRQ10_MCU_MODE_MASK,2153		.irq_en_reg = AFE_IRQ_MCU_CON0,2154		.irq_en_shift = IRQ10_MCU_ON_SFT,2155		.irq_clr_reg = AFE_IRQ_MCU_CLR,2156		.irq_clr_shift = IRQ10_MCU_CLR_SFT,2157	},2158	[MT8186_IRQ_11] = {2159		.id = MT8186_IRQ_11,2160		.irq_cnt_reg = AFE_IRQ_MCU_CNT11,2161		.irq_cnt_shift = AFE_IRQ_CNT_SHIFT,2162		.irq_cnt_maskbit = AFE_IRQ_CNT_MASK,2163		.irq_fs_reg = AFE_IRQ_MCU_CON2,2164		.irq_fs_shift = IRQ11_MCU_MODE_SFT,2165		.irq_fs_maskbit = IRQ11_MCU_MODE_MASK,2166		.irq_en_reg = AFE_IRQ_MCU_CON0,2167		.irq_en_shift = IRQ11_MCU_ON_SFT,2168		.irq_clr_reg = AFE_IRQ_MCU_CLR,2169		.irq_clr_shift = IRQ11_MCU_CLR_SFT,2170	},2171	[MT8186_IRQ_12] = {2172		.id = MT8186_IRQ_12,2173		.irq_cnt_reg = AFE_IRQ_MCU_CNT12,2174		.irq_cnt_shift = AFE_IRQ_CNT_SHIFT,2175		.irq_cnt_maskbit = AFE_IRQ_CNT_MASK,2176		.irq_fs_reg = AFE_IRQ_MCU_CON2,2177		.irq_fs_shift = IRQ12_MCU_MODE_SFT,2178		.irq_fs_maskbit = IRQ12_MCU_MODE_MASK,2179		.irq_en_reg = AFE_IRQ_MCU_CON0,2180		.irq_en_shift = IRQ12_MCU_ON_SFT,2181		.irq_clr_reg = AFE_IRQ_MCU_CLR,2182		.irq_clr_shift = IRQ12_MCU_CLR_SFT,2183	},2184	[MT8186_IRQ_13] = {2185		.id = MT8186_IRQ_13,2186		.irq_cnt_reg = AFE_IRQ_MCU_CNT13,2187		.irq_cnt_shift = AFE_IRQ_CNT_SHIFT,2188		.irq_cnt_maskbit = AFE_IRQ_CNT_MASK,2189		.irq_fs_reg = AFE_IRQ_MCU_CON2,2190		.irq_fs_shift = IRQ13_MCU_MODE_SFT,2191		.irq_fs_maskbit = IRQ13_MCU_MODE_MASK,2192		.irq_en_reg = AFE_IRQ_MCU_CON0,2193		.irq_en_shift = IRQ13_MCU_ON_SFT,2194		.irq_clr_reg = AFE_IRQ_MCU_CLR,2195		.irq_clr_shift = IRQ13_MCU_CLR_SFT,2196	},2197	[MT8186_IRQ_14] = {2198		.id = MT8186_IRQ_14,2199		.irq_cnt_reg = AFE_IRQ_MCU_CNT14,2200		.irq_cnt_shift = AFE_IRQ_CNT_SHIFT,2201		.irq_cnt_maskbit = AFE_IRQ_CNT_MASK,2202		.irq_fs_reg = AFE_IRQ_MCU_CON2,2203		.irq_fs_shift = IRQ14_MCU_MODE_SFT,2204		.irq_fs_maskbit = IRQ14_MCU_MODE_MASK,2205		.irq_en_reg = AFE_IRQ_MCU_CON0,2206		.irq_en_shift = IRQ14_MCU_ON_SFT,2207		.irq_clr_reg = AFE_IRQ_MCU_CLR,2208		.irq_clr_shift = IRQ14_MCU_CLR_SFT,2209	},2210	[MT8186_IRQ_15] = {2211		.id = MT8186_IRQ_15,2212		.irq_cnt_reg = AFE_IRQ_MCU_CNT15,2213		.irq_cnt_shift = AFE_IRQ_CNT_SHIFT,2214		.irq_cnt_maskbit = AFE_IRQ_CNT_MASK,2215		.irq_fs_reg = AFE_IRQ_MCU_CON2,2216		.irq_fs_shift = IRQ15_MCU_MODE_SFT,2217		.irq_fs_maskbit = IRQ15_MCU_MODE_MASK,2218		.irq_en_reg = AFE_IRQ_MCU_CON0,2219		.irq_en_shift = IRQ15_MCU_ON_SFT,2220		.irq_clr_reg = AFE_IRQ_MCU_CLR,2221		.irq_clr_shift = IRQ15_MCU_CLR_SFT,2222	},2223	[MT8186_IRQ_16] = {2224		.id = MT8186_IRQ_16,2225		.irq_cnt_reg = AFE_IRQ_MCU_CNT16,2226		.irq_cnt_shift = AFE_IRQ_CNT_SHIFT,2227		.irq_cnt_maskbit = AFE_IRQ_CNT_MASK,2228		.irq_fs_reg = AFE_IRQ_MCU_CON3,2229		.irq_fs_shift = IRQ16_MCU_MODE_SFT,2230		.irq_fs_maskbit = IRQ16_MCU_MODE_MASK,2231		.irq_en_reg = AFE_IRQ_MCU_CON0,2232		.irq_en_shift = IRQ16_MCU_ON_SFT,2233		.irq_clr_reg = AFE_IRQ_MCU_CLR,2234		.irq_clr_shift = IRQ16_MCU_CLR_SFT,2235	},2236	[MT8186_IRQ_17] = {2237		.id = MT8186_IRQ_17,2238		.irq_cnt_reg = AFE_IRQ_MCU_CNT17,2239		.irq_cnt_shift = AFE_IRQ_CNT_SHIFT,2240		.irq_cnt_maskbit = AFE_IRQ_CNT_MASK,2241		.irq_fs_reg = AFE_IRQ_MCU_CON3,2242		.irq_fs_shift = IRQ17_MCU_MODE_SFT,2243		.irq_fs_maskbit = IRQ17_MCU_MODE_MASK,2244		.irq_en_reg = AFE_IRQ_MCU_CON0,2245		.irq_en_shift = IRQ17_MCU_ON_SFT,2246		.irq_clr_reg = AFE_IRQ_MCU_CLR,2247		.irq_clr_shift = IRQ17_MCU_CLR_SFT,2248	},2249	[MT8186_IRQ_18] = {2250		.id = MT8186_IRQ_18,2251		.irq_cnt_reg = AFE_IRQ_MCU_CNT18,2252		.irq_cnt_shift = AFE_IRQ_CNT_SHIFT,2253		.irq_cnt_maskbit = AFE_IRQ_CNT_MASK,2254		.irq_fs_reg = AFE_IRQ_MCU_CON3,2255		.irq_fs_shift = IRQ18_MCU_MODE_SFT,2256		.irq_fs_maskbit = IRQ18_MCU_MODE_MASK,2257		.irq_en_reg = AFE_IRQ_MCU_CON0,2258		.irq_en_shift = IRQ18_MCU_ON_SFT,2259		.irq_clr_reg = AFE_IRQ_MCU_CLR,2260		.irq_clr_shift = IRQ18_MCU_CLR_SFT,2261	},2262	[MT8186_IRQ_19] = {2263		.id = MT8186_IRQ_19,2264		.irq_cnt_reg = AFE_IRQ_MCU_CNT19,2265		.irq_cnt_shift = AFE_IRQ_CNT_SHIFT,2266		.irq_cnt_maskbit = AFE_IRQ_CNT_MASK,2267		.irq_fs_reg = AFE_IRQ_MCU_CON3,2268		.irq_fs_shift = IRQ19_MCU_MODE_SFT,2269		.irq_fs_maskbit = IRQ19_MCU_MODE_MASK,2270		.irq_en_reg = AFE_IRQ_MCU_CON0,2271		.irq_en_shift = IRQ19_MCU_ON_SFT,2272		.irq_clr_reg = AFE_IRQ_MCU_CLR,2273		.irq_clr_shift = IRQ19_MCU_CLR_SFT,2274	},2275	[MT8186_IRQ_20] = {2276		.id = MT8186_IRQ_20,2277		.irq_cnt_reg = AFE_IRQ_MCU_CNT20,2278		.irq_cnt_shift = AFE_IRQ_CNT_SHIFT,2279		.irq_cnt_maskbit = AFE_IRQ_CNT_MASK,2280		.irq_fs_reg = AFE_IRQ_MCU_CON3,2281		.irq_fs_shift = IRQ20_MCU_MODE_SFT,2282		.irq_fs_maskbit = IRQ20_MCU_MODE_MASK,2283		.irq_en_reg = AFE_IRQ_MCU_CON0,2284		.irq_en_shift = IRQ20_MCU_ON_SFT,2285		.irq_clr_reg = AFE_IRQ_MCU_CLR,2286		.irq_clr_shift = IRQ20_MCU_CLR_SFT,2287	},2288	[MT8186_IRQ_21] = {2289		.id = MT8186_IRQ_21,2290		.irq_cnt_reg = AFE_IRQ_MCU_CNT21,2291		.irq_cnt_shift = AFE_IRQ_CNT_SHIFT,2292		.irq_cnt_maskbit = AFE_IRQ_CNT_MASK,2293		.irq_fs_reg = AFE_IRQ_MCU_CON3,2294		.irq_fs_shift = IRQ21_MCU_MODE_SFT,2295		.irq_fs_maskbit = IRQ21_MCU_MODE_MASK,2296		.irq_en_reg = AFE_IRQ_MCU_CON0,2297		.irq_en_shift = IRQ21_MCU_ON_SFT,2298		.irq_clr_reg = AFE_IRQ_MCU_CLR,2299		.irq_clr_shift = IRQ21_MCU_CLR_SFT,2300	},2301	[MT8186_IRQ_22] = {2302		.id = MT8186_IRQ_22,2303		.irq_cnt_reg = AFE_IRQ_MCU_CNT22,2304		.irq_cnt_shift = AFE_IRQ_CNT_SHIFT,2305		.irq_cnt_maskbit = AFE_IRQ_CNT_MASK,2306		.irq_fs_reg = AFE_IRQ_MCU_CON3,2307		.irq_fs_shift = IRQ22_MCU_MODE_SFT,2308		.irq_fs_maskbit = IRQ22_MCU_MODE_MASK,2309		.irq_en_reg = AFE_IRQ_MCU_CON0,2310		.irq_en_shift = IRQ22_MCU_ON_SFT,2311		.irq_clr_reg = AFE_IRQ_MCU_CLR,2312		.irq_clr_shift = IRQ22_MCU_CLR_SFT,2313	},2314	[MT8186_IRQ_23] = {2315		.id = MT8186_IRQ_23,2316		.irq_cnt_reg = AFE_IRQ_MCU_CNT23,2317		.irq_cnt_shift = AFE_IRQ_CNT_SHIFT,2318		.irq_cnt_maskbit = AFE_IRQ_CNT_MASK,2319		.irq_fs_reg = AFE_IRQ_MCU_CON3,2320		.irq_fs_shift = IRQ23_MCU_MODE_SFT,2321		.irq_fs_maskbit = IRQ23_MCU_MODE_MASK,2322		.irq_en_reg = AFE_IRQ_MCU_CON0,2323		.irq_en_shift = IRQ23_MCU_ON_SFT,2324		.irq_clr_reg = AFE_IRQ_MCU_CLR,2325		.irq_clr_shift = IRQ23_MCU_CLR_SFT,2326	},2327	[MT8186_IRQ_24] = {2328		.id = MT8186_IRQ_24,2329		.irq_cnt_reg = AFE_IRQ_MCU_CNT24,2330		.irq_cnt_shift = AFE_IRQ_CNT_SHIFT,2331		.irq_cnt_maskbit = AFE_IRQ_CNT_MASK,2332		.irq_fs_reg = AFE_IRQ_MCU_CON4,2333		.irq_fs_shift = IRQ24_MCU_MODE_SFT,2334		.irq_fs_maskbit = IRQ24_MCU_MODE_MASK,2335		.irq_en_reg = AFE_IRQ_MCU_CON0,2336		.irq_en_shift = IRQ24_MCU_ON_SFT,2337		.irq_clr_reg = AFE_IRQ_MCU_CLR,2338		.irq_clr_shift = IRQ24_MCU_CLR_SFT,2339	},2340	[MT8186_IRQ_25] = {2341		.id = MT8186_IRQ_25,2342		.irq_cnt_reg = AFE_IRQ_MCU_CNT25,2343		.irq_cnt_shift = AFE_IRQ_CNT_SHIFT,2344		.irq_cnt_maskbit = AFE_IRQ_CNT_MASK,2345		.irq_fs_reg = AFE_IRQ_MCU_CON4,2346		.irq_fs_shift = IRQ25_MCU_MODE_SFT,2347		.irq_fs_maskbit = IRQ25_MCU_MODE_MASK,2348		.irq_en_reg = AFE_IRQ_MCU_CON0,2349		.irq_en_shift = IRQ25_MCU_ON_SFT,2350		.irq_clr_reg = AFE_IRQ_MCU_CLR,2351		.irq_clr_shift = IRQ25_MCU_CLR_SFT,2352	},2353	[MT8186_IRQ_26] = {2354		.id = MT8186_IRQ_26,2355		.irq_cnt_reg = AFE_IRQ_MCU_CNT26,2356		.irq_cnt_shift = AFE_IRQ_CNT_SHIFT,2357		.irq_cnt_maskbit = AFE_IRQ_CNT_MASK,2358		.irq_fs_reg = AFE_IRQ_MCU_CON4,2359		.irq_fs_shift = IRQ26_MCU_MODE_SFT,2360		.irq_fs_maskbit = IRQ26_MCU_MODE_MASK,2361		.irq_en_reg = AFE_IRQ_MCU_CON0,2362		.irq_en_shift = IRQ26_MCU_ON_SFT,2363		.irq_clr_reg = AFE_IRQ_MCU_CLR,2364		.irq_clr_shift = IRQ26_MCU_CLR_SFT,2365	},2366};2367 2368static const int memif_irq_usage[MT8186_MEMIF_NUM] = {2369	/* TODO: verify each memif & irq */2370	[MT8186_MEMIF_DL1] = MT8186_IRQ_0,2371	[MT8186_MEMIF_DL2] = MT8186_IRQ_1,2372	[MT8186_MEMIF_DL3] = MT8186_IRQ_2,2373	[MT8186_MEMIF_DL4] = MT8186_IRQ_3,2374	[MT8186_MEMIF_DL5] = MT8186_IRQ_4,2375	[MT8186_MEMIF_DL6] = MT8186_IRQ_5,2376	[MT8186_MEMIF_DL7] = MT8186_IRQ_6,2377	[MT8186_MEMIF_DL8] = MT8186_IRQ_7,2378	[MT8186_MEMIF_DL12] = MT8186_IRQ_9,2379	[MT8186_MEMIF_VUL12] = MT8186_IRQ_10,2380	[MT8186_MEMIF_VUL2] = MT8186_IRQ_11,2381	[MT8186_MEMIF_AWB] = MT8186_IRQ_12,2382	[MT8186_MEMIF_AWB2] = MT8186_IRQ_13,2383	[MT8186_MEMIF_VUL3] = MT8186_IRQ_14,2384	[MT8186_MEMIF_VUL4] = MT8186_IRQ_15,2385	[MT8186_MEMIF_VUL5] = MT8186_IRQ_16,2386	[MT8186_MEMIF_VUL6] = MT8186_IRQ_17,2387};2388 2389static bool mt8186_is_volatile_reg(struct device *dev, unsigned int reg)2390{2391	/* these auto-gen reg has read-only bit, so put it as volatile */2392	/* volatile reg cannot be cached, so cannot be set when power off */2393	switch (reg) {2394	case AUDIO_TOP_CON0:	/* reg bit controlled by CCF */2395	case AUDIO_TOP_CON1:	/* reg bit controlled by CCF */2396	case AUDIO_TOP_CON2:2397	case AUDIO_TOP_CON3:2398	case AFE_DAC_CON0:2399	case AFE_DL1_CUR_MSB:2400	case AFE_DL1_CUR:2401	case AFE_DL1_END:2402	case AFE_DL2_CUR_MSB:2403	case AFE_DL2_CUR:2404	case AFE_DL2_END:2405	case AFE_DL3_CUR_MSB:2406	case AFE_DL3_CUR:2407	case AFE_DL3_END:2408	case AFE_DL4_CUR_MSB:2409	case AFE_DL4_CUR:2410	case AFE_DL4_END:2411	case AFE_DL12_CUR_MSB:2412	case AFE_DL12_CUR:2413	case AFE_DL12_END:2414	case AFE_ADDA_SRC_DEBUG_MON0:2415	case AFE_ADDA_SRC_DEBUG_MON1:2416	case AFE_ADDA_UL_SRC_MON0:2417	case AFE_ADDA_UL_SRC_MON1:2418	case AFE_SECURE_CON0:2419	case AFE_SRAM_BOUND:2420	case AFE_SECURE_CON1:2421	case AFE_VUL_CUR_MSB:2422	case AFE_VUL_CUR:2423	case AFE_VUL_END:2424	case AFE_SIDETONE_MON:2425	case AFE_SIDETONE_CON0:2426	case AFE_SIDETONE_COEFF:2427	case AFE_VUL2_CUR_MSB:2428	case AFE_VUL2_CUR:2429	case AFE_VUL2_END:2430	case AFE_VUL3_CUR_MSB:2431	case AFE_VUL3_CUR:2432	case AFE_VUL3_END:2433	case AFE_I2S_MON:2434	case AFE_DAC_MON:2435	case AFE_IRQ0_MCU_CNT_MON:2436	case AFE_IRQ6_MCU_CNT_MON:2437	case AFE_VUL4_CUR_MSB:2438	case AFE_VUL4_CUR:2439	case AFE_VUL4_END:2440	case AFE_VUL12_CUR_MSB:2441	case AFE_VUL12_CUR:2442	case AFE_VUL12_END:2443	case AFE_IRQ3_MCU_CNT_MON:2444	case AFE_IRQ4_MCU_CNT_MON:2445	case AFE_IRQ_MCU_STATUS:2446	case AFE_IRQ_MCU_CLR:2447	case AFE_IRQ_MCU_MON2:2448	case AFE_IRQ1_MCU_CNT_MON:2449	case AFE_IRQ2_MCU_CNT_MON:2450	case AFE_IRQ5_MCU_CNT_MON:2451	case AFE_IRQ7_MCU_CNT_MON:2452	case AFE_IRQ_MCU_MISS_CLR:2453	case AFE_GAIN1_CUR:2454	case AFE_GAIN2_CUR:2455	case AFE_SRAM_DELSEL_CON1:2456	case PCM_INTF_CON2:2457	case FPGA_CFG0:2458	case FPGA_CFG1:2459	case FPGA_CFG2:2460	case FPGA_CFG3:2461	case AUDIO_TOP_DBG_MON0:2462	case AUDIO_TOP_DBG_MON1:2463	case AFE_IRQ8_MCU_CNT_MON:2464	case AFE_IRQ11_MCU_CNT_MON:2465	case AFE_IRQ12_MCU_CNT_MON:2466	case AFE_IRQ9_MCU_CNT_MON:2467	case AFE_IRQ10_MCU_CNT_MON:2468	case AFE_IRQ13_MCU_CNT_MON:2469	case AFE_IRQ14_MCU_CNT_MON:2470	case AFE_IRQ15_MCU_CNT_MON:2471	case AFE_IRQ16_MCU_CNT_MON:2472	case AFE_IRQ17_MCU_CNT_MON:2473	case AFE_IRQ18_MCU_CNT_MON:2474	case AFE_IRQ19_MCU_CNT_MON:2475	case AFE_IRQ20_MCU_CNT_MON:2476	case AFE_IRQ21_MCU_CNT_MON:2477	case AFE_IRQ22_MCU_CNT_MON:2478	case AFE_IRQ23_MCU_CNT_MON:2479	case AFE_IRQ24_MCU_CNT_MON:2480	case AFE_IRQ25_MCU_CNT_MON:2481	case AFE_IRQ26_MCU_CNT_MON:2482	case AFE_IRQ31_MCU_CNT_MON:2483	case AFE_CBIP_MON0:2484	case AFE_CBIP_SLV_MUX_MON0:2485	case AFE_CBIP_SLV_DECODER_MON0:2486	case AFE_ADDA6_MTKAIF_MON0:2487	case AFE_ADDA6_MTKAIF_MON1:2488	case AFE_AWB_CUR_MSB:2489	case AFE_AWB_CUR:2490	case AFE_AWB_END:2491	case AFE_AWB2_CUR_MSB:2492	case AFE_AWB2_CUR:2493	case AFE_AWB2_END:2494	case AFE_DAI_CUR_MSB:2495	case AFE_DAI_CUR:2496	case AFE_DAI_END:2497	case AFE_DAI2_CUR_MSB:2498	case AFE_DAI2_CUR:2499	case AFE_DAI2_END:2500	case AFE_ADDA6_SRC_DEBUG_MON0:2501	case AFE_ADD6A_UL_SRC_MON0:2502	case AFE_ADDA6_UL_SRC_MON1:2503	case AFE_MOD_DAI_CUR_MSB:2504	case AFE_MOD_DAI_CUR:2505	case AFE_MOD_DAI_END:2506	case AFE_AWB_RCH_MON:2507	case AFE_AWB_LCH_MON:2508	case AFE_VUL_RCH_MON:2509	case AFE_VUL_LCH_MON:2510	case AFE_VUL12_RCH_MON:2511	case AFE_VUL12_LCH_MON:2512	case AFE_VUL2_RCH_MON:2513	case AFE_VUL2_LCH_MON:2514	case AFE_DAI_DATA_MON:2515	case AFE_MOD_DAI_DATA_MON:2516	case AFE_DAI2_DATA_MON:2517	case AFE_AWB2_RCH_MON:2518	case AFE_AWB2_LCH_MON:2519	case AFE_VUL3_RCH_MON:2520	case AFE_VUL3_LCH_MON:2521	case AFE_VUL4_RCH_MON:2522	case AFE_VUL4_LCH_MON:2523	case AFE_VUL5_RCH_MON:2524	case AFE_VUL5_LCH_MON:2525	case AFE_VUL6_RCH_MON:2526	case AFE_VUL6_LCH_MON:2527	case AFE_DL1_RCH_MON:2528	case AFE_DL1_LCH_MON:2529	case AFE_DL2_RCH_MON:2530	case AFE_DL2_LCH_MON:2531	case AFE_DL12_RCH1_MON:2532	case AFE_DL12_LCH1_MON:2533	case AFE_DL12_RCH2_MON:2534	case AFE_DL12_LCH2_MON:2535	case AFE_DL3_RCH_MON:2536	case AFE_DL3_LCH_MON:2537	case AFE_DL4_RCH_MON:2538	case AFE_DL4_LCH_MON:2539	case AFE_DL5_RCH_MON:2540	case AFE_DL5_LCH_MON:2541	case AFE_DL6_RCH_MON:2542	case AFE_DL6_LCH_MON:2543	case AFE_DL7_RCH_MON:2544	case AFE_DL7_LCH_MON:2545	case AFE_DL8_RCH_MON:2546	case AFE_DL8_LCH_MON:2547	case AFE_VUL5_CUR_MSB:2548	case AFE_VUL5_CUR:2549	case AFE_VUL5_END:2550	case AFE_VUL6_CUR_MSB:2551	case AFE_VUL6_CUR:2552	case AFE_VUL6_END:2553	case AFE_ADDA_DL_SDM_FIFO_MON:2554	case AFE_ADDA_DL_SRC_LCH_MON:2555	case AFE_ADDA_DL_SRC_RCH_MON:2556	case AFE_ADDA_DL_SDM_OUT_MON:2557	case AFE_CONNSYS_I2S_MON:2558	case AFE_ASRC_2CH_CON0:2559	case AFE_ASRC_2CH_CON2:2560	case AFE_ASRC_2CH_CON3:2561	case AFE_ASRC_2CH_CON4:2562	case AFE_ASRC_2CH_CON5:2563	case AFE_ASRC_2CH_CON7:2564	case AFE_ASRC_2CH_CON8:2565	case AFE_ASRC_2CH_CON12:2566	case AFE_ASRC_2CH_CON13:2567	case AFE_ADDA_MTKAIF_MON0:2568	case AFE_ADDA_MTKAIF_MON1:2569	case AFE_AUD_PAD_TOP:2570	case AFE_DL_NLE_R_MON0:2571	case AFE_DL_NLE_R_MON1:2572	case AFE_DL_NLE_R_MON2:2573	case AFE_DL_NLE_L_MON0:2574	case AFE_DL_NLE_L_MON1:2575	case AFE_DL_NLE_L_MON2:2576	case AFE_GENERAL1_ASRC_2CH_CON0:2577	case AFE_GENERAL1_ASRC_2CH_CON2:2578	case AFE_GENERAL1_ASRC_2CH_CON3:2579	case AFE_GENERAL1_ASRC_2CH_CON4:2580	case AFE_GENERAL1_ASRC_2CH_CON5:2581	case AFE_GENERAL1_ASRC_2CH_CON7:2582	case AFE_GENERAL1_ASRC_2CH_CON8:2583	case AFE_GENERAL1_ASRC_2CH_CON12:2584	case AFE_GENERAL1_ASRC_2CH_CON13:2585	case AFE_GENERAL2_ASRC_2CH_CON0:2586	case AFE_GENERAL2_ASRC_2CH_CON2:2587	case AFE_GENERAL2_ASRC_2CH_CON3:2588	case AFE_GENERAL2_ASRC_2CH_CON4:2589	case AFE_GENERAL2_ASRC_2CH_CON5:2590	case AFE_GENERAL2_ASRC_2CH_CON7:2591	case AFE_GENERAL2_ASRC_2CH_CON8:2592	case AFE_GENERAL2_ASRC_2CH_CON12:2593	case AFE_GENERAL2_ASRC_2CH_CON13:2594	case AFE_DL5_CUR_MSB:2595	case AFE_DL5_CUR:2596	case AFE_DL5_END:2597	case AFE_DL6_CUR_MSB:2598	case AFE_DL6_CUR:2599	case AFE_DL6_END:2600	case AFE_DL7_CUR_MSB:2601	case AFE_DL7_CUR:2602	case AFE_DL7_END:2603	case AFE_DL8_CUR_MSB:2604	case AFE_DL8_CUR:2605	case AFE_DL8_END:2606	case AFE_PROT_SIDEBAND_MON:2607	case AFE_DOMAIN_SIDEBAND0_MON:2608	case AFE_DOMAIN_SIDEBAND1_MON:2609	case AFE_DOMAIN_SIDEBAND2_MON:2610	case AFE_DOMAIN_SIDEBAND3_MON:2611	case AFE_APLL1_TUNER_CFG:	/* [20:31] is monitor */2612	case AFE_APLL2_TUNER_CFG:	/* [20:31] is monitor */2613		return true;2614	default:2615		return false;2616	};2617}2618 2619static const struct regmap_config mt8186_afe_regmap_config = {2620	.reg_bits = 32,2621	.reg_stride = 4,2622	.val_bits = 32,2623 2624	.volatile_reg = mt8186_is_volatile_reg,2625 2626	.max_register = AFE_MAX_REGISTER,2627	.num_reg_defaults_raw = AFE_MAX_REGISTER,2628 2629	.cache_type = REGCACHE_FLAT,2630};2631 2632static irqreturn_t mt8186_afe_irq_handler(int irq_id, void *dev)2633{2634	struct mtk_base_afe *afe = dev;2635	struct mtk_base_afe_irq *irq;2636	unsigned int status;2637	unsigned int status_mcu;2638	unsigned int mcu_en;2639	int ret;2640	int i;2641 2642	/* get irq that is sent to MCU */2643	ret = regmap_read(afe->regmap, AFE_IRQ_MCU_EN, &mcu_en);2644	if (ret) {2645		dev_err(afe->dev, "%s, get irq direction fail, ret %d", __func__, ret);2646		return ret;2647	}2648 2649	ret = regmap_read(afe->regmap, AFE_IRQ_MCU_STATUS, &status);2650	/* only care IRQ which is sent to MCU */2651	status_mcu = status & mcu_en & AFE_IRQ_STATUS_BITS;2652 2653	if (ret || status_mcu == 0) {2654		dev_err(afe->dev, "%s(), irq status err, ret %d, status 0x%x, mcu_en 0x%x\n",2655			__func__, ret, status, mcu_en);2656 2657		goto err_irq;2658	}2659 2660	for (i = 0; i < MT8186_MEMIF_NUM; i++) {2661		struct mtk_base_afe_memif *memif = &afe->memif[i];2662 2663		if (!memif->substream)2664			continue;2665 2666		if (memif->irq_usage < 0)2667			continue;2668 2669		irq = &afe->irqs[memif->irq_usage];2670 2671		if (status_mcu & (1 << irq->irq_data->irq_en_shift))2672			snd_pcm_period_elapsed(memif->substream);2673	}2674 2675err_irq:2676	/* clear irq */2677	regmap_write(afe->regmap, AFE_IRQ_MCU_CLR, status_mcu);2678 2679	return IRQ_HANDLED;2680}2681 2682static int mt8186_afe_runtime_suspend(struct device *dev)2683{2684	struct mtk_base_afe *afe = dev_get_drvdata(dev);2685	struct mt8186_afe_private *afe_priv = afe->platform_priv;2686	unsigned int value = 0;2687	int ret;2688 2689	if (!afe->regmap || afe_priv->pm_runtime_bypass_reg_ctl)2690		goto skip_regmap;2691 2692	/* disable AFE */2693	regmap_update_bits(afe->regmap, AFE_DAC_CON0, 0x1, 0x0);2694 2695	ret = regmap_read_poll_timeout(afe->regmap,2696				       AFE_DAC_MON,2697				       value,2698				       (value & AFE_ON_RETM_MASK_SFT) == 0,2699				       20,2700				       1 * 1000 * 1000);2701	if (ret) {2702		dev_err(afe->dev, "%s(), ret %d\n", __func__, ret);2703		return ret;2704	}2705 2706	/* make sure all irq status are cleared */2707	regmap_write(afe->regmap, AFE_IRQ_MCU_CLR, 0xffffffff);2708	regmap_write(afe->regmap, AFE_IRQ_MCU_CLR, 0xffffffff);2709 2710	/* reset sgen */2711	regmap_write(afe->regmap, AFE_SINEGEN_CON0, 0x0);2712	regmap_update_bits(afe->regmap, AFE_SINEGEN_CON2,2713			   INNER_LOOP_BACK_MODE_MASK_SFT,2714			   0x3f << INNER_LOOP_BACK_MODE_SFT);2715 2716	/* cache only */2717	regcache_cache_only(afe->regmap, true);2718	regcache_mark_dirty(afe->regmap);2719 2720skip_regmap:2721	mt8186_afe_disable_cgs(afe);2722	mt8186_afe_disable_clock(afe);2723 2724	return 0;2725}2726 2727static int mt8186_afe_runtime_resume(struct device *dev)2728{2729	struct mtk_base_afe *afe = dev_get_drvdata(dev);2730	struct mt8186_afe_private *afe_priv = afe->platform_priv;2731	int ret;2732 2733	ret = mt8186_afe_enable_clock(afe);2734	if (ret)2735		return ret;2736 2737	ret = mt8186_afe_enable_cgs(afe);2738	if (ret)2739		return ret;2740 2741	if (!afe->regmap || afe_priv->pm_runtime_bypass_reg_ctl)2742		goto skip_regmap;2743 2744	regcache_cache_only(afe->regmap, false);2745	regcache_sync(afe->regmap);2746 2747	/* enable audio sys DCM for power saving */2748	regmap_update_bits(afe_priv->infracfg, PERI_BUS_DCM_CTRL, BIT(29), BIT(29));2749	regmap_update_bits(afe->regmap, AUDIO_TOP_CON0, BIT(29), BIT(29));2750 2751	/* force cpu use 8_24 format when writing 32bit data */2752	regmap_update_bits(afe->regmap, AFE_MEMIF_CON0, CPU_HD_ALIGN_MASK_SFT, 0);2753 2754	/* set all output port to 24bit */2755	regmap_write(afe->regmap, AFE_CONN_24BIT, 0xffffffff);2756	regmap_write(afe->regmap, AFE_CONN_24BIT_1, 0xffffffff);2757 2758	/* enable AFE */2759	regmap_update_bits(afe->regmap, AFE_DAC_CON0, AUDIO_AFE_ON_MASK_SFT, BIT(0));2760 2761skip_regmap:2762	return 0;2763}2764 2765static int mt8186_afe_component_probe(struct snd_soc_component *component)2766{2767	mtk_afe_add_sub_dai_control(component);2768	mt8186_add_misc_control(component);2769 2770	return 0;2771}2772 2773static const struct snd_soc_component_driver mt8186_afe_component = {2774	.name = AFE_PCM_NAME,2775	.pcm_construct = mtk_afe_pcm_new,2776	.pointer = mtk_afe_pcm_pointer,2777	.probe = mt8186_afe_component_probe,2778};2779 2780static int mt8186_dai_memif_register(struct mtk_base_afe *afe)2781{2782	struct mtk_base_afe_dai *dai;2783 2784	dai = devm_kzalloc(afe->dev, sizeof(*dai), GFP_KERNEL);2785	if (!dai)2786		return -ENOMEM;2787 2788	list_add(&dai->list, &afe->sub_dais);2789 2790	dai->dai_drivers = mt8186_memif_dai_driver;2791	dai->num_dai_drivers = ARRAY_SIZE(mt8186_memif_dai_driver);2792 2793	dai->controls = mt8186_pcm_kcontrols;2794	dai->num_controls = ARRAY_SIZE(mt8186_pcm_kcontrols);2795	dai->dapm_widgets = mt8186_memif_widgets;2796	dai->num_dapm_widgets = ARRAY_SIZE(mt8186_memif_widgets);2797	dai->dapm_routes = mt8186_memif_routes;2798	dai->num_dapm_routes = ARRAY_SIZE(mt8186_memif_routes);2799	return 0;2800}2801 2802typedef int (*dai_register_cb)(struct mtk_base_afe *);2803static const dai_register_cb dai_register_cbs[] = {2804	mt8186_dai_adda_register,2805	mt8186_dai_i2s_register,2806	mt8186_dai_tdm_register,2807	mt8186_dai_hw_gain_register,2808	mt8186_dai_src_register,2809	mt8186_dai_pcm_register,2810	mt8186_dai_hostless_register,2811	mt8186_dai_memif_register,2812};2813 2814static int mt8186_afe_pcm_dev_probe(struct platform_device *pdev)2815{2816	struct mtk_base_afe *afe;2817	struct mt8186_afe_private *afe_priv;2818	struct reset_control *rstc;2819	struct device *dev = &pdev->dev;2820	int i, ret, irq_id;2821 2822	ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(34));2823	if (ret)2824		return ret;2825 2826	afe = devm_kzalloc(dev, sizeof(*afe), GFP_KERNEL);2827	if (!afe)2828		return -ENOMEM;2829	platform_set_drvdata(pdev, afe);2830 2831	afe->platform_priv = devm_kzalloc(dev, sizeof(*afe_priv), GFP_KERNEL);2832	if (!afe->platform_priv)2833		return -ENOMEM;2834 2835	afe_priv = afe->platform_priv;2836	afe->dev = &pdev->dev;2837 2838	afe->base_addr = devm_platform_ioremap_resource(pdev, 0);2839	if (IS_ERR(afe->base_addr))2840		return PTR_ERR(afe->base_addr);2841 2842	/* init audio related clock */2843	ret = mt8186_init_clock(afe);2844	if (ret) {2845		dev_err(dev, "init clock error, ret %d\n", ret);2846		return ret;2847	}2848 2849	/* init memif */2850	afe->memif_32bit_supported = 0;2851	afe->memif_size = MT8186_MEMIF_NUM;2852	afe->memif = devm_kcalloc(dev, afe->memif_size, sizeof(*afe->memif), GFP_KERNEL);2853	if (!afe->memif)2854		return -ENOMEM;2855 2856	for (i = 0; i < afe->memif_size; i++) {2857		afe->memif[i].data = &memif_data[i];2858		afe->memif[i].irq_usage = memif_irq_usage[i];2859		afe->memif[i].const_irq = 1;2860	}2861 2862	mutex_init(&afe->irq_alloc_lock);	/* needed when dynamic irq */2863 2864	/* init irq */2865	afe->irqs_size = MT8186_IRQ_NUM;2866	afe->irqs = devm_kcalloc(dev, afe->irqs_size, sizeof(*afe->irqs),2867				 GFP_KERNEL);2868 2869	if (!afe->irqs)2870		return -ENOMEM;2871 2872	for (i = 0; i < afe->irqs_size; i++)2873		afe->irqs[i].irq_data = &irq_data[i];2874 2875	/* request irq */2876	irq_id = platform_get_irq(pdev, 0);2877	if (irq_id <= 0)2878		return dev_err_probe(dev, irq_id < 0 ? irq_id : -ENXIO,2879				     "no irq found");2880 2881	ret = devm_request_irq(dev, irq_id, mt8186_afe_irq_handler,2882			       IRQF_TRIGGER_NONE,2883			       "Afe_ISR_Handle", (void *)afe);2884	if (ret)2885		return dev_err_probe(dev, ret, "could not request_irq for Afe_ISR_Handle\n");2886 2887	ret = enable_irq_wake(irq_id);2888	if (ret < 0)2889		return dev_err_probe(dev, ret, "enable_irq_wake %d\n", irq_id);2890 2891	/* init sub_dais */2892	INIT_LIST_HEAD(&afe->sub_dais);2893 2894	for (i = 0; i < ARRAY_SIZE(dai_register_cbs); i++) {2895		ret = dai_register_cbs[i](afe);2896		if (ret)2897			return dev_err_probe(dev, ret, "dai register i %d fail\n", i);2898	}2899 2900	/* init dai_driver and component_driver */2901	ret = mtk_afe_combine_sub_dai(afe);2902	if (ret)2903		return dev_err_probe(dev, ret, "mtk_afe_combine_sub_dai fail\n");2904 2905	/* reset controller to reset audio regs before regmap cache */2906	rstc = devm_reset_control_get_exclusive(dev, "audiosys");2907	if (IS_ERR(rstc))2908		return dev_err_probe(dev, PTR_ERR(rstc), "could not get audiosys reset\n");2909 2910	ret = reset_control_reset(rstc);2911	if (ret)2912		return dev_err_probe(dev, ret, "failed to trigger audio reset\n");2913 2914	/* enable clock for regcache get default value from hw */2915	afe_priv->pm_runtime_bypass_reg_ctl = true;2916 2917	ret = devm_pm_runtime_enable(dev);2918	if (ret)2919		return ret;2920 2921	ret = pm_runtime_resume_and_get(dev);2922	if (ret)2923		return dev_err_probe(dev, ret, "failed to resume device\n");2924 2925	afe->regmap = devm_regmap_init_mmio(dev, afe->base_addr,2926					    &mt8186_afe_regmap_config);2927	if (IS_ERR(afe->regmap)) {2928		ret = PTR_ERR(afe->regmap);2929		goto err_pm_disable;2930	}2931 2932	/* others */2933	afe->mtk_afe_hardware = &mt8186_afe_hardware;2934	afe->memif_fs = mt8186_memif_fs;2935	afe->irq_fs = mt8186_irq_fs;2936	afe->get_dai_fs = mt8186_get_dai_fs;2937	afe->get_memif_pbuf_size = mt8186_get_memif_pbuf_size;2938 2939	afe->runtime_resume = mt8186_afe_runtime_resume;2940	afe->runtime_suspend = mt8186_afe_runtime_suspend;2941 2942	/* register platform */2943	dev_dbg(dev, "%s(), devm_snd_soc_register_component\n", __func__);2944 2945	ret = devm_snd_soc_register_component(dev,2946					      &mt8186_afe_component,2947					      afe->dai_drivers,2948					      afe->num_dai_drivers);2949	if (ret) {2950		dev_err(dev, "err_dai_component\n");2951		goto err_pm_disable;2952	}2953 2954	ret = pm_runtime_put_sync(dev);2955	if (ret) {2956		pm_runtime_get_noresume(dev);2957		dev_err(dev, "failed to suspend device: %d\n", ret);2958		goto err_pm_disable;2959	}2960	afe_priv->pm_runtime_bypass_reg_ctl = false;2961 2962	regcache_cache_only(afe->regmap, true);2963	regcache_mark_dirty(afe->regmap);2964 2965	return 0;2966 2967err_pm_disable:2968	pm_runtime_put_noidle(dev);2969	pm_runtime_set_suspended(dev);2970 2971	return ret;2972}2973 2974static const struct of_device_id mt8186_afe_pcm_dt_match[] = {2975	{ .compatible = "mediatek,mt8186-sound", },2976	{},2977};2978MODULE_DEVICE_TABLE(of, mt8186_afe_pcm_dt_match);2979 2980static const struct dev_pm_ops mt8186_afe_pm_ops = {2981	SET_RUNTIME_PM_OPS(mt8186_afe_runtime_suspend,2982			   mt8186_afe_runtime_resume, NULL)2983};2984 2985static struct platform_driver mt8186_afe_pcm_driver = {2986	.driver = {2987		   .name = "mt8186-audio",2988		   .of_match_table = mt8186_afe_pcm_dt_match,2989		   .pm = &mt8186_afe_pm_ops,2990	},2991	.probe = mt8186_afe_pcm_dev_probe,2992};2993 2994module_platform_driver(mt8186_afe_pcm_driver);2995 2996MODULE_DESCRIPTION("Mediatek ALSA SoC AFE platform driver for 8186");2997MODULE_AUTHOR("Jiaxin Yu <jiaxin.yu@mediatek.com>");2998MODULE_LICENSE("GPL v2");2999