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1// SPDX-License-Identifier: GPL-2.02//3// MediaTek ALSA SoC Audio DAI ADDA Control4//5// Copyright (c) 2022 MediaTek Inc.6// Author: Jiaxin Yu <jiaxin.yu@mediatek.com>7 8#include <linux/regmap.h>9#include <linux/delay.h>10#include "mt8186-afe-clk.h"11#include "mt8186-afe-common.h"12#include "mt8186-afe-gpio.h"13#include "mt8186-interconnection.h"14#include "../common/mtk-dai-adda-common.h"15 16enum {17 UL_IIR_SW = 0,18 UL_IIR_5HZ,19 UL_IIR_10HZ,20 UL_IIR_25HZ,21 UL_IIR_50HZ,22 UL_IIR_75HZ,23};24 25enum {26 AUDIO_SDM_LEVEL_MUTE = 0,27 AUDIO_SDM_LEVEL_NORMAL = 0x1d,28 /* if you change level normal */29 /* you need to change formula of hp impedance and dc trim too */30};31 32enum {33 AUDIO_SDM_2ND = 0,34 AUDIO_SDM_3RD,35};36 37#define SDM_AUTO_RESET_THRESHOLD 0x19000038 39struct mtk_afe_adda_priv {40 int dl_rate;41 int ul_rate;42};43 44static struct mtk_afe_adda_priv *get_adda_priv_by_name(struct mtk_base_afe *afe,45 const char *name)46{47 struct mt8186_afe_private *afe_priv = afe->platform_priv;48 int dai_id;49 50 if (strncmp(name, "aud_dac", 7) == 0 || strncmp(name, "aud_adc", 7) == 0)51 dai_id = MT8186_DAI_ADDA;52 else53 return NULL;54 55 return afe_priv->dai_priv[dai_id];56}57 58/* dai component */59static const struct snd_kcontrol_new mtk_adda_dl_ch1_mix[] = {60 SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH1 Switch", AFE_CONN3, I_DL1_CH1, 1, 0),61 SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH1 Switch", AFE_CONN3, I_DL12_CH1, 1, 0),62 SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1 Switch", AFE_CONN3, I_DL2_CH1, 1, 0),63 SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH1 Switch", AFE_CONN3, I_DL3_CH1, 1, 0),64 SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH1 Switch", AFE_CONN3_1, I_DL4_CH1, 1, 0),65 SOC_DAPM_SINGLE_AUTODISABLE("DL5_CH1 Switch", AFE_CONN3_1, I_DL5_CH1, 1, 0),66 SOC_DAPM_SINGLE_AUTODISABLE("DL6_CH1 Switch", AFE_CONN3_1, I_DL6_CH1, 1, 0),67 SOC_DAPM_SINGLE_AUTODISABLE("DL8_CH1 Switch", AFE_CONN3_1, I_DL8_CH1, 1, 0),68 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2 Switch", AFE_CONN3,69 I_ADDA_UL_CH2, 1, 0),70 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1 Switch", AFE_CONN3,71 I_ADDA_UL_CH1, 1, 0),72 SOC_DAPM_SINGLE_AUTODISABLE("GAIN1_OUT_CH1 Switch", AFE_CONN3,73 I_GAIN1_OUT_CH1, 1, 0),74 SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH1 Switch", AFE_CONN3,75 I_PCM_1_CAP_CH1, 1, 0),76 SOC_DAPM_SINGLE_AUTODISABLE("PCM_2_CAP_CH1 Switch", AFE_CONN3,77 I_PCM_2_CAP_CH1, 1, 0),78 SOC_DAPM_SINGLE_AUTODISABLE("SRC_1_OUT_CH1 Switch", AFE_CONN3_1,79 I_SRC_1_OUT_CH1, 1, 0),80 SOC_DAPM_SINGLE_AUTODISABLE("SRC_2_OUT_CH1 Switch", AFE_CONN3_1,81 I_SRC_2_OUT_CH1, 1, 0),82};83 84static const struct snd_kcontrol_new mtk_adda_dl_ch2_mix[] = {85 SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH1 Switch", AFE_CONN4, I_DL1_CH1, 1, 0),86 SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH2 Switch", AFE_CONN4, I_DL1_CH2, 1, 0),87 SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH2 Switch", AFE_CONN4, I_DL12_CH2, 1, 0),88 SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1 Switch", AFE_CONN4, I_DL2_CH1, 1, 0),89 SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH2 Switch", AFE_CONN4, I_DL2_CH2, 1, 0),90 SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH1 Switch", AFE_CONN4, I_DL3_CH1, 1, 0),91 SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH2 Switch", AFE_CONN4, I_DL3_CH2, 1, 0),92 SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH2 Switch", AFE_CONN4_1, I_DL4_CH2, 1, 0),93 SOC_DAPM_SINGLE_AUTODISABLE("DL5_CH2 Switch", AFE_CONN4_1, I_DL5_CH2, 1, 0),94 SOC_DAPM_SINGLE_AUTODISABLE("DL6_CH2 Switch", AFE_CONN4_1, I_DL6_CH2, 1, 0),95 SOC_DAPM_SINGLE_AUTODISABLE("DL8_CH2 Switch", AFE_CONN4_1, I_DL8_CH2, 1, 0),96 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2 Switch", AFE_CONN4,97 I_ADDA_UL_CH2, 1, 0),98 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1 Switch", AFE_CONN4,99 I_ADDA_UL_CH1, 1, 0),100 SOC_DAPM_SINGLE_AUTODISABLE("GAIN1_OUT_CH2 Switch", AFE_CONN4,101 I_GAIN1_OUT_CH2, 1, 0),102 SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH2 Switch", AFE_CONN4,103 I_PCM_1_CAP_CH2, 1, 0),104 SOC_DAPM_SINGLE_AUTODISABLE("PCM_2_CAP_CH2 Switch", AFE_CONN4,105 I_PCM_2_CAP_CH2, 1, 0),106 SOC_DAPM_SINGLE_AUTODISABLE("SRC_1_OUT_CH2 Switch", AFE_CONN4_1,107 I_SRC_1_OUT_CH2, 1, 0),108 SOC_DAPM_SINGLE_AUTODISABLE("SRC_2_OUT_CH2 Switch", AFE_CONN4_1,109 I_SRC_2_OUT_CH2, 1, 0),110};111 112enum {113 SUPPLY_SEQ_ADDA_AFE_ON,114 SUPPLY_SEQ_ADDA_DL_ON,115 SUPPLY_SEQ_ADDA_AUD_PAD_TOP,116 SUPPLY_SEQ_ADDA_MTKAIF_CFG,117 SUPPLY_SEQ_ADDA_FIFO,118 SUPPLY_SEQ_ADDA_AP_DMIC,119 SUPPLY_SEQ_ADDA_UL_ON,120};121 122static int mtk_adda_ul_src_dmic(struct mtk_base_afe *afe, int id)123{124 unsigned int reg;125 126 switch (id) {127 case MT8186_DAI_ADDA:128 case MT8186_DAI_AP_DMIC:129 reg = AFE_ADDA_UL_SRC_CON0;130 break;131 default:132 return -EINVAL;133 }134 135 /* dmic mode, 3.25M*/136 regmap_update_bits(afe->regmap, reg,137 DIGMIC_3P25M_1P625M_SEL_MASK_SFT, 0);138 regmap_update_bits(afe->regmap, reg,139 DMIC_LOW_POWER_CTL_MASK_SFT, 0);140 141 /* turn on dmic, ch1, ch2 */142 regmap_update_bits(afe->regmap, reg,143 UL_SDM_3_LEVEL_MASK_SFT,144 BIT(UL_SDM_3_LEVEL_SFT));145 regmap_update_bits(afe->regmap, reg,146 UL_MODE_3P25M_CH1_CTL_MASK_SFT,147 BIT(UL_MODE_3P25M_CH1_CTL_SFT));148 regmap_update_bits(afe->regmap, reg,149 UL_MODE_3P25M_CH2_CTL_MASK_SFT,150 BIT(UL_MODE_3P25M_CH2_CTL_SFT));151 152 return 0;153}154 155static int mtk_adda_ul_event(struct snd_soc_dapm_widget *w,156 struct snd_kcontrol *kcontrol,157 int event)158{159 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);160 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);161 struct mt8186_afe_private *afe_priv = afe->platform_priv;162 int mtkaif_dmic = afe_priv->mtkaif_dmic;163 164 dev_dbg(afe->dev, "%s(), name %s, event 0x%x, mtkaif_dmic %d\n",165 __func__, w->name, event, mtkaif_dmic);166 167 switch (event) {168 case SND_SOC_DAPM_PRE_PMU:169 mt8186_afe_gpio_request(afe->dev, true, MT8186_DAI_ADDA, 1);170 171 /* update setting to dmic */172 if (mtkaif_dmic) {173 /* mtkaif_rxif_data_mode = 1, dmic */174 regmap_update_bits(afe->regmap, AFE_ADDA_MTKAIF_RX_CFG0,175 0x1, 0x1);176 177 /* dmic mode, 3.25M*/178 regmap_update_bits(afe->regmap, AFE_ADDA_MTKAIF_RX_CFG0,179 MTKAIF_RXIF_VOICE_MODE_MASK_SFT,180 0x0);181 mtk_adda_ul_src_dmic(afe, MT8186_DAI_ADDA);182 }183 break;184 case SND_SOC_DAPM_POST_PMD:185 /* should delayed 1/fs(smallest is 8k) = 125us before afe off */186 usleep_range(125, 135);187 mt8186_afe_gpio_request(afe->dev, false, MT8186_DAI_ADDA, 1);188 break;189 default:190 break;191 }192 193 return 0;194}195 196static int mtk_adda_pad_top_event(struct snd_soc_dapm_widget *w,197 struct snd_kcontrol *kcontrol,198 int event)199{200 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);201 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);202 struct mt8186_afe_private *afe_priv = afe->platform_priv;203 204 switch (event) {205 case SND_SOC_DAPM_PRE_PMU:206 if (afe_priv->mtkaif_protocol == MTKAIF_PROTOCOL_2_CLK_P2)207 regmap_write(afe->regmap, AFE_AUD_PAD_TOP, 0x39);208 else209 regmap_write(afe->regmap, AFE_AUD_PAD_TOP, 0x31);210 break;211 default:212 break;213 }214 215 return 0;216}217 218static int mtk_adda_mtkaif_cfg_event(struct snd_soc_dapm_widget *w,219 struct snd_kcontrol *kcontrol,220 int event)221{222 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);223 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);224 struct mt8186_afe_private *afe_priv = afe->platform_priv;225 int delay_data;226 int delay_cycle;227 228 switch (event) {229 case SND_SOC_DAPM_PRE_PMU:230 if (afe_priv->mtkaif_protocol == MTKAIF_PROTOCOL_2_CLK_P2) {231 /* set protocol 2 */232 regmap_write(afe->regmap, AFE_ADDA_MTKAIF_CFG0, 0x10000);233 /* mtkaif_rxif_clkinv_adc inverse */234 regmap_update_bits(afe->regmap, AFE_ADDA_MTKAIF_CFG0,235 MTKAIF_RXIF_CLKINV_ADC_MASK_SFT,236 BIT(MTKAIF_RXIF_CLKINV_ADC_SFT));237 238 if (snd_soc_dapm_widget_name_cmp(w, "ADDA_MTKAIF_CFG") == 0) {239 if (afe_priv->mtkaif_chosen_phase[0] < 0 &&240 afe_priv->mtkaif_chosen_phase[1] < 0) {241 dev_err(afe->dev,242 "%s(), calib fail mtkaif_chosen_phase[0/1]:%d/%d\n",243 __func__,244 afe_priv->mtkaif_chosen_phase[0],245 afe_priv->mtkaif_chosen_phase[1]);246 break;247 }248 249 if (afe_priv->mtkaif_chosen_phase[0] < 0 ||250 afe_priv->mtkaif_chosen_phase[1] < 0) {251 dev_err(afe->dev,252 "%s(), skip delay setting mtkaif_chosen_phase[0/1]:%d/%d\n",253 __func__,254 afe_priv->mtkaif_chosen_phase[0],255 afe_priv->mtkaif_chosen_phase[1]);256 break;257 }258 }259 260 /* set delay for ch12 */261 if (afe_priv->mtkaif_phase_cycle[0] >=262 afe_priv->mtkaif_phase_cycle[1]) {263 delay_data = DELAY_DATA_MISO1;264 delay_cycle = afe_priv->mtkaif_phase_cycle[0] -265 afe_priv->mtkaif_phase_cycle[1];266 } else {267 delay_data = DELAY_DATA_MISO2;268 delay_cycle = afe_priv->mtkaif_phase_cycle[1] -269 afe_priv->mtkaif_phase_cycle[0];270 }271 272 regmap_update_bits(afe->regmap,273 AFE_ADDA_MTKAIF_RX_CFG2,274 MTKAIF_RXIF_DELAY_DATA_MASK_SFT,275 delay_data <<276 MTKAIF_RXIF_DELAY_DATA_SFT);277 278 regmap_update_bits(afe->regmap,279 AFE_ADDA_MTKAIF_RX_CFG2,280 MTKAIF_RXIF_DELAY_CYCLE_MASK_SFT,281 delay_cycle <<282 MTKAIF_RXIF_DELAY_CYCLE_SFT);283 284 } else if (afe_priv->mtkaif_protocol == MTKAIF_PROTOCOL_2) {285 regmap_write(afe->regmap, AFE_ADDA_MTKAIF_CFG0, 0x10000);286 } else {287 regmap_write(afe->regmap, AFE_ADDA_MTKAIF_CFG0, 0);288 }289 290 break;291 default:292 break;293 }294 295 return 0;296}297 298static int mtk_adda_dl_event(struct snd_soc_dapm_widget *w,299 struct snd_kcontrol *kcontrol,300 int event)301{302 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);303 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);304 305 dev_dbg(afe->dev, "%s(), name %s, event 0x%x\n",306 __func__, w->name, event);307 308 switch (event) {309 case SND_SOC_DAPM_PRE_PMU:310 mt8186_afe_gpio_request(afe->dev, true, MT8186_DAI_ADDA, 0);311 break;312 case SND_SOC_DAPM_POST_PMD:313 /* should delayed 1/fs(smallest is 8k) = 125us before afe off */314 usleep_range(125, 135);315 mt8186_afe_gpio_request(afe->dev, false, MT8186_DAI_ADDA, 0);316 break;317 default:318 break;319 }320 321 return 0;322}323 324static int mt8186_adda_dmic_get(struct snd_kcontrol *kcontrol,325 struct snd_ctl_elem_value *ucontrol)326{327 struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);328 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);329 struct mt8186_afe_private *afe_priv = afe->platform_priv;330 331 ucontrol->value.integer.value[0] = afe_priv->mtkaif_dmic;332 333 return 0;334}335 336static int mt8186_adda_dmic_set(struct snd_kcontrol *kcontrol,337 struct snd_ctl_elem_value *ucontrol)338{339 struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);340 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);341 struct mt8186_afe_private *afe_priv = afe->platform_priv;342 int dmic_on;343 344 dmic_on = ucontrol->value.integer.value[0];345 346 dev_dbg(afe->dev, "%s(), kcontrol name %s, dmic_on %d\n",347 __func__, kcontrol->id.name, dmic_on);348 349 if (afe_priv->mtkaif_dmic == dmic_on)350 return 0;351 352 afe_priv->mtkaif_dmic = dmic_on;353 354 return 1;355}356 357static const struct snd_kcontrol_new mtk_adda_controls[] = {358 SOC_SINGLE("ADDA_DL_GAIN", AFE_ADDA_DL_SRC2_CON1,359 DL_2_GAIN_CTL_PRE_SFT, DL_2_GAIN_CTL_PRE_MASK, 0),360 SOC_SINGLE_BOOL_EXT("MTKAIF_DMIC Switch", 0,361 mt8186_adda_dmic_get, mt8186_adda_dmic_set),362};363 364/* ADDA UL MUX */365enum {366 ADDA_UL_MUX_MTKAIF = 0,367 ADDA_UL_MUX_AP_DMIC,368 ADDA_UL_MUX_MASK = 0x1,369};370 371static const char * const adda_ul_mux_map[] = {372 "MTKAIF", "AP_DMIC"373};374 375static int adda_ul_map_value[] = {376 ADDA_UL_MUX_MTKAIF,377 ADDA_UL_MUX_AP_DMIC,378};379 380static SOC_VALUE_ENUM_SINGLE_DECL(adda_ul_mux_map_enum,381 SND_SOC_NOPM,382 0,383 ADDA_UL_MUX_MASK,384 adda_ul_mux_map,385 adda_ul_map_value);386 387static const struct snd_kcontrol_new adda_ul_mux_control =388 SOC_DAPM_ENUM("ADDA_UL_MUX Select", adda_ul_mux_map_enum);389 390static const struct snd_soc_dapm_widget mtk_dai_adda_widgets[] = {391 /* inter-connections */392 SND_SOC_DAPM_MIXER("ADDA_DL_CH1", SND_SOC_NOPM, 0, 0,393 mtk_adda_dl_ch1_mix,394 ARRAY_SIZE(mtk_adda_dl_ch1_mix)),395 SND_SOC_DAPM_MIXER("ADDA_DL_CH2", SND_SOC_NOPM, 0, 0,396 mtk_adda_dl_ch2_mix,397 ARRAY_SIZE(mtk_adda_dl_ch2_mix)),398 399 SND_SOC_DAPM_SUPPLY_S("ADDA Enable", SUPPLY_SEQ_ADDA_AFE_ON,400 AFE_ADDA_UL_DL_CON0, ADDA_AFE_ON_SFT, 0,401 NULL, 0),402 403 SND_SOC_DAPM_SUPPLY_S("ADDA Playback Enable", SUPPLY_SEQ_ADDA_DL_ON,404 AFE_ADDA_DL_SRC2_CON0,405 DL_2_SRC_ON_CTL_PRE_SFT, 0,406 mtk_adda_dl_event,407 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),408 409 SND_SOC_DAPM_SUPPLY_S("ADDA Capture Enable", SUPPLY_SEQ_ADDA_UL_ON,410 AFE_ADDA_UL_SRC_CON0,411 UL_SRC_ON_CTL_SFT, 0,412 mtk_adda_ul_event,413 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),414 415 SND_SOC_DAPM_SUPPLY_S("AUD_PAD_TOP", SUPPLY_SEQ_ADDA_AUD_PAD_TOP,416 AFE_AUD_PAD_TOP, RG_RX_FIFO_ON_SFT, 0,417 mtk_adda_pad_top_event,418 SND_SOC_DAPM_PRE_PMU),419 SND_SOC_DAPM_SUPPLY_S("ADDA_MTKAIF_CFG", SUPPLY_SEQ_ADDA_MTKAIF_CFG,420 SND_SOC_NOPM, 0, 0,421 mtk_adda_mtkaif_cfg_event,422 SND_SOC_DAPM_PRE_PMU),423 424 SND_SOC_DAPM_SUPPLY_S("AP_DMIC_EN", SUPPLY_SEQ_ADDA_AP_DMIC,425 AFE_ADDA_UL_SRC_CON0,426 UL_AP_DMIC_ON_SFT, 0,427 NULL, 0),428 429 SND_SOC_DAPM_SUPPLY_S("ADDA_FIFO", SUPPLY_SEQ_ADDA_FIFO,430 AFE_ADDA_UL_DL_CON0,431 AFE_ADDA_FIFO_AUTO_RST_SFT, 1,432 NULL, 0),433 434 SND_SOC_DAPM_MUX("ADDA_UL_Mux", SND_SOC_NOPM, 0, 0,435 &adda_ul_mux_control),436 437 SND_SOC_DAPM_INPUT("AP_DMIC_INPUT"),438 439 /* clock */440 SND_SOC_DAPM_CLOCK_SUPPLY("top_mux_audio_h"),441 442 SND_SOC_DAPM_CLOCK_SUPPLY("aud_dac_clk"),443 SND_SOC_DAPM_CLOCK_SUPPLY("aud_dac_hires_clk"),444 SND_SOC_DAPM_CLOCK_SUPPLY("aud_dac_predis_clk"),445 446 SND_SOC_DAPM_CLOCK_SUPPLY("aud_adc_clk"),447 SND_SOC_DAPM_CLOCK_SUPPLY("aud_adc_hires_clk"),448};449 450#define HIRES_THRESHOLD 48000451static int mtk_afe_dac_hires_connect(struct snd_soc_dapm_widget *source,452 struct snd_soc_dapm_widget *sink)453{454 struct snd_soc_dapm_widget *w = source;455 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);456 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);457 struct mtk_afe_adda_priv *adda_priv;458 459 adda_priv = get_adda_priv_by_name(afe, w->name);460 461 if (!adda_priv) {462 dev_err(afe->dev, "%s(), adda_priv == NULL", __func__);463 return 0;464 }465 466 return (adda_priv->dl_rate > HIRES_THRESHOLD) ? 1 : 0;467}468 469static int mtk_afe_adc_hires_connect(struct snd_soc_dapm_widget *source,470 struct snd_soc_dapm_widget *sink)471{472 struct snd_soc_dapm_widget *w = source;473 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);474 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);475 struct mtk_afe_adda_priv *adda_priv;476 477 adda_priv = get_adda_priv_by_name(afe, w->name);478 479 if (!adda_priv) {480 dev_err(afe->dev, "%s(), adda_priv == NULL", __func__);481 return 0;482 }483 484 return (adda_priv->ul_rate > HIRES_THRESHOLD) ? 1 : 0;485}486 487static const struct snd_soc_dapm_route mtk_dai_adda_routes[] = {488 /* playback */489 {"ADDA_DL_CH1", "DL1_CH1 Switch", "DL1"},490 {"ADDA_DL_CH2", "DL1_CH1 Switch", "DL1"},491 {"ADDA_DL_CH2", "DL1_CH2 Switch", "DL1"},492 493 {"ADDA_DL_CH1", "DL12_CH1 Switch", "DL12"},494 {"ADDA_DL_CH2", "DL12_CH2 Switch", "DL12"},495 496 {"ADDA_DL_CH1", "DL6_CH1 Switch", "DL6"},497 {"ADDA_DL_CH2", "DL6_CH2 Switch", "DL6"},498 499 {"ADDA_DL_CH1", "DL8_CH1 Switch", "DL8"},500 {"ADDA_DL_CH2", "DL8_CH2 Switch", "DL8"},501 502 {"ADDA_DL_CH1", "DL2_CH1 Switch", "DL2"},503 {"ADDA_DL_CH2", "DL2_CH1 Switch", "DL2"},504 {"ADDA_DL_CH2", "DL2_CH2 Switch", "DL2"},505 506 {"ADDA_DL_CH1", "DL3_CH1 Switch", "DL3"},507 {"ADDA_DL_CH2", "DL3_CH1 Switch", "DL3"},508 {"ADDA_DL_CH2", "DL3_CH2 Switch", "DL3"},509 510 {"ADDA_DL_CH1", "DL4_CH1 Switch", "DL4"},511 {"ADDA_DL_CH2", "DL4_CH2 Switch", "DL4"},512 513 {"ADDA_DL_CH1", "DL5_CH1 Switch", "DL5"},514 {"ADDA_DL_CH2", "DL5_CH2 Switch", "DL5"},515 516 {"ADDA Playback", NULL, "ADDA_DL_CH1"},517 {"ADDA Playback", NULL, "ADDA_DL_CH2"},518 519 {"ADDA Playback", NULL, "ADDA Enable"},520 {"ADDA Playback", NULL, "ADDA Playback Enable"},521 522 /* capture */523 {"ADDA_UL_Mux", "MTKAIF", "ADDA Capture"},524 {"ADDA_UL_Mux", "AP_DMIC", "AP DMIC Capture"},525 526 {"ADDA Capture", NULL, "ADDA Enable"},527 {"ADDA Capture", NULL, "ADDA Capture Enable"},528 {"ADDA Capture", NULL, "AUD_PAD_TOP"},529 {"ADDA Capture", NULL, "ADDA_MTKAIF_CFG"},530 531 {"AP DMIC Capture", NULL, "ADDA Enable"},532 {"AP DMIC Capture", NULL, "ADDA Capture Enable"},533 {"AP DMIC Capture", NULL, "ADDA_FIFO"},534 {"AP DMIC Capture", NULL, "AP_DMIC_EN"},535 536 {"AP DMIC Capture", NULL, "AP_DMIC_INPUT"},537 538 /* clk */539 {"ADDA Playback", NULL, "aud_dac_clk"},540 {"ADDA Playback", NULL, "aud_dac_predis_clk"},541 {"ADDA Playback", NULL, "aud_dac_hires_clk", mtk_afe_dac_hires_connect},542 543 {"ADDA Capture Enable", NULL, "aud_adc_clk"},544 {"ADDA Capture Enable", NULL, "aud_adc_hires_clk",545 mtk_afe_adc_hires_connect},546 547 /* hires source from apll1 */548 {"top_mux_audio_h", NULL, APLL2_W_NAME},549 550 {"aud_dac_hires_clk", NULL, "top_mux_audio_h"},551 {"aud_adc_hires_clk", NULL, "top_mux_audio_h"},552};553 554/* dai ops */555static int mtk_dai_adda_hw_params(struct snd_pcm_substream *substream,556 struct snd_pcm_hw_params *params,557 struct snd_soc_dai *dai)558{559 struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);560 struct mt8186_afe_private *afe_priv = afe->platform_priv;561 unsigned int rate = params_rate(params);562 int id = dai->id;563 struct mtk_afe_adda_priv *adda_priv = afe_priv->dai_priv[id];564 565 dev_dbg(afe->dev, "%s(), id %d, stream %d, rate %d\n",566 __func__, id, substream->stream, rate);567 568 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {569 unsigned int dl_src2_con0;570 unsigned int dl_src2_con1;571 572 adda_priv->dl_rate = rate;573 574 /* set sampling rate */575 dl_src2_con0 = mtk_adda_dl_rate_transform(afe, rate) <<576 DL_2_INPUT_MODE_CTL_SFT;577 578 /* set output mode, UP_SAMPLING_RATE_X8 */579 dl_src2_con0 |= (0x3 << DL_2_OUTPUT_SEL_CTL_SFT);580 581 /* turn off mute function */582 dl_src2_con0 |= BIT(DL_2_MUTE_CH2_OFF_CTL_PRE_SFT);583 dl_src2_con0 |= BIT(DL_2_MUTE_CH1_OFF_CTL_PRE_SFT);584 585 /* set voice input data if input sample rate is 8k or 16k */586 if (rate == 8000 || rate == 16000)587 dl_src2_con0 |= BIT(DL_2_VOICE_MODE_CTL_PRE_SFT);588 589 /* SA suggest apply -0.3db to audio/speech path */590 dl_src2_con1 = MTK_AFE_ADDA_DL_GAIN_NORMAL <<591 DL_2_GAIN_CTL_PRE_SFT;592 593 /* turn on down-link gain */594 dl_src2_con0 |= BIT(DL_2_GAIN_ON_CTL_PRE_SFT);595 596 if (id == MT8186_DAI_ADDA) {597 /* clean predistortion */598 regmap_write(afe->regmap, AFE_ADDA_PREDIS_CON0, 0);599 regmap_write(afe->regmap, AFE_ADDA_PREDIS_CON1, 0);600 601 regmap_write(afe->regmap,602 AFE_ADDA_DL_SRC2_CON0, dl_src2_con0);603 regmap_write(afe->regmap,604 AFE_ADDA_DL_SRC2_CON1, dl_src2_con1);605 606 /* set sdm gain */607 regmap_update_bits(afe->regmap,608 AFE_ADDA_DL_SDM_DCCOMP_CON,609 ATTGAIN_CTL_MASK_SFT,610 AUDIO_SDM_LEVEL_NORMAL <<611 ATTGAIN_CTL_SFT);612 613 /* Use new 2nd sdm */614 regmap_update_bits(afe->regmap,615 AFE_ADDA_DL_SDM_DITHER_CON,616 AFE_DL_SDM_DITHER_64TAP_EN_MASK_SFT,617 BIT(AFE_DL_SDM_DITHER_64TAP_EN_SFT));618 regmap_update_bits(afe->regmap,619 AFE_ADDA_DL_SDM_AUTO_RESET_CON,620 AFE_DL_USE_NEW_2ND_SDM_MASK_SFT,621 BIT(AFE_DL_USE_NEW_2ND_SDM_SFT));622 regmap_update_bits(afe->regmap,623 AFE_ADDA_DL_SDM_DCCOMP_CON,624 USE_3RD_SDM_MASK_SFT,625 AUDIO_SDM_2ND << USE_3RD_SDM_SFT);626 627 /* sdm auto reset */628 regmap_write(afe->regmap,629 AFE_ADDA_DL_SDM_AUTO_RESET_CON,630 SDM_AUTO_RESET_THRESHOLD);631 regmap_update_bits(afe->regmap,632 AFE_ADDA_DL_SDM_AUTO_RESET_CON,633 SDM_AUTO_RESET_TEST_ON_MASK_SFT,634 BIT(SDM_AUTO_RESET_TEST_ON_SFT));635 }636 } else {637 unsigned int ul_src_con0 = 0;638 unsigned int voice_mode = mtk_adda_ul_rate_transform(afe, rate);639 640 adda_priv->ul_rate = rate;641 ul_src_con0 |= (voice_mode << 17) & (0x7 << 17);642 643 /* enable iir */644 ul_src_con0 |= (1 << UL_IIR_ON_TMP_CTL_SFT) &645 UL_IIR_ON_TMP_CTL_MASK_SFT;646 ul_src_con0 |= (UL_IIR_SW << UL_IIRMODE_CTL_SFT) &647 UL_IIRMODE_CTL_MASK_SFT;648 switch (id) {649 case MT8186_DAI_ADDA:650 case MT8186_DAI_AP_DMIC:651 /* 35Hz @ 48k */652 regmap_write(afe->regmap,653 AFE_ADDA_IIR_COEF_02_01, 0);654 regmap_write(afe->regmap,655 AFE_ADDA_IIR_COEF_04_03, 0x3fb8);656 regmap_write(afe->regmap,657 AFE_ADDA_IIR_COEF_06_05, 0x3fb80000);658 regmap_write(afe->regmap,659 AFE_ADDA_IIR_COEF_08_07, 0x3fb80000);660 regmap_write(afe->regmap,661 AFE_ADDA_IIR_COEF_10_09, 0xc048);662 663 regmap_write(afe->regmap,664 AFE_ADDA_UL_SRC_CON0, ul_src_con0);665 666 /* Using Internal ADC */667 regmap_update_bits(afe->regmap, AFE_ADDA_TOP_CON0, BIT(0), 0);668 669 /* mtkaif_rxif_data_mode = 0, amic */670 regmap_update_bits(afe->regmap, AFE_ADDA_MTKAIF_RX_CFG0, BIT(0), 0);671 break;672 default:673 break;674 }675 676 /* ap dmic */677 switch (id) {678 case MT8186_DAI_AP_DMIC:679 mtk_adda_ul_src_dmic(afe, id);680 break;681 default:682 break;683 }684 }685 686 return 0;687}688 689static const struct snd_soc_dai_ops mtk_dai_adda_ops = {690 .hw_params = mtk_dai_adda_hw_params,691};692 693/* dai driver */694#define MTK_ADDA_PLAYBACK_RATES (SNDRV_PCM_RATE_8000_48000 |\695 SNDRV_PCM_RATE_96000 |\696 SNDRV_PCM_RATE_192000)697 698#define MTK_ADDA_CAPTURE_RATES (SNDRV_PCM_RATE_8000 |\699 SNDRV_PCM_RATE_16000 |\700 SNDRV_PCM_RATE_32000 |\701 SNDRV_PCM_RATE_48000 |\702 SNDRV_PCM_RATE_96000 |\703 SNDRV_PCM_RATE_192000)704 705#define MTK_ADDA_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\706 SNDRV_PCM_FMTBIT_S24_LE |\707 SNDRV_PCM_FMTBIT_S32_LE)708 709static struct snd_soc_dai_driver mtk_dai_adda_driver[] = {710 {711 .name = "ADDA",712 .id = MT8186_DAI_ADDA,713 .playback = {714 .stream_name = "ADDA Playback",715 .channels_min = 1,716 .channels_max = 2,717 .rates = MTK_ADDA_PLAYBACK_RATES,718 .formats = MTK_ADDA_FORMATS,719 },720 .capture = {721 .stream_name = "ADDA Capture",722 .channels_min = 1,723 .channels_max = 2,724 .rates = MTK_ADDA_CAPTURE_RATES,725 .formats = MTK_ADDA_FORMATS,726 },727 .ops = &mtk_dai_adda_ops,728 },729 {730 .name = "AP_DMIC",731 .id = MT8186_DAI_AP_DMIC,732 .capture = {733 .stream_name = "AP DMIC Capture",734 .channels_min = 1,735 .channels_max = 2,736 .rates = MTK_ADDA_CAPTURE_RATES,737 .formats = MTK_ADDA_FORMATS,738 },739 .ops = &mtk_dai_adda_ops,740 },741};742 743int mt8186_dai_adda_register(struct mtk_base_afe *afe)744{745 struct mtk_base_afe_dai *dai;746 struct mt8186_afe_private *afe_priv = afe->platform_priv;747 int ret;748 749 dai = devm_kzalloc(afe->dev, sizeof(*dai), GFP_KERNEL);750 if (!dai)751 return -ENOMEM;752 753 list_add(&dai->list, &afe->sub_dais);754 755 dai->dai_drivers = mtk_dai_adda_driver;756 dai->num_dai_drivers = ARRAY_SIZE(mtk_dai_adda_driver);757 758 dai->controls = mtk_adda_controls;759 dai->num_controls = ARRAY_SIZE(mtk_adda_controls);760 dai->dapm_widgets = mtk_dai_adda_widgets;761 dai->num_dapm_widgets = ARRAY_SIZE(mtk_dai_adda_widgets);762 dai->dapm_routes = mtk_dai_adda_routes;763 dai->num_dapm_routes = ARRAY_SIZE(mtk_dai_adda_routes);764 765 /* set dai priv */766 ret = mt8186_dai_set_priv(afe, MT8186_DAI_ADDA,767 sizeof(struct mtk_afe_adda_priv), NULL);768 if (ret)769 return ret;770 771 /* ap dmic priv share with adda */772 afe_priv->dai_priv[MT8186_DAI_AP_DMIC] =773 afe_priv->dai_priv[MT8186_DAI_ADDA];774 775 return 0;776}777