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1/* SPDX-License-Identifier: GPL-2.02 *3 * mt8186-reg.h -- Mediatek 8186 audio driver reg definition4 *5 * Copyright (c) 2022 MediaTek Inc.6 * Author: Jiaxin Yu <jiaxin.yu@mediatek.com>7 */8 9#ifndef _MT8186_REG_H_10#define _MT8186_REG_H_11 12/* reg bit enum */13enum {14 MT8186_MEMIF_PBUF_SIZE_32_BYTES,15 MT8186_MEMIF_PBUF_SIZE_64_BYTES,16 MT8186_MEMIF_PBUF_SIZE_128_BYTES,17 MT8186_MEMIF_PBUF_SIZE_256_BYTES,18 MT8186_MEMIF_PBUF_SIZE_NUM,19};20 21/*****************************************************************************22 * R E G I S T E R D E F I N I T I O N23 *****************************************************************************/24/* AUDIO_TOP_CON0 */25#define RESERVED_SFT 3126#define RESERVED_MASK_SFT BIT(31)27#define AHB_IDLE_EN_INT_SFT 3028#define AHB_IDLE_EN_INT_MASK_SFT BIT(30)29#define AHB_IDLE_EN_EXT_SFT 2930#define AHB_IDLE_EN_EXT_MASK_SFT BIT(29)31#define PDN_NLE_SFT 2832#define PDN_NLE_MASK_SFT BIT(28)33#define PDN_TML_SFT 2734#define PDN_TML_MASK_SFT BIT(27)35#define PDN_DAC_PREDIS_SFT 2636#define PDN_DAC_PREDIS_MASK_SFT BIT(26)37#define PDN_DAC_SFT 2538#define PDN_DAC_MASK_SFT BIT(25)39#define PDN_ADC_SFT 2440#define PDN_ADC_MASK_SFT BIT(24)41#define PDN_TDM_CK_SFT 2042#define PDN_TDM_CK_MASK_SFT BIT(20)43#define PDN_APLL_TUNER_SFT 1944#define PDN_APLL_TUNER_MASK_SFT BIT(19)45#define PDN_APLL2_TUNER_SFT 1846#define PDN_APLL2_TUNER_MASK_SFT BIT(18)47#define APB3_SEL_SFT 1448#define APB3_SEL_MASK_SFT BIT(14)49#define APB_R2T_SFT 1350#define APB_R2T_MASK_SFT BIT(13)51#define APB_W2T_SFT 1252#define APB_W2T_MASK_SFT BIT(12)53#define PDN_24M_SFT 954#define PDN_24M_MASK_SFT BIT(9)55#define PDN_22M_SFT 856#define PDN_22M_MASK_SFT BIT(8)57#define PDN_AFE_SFT 258#define PDN_AFE_MASK_SFT BIT(2)59 60/* AUDIO_TOP_CON1 */61#define PDN_3RD_DAC_HIRES_SFT 3162#define PDN_3RD_DAC_HIRES_MASK_SFT BIT(31)63#define PDN_3RD_DAC_TML_SFT 3064#define PDN_3RD_DAC_TML_MASK_SFT BIT(30)65#define PDN_3RD_DAC_PREDIS_SFT 2966#define PDN_3RD_DAC_PREDIS_MASK_SFT BIT(29)67#define PDN_3RD_DAC_SFT 2868#define PDN_3RD_DAC_MASK_SFT BIT(28)69#define I2S_SOFT_RST5_SFT 2270#define I2S_SOFT_RST5_MASK_SFT BIT(22)71#define PDN_ADDA6_ADC_HIRES_SFT 2172#define PDN_ADDA6_ADC_HIRES_MASK_SFT BIT(21)73#define PDN_ADDA6_ADC_SFT 2074#define PDN_ADDA6_ADC_MASK_SFT BIT(20)75#define PDN_ADC_HIRES_TML_SFT 1776#define PDN_ADC_HIRES_TML_MASK_SFT BIT(17)77#define PDN_ADC_HIRES_SFT 1678#define PDN_ADC_HIRES_MASK_SFT BIT(16)79#define PDN_DAC_HIRES_SFT 1580#define PDN_DAC_HIRES_MASK_SFT BIT(15)81#define PDN_GENERAL2_ASRC_SFT 1482#define PDN_GENERAL2_ASRC_MASK_SFT BIT(14)83#define PDN_GENERAL1_ASRC_SFT 1384#define PDN_GENERAL1_ASRC_MASK_SFT BIT(13)85#define PDN_CONNSYS_I2S_ASRC_SFT 1286#define PDN_CONNSYS_I2S_ASRC_MASK_SFT BIT(12)87#define I2S4_BCLK_SW_CG_SFT 788#define I2S4_BCLK_SW_CG_MASK_SFT BIT(7)89#define I2S3_BCLK_SW_CG_SFT 690#define I2S3_BCLK_SW_CG_MASK_SFT BIT(6)91#define I2S2_BCLK_SW_CG_SFT 592#define I2S2_BCLK_SW_CG_MASK_SFT BIT(5)93#define I2S1_BCLK_SW_CG_SFT 494#define I2S1_BCLK_SW_CG_MASK_SFT BIT(4)95#define I2S_SOFT_RST2_SFT 296#define I2S_SOFT_RST2_MASK_SFT BIT(2)97#define I2S_SOFT_RST_SFT 198#define I2S_SOFT_RST_MASK_SFT BIT(1)99 100/* AUDIO_TOP_CON3 */101#define BUSY_SFT 31102#define BUSY_MASK_SFT BIT(31)103#define OS_DISABLE_SFT 30104#define OS_DISABLE_MASK_SFT BIT(30)105#define CG_DISABLE_SFT 29106#define CG_DISABLE_MASK_SFT BIT(29)107#define CLEAR_FLAG_SFT 0108#define CLEAR_FLAG_MASK_SFT BIT(0)109 110/* AFE_DAC_CON0 */111#define VUL12_ON_SFT 31112#define VUL12_ON_MASK_SFT BIT(31)113#define MOD_DAI_ON_SFT 30114#define MOD_DAI_ON_MASK_SFT BIT(30)115#define DAI_ON_SFT 29116#define DAI_ON_MASK_SFT BIT(29)117#define DAI2_ON_SFT 28118#define DAI2_ON_MASK_SFT BIT(28)119#define VUL6_ON_SFT 23120#define VUL6_ON_MASK_SFT BIT(23)121#define VUL5_ON_SFT 22122#define VUL5_ON_MASK_SFT BIT(22)123#define VUL4_ON_SFT 21124#define VUL4_ON_MASK_SFT BIT(21)125#define VUL3_ON_SFT 20126#define VUL3_ON_MASK_SFT BIT(20)127#define VUL2_ON_SFT 19128#define VUL2_ON_MASK_SFT BIT(19)129#define VUL_ON_SFT 18130#define VUL_ON_MASK_SFT BIT(18)131#define AWB2_ON_SFT 17132#define AWB2_ON_MASK_SFT BIT(17)133#define AWB_ON_SFT 16134#define AWB_ON_MASK_SFT BIT(16)135#define DL12_ON_SFT 15136#define DL12_ON_MASK_SFT BIT(15)137#define DL8_ON_SFT 11138#define DL8_ON_MASK_SFT BIT(11)139#define DL7_ON_SFT 10140#define DL7_ON_MASK_SFT BIT(10)141#define DL6_ON_SFT 9142#define DL6_ON_MASK_SFT BIT(9)143#define DL5_ON_SFT 8144#define DL5_ON_MASK_SFT BIT(8)145#define DL4_ON_SFT 7146#define DL4_ON_MASK_SFT BIT(7)147#define DL3_ON_SFT 6148#define DL3_ON_MASK_SFT BIT(6)149#define DL2_ON_SFT 5150#define DL2_ON_MASK_SFT BIT(5)151#define DL1_ON_SFT 4152#define DL1_ON_MASK_SFT BIT(4)153#define AUDIO_AFE_ON_SFT 0154#define AUDIO_AFE_ON_MASK_SFT BIT(0)155 156/* AFE_DAC_MON */157#define AFE_ON_RETM_SFT 0158#define AFE_ON_RETM_MASK_SFT BIT(0)159 160/* AFE_I2S_CON */161#define BCK_NEG_EG_LATCH_SFT 30162#define BCK_NEG_EG_LATCH_MASK_SFT BIT(30)163#define BCK_INV_SFT 29164#define BCK_INV_MASK_SFT BIT(29)165#define I2SIN_PAD_SEL_SFT 28166#define I2SIN_PAD_SEL_MASK_SFT BIT(28)167#define I2S_LOOPBACK_SFT 20168#define I2S_LOOPBACK_MASK_SFT BIT(20)169#define I2S_ONOFF_NOT_RESET_CK_ENABLE_SFT 17170#define I2S_ONOFF_NOT_RESET_CK_ENABLE_MASK_SFT BIT(17)171#define I2S1_HD_EN_SFT 12172#define I2S1_HD_EN_MASK_SFT BIT(12)173#define I2S_OUT_MODE_SFT 8174#define I2S_OUT_MODE_MASK_SFT GENMASK(11, 8)175#define INV_PAD_CTRL_SFT 7176#define INV_PAD_CTRL_MASK_SFT BIT(7)177#define I2S_BYPSRC_SFT 6178#define I2S_BYPSRC_MASK_SFT BIT(6)179#define INV_LRCK_SFT 5180#define INV_LRCK_MASK_SFT BIT(5)181#define I2S_FMT_SFT 3182#define I2S_FMT_MASK_SFT BIT(3)183#define I2S_SRC_SFT 2184#define I2S_SRC_MASK_SFT BIT(2)185#define I2S_WLEN_SFT 1186#define I2S_WLEN_MASK_SFT BIT(1)187#define I2S_EN_SFT 0188#define I2S_EN_MASK_SFT BIT(0)189 190/* AFE_I2S_CON1 */191#define I2S2_LR_SWAP_SFT 31192#define I2S2_LR_SWAP_MASK_SFT BIT(31)193#define I2S2_SEL_O19_O20_SFT 18194#define I2S2_SEL_O19_O20_MASK_SFT BIT(18)195#define I2S_ONOFF_NOT_RESET_CK_ENABLE_SFT 17196#define I2S_ONOFF_NOT_RESET_CK_ENABLE_MASK_SFT BIT(17)197#define I2S2_SEL_O03_O04_SFT 16198#define I2S2_SEL_O03_O04_MASK_SFT BIT(16)199#define I2S2_HD_EN_SFT 12200#define I2S2_HD_EN_MASK_SFT BIT(12)201#define I2S2_OUT_MODE_SFT 8202#define I2S2_OUT_MODE_MASK_SFT GENMASK(11, 8)203#define INV_LRCK_SFT 5204#define INV_LRCK_MASK_SFT BIT(5)205#define I2S2_FMT_SFT 3206#define I2S2_FMT_MASK_SFT BIT(3)207#define I2S2_WLEN_SFT 1208#define I2S2_WLEN_MASK_SFT BIT(1)209#define I2S2_EN_SFT 0210#define I2S2_EN_MASK_SFT BIT(0)211 212/* AFE_I2S_CON2 */213#define I2S3_LR_SWAP_SFT 31214#define I2S3_LR_SWAP_MASK_SFT BIT(31)215#define I2S3_UPDATE_WORD_SFT 24216#define I2S3_UPDATE_WORD_MASK_SFT GENMASK(28, 24)217#define I2S3_BCK_INV_SFT 23218#define I2S3_BCK_INV_MASK_SFT BIT(23)219#define I2S3_FPGA_BIT_TEST_SFT 22220#define I2S3_FPGA_BIT_TEST_MASK_SFT BIT(22)221#define I2S3_FPGA_BIT_SFT 21222#define I2S3_FPGA_BIT_MASK_SFT BIT(21)223#define I2S3_LOOPBACK_SFT 20224#define I2S3_LOOPBACK_MASK_SFT BIT(20)225#define I2S_ONOFF_NOT_RESET_CK_ENABLE_SFT 17226#define I2S_ONOFF_NOT_RESET_CK_ENABLE_MASK_SFT BIT(17)227#define I2S3_HD_EN_SFT 12228#define I2S3_HD_EN_MASK_SFT BIT(12)229#define I2S3_OUT_MODE_SFT 8230#define I2S3_OUT_MODE_MASK_SFT GENMASK(11, 8)231#define I2S3_FMT_SFT 3232#define I2S3_FMT_MASK_SFT BIT(3)233#define I2S3_WLEN_SFT 1234#define I2S3_WLEN_MASK_SFT BIT(1)235#define I2S3_EN_SFT 0236#define I2S3_EN_MASK_SFT BIT(0)237 238/* AFE_I2S_CON3 */239#define I2S4_LR_SWAP_SFT 31240#define I2S4_LR_SWAP_MASK_SFT BIT(31)241#define I2S_ONOFF_NOT_RESET_CK_ENABLE_SFT 17242#define I2S_ONOFF_NOT_RESET_CK_ENABLE_MASK_SFT BIT(17)243#define I2S4_HD_EN_SFT 12244#define I2S4_HD_EN_MASK_SFT BIT(12)245#define I2S4_OUT_MODE_SFT 8246#define I2S4_OUT_MODE_MASK_SFT GENMASK(11, 8)247#define INV_LRCK_SFT 5248#define INV_LRCK_MASK_SFT BIT(5)249#define I2S4_FMT_SFT 3250#define I2S4_FMT_MASK_SFT BIT(3)251#define I2S4_WLEN_SFT 1252#define I2S4_WLEN_MASK_SFT BIT(1)253#define I2S4_EN_SFT 0254#define I2S4_EN_MASK_SFT BIT(0)255 256/* AFE_I2S_CON4 */257#define I2S_LOOPBACK_SFT 20258#define I2S_LOOPBACK_MASK 0x1259#define I2S_LOOPBACK_MASK_SFT BIT(20)260#define I2S_ONOFF_NOT_RESET_CK_ENABLE_SFT 17261#define I2S_ONOFF_NOT_RESET_CK_ENABLE_MASK 0x1262#define I2S_ONOFF_NOT_RESET_CK_ENABLE_MASK_SFT BIT(17)263#define INV_LRCK_SFT 5264#define INV_LRCK_MASK 0x1265#define INV_LRCK_MASK_SFT BIT(5)266 267/* AFE_CONNSYS_I2S_CON */268#define BCK_NEG_EG_LATCH_SFT 30269#define BCK_NEG_EG_LATCH_MASK_SFT BIT(30)270#define BCK_INV_SFT 29271#define BCK_INV_MASK_SFT BIT(29)272#define I2SIN_PAD_SEL_SFT 28273#define I2SIN_PAD_SEL_MASK_SFT BIT(28)274#define I2S_LOOPBACK_SFT 20275#define I2S_LOOPBACK_MASK_SFT BIT(20)276#define I2S_ONOFF_NOT_RESET_CK_ENABLE_SFT 17277#define I2S_ONOFF_NOT_RESET_CK_ENABLE_MASK_SFT BIT(17)278#define I2S_MODE_SFT 8279#define I2S_MODE_MASK_SFT GENMASK(11, 8)280#define INV_PAD_CTRL_SFT 7281#define INV_PAD_CTRL_MASK_SFT BIT(7)282#define I2S_BYPSRC_SFT 6283#define I2S_BYPSRC_MASK_SFT BIT(6)284#define INV_LRCK_SFT 5285#define INV_LRCK_MASK_SFT BIT(5)286#define I2S_FMT_SFT 3287#define I2S_FMT_MASK_SFT BIT(3)288#define I2S_SRC_SFT 2289#define I2S_SRC_MASK_SFT BIT(2)290#define I2S_WLEN_SFT 1291#define I2S_WLEN_MASK_SFT BIT(1)292#define I2S_EN_SFT 0293#define I2S_EN_MASK_SFT BIT(0)294 295/* AFE_ASRC_2CH_CON2 */296#define CHSET_O16BIT_SFT 19297#define CHSET_O16BIT_MASK_SFT BIT(19)298#define CHSET_CLR_IIR_HISTORY_SFT 17299#define CHSET_CLR_IIR_HISTORY_MASK_SFT BIT(17)300#define CHSET_IS_MONO_SFT 16301#define CHSET_IS_MONO_MASK_SFT BIT(16)302#define CHSET_IIR_EN_SFT 11303#define CHSET_IIR_EN_MASK_SFT BIT(11)304#define CHSET_IIR_STAGE_SFT 8305#define CHSET_IIR_STAGE_MASK_SFT GENMASK(10, 8)306#define CHSET_STR_CLR_SFT 5307#define CHSET_STR_CLR_MASK_SFT BIT(5)308#define CHSET_ON_SFT 2309#define CHSET_ON_MASK_SFT BIT(2)310#define COEFF_SRAM_CTRL_SFT 1311#define COEFF_SRAM_CTRL_MASK_SFT BIT(1)312#define ASM_ON_SFT 0313#define ASM_ON_MASK_SFT BIT(0)314 315/* AFE_GAIN1_CON0 */316#define GAIN1_SAMPLE_PER_STEP_SFT 8317#define GAIN1_SAMPLE_PER_STEP_MASK_SFT GENMASK(15, 8)318#define GAIN1_MODE_SFT 4319#define GAIN1_MODE_MASK_SFT GENMASK(7, 4)320#define GAIN1_ON_SFT 0321#define GAIN1_ON_MASK_SFT BIT(0)322 323/* AFE_GAIN1_CON1 */324#define GAIN1_TARGET_SFT 0325#define GAIN1_TARGET_MASK 0xfffffff326#define GAIN1_TARGET_MASK_SFT GENMASK(27, 0)327 328/* AFE_GAIN2_CON0 */329#define GAIN2_SAMPLE_PER_STEP_SFT 8330#define GAIN2_SAMPLE_PER_STEP_MASK_SFT GENMASK(15, 8)331#define GAIN2_MODE_SFT 4332#define GAIN2_MODE_MASK_SFT GENMASK(7, 4)333#define GAIN2_ON_SFT 0334#define GAIN2_ON_MASK_SFT BIT(0)335 336/* AFE_GAIN2_CON1 */337#define GAIN2_TARGET_SFT 0338#define GAIN2_TARGET_MASK 0xfffffff339#define GAIN2_TARGET_MASK_SFT GENMASK(27, 0)340 341/* AFE_GAIN1_CUR */342#define AFE_GAIN1_CUR_SFT 0343#define AFE_GAIN1_CUR_MASK_SFT GENMASK(27, 0)344 345/* AFE_GAIN2_CUR */346#define AFE_GAIN2_CUR_SFT 0347#define AFE_GAIN2_CUR_MASK_SFT GENMASK(27, 0)348 349/* PCM_INTF_CON1 */350#define PCM_FIX_VALUE_SEL_SFT 31351#define PCM_FIX_VALUE_SEL_MASK_SFT BIT(31)352#define PCM_BUFFER_LOOPBACK_SFT 30353#define PCM_BUFFER_LOOPBACK_MASK_SFT BIT(30)354#define PCM_PARALLEL_LOOPBACK_SFT 29355#define PCM_PARALLEL_LOOPBACK_MASK_SFT BIT(29)356#define PCM_SERIAL_LOOPBACK_SFT 28357#define PCM_SERIAL_LOOPBACK_MASK_SFT BIT(28)358#define PCM_DAI_PCM_LOOPBACK_SFT 27359#define PCM_DAI_PCM_LOOPBACK_MASK_SFT BIT(27)360#define PCM_I2S_PCM_LOOPBACK_SFT 26361#define PCM_I2S_PCM_LOOPBACK_MASK_SFT BIT(26)362#define PCM_SYNC_DELSEL_SFT 25363#define PCM_SYNC_DELSEL_MASK_SFT BIT(25)364#define PCM_TX_LR_SWAP_SFT 24365#define PCM_TX_LR_SWAP_MASK_SFT BIT(24)366#define PCM_SYNC_OUT_INV_SFT 23367#define PCM_SYNC_OUT_INV_MASK_SFT BIT(23)368#define PCM_BCLK_OUT_INV_SFT 22369#define PCM_BCLK_OUT_INV_MASK_SFT BIT(22)370#define PCM_SYNC_IN_INV_SFT 21371#define PCM_SYNC_IN_INV_MASK_SFT BIT(21)372#define PCM_BCLK_IN_INV_SFT 20373#define PCM_BCLK_IN_INV_MASK_SFT BIT(20)374#define PCM_TX_LCH_RPT_SFT 19375#define PCM_TX_LCH_RPT_MASK_SFT BIT(19)376#define PCM_VBT_16K_MODE_SFT 18377#define PCM_VBT_16K_MODE_MASK_SFT BIT(18)378#define PCM_EXT_MODEM_SFT 17379#define PCM_EXT_MODEM_MASK_SFT BIT(17)380#define PCM_24BIT_SFT 16381#define PCM_24BIT_MASK_SFT BIT(16)382#define PCM_WLEN_SFT 14383#define PCM_WLEN_MASK_SFT GENMASK(15, 14)384#define PCM_SYNC_LENGTH_SFT 9385#define PCM_SYNC_LENGTH_MASK_SFT GENMASK(13, 9)386#define PCM_SYNC_TYPE_SFT 8387#define PCM_SYNC_TYPE_MASK_SFT BIT(8)388#define PCM_BT_MODE_SFT 7389#define PCM_BT_MODE_MASK_SFT BIT(7)390#define PCM_BYP_ASRC_SFT 6391#define PCM_BYP_ASRC_MASK_SFT BIT(6)392#define PCM_SLAVE_SFT 5393#define PCM_SLAVE_MASK_SFT BIT(5)394#define PCM_MODE_SFT 3395#define PCM_MODE_MASK_SFT GENMASK(4, 3)396#define PCM_FMT_SFT 1397#define PCM_FMT_MASK_SFT GENMASK(2, 1)398#define PCM_EN_SFT 0399#define PCM_EN_MASK_SFT BIT(0)400 401/* PCM_INTF_CON2 */402#define PCM1_TX_FIFO_OV_SFT 31403#define PCM1_TX_FIFO_OV_MASK_SFT BIT(31)404#define PCM1_RX_FIFO_OV_SFT 30405#define PCM1_RX_FIFO_OV_MASK_SFT BIT(30)406#define PCM2_TX_FIFO_OV_SFT 29407#define PCM2_TX_FIFO_OV_MASK_SFT BIT(29)408#define PCM2_RX_FIFO_OV_SFT 28409#define PCM2_RX_FIFO_OV_MASK_SFT BIT(28)410#define PCM1_SYNC_GLITCH_SFT 27411#define PCM1_SYNC_GLITCH_MASK_SFT BIT(27)412#define PCM2_SYNC_GLITCH_SFT 26413#define PCM2_SYNC_GLITCH_MASK_SFT BIT(26)414#define TX3_RCH_DBG_MODE_SFT 17415#define TX3_RCH_DBG_MODE_MASK_SFT BIT(17)416#define PCM1_PCM2_LOOPBACK_SFT 16417#define PCM1_PCM2_LOOPBACK_MASK_SFT BIT(16)418#define DAI_PCM_LOOPBACK_CH_SFT 14419#define DAI_PCM_LOOPBACK_CH_MASK_SFT GENMASK(15, 14)420#define I2S_PCM_LOOPBACK_CH_SFT 12421#define I2S_PCM_LOOPBACK_CH_MASK_SFT GENMASK(13, 12)422#define TX_FIX_VALUE_SFT 0423#define TX_FIX_VALUE_MASK_SFT GENMASK(7, 0)424 425/* PCM2_INTF_CON */426#define PCM2_TX_FIX_VALUE_SFT 24427#define PCM2_TX_FIX_VALUE_MASK_SFT GENMASK(31, 24)428#define PCM2_FIX_VALUE_SEL_SFT 23429#define PCM2_FIX_VALUE_SEL_MASK_SFT BIT(23)430#define PCM2_BUFFER_LOOPBACK_SFT 22431#define PCM2_BUFFER_LOOPBACK_MASK_SFT BIT(22)432#define PCM2_PARALLEL_LOOPBACK_SFT 21433#define PCM2_PARALLEL_LOOPBACK_MASK_SFT BIT(21)434#define PCM2_SERIAL_LOOPBACK_SFT 20435#define PCM2_SERIAL_LOOPBACK_MASK_SFT BIT(20)436#define PCM2_DAI_PCM_LOOPBACK_SFT 19437#define PCM2_DAI_PCM_LOOPBACK_MASK_SFT BIT(19)438#define PCM2_I2S_PCM_LOOPBACK_SFT 18439#define PCM2_I2S_PCM_LOOPBACK_MASK_SFT BIT(18)440#define PCM2_SYNC_DELSEL_SFT 17441#define PCM2_SYNC_DELSEL_MASK_SFT BIT(17)442#define PCM2_TX_LR_SWAP_SFT 16443#define PCM2_TX_LR_SWAP_MASK_SFT BIT(16)444#define PCM2_SYNC_IN_INV_SFT 15445#define PCM2_SYNC_IN_INV_MASK_SFT BIT(15)446#define PCM2_BCLK_IN_INV_SFT 14447#define PCM2_BCLK_IN_INV_MASK_SFT BIT(14)448#define PCM2_TX_LCH_RPT_SFT 13449#define PCM2_TX_LCH_RPT_MASK_SFT BIT(13)450#define PCM2_VBT_16K_MODE_SFT 12451#define PCM2_VBT_16K_MODE_MASK_SFT BIT(12)452#define PCM2_LOOPBACK_CH_SEL_SFT 10453#define PCM2_LOOPBACK_CH_SEL_MASK_SFT GENMASK(11, 10)454#define PCM2_TX2_BT_MODE_SFT 8455#define PCM2_TX2_BT_MODE_MASK_SFT BIT(8)456#define PCM2_BT_MODE_SFT 7457#define PCM2_BT_MODE_MASK_SFT BIT(7)458#define PCM2_AFIFO_SFT 6459#define PCM2_AFIFO_MASK_SFT BIT(6)460#define PCM2_WLEN_SFT 5461#define PCM2_WLEN_MASK_SFT BIT(5)462#define PCM2_MODE_SFT 3463#define PCM2_MODE_MASK_SFT GENMASK(4, 3)464#define PCM2_FMT_SFT 1465#define PCM2_FMT_MASK_SFT GENMASK(2, 1)466#define PCM2_EN_SFT 0467#define PCM2_EN_MASK_SFT BIT(0)468 469// AFE_CM1_CON470#define CHANNEL_MERGE0_DEBUG_MODE_SFT (31)471#define CHANNEL_MERGE0_DEBUG_MODE_MASK_SFT BIT(31)472#define VUL3_BYPASS_CM_SFT (30)473#define VUL3_BYPASS_CM_MASK (0x1)474#define VUL3_BYPASS_CM_MASK_SFT BIT(30)475#define CM1_DEBUG_MODE_SEL_SFT (29)476#define CM1_DEBUG_MODE_SEL_MASK_SFT BIT(29)477#define CHANNEL_MERGE0_UPDATE_CNT_SFT (16)478#define CHANNEL_MERGE0_UPDATE_CNT_MASK_SFT GENMASK(28, 16)479#define CM1_FS_SELECT_SFT (8)480#define CM1_FS_SELECT_MASK_SFT GENMASK(12, 8)481#define CHANNEL_MERGE0_CHNUM_SFT (3)482#define CHANNEL_MERGE0_CHNUM_MASK_SFT GENMASK(7, 3)483#define CHANNEL_MERGE0_BYTE_SWAP_SFT (1)484#define CHANNEL_MERGE0_BYTE_SWAP_MASK_SFT BIT(1)485#define CHANNEL_MERGE0_EN_SFT (0)486#define CHANNEL_MERGE0_EN_MASK_SFT BIT(0)487 488/* AFE_ADDA_MTKAIF_CFG0 */489#define MTKAIF_RXIF_CLKINV_ADC_SFT 31490#define MTKAIF_RXIF_CLKINV_ADC_MASK_SFT BIT(31)491#define MTKAIF_RXIF_BYPASS_SRC_SFT 17492#define MTKAIF_RXIF_BYPASS_SRC_MASK_SFT BIT(17)493#define MTKAIF_RXIF_PROTOCOL2_SFT 16494#define MTKAIF_RXIF_PROTOCOL2_MASK_SFT BIT(16)495#define MTKAIF_TXIF_BYPASS_SRC_SFT 5496#define MTKAIF_TXIF_BYPASS_SRC_MASK_SFT BIT(5)497#define MTKAIF_TXIF_PROTOCOL2_SFT 4498#define MTKAIF_TXIF_PROTOCOL2_MASK_SFT BIT(4)499#define MTKAIF_TXIF_8TO5_SFT 2500#define MTKAIF_TXIF_8TO5_MASK_SFT BIT(2)501#define MTKAIF_RXIF_8TO5_SFT 1502#define MTKAIF_RXIF_8TO5_MASK_SFT BIT(1)503#define MTKAIF_IF_LOOPBACK1_SFT 0504#define MTKAIF_IF_LOOPBACK1_MASK_SFT BIT(0)505 506/* AFE_ADDA_MTKAIF_RX_CFG2 */507#define MTKAIF_RXIF_DETECT_ON_PROTOCOL2_SFT 16508#define MTKAIF_RXIF_DETECT_ON_PROTOCOL2_MASK_SFT BIT(16)509#define MTKAIF_RXIF_DELAY_CYCLE_SFT 12510#define MTKAIF_RXIF_DELAY_CYCLE_MASK_SFT GENMASK(15, 12)511#define MTKAIF_RXIF_DELAY_DATA_SFT 8512#define MTKAIF_RXIF_DELAY_DATA_MASK 0x1513#define MTKAIF_RXIF_DELAY_DATA_MASK_SFT BIT(8)514#define MTKAIF_RXIF_FIFO_RSP_PROTOCOL2_SFT 4515#define MTKAIF_RXIF_FIFO_RSP_PROTOCOL2_MASK_SFT GENMASK(6, 4)516 517/* AFE_ADDA_DL_SRC2_CON0 */518#define DL_2_INPUT_MODE_CTL_SFT 28519#define DL_2_INPUT_MODE_CTL_MASK_SFT GENMASK(31, 28)520#define DL_2_CH1_SATURATION_EN_CTL_SFT 27521#define DL_2_CH1_SATURATION_EN_CTL_MASK_SFT BIT(27)522#define DL_2_CH2_SATURATION_EN_CTL_SFT 26523#define DL_2_CH2_SATURATION_EN_CTL_MASK_SFT BIT(26)524#define DL_2_OUTPUT_SEL_CTL_SFT 24525#define DL_2_OUTPUT_SEL_CTL_MASK_SFT GENMASK(25, 24)526#define DL_2_FADEIN_0START_EN_SFT 16527#define DL_2_FADEIN_0START_EN_MASK_SFT GENMASK(17, 16)528#define DL_DISABLE_HW_CG_CTL_SFT 15529#define DL_DISABLE_HW_CG_CTL_MASK_SFT BIT(15)530#define C_DATA_EN_SEL_CTL_PRE_SFT 14531#define C_DATA_EN_SEL_CTL_PRE_MASK_SFT BIT(14)532#define DL_2_SIDE_TONE_ON_CTL_PRE_SFT 13533#define DL_2_SIDE_TONE_ON_CTL_PRE_MASK_SFT BIT(13)534#define DL_2_MUTE_CH1_OFF_CTL_PRE_SFT 12535#define DL_2_MUTE_CH1_OFF_CTL_PRE_MASK_SFT BIT(12)536#define DL_2_MUTE_CH2_OFF_CTL_PRE_SFT 11537#define DL_2_MUTE_CH2_OFF_CTL_PRE_MASK_SFT BIT(11)538#define DL2_ARAMPSP_CTL_PRE_SFT 9539#define DL2_ARAMPSP_CTL_PRE_MASK_SFT GENMASK(10, 9)540#define DL_2_IIRMODE_CTL_PRE_SFT 6541#define DL_2_IIRMODE_CTL_PRE_MASK_SFT GENMASK(8, 6)542#define DL_2_VOICE_MODE_CTL_PRE_SFT 5543#define DL_2_VOICE_MODE_CTL_PRE_MASK_SFT BIT(5)544#define D2_2_MUTE_CH1_ON_CTL_PRE_SFT 4545#define D2_2_MUTE_CH1_ON_CTL_PRE_MASK_SFT BIT(4)546#define D2_2_MUTE_CH2_ON_CTL_PRE_SFT 3547#define D2_2_MUTE_CH2_ON_CTL_PRE_MASK_SFT BIT(3)548#define DL_2_IIR_ON_CTL_PRE_SFT 2549#define DL_2_IIR_ON_CTL_PRE_MASK_SFT BIT(2)550#define DL_2_GAIN_ON_CTL_PRE_SFT 1551#define DL_2_GAIN_ON_CTL_PRE_MASK_SFT BIT(1)552#define DL_2_SRC_ON_CTL_PRE_SFT 0553#define DL_2_SRC_ON_CTL_PRE_MASK_SFT BIT(0)554 555/* AFE_ADDA_DL_SRC2_CON1 */556#define DL_2_GAIN_CTL_PRE_SFT 16557#define DL_2_GAIN_CTL_PRE_MASK 0xffff558#define DL_2_GAIN_CTL_PRE_MASK_SFT GENMASK(31, 16)559#define DL_2_GAIN_MODE_CTL_SFT 0560#define DL_2_GAIN_MODE_CTL_MASK_SFT BIT(0)561 562/* AFE_ADDA_UL_SRC_CON0 */563#define ULCF_CFG_EN_CTL_SFT 31564#define ULCF_CFG_EN_CTL_MASK_SFT BIT(31)565#define UL_DMIC_PHASE_SEL_CH1_SFT 27566#define UL_DMIC_PHASE_SEL_CH1_MASK_SFT GENMASK(29, 27)567#define UL_DMIC_PHASE_SEL_CH2_SFT 24568#define UL_DMIC_PHASE_SEL_CH2_MASK_SFT GENMASK(26, 24)569#define UL_MODE_3P25M_CH2_CTL_SFT 22570#define UL_MODE_3P25M_CH2_CTL_MASK_SFT BIT(22)571#define UL_MODE_3P25M_CH1_CTL_SFT 21572#define UL_MODE_3P25M_CH1_CTL_MASK_SFT BIT(21)573#define UL_VOICE_MODE_CH1_CH2_CTL_SFT 17574#define UL_VOICE_MODE_CH1_CH2_CTL_MASK_SFT GENMASK(19, 17)575#define UL_AP_DMIC_ON_SFT 16576#define UL_AP_DMIC_ON_MASK_SFT BIT(16)577#define DMIC_LOW_POWER_CTL_SFT 14578#define DMIC_LOW_POWER_CTL_MASK_SFT GENMASK(15, 14)579#define UL_DISABLE_HW_CG_CTL_SFT 12580#define UL_DISABLE_HW_CG_CTL_MASK_SFT BIT(12)581#define UL_IIR_ON_TMP_CTL_SFT 10582#define UL_IIR_ON_TMP_CTL_MASK_SFT BIT(10)583#define UL_IIRMODE_CTL_SFT 7584#define UL_IIRMODE_CTL_MASK_SFT GENMASK(9, 7)585#define DIGMIC_4P33M_SEL_SFT 6586#define DIGMIC_4P33M_SEL_MASK_SFT BIT(6)587#define DIGMIC_3P25M_1P625M_SEL_SFT 5588#define DIGMIC_3P25M_1P625M_SEL_MASK_SFT BIT(5)589#define UL_LOOP_BACK_MODE_SFT 2590#define UL_LOOP_BACK_MODE_MASK_SFT BIT(2)591#define UL_SDM_3_LEVEL_SFT 1592#define UL_SDM_3_LEVEL_MASK_SFT BIT(1)593#define UL_SRC_ON_CTL_SFT 0594#define UL_SRC_ON_CTL_MASK_SFT BIT(0)595 596/* AFE_ADDA_UL_SRC_CON1 */597#define C_DAC_EN_CTL_SFT 27598#define C_DAC_EN_CTL_MASK_SFT BIT(27)599#define C_MUTE_SW_CTL_SFT 26600#define C_MUTE_SW_CTL_MASK_SFT BIT(26)601#define ASDM_SRC_SEL_CTL_SFT 25602#define ASDM_SRC_SEL_CTL_MASK_SFT BIT(25)603#define C_AMP_DIV_CH2_CTL_SFT 21604#define C_AMP_DIV_CH2_CTL_MASK_SFT GENMASK(23, 21)605#define C_FREQ_DIV_CH2_CTL_SFT 16606#define C_FREQ_DIV_CH2_CTL_MASK_SFT GENMASK(20, 16)607#define C_SINE_MODE_CH2_CTL_SFT 12608#define C_SINE_MODE_CH2_CTL_MASK_SFT GENMASK(15, 12)609#define C_AMP_DIV_CH1_CTL_SFT 9610#define C_AMP_DIV_CH1_CTL_MASK_SFT GENMASK(11, 9)611#define C_FREQ_DIV_CH1_CTL_SFT 4612#define C_FREQ_DIV_CH1_CTL_MASK_SFT GENMASK(8, 4)613#define C_SINE_MODE_CH1_CTL_SFT 0614#define C_SINE_MODE_CH1_CTL_MASK_SFT GENMASK(3, 0)615 616/* AFE_ADDA_TOP_CON0 */617#define C_LOOP_BACK_MODE_CTL_SFT 12618#define C_LOOP_BACK_MODE_CTL_MASK_SFT GENMASK(15, 12)619#define ADDA_UL_GAIN_MODE_SFT 8620#define ADDA_UL_GAIN_MODE_MASK_SFT GENMASK(9, 8)621#define C_EXT_ADC_CTL_SFT 0622#define C_EXT_ADC_CTL_MASK_SFT BIT(0)623 624/* AFE_ADDA_UL_DL_CON0 */625#define AFE_ADDA_UL_LR_SWAP_SFT 31626#define AFE_ADDA_UL_LR_SWAP_MASK_SFT BIT(31)627#define AFE_ADDA_CKDIV_RST_SFT 30628#define AFE_ADDA_CKDIV_RST_MASK_SFT BIT(30)629#define AFE_ADDA_FIFO_AUTO_RST_SFT 29630#define AFE_ADDA_FIFO_AUTO_RST_MASK_SFT BIT(29)631#define AFE_ADDA_UL_FIFO_DIGMIC_TESTIN_SFT 21632#define AFE_ADDA_UL_FIFO_DIGMIC_TESTIN_MASK_SFT GENMASK(22, 21)633#define AFE_ADDA_UL_FIFO_DIGMIC_WDATA_TESTEN_SFT 20634#define AFE_ADDA_UL_FIFO_DIGMIC_WDATA_TESTEN_MASK_SFT BIT(20)635#define AFE_ADDA6_UL_LR_SWAP_SFT 15636#define AFE_ADDA6_UL_LR_SWAP_MASK_SFT BIT(15)637#define AFE_ADDA6_CKDIV_RST_SFT 14638#define AFE_ADDA6_CKDIV_RST_MASK_SFT BIT(14)639#define AFE_ADDA6_FIFO_AUTO_RST_SFT 13640#define AFE_ADDA6_FIFO_AUTO_RST_MASK_SFT BIT(13)641#define AFE_ADDA6_UL_FIFO_DIGMIC_TESTIN_SFT 5642#define AFE_ADDA6_UL_FIFO_DIGMIC_TESTIN_MASK_SFT GENMASK(6, 5)643#define AFE_ADDA6_UL_FIFO_DIGMIC_WDATA_TESTEN_SFT 4644#define AFE_ADDA6_UL_FIFO_DIGMIC_WDATA_TESTEN_MASK_SFT BIT(4)645#define ADDA_AFE_ON_SFT 0646#define ADDA_AFE_ON_MASK_SFT BIT(0)647 648/* AFE_SIDETONE_CON0 */649#define R_RDY_SFT 30650#define R_RDY_MASK_SFT BIT(30)651#define W_RDY_SFT 29652#define W_RDY_MASK_SFT BIT(29)653#define R_W_EN_SFT 25654#define R_W_EN_MASK_SFT BIT(25)655#define R_W_SEL_SFT 24656#define R_W_SEL_MASK_SFT BIT(24)657#define SEL_CH2_SFT 23658#define SEL_CH2_MASK_SFT BIT(23)659#define SIDE_TONE_COEFFICIENT_ADDR_SFT 16660#define SIDE_TONE_COEFFICIENT_ADDR_MASK_SFT GENMASK(20, 16)661#define SIDE_TONE_COEFFICIENT_SFT 0662#define SIDE_TONE_COEFFICIENT_MASK_SFT GENMASK(15, 0)663 664/* AFE_SIDETONE_COEFF */665#define SIDE_TONE_COEFF_SFT 0666#define SIDE_TONE_COEFF_MASK_SFT GENMASK(15, 0)667 668/* AFE_SIDETONE_CON1 */669#define STF_BYPASS_MODE_SFT 31670#define STF_BYPASS_MODE_MASK_SFT BIT(31)671#define STF_BYPASS_MODE_O28_O29_SFT 30672#define STF_BYPASS_MODE_O28_O29_MASK_SFT BIT(30)673#define STF_BYPASS_MODE_I2S4_SFT 29674#define STF_BYPASS_MODE_I2S4_MASK_SFT BIT(29)675#define STF_BYPASS_MODE_DL3_SFT 27676#define STF_BYPASS_MODE_DL3_MASK_SFT BIT(27)677#define STF_BYPASS_MODE_I2S7_SFT 26678#define STF_BYPASS_MODE_I2S7_MASK_SFT BIT(26)679#define STF_BYPASS_MODE_I2S9_SFT 25680#define STF_BYPASS_MODE_I2S9_MASK_SFT BIT(25)681#define STF_O19O20_OUT_EN_SEL_SFT 13682#define STF_O19O20_OUT_EN_SEL_MASK_SFT BIT(13)683#define STF_SOURCE_FROM_O19O20_SFT 12684#define STF_SOURCE_FROM_O19O20_MASK_SFT BIT(12)685#define SIDE_TONE_ON_SFT 8686#define SIDE_TONE_ON_MASK_SFT BIT(8)687#define SIDE_TONE_HALF_TAP_NUM_SFT 0688#define SIDE_TONE_HALF_TAP_NUM_MASK_SFT GENMASK(5, 0)689 690/* AFE_SIDETONE_GAIN */691#define POSITIVE_GAIN_SFT 16692#define POSITIVE_GAIN_MASK_SFT GENMASK(18, 16)693#define SIDE_TONE_GAIN_SFT 0694#define SIDE_TONE_GAIN_MASK_SFT GENMASK(15, 0)695 696/* AFE_ADDA_DL_SDM_DCCOMP_CON */697#define USE_3RD_SDM_SFT 28698#define USE_3RD_SDM_MASK_SFT BIT(28)699#define DL_FIFO_START_POINT_SFT 24700#define DL_FIFO_START_POINT_MASK_SFT GENMASK(26, 24)701#define DL_FIFO_SWAP_SFT 20702#define DL_FIFO_SWAP_MASK_SFT BIT(20)703#define C_AUDSDM1ORDSELECT_CTL_SFT 19704#define C_AUDSDM1ORDSELECT_CTL_MASK_SFT BIT(19)705#define C_SDM7BITSEL_CTL_SFT 18706#define C_SDM7BITSEL_CTL_MASK_SFT BIT(18)707#define GAIN_AT_SDM_RST_PRE_CTL_SFT 15708#define GAIN_AT_SDM_RST_PRE_CTL_MASK_SFT BIT(15)709#define DL_DCM_AUTO_IDLE_EN_SFT 14710#define DL_DCM_AUTO_IDLE_EN_MASK_SFT BIT(14)711#define AFE_DL_SRC_DCM_EN_SFT 13712#define AFE_DL_SRC_DCM_EN_MASK_SFT BIT(13)713#define AFE_DL_POST_SRC_DCM_EN_SFT 12714#define AFE_DL_POST_SRC_DCM_EN_MASK_SFT BIT(12)715#define AUD_SDM_MONO_SFT 9716#define AUD_SDM_MONO_MASK_SFT BIT(9)717#define AUD_DC_COMP_EN_SFT 8718#define AUD_DC_COMP_EN_MASK_SFT BIT(8)719#define ATTGAIN_CTL_SFT 0720#define ATTGAIN_CTL_MASK_SFT GENMASK(5, 0)721 722/* AFE_SINEGEN_CON0 */723#define DAC_EN_SFT 26724#define DAC_EN_MASK 0x1725#define DAC_EN_MASK_SFT BIT(26)726#define MUTE_SW_CH2_SFT 25727#define MUTE_SW_CH2_MASK 0x1728#define MUTE_SW_CH2_MASK_SFT BIT(25)729#define MUTE_SW_CH1_SFT 24730#define MUTE_SW_CH1_MASK 0x1731#define MUTE_SW_CH1_MASK_SFT BIT(24)732#define SINE_MODE_CH2_SFT 20733#define SINE_MODE_CH2_MASK 0xf734#define SINE_MODE_CH2_MASK_SFT GENMASK(23, 20)735#define AMP_DIV_CH2_SFT 17736#define AMP_DIV_CH2_MASK 0x7737#define AMP_DIV_CH2_MASK_SFT GENMASK(19, 17)738#define FREQ_DIV_CH2_SFT 12739#define FREQ_DIV_CH2_MASK 0x1f740#define FREQ_DIV_CH2_MASK_SFT GENMASK(16, 12)741#define SINE_MODE_CH1_SFT 8742#define SINE_MODE_CH1_MASK 0xf743#define SINE_MODE_CH1_MASK_SFT GENMASK(11, 8)744#define AMP_DIV_CH1_SFT 5745#define AMP_DIV_CH1_MASK 0x7746#define AMP_DIV_CH1_MASK_SFT GENMASK(7, 5)747#define FREQ_DIV_CH1_SFT 0748#define FREQ_DIV_CH1_MASK 0x1f749#define FREQ_DIV_CH1_MASK_SFT GENMASK(4, 0)750 751/* AFE_SINEGEN_CON2 */752#define INNER_LOOP_BACK_MODE_SFT 0753#define INNER_LOOP_BACK_MODE_MASK_SFT GENMASK(7, 0)754 755/* AFE_HD_ENGEN_ENABLE */756#define AFE_24M_ON_SFT 1757#define AFE_24M_ON_MASK_SFT BIT(1)758#define AFE_22M_ON_SFT 0759#define AFE_22M_ON_MASK_SFT BIT(0)760 761/* AFE_ADDA_DL_NLE_FIFO_MON */762#define DL_NLE_FIFO_WBIN_SFT 8763#define DL_NLE_FIFO_WBIN_MASK_SFT GENMASK(11, 8)764#define DL_NLE_FIFO_RBIN_SFT 4765#define DL_NLE_FIFO_RBIN_MASK_SFT GENMASK(7, 4)766#define DL_NLE_FIFO_RDACTIVE_SFT 3767#define DL_NLE_FIFO_RDACTIVE_MASK_SFT BIT(3)768#define DL_NLE_FIFO_STARTRD_SFT 2769#define DL_NLE_FIFO_STARTRD_MASK_SFT BIT(2)770#define DL_NLE_FIFO_RD_EMPTY_SFT 1771#define DL_NLE_FIFO_RD_EMPTY_MASK_SFT BIT(1)772#define DL_NLE_FIFO_WR_FULL_SFT 0773#define DL_NLE_FIFO_WR_FULL_MASK_SFT BIT(0)774 775/* AFE_DL1_CON0 */776#define DL1_MODE_SFT 24777#define DL1_MODE_MASK 0xf778#define DL1_MODE_MASK_SFT GENMASK(27, 24)779#define DL1_MINLEN_SFT 20780#define DL1_MINLEN_MASK 0xf781#define DL1_MINLEN_MASK_SFT GENMASK(23, 20)782#define DL1_MAXLEN_SFT 16783#define DL1_MAXLEN_MASK 0xf784#define DL1_MAXLEN_MASK_SFT GENMASK(19, 16)785#define DL1_SW_CLEAR_BUF_EMPTY_SFT 15786#define DL1_SW_CLEAR_BUF_EMPTY_MASK 0x1787#define DL1_SW_CLEAR_BUF_EMPTY_MASK_SFT BIT(15)788#define DL1_PBUF_SIZE_SFT 12789#define DL1_PBUF_SIZE_MASK 0x3790#define DL1_PBUF_SIZE_MASK_SFT GENMASK(13, 12)791#define DL1_MONO_SFT 8792#define DL1_MONO_MASK 0x1793#define DL1_MONO_MASK_SFT BIT(8)794#define DL1_NORMAL_MODE_SFT 5795#define DL1_NORMAL_MODE_MASK 0x1796#define DL1_NORMAL_MODE_MASK_SFT BIT(5)797#define DL1_HALIGN_SFT 4798#define DL1_HALIGN_MASK 0x1799#define DL1_HALIGN_MASK_SFT BIT(4)800#define DL1_HD_MODE_SFT 0801#define DL1_HD_MODE_MASK 0x3802#define DL1_HD_MODE_MASK_SFT GENMASK(1, 0)803 804/* AFE_DL2_CON0 */805#define DL2_MODE_SFT 24806#define DL2_MODE_MASK 0xf807#define DL2_MODE_MASK_SFT GENMASK(27, 24)808#define DL2_MINLEN_SFT 20809#define DL2_MINLEN_MASK 0xf810#define DL2_MINLEN_MASK_SFT GENMASK(23, 20)811#define DL2_MAXLEN_SFT 16812#define DL2_MAXLEN_MASK 0xf813#define DL2_MAXLEN_MASK_SFT GENMASK(19, 16)814#define DL2_SW_CLEAR_BUF_EMPTY_SFT 15815#define DL2_SW_CLEAR_BUF_EMPTY_MASK 0x1816#define DL2_SW_CLEAR_BUF_EMPTY_MASK_SFT BIT(15)817#define DL2_PBUF_SIZE_SFT 12818#define DL2_PBUF_SIZE_MASK 0x3819#define DL2_PBUF_SIZE_MASK_SFT GENMASK(13, 12)820#define DL2_MONO_SFT 8821#define DL2_MONO_MASK 0x1822#define DL2_MONO_MASK_SFT BIT(8)823#define DL2_NORMAL_MODE_SFT 5824#define DL2_NORMAL_MODE_MASK 0x1825#define DL2_NORMAL_MODE_MASK_SFT BIT(5)826#define DL2_HALIGN_SFT 4827#define DL2_HALIGN_MASK 0x1828#define DL2_HALIGN_MASK_SFT BIT(4)829#define DL2_HD_MODE_SFT 0830#define DL2_HD_MODE_MASK 0x3831#define DL2_HD_MODE_MASK_SFT GENMASK(1, 0)832 833/* AFE_DL3_CON0 */834#define DL3_MODE_SFT 24835#define DL3_MODE_MASK 0xf836#define DL3_MODE_MASK_SFT GENMASK(27, 24)837#define DL3_MINLEN_SFT 20838#define DL3_MINLEN_MASK 0xf839#define DL3_MINLEN_MASK_SFT GENMASK(23, 20)840#define DL3_MAXLEN_SFT 16841#define DL3_MAXLEN_MASK 0xf842#define DL3_MAXLEN_MASK_SFT GENMASK(19, 16)843#define DL3_SW_CLEAR_BUF_EMPTY_SFT 15844#define DL3_SW_CLEAR_BUF_EMPTY_MASK 0x1845#define DL3_SW_CLEAR_BUF_EMPTY_MASK_SFT BIT(15)846#define DL3_PBUF_SIZE_SFT 12847#define DL3_PBUF_SIZE_MASK 0x3848#define DL3_PBUF_SIZE_MASK_SFT GENMASK(13, 12)849#define DL3_MONO_SFT 8850#define DL3_MONO_MASK 0x1851#define DL3_MONO_MASK_SFT BIT(8)852#define DL3_NORMAL_MODE_SFT 5853#define DL3_NORMAL_MODE_MASK 0x1854#define DL3_NORMAL_MODE_MASK_SFT BIT(5)855#define DL3_HALIGN_SFT 4856#define DL3_HALIGN_MASK 0x1857#define DL3_HALIGN_MASK_SFT BIT(4)858#define DL3_HD_MODE_SFT 0859#define DL3_HD_MODE_MASK 0x3860#define DL3_HD_MODE_MASK_SFT GENMASK(1, 0)861 862/* AFE_DL4_CON0 */863#define DL4_MODE_SFT 24864#define DL4_MODE_MASK 0xf865#define DL4_MODE_MASK_SFT GENMASK(27, 24)866#define DL4_MINLEN_SFT 20867#define DL4_MINLEN_MASK 0xf868#define DL4_MINLEN_MASK_SFT GENMASK(23, 20)869#define DL4_MAXLEN_SFT 16870#define DL4_MAXLEN_MASK 0xf871#define DL4_MAXLEN_MASK_SFT GENMASK(19, 16)872#define DL4_SW_CLEAR_BUF_EMPTY_SFT 15873#define DL4_SW_CLEAR_BUF_EMPTY_MASK 0x1874#define DL4_SW_CLEAR_BUF_EMPTY_MASK_SFT BIT(15)875#define DL4_PBUF_SIZE_SFT 12876#define DL4_PBUF_SIZE_MASK 0x3877#define DL4_PBUF_SIZE_MASK_SFT GENMASK(13, 12)878#define DL4_MONO_SFT 8879#define DL4_MONO_MASK 0x1880#define DL4_MONO_MASK_SFT BIT(8)881#define DL4_NORMAL_MODE_SFT 5882#define DL4_NORMAL_MODE_MASK 0x1883#define DL4_NORMAL_MODE_MASK_SFT BIT(5)884#define DL4_HALIGN_SFT 4885#define DL4_HALIGN_MASK 0x1886#define DL4_HALIGN_MASK_SFT BIT(4)887#define DL4_HD_MODE_SFT 0888#define DL4_HD_MODE_MASK 0x3889#define DL4_HD_MODE_MASK_SFT GENMASK(1, 0)890 891/* AFE_DL5_CON0 */892#define DL5_MODE_SFT 24893#define DL5_MODE_MASK 0xf894#define DL5_MODE_MASK_SFT GENMASK(27, 24)895#define DL5_MINLEN_SFT 20896#define DL5_MINLEN_MASK 0xf897#define DL5_MINLEN_MASK_SFT GENMASK(23, 20)898#define DL5_MAXLEN_SFT 16899#define DL5_MAXLEN_MASK 0xf900#define DL5_MAXLEN_MASK_SFT GENMASK(19, 16)901#define DL5_SW_CLEAR_BUF_EMPTY_SFT 15902#define DL5_SW_CLEAR_BUF_EMPTY_MASK 0x1903#define DL5_SW_CLEAR_BUF_EMPTY_MASK_SFT BIT(15)904#define DL5_PBUF_SIZE_SFT 12905#define DL5_PBUF_SIZE_MASK 0x3906#define DL5_PBUF_SIZE_MASK_SFT GENMASK(13, 12)907#define DL5_MONO_SFT 8908#define DL5_MONO_MASK 0x1909#define DL5_MONO_MASK_SFT BIT(8)910#define DL5_NORMAL_MODE_SFT 5911#define DL5_NORMAL_MODE_MASK 0x1912#define DL5_NORMAL_MODE_MASK_SFT BIT(5)913#define DL5_HALIGN_SFT 4914#define DL5_HALIGN_MASK 0x1915#define DL5_HALIGN_MASK_SFT BIT(4)916#define DL5_HD_MODE_SFT 0917#define DL5_HD_MODE_MASK 0x3918#define DL5_HD_MODE_MASK_SFT GENMASK(1, 0)919 920/* AFE_DL6_CON0 */921#define DL6_MODE_SFT 24922#define DL6_MODE_MASK 0xf923#define DL6_MODE_MASK_SFT GENMASK(27, 24)924#define DL6_MINLEN_SFT 20925#define DL6_MINLEN_MASK 0xf926#define DL6_MINLEN_MASK_SFT GENMASK(23, 20)927#define DL6_MAXLEN_SFT 16928#define DL6_MAXLEN_MASK 0xf929#define DL6_MAXLEN_MASK_SFT GENMASK(19, 16)930#define DL6_SW_CLEAR_BUF_EMPTY_SFT 15931#define DL6_SW_CLEAR_BUF_EMPTY_MASK 0x1932#define DL6_SW_CLEAR_BUF_EMPTY_MASK_SFT BIT(15)933#define DL6_PBUF_SIZE_SFT 12934#define DL6_PBUF_SIZE_MASK 0x3935#define DL6_PBUF_SIZE_MASK_SFT GENMASK(13, 12)936#define DL6_MONO_SFT 8937#define DL6_MONO_MASK 0x1938#define DL6_MONO_MASK_SFT BIT(8)939#define DL6_NORMAL_MODE_SFT 5940#define DL6_NORMAL_MODE_MASK 0x1941#define DL6_NORMAL_MODE_MASK_SFT BIT(5)942#define DL6_HALIGN_SFT 4943#define DL6_HALIGN_MASK 0x1944#define DL6_HALIGN_MASK_SFT BIT(4)945#define DL6_HD_MODE_SFT 0946#define DL6_HD_MODE_MASK 0x3947#define DL6_HD_MODE_MASK_SFT GENMASK(1, 0)948 949/* AFE_DL7_CON0 */950#define DL7_MODE_SFT 24951#define DL7_MODE_MASK 0xf952#define DL7_MODE_MASK_SFT GENMASK(27, 24)953#define DL7_MINLEN_SFT 20954#define DL7_MINLEN_MASK 0xf955#define DL7_MINLEN_MASK_SFT GENMASK(23, 20)956#define DL7_MAXLEN_SFT 16957#define DL7_MAXLEN_MASK 0xf958#define DL7_MAXLEN_MASK_SFT GENMASK(19, 16)959#define DL7_SW_CLEAR_BUF_EMPTY_SFT 15960#define DL7_SW_CLEAR_BUF_EMPTY_MASK 0x1961#define DL7_SW_CLEAR_BUF_EMPTY_MASK_SFT BIT(15)962#define DL7_PBUF_SIZE_SFT 12963#define DL7_PBUF_SIZE_MASK 0x3964#define DL7_PBUF_SIZE_MASK_SFT GENMASK(13, 12)965#define DL7_MONO_SFT 8966#define DL7_MONO_MASK 0x1967#define DL7_MONO_MASK_SFT BIT(8)968#define DL7_NORMAL_MODE_SFT 5969#define DL7_NORMAL_MODE_MASK 0x1970#define DL7_NORMAL_MODE_MASK_SFT BIT(5)971#define DL7_HALIGN_SFT 4972#define DL7_HALIGN_MASK 0x1973#define DL7_HALIGN_MASK_SFT BIT(4)974#define DL7_HD_MODE_SFT 0975#define DL7_HD_MODE_MASK 0x3976#define DL7_HD_MODE_MASK_SFT GENMASK(1, 0)977 978/* AFE_DL8_CON0 */979#define DL8_MODE_SFT 24980#define DL8_MODE_MASK 0xf981#define DL8_MODE_MASK_SFT GENMASK(27, 24)982#define DL8_MINLEN_SFT 20983#define DL8_MINLEN_MASK 0xf984#define DL8_MINLEN_MASK_SFT GENMASK(23, 20)985#define DL8_MAXLEN_SFT 16986#define DL8_MAXLEN_MASK 0xf987#define DL8_MAXLEN_MASK_SFT GENMASK(19, 16)988#define DL8_SW_CLEAR_BUF_EMPTY_SFT 15989#define DL8_SW_CLEAR_BUF_EMPTY_MASK 0x1990#define DL8_SW_CLEAR_BUF_EMPTY_MASK_SFT BIT(15)991#define DL8_PBUF_SIZE_SFT 12992#define DL8_PBUF_SIZE_MASK 0x3993#define DL8_PBUF_SIZE_MASK_SFT GENMASK(13, 12)994#define DL8_MONO_SFT 8995#define DL8_MONO_MASK 0x1996#define DL8_MONO_MASK_SFT BIT(8)997#define DL8_NORMAL_MODE_SFT 5998#define DL8_NORMAL_MODE_MASK 0x1999#define DL8_NORMAL_MODE_MASK_SFT BIT(5)1000#define DL8_HALIGN_SFT 41001#define DL8_HALIGN_MASK 0x11002#define DL8_HALIGN_MASK_SFT BIT(4)1003#define DL8_HD_MODE_SFT 01004#define DL8_HD_MODE_MASK 0x31005#define DL8_HD_MODE_MASK_SFT GENMASK(1, 0)1006 1007/* AFE_DL12_CON0 */1008#define DL12_MODE_SFT 241009#define DL12_MODE_MASK 0xf1010#define DL12_MODE_MASK_SFT GENMASK(27, 24)1011#define DL12_MINLEN_SFT 201012#define DL12_MINLEN_MASK 0xf1013#define DL12_MINLEN_MASK_SFT GENMASK(23, 20)1014#define DL12_MAXLEN_SFT 161015#define DL12_MAXLEN_MASK 0xf1016#define DL12_MAXLEN_MASK_SFT GENMASK(19, 16)1017#define DL12_SW_CLEAR_BUF_EMPTY_SFT 151018#define DL12_SW_CLEAR_BUF_EMPTY_MASK 0x11019#define DL12_SW_CLEAR_BUF_EMPTY_MASK_SFT BIT(15)1020#define DL12_PBUF_SIZE_SFT 121021#define DL12_PBUF_SIZE_MASK 0x31022#define DL12_PBUF_SIZE_MASK_SFT GENMASK(13, 12)1023#define DL12_4CH_EN_SFT 111024#define DL12_4CH_EN_MASK 0x11025#define DL12_4CH_EN_MASK_SFT BIT(11)1026#define DL12_MONO_SFT 81027#define DL12_MONO_MASK 0x11028#define DL12_MONO_MASK_SFT BIT(8)1029#define DL12_NORMAL_MODE_SFT 51030#define DL12_NORMAL_MODE_MASK 0x11031#define DL12_NORMAL_MODE_MASK_SFT BIT(5)1032#define DL12_HALIGN_SFT 41033#define DL12_HALIGN_MASK 0x11034#define DL12_HALIGN_MASK_SFT BIT(4)1035#define DL12_HD_MODE_SFT 01036#define DL12_HD_MODE_MASK 0x31037#define DL12_HD_MODE_MASK_SFT GENMASK(1, 0)1038 1039/* AFE_AWB_CON0 */1040#define AWB_MODE_SFT 241041#define AWB_MODE_MASK 0xf1042#define AWB_MODE_MASK_SFT GENMASK(27, 24)1043#define AWB_SW_CLEAR_BUF_FULL_SFT 151044#define AWB_SW_CLEAR_BUF_FULL_MASK 0x11045#define AWB_SW_CLEAR_BUF_FULL_MASK_SFT BIT(15)1046#define AWB_R_MONO_SFT 91047#define AWB_R_MONO_MASK 0x11048#define AWB_R_MONO_MASK_SFT BIT(9)1049#define AWB_MONO_SFT 81050#define AWB_MONO_MASK 0x11051#define AWB_MONO_MASK_SFT BIT(8)1052#define AWB_WR_SIGN_SFT 61053#define AWB_WR_SIGN_MASK 0x11054#define AWB_WR_SIGN_MASK_SFT BIT(6)1055#define AWB_NORMAL_MODE_SFT 51056#define AWB_NORMAL_MODE_MASK 0x11057#define AWB_NORMAL_MODE_MASK_SFT BIT(5)1058#define AWB_HALIGN_SFT 41059#define AWB_HALIGN_MASK 0x11060#define AWB_HALIGN_MASK_SFT BIT(4)1061#define AWB_HD_MODE_SFT 01062#define AWB_HD_MODE_MASK 0x31063#define AWB_HD_MODE_MASK_SFT GENMASK(1, 0)1064 1065/* AFE_AWB2_CON0 */1066#define AWB2_MODE_SFT 241067#define AWB2_MODE_MASK 0xf1068#define AWB2_MODE_MASK_SFT GENMASK(27, 24)1069#define AWB2_SW_CLEAR_BUF_FULL_SFT 151070#define AWB2_SW_CLEAR_BUF_FULL_MASK 0x11071#define AWB2_SW_CLEAR_BUF_FULL_MASK_SFT BIT(15)1072#define AWB2_R_MONO_SFT 91073#define AWB2_R_MONO_MASK 0x11074#define AWB2_R_MONO_MASK_SFT BIT(9)1075#define AWB2_MONO_SFT 81076#define AWB2_MONO_MASK 0x11077#define AWB2_MONO_MASK_SFT BIT(8)1078#define AWB2_WR_SIGN_SFT 61079#define AWB2_WR_SIGN_MASK 0x11080#define AWB2_WR_SIGN_MASK_SFT BIT(6)1081#define AWB2_NORMAL_MODE_SFT 51082#define AWB2_NORMAL_MODE_MASK 0x11083#define AWB2_NORMAL_MODE_MASK_SFT BIT(5)1084#define AWB2_HALIGN_SFT 41085#define AWB2_HALIGN_MASK 0x11086#define AWB2_HALIGN_MASK_SFT BIT(4)1087#define AWB2_HD_MODE_SFT 01088#define AWB2_HD_MODE_MASK 0x31089#define AWB2_HD_MODE_MASK_SFT GENMASK(1, 0)1090 1091/* AFE_VUL_CON0 */1092#define VUL_MODE_SFT 241093#define VUL_MODE_MASK 0xf1094#define VUL_MODE_MASK_SFT GENMASK(27, 24)1095#define VUL_SW_CLEAR_BUF_FULL_SFT 151096#define VUL_SW_CLEAR_BUF_FULL_MASK 0x11097#define VUL_SW_CLEAR_BUF_FULL_MASK_SFT BIT(15)1098#define VUL_R_MONO_SFT 91099#define VUL_R_MONO_MASK 0x11100#define VUL_R_MONO_MASK_SFT BIT(9)1101#define VUL_MONO_SFT 81102#define VUL_MONO_MASK 0x11103#define VUL_MONO_MASK_SFT BIT(8)1104#define VUL_WR_SIGN_SFT 61105#define VUL_WR_SIGN_MASK 0x11106#define VUL_WR_SIGN_MASK_SFT BIT(6)1107#define VUL_NORMAL_MODE_SFT 51108#define VUL_NORMAL_MODE_MASK 0x11109#define VUL_NORMAL_MODE_MASK_SFT BIT(5)1110#define VUL_HALIGN_SFT 41111#define VUL_HALIGN_MASK 0x11112#define VUL_HALIGN_MASK_SFT BIT(4)1113#define VUL_HD_MODE_SFT 01114#define VUL_HD_MODE_MASK 0x31115#define VUL_HD_MODE_MASK_SFT GENMASK(1, 0)1116 1117/* AFE_VUL12_CON0 */1118#define VUL12_MODE_SFT 241119#define VUL12_MODE_MASK 0xf1120#define VUL12_MODE_MASK_SFT GENMASK(27, 24)1121#define VUL12_SW_CLEAR_BUF_FULL_SFT 151122#define VUL12_SW_CLEAR_BUF_FULL_MASK 0x11123#define VUL12_SW_CLEAR_BUF_FULL_MASK_SFT BIT(15)1124#define VUL12_4CH_EN_SFT 111125#define VUL12_4CH_EN_MASK 0x11126#define VUL12_4CH_EN_MASK_SFT BIT(11)1127#define VUL12_R_MONO_SFT 91128#define VUL12_R_MONO_MASK 0x11129#define VUL12_R_MONO_MASK_SFT BIT(9)1130#define VUL12_MONO_SFT 81131#define VUL12_MONO_MASK 0x11132#define VUL12_MONO_MASK_SFT BIT(8)1133#define VUL12_WR_SIGN_SFT 61134#define VUL12_WR_SIGN_MASK 0x11135#define VUL12_WR_SIGN_MASK_SFT BIT(6)1136#define VUL12_NORMAL_MODE_SFT 51137#define VUL12_NORMAL_MODE_MASK 0x11138#define VUL12_NORMAL_MODE_MASK_SFT BIT(5)1139#define VUL12_HALIGN_SFT 41140#define VUL12_HALIGN_MASK 0x11141#define VUL12_HALIGN_MASK_SFT BIT(4)1142#define VUL12_HD_MODE_SFT 01143#define VUL12_HD_MODE_MASK 0x31144#define VUL12_HD_MODE_MASK_SFT GENMASK(1, 0)1145 1146/* AFE_VUL2_CON0 */1147#define VUL2_MODE_SFT 241148#define VUL2_MODE_MASK 0xf1149#define VUL2_MODE_MASK_SFT GENMASK(27, 24)1150#define VUL2_SW_CLEAR_BUF_FULL_SFT 151151#define VUL2_SW_CLEAR_BUF_FULL_MASK 0x11152#define VUL2_SW_CLEAR_BUF_FULL_MASK_SFT BIT(15)1153#define VUL2_R_MONO_SFT 91154#define VUL2_R_MONO_MASK 0x11155#define VUL2_R_MONO_MASK_SFT BIT(9)1156#define VUL2_MONO_SFT 81157#define VUL2_MONO_MASK 0x11158#define VUL2_MONO_MASK_SFT BIT(8)1159#define VUL2_WR_SIGN_SFT 61160#define VUL2_WR_SIGN_MASK 0x11161#define VUL2_WR_SIGN_MASK_SFT BIT(6)1162#define VUL2_NORMAL_MODE_SFT 51163#define VUL2_NORMAL_MODE_MASK 0x11164#define VUL2_NORMAL_MODE_MASK_SFT BIT(5)1165#define VUL2_HALIGN_SFT 41166#define VUL2_HALIGN_MASK 0x11167#define VUL2_HALIGN_MASK_SFT BIT(4)1168#define VUL2_HD_MODE_SFT 01169#define VUL2_HD_MODE_MASK 0x31170#define VUL2_HD_MODE_MASK_SFT GENMASK(1, 0)1171 1172/* AFE_VUL3_CON0 */1173#define VUL3_MODE_SFT 241174#define VUL3_MODE_MASK 0xf1175#define VUL3_MODE_MASK_SFT GENMASK(27, 24)1176#define VUL3_SW_CLEAR_BUF_FULL_SFT 151177#define VUL3_SW_CLEAR_BUF_FULL_MASK 0x11178#define VUL3_SW_CLEAR_BUF_FULL_MASK_SFT BIT(15)1179#define VUL3_R_MONO_SFT 91180#define VUL3_R_MONO_MASK 0x11181#define VUL3_R_MONO_MASK_SFT BIT(9)1182#define VUL3_MONO_SFT 81183#define VUL3_MONO_MASK 0x11184#define VUL3_MONO_MASK_SFT BIT(8)1185#define VUL3_WR_SIGN_SFT 61186#define VUL3_WR_SIGN_MASK 0x11187#define VUL3_WR_SIGN_MASK_SFT BIT(6)1188#define VUL3_NORMAL_MODE_SFT 51189#define VUL3_NORMAL_MODE_MASK 0x11190#define VUL3_NORMAL_MODE_MASK_SFT BIT(5)1191#define VUL3_HALIGN_SFT 41192#define VUL3_HALIGN_MASK 0x11193#define VUL3_HALIGN_MASK_SFT BIT(4)1194#define VUL3_HD_MODE_SFT 01195#define VUL3_HD_MODE_MASK 0x31196#define VUL3_HD_MODE_MASK_SFT GENMASK(1, 0)1197 1198/* AFE_VUL4_CON0 */1199#define VUL4_MODE_SFT 241200#define VUL4_MODE_MASK 0xf1201#define VUL4_MODE_MASK_SFT GENMASK(27, 24)1202#define VUL4_SW_CLEAR_BUF_FULL_SFT 151203#define VUL4_SW_CLEAR_BUF_FULL_MASK 0x11204#define VUL4_SW_CLEAR_BUF_FULL_MASK_SFT BIT(15)1205#define VUL4_R_MONO_SFT 91206#define VUL4_R_MONO_MASK 0x11207#define VUL4_R_MONO_MASK_SFT BIT(9)1208#define VUL4_MONO_SFT 81209#define VUL4_MONO_MASK 0x11210#define VUL4_MONO_MASK_SFT BIT(8)1211#define VUL4_WR_SIGN_SFT 61212#define VUL4_WR_SIGN_MASK 0x11213#define VUL4_WR_SIGN_MASK_SFT BIT(6)1214#define VUL4_NORMAL_MODE_SFT 51215#define VUL4_NORMAL_MODE_MASK 0x11216#define VUL4_NORMAL_MODE_MASK_SFT BIT(5)1217#define VUL4_HALIGN_SFT 41218#define VUL4_HALIGN_MASK 0x11219#define VUL4_HALIGN_MASK_SFT BIT(4)1220#define VUL4_HD_MODE_SFT 01221#define VUL4_HD_MODE_MASK 0x31222#define VUL4_HD_MODE_MASK_SFT GENMASK(1, 0)1223 1224/* AFE_VUL5_CON0 */1225#define VUL5_MODE_SFT 241226#define VUL5_MODE_MASK 0xf1227#define VUL5_MODE_MASK_SFT GENMASK(27, 24)1228#define VUL5_SW_CLEAR_BUF_FULL_SFT 151229#define VUL5_SW_CLEAR_BUF_FULL_MASK 0x11230#define VUL5_SW_CLEAR_BUF_FULL_MASK_SFT BIT(15)1231#define VUL5_R_MONO_SFT 91232#define VUL5_R_MONO_MASK 0x11233#define VUL5_R_MONO_MASK_SFT BIT(9)1234#define VUL5_MONO_SFT 81235#define VUL5_MONO_MASK 0x11236#define VUL5_MONO_MASK_SFT BIT(8)1237#define VUL5_WR_SIGN_SFT 61238#define VUL5_WR_SIGN_MASK 0x11239#define VUL5_WR_SIGN_MASK_SFT BIT(6)1240#define VUL5_NORMAL_MODE_SFT 51241#define VUL5_NORMAL_MODE_MASK 0x11242#define VUL5_NORMAL_MODE_MASK_SFT BIT(5)1243#define VUL5_HALIGN_SFT 41244#define VUL5_HALIGN_MASK 0x11245#define VUL5_HALIGN_MASK_SFT BIT(4)1246#define VUL5_HD_MODE_SFT 01247#define VUL5_HD_MODE_MASK 0x31248#define VUL5_HD_MODE_MASK_SFT GENMASK(1, 0)1249 1250/* AFE_VUL6_CON0 */1251#define VUL6_MODE_SFT 241252#define VUL6_MODE_MASK 0xf1253#define VUL6_MODE_MASK_SFT GENMASK(27, 24)1254#define VUL6_SW_CLEAR_BUF_FULL_SFT 151255#define VUL6_SW_CLEAR_BUF_FULL_MASK 0x11256#define VUL6_SW_CLEAR_BUF_FULL_MASK_SFT BIT(15)1257#define VUL6_R_MONO_SFT 91258#define VUL6_R_MONO_MASK 0x11259#define VUL6_R_MONO_MASK_SFT BIT(9)1260#define VUL6_MONO_SFT 81261#define VUL6_MONO_MASK 0x11262#define VUL6_MONO_MASK_SFT BIT(8)1263#define VUL6_WR_SIGN_SFT 61264#define VUL6_WR_SIGN_MASK 0x11265#define VUL6_WR_SIGN_MASK_SFT BIT(6)1266#define VUL6_NORMAL_MODE_SFT 51267#define VUL6_NORMAL_MODE_MASK 0x11268#define VUL6_NORMAL_MODE_MASK_SFT BIT(5)1269#define VUL6_HALIGN_SFT 41270#define VUL6_HALIGN_MASK 0x11271#define VUL6_HALIGN_MASK_SFT BIT(4)1272#define VUL6_HD_MODE_SFT 01273#define VUL6_HD_MODE_MASK 0x31274#define VUL6_HD_MODE_MASK_SFT GENMASK(1, 0)1275 1276/* AFE_DAI_CON0 */1277#define DAI_MODE_SFT 241278#define DAI_MODE_MASK 0x31279#define DAI_MODE_MASK_SFT GENMASK(25, 24)1280#define DAI_SW_CLEAR_BUF_FULL_SFT 151281#define DAI_SW_CLEAR_BUF_FULL_MASK 0x11282#define DAI_SW_CLEAR_BUF_FULL_MASK_SFT BIT(15)1283#define DAI_DUPLICATE_WR_SFT 101284#define DAI_DUPLICATE_WR_MASK 0x11285#define DAI_DUPLICATE_WR_MASK_SFT BIT(10)1286#define DAI_MONO_SFT 81287#define DAI_MONO_MASK 0x11288#define DAI_MONO_MASK_SFT BIT(8)1289#define DAI_WR_SIGN_SFT 61290#define DAI_WR_SIGN_MASK 0x11291#define DAI_WR_SIGN_MASK_SFT BIT(6)1292#define DAI_NORMAL_MODE_SFT 51293#define DAI_NORMAL_MODE_MASK 0x11294#define DAI_NORMAL_MODE_MASK_SFT BIT(5)1295#define DAI_HALIGN_SFT 41296#define DAI_HALIGN_MASK 0x11297#define DAI_HALIGN_MASK_SFT BIT(4)1298#define DAI_HD_MODE_SFT 01299#define DAI_HD_MODE_MASK 0x31300#define DAI_HD_MODE_MASK_SFT GENMASK(1, 0)1301 1302/* AFE_MOD_DAI_CON0 */1303#define MOD_DAI_MODE_SFT 241304#define MOD_DAI_MODE_MASK 0x31305#define MOD_DAI_MODE_MASK_SFT GENMASK(25, 24)1306#define MOD_DAI_SW_CLEAR_BUF_FULL_SFT 151307#define MOD_DAI_SW_CLEAR_BUF_FULL_MASK 0x11308#define MOD_DAI_SW_CLEAR_BUF_FULL_MASK_SFT BIT(15)1309#define MOD_DAI_DUPLICATE_WR_SFT 101310#define MOD_DAI_DUPLICATE_WR_MASK 0x11311#define MOD_DAI_DUPLICATE_WR_MASK_SFT BIT(10)1312#define MOD_DAI_MONO_SFT 81313#define MOD_DAI_MONO_MASK 0x11314#define MOD_DAI_MONO_MASK_SFT BIT(8)1315#define MOD_DAI_WR_SIGN_SFT 61316#define MOD_DAI_WR_SIGN_MASK 0x11317#define MOD_DAI_WR_SIGN_MASK_SFT BIT(6)1318#define MOD_DAI_NORMAL_MODE_SFT 51319#define MOD_DAI_NORMAL_MODE_MASK 0x11320#define MOD_DAI_NORMAL_MODE_MASK_SFT BIT(5)1321#define MOD_DAI_HALIGN_SFT 41322#define MOD_DAI_HALIGN_MASK 0x11323#define MOD_DAI_HALIGN_MASK_SFT BIT(4)1324#define MOD_DAI_HD_MODE_SFT 01325#define MOD_DAI_HD_MODE_MASK 0x31326#define MOD_DAI_HD_MODE_MASK_SFT GENMASK(1, 0)1327 1328/* AFE_DAI2_CON0 */1329#define DAI2_MODE_SFT 241330#define DAI2_MODE_MASK 0xf1331#define DAI2_MODE_MASK_SFT GENMASK(27, 24)1332#define DAI2_SW_CLEAR_BUF_FULL_SFT 151333#define DAI2_SW_CLEAR_BUF_FULL_MASK 0x11334#define DAI2_SW_CLEAR_BUF_FULL_MASK_SFT BIT(15)1335#define DAI2_DUPLICATE_WR_SFT 101336#define DAI2_DUPLICATE_WR_MASK 0x11337#define DAI2_DUPLICATE_WR_MASK_SFT BIT(10)1338#define DAI2_MONO_SFT 81339#define DAI2_MONO_MASK 0x11340#define DAI2_MONO_MASK_SFT BIT(8)1341#define DAI2_WR_SIGN_SFT 61342#define DAI2_WR_SIGN_MASK 0x11343#define DAI2_WR_SIGN_MASK_SFT BIT(6)1344#define DAI2_NORMAL_MODE_SFT 51345#define DAI2_NORMAL_MODE_MASK 0x11346#define DAI2_NORMAL_MODE_MASK_SFT BIT(5)1347#define DAI2_HALIGN_SFT 41348#define DAI2_HALIGN_MASK 0x11349#define DAI2_HALIGN_MASK_SFT BIT(4)1350#define DAI2_HD_MODE_SFT 01351#define DAI2_HD_MODE_MASK 0x31352#define DAI2_HD_MODE_MASK_SFT GENMASK(1, 0)1353 1354/* AFE_MEMIF_CON0 */1355#define CPU_COMPACT_MODE_SFT 21356#define CPU_COMPACT_MODE_MASK_SFT BIT(2)1357#define CPU_HD_ALIGN_SFT 11358#define CPU_HD_ALIGN_MASK_SFT BIT(1)1359#define SYSRAM_SIGN_SFT 01360#define SYSRAM_SIGN_MASK_SFT BIT(0)1361 1362/* AFE_IRQ_MCU_CON0 */1363#define IRQ31_MCU_ON_SFT 311364#define IRQ31_MCU_ON_MASK 0x11365#define IRQ31_MCU_ON_MASK_SFT BIT(31)1366#define IRQ26_MCU_ON_SFT 261367#define IRQ26_MCU_ON_MASK 0x11368#define IRQ26_MCU_ON_MASK_SFT BIT(26)1369#define IRQ25_MCU_ON_SFT 251370#define IRQ25_MCU_ON_MASK 0x11371#define IRQ25_MCU_ON_MASK_SFT BIT(25)1372#define IRQ24_MCU_ON_SFT 241373#define IRQ24_MCU_ON_MASK 0x11374#define IRQ24_MCU_ON_MASK_SFT BIT(24)1375#define IRQ23_MCU_ON_SFT 231376#define IRQ23_MCU_ON_MASK 0x11377#define IRQ23_MCU_ON_MASK_SFT BIT(23)1378#define IRQ22_MCU_ON_SFT 221379#define IRQ22_MCU_ON_MASK 0x11380#define IRQ22_MCU_ON_MASK_SFT BIT(22)1381#define IRQ21_MCU_ON_SFT 211382#define IRQ21_MCU_ON_MASK 0x11383#define IRQ21_MCU_ON_MASK_SFT BIT(21)1384#define IRQ20_MCU_ON_SFT 201385#define IRQ20_MCU_ON_MASK 0x11386#define IRQ20_MCU_ON_MASK_SFT BIT(20)1387#define IRQ19_MCU_ON_SFT 191388#define IRQ19_MCU_ON_MASK 0x11389#define IRQ19_MCU_ON_MASK_SFT BIT(19)1390#define IRQ18_MCU_ON_SFT 181391#define IRQ18_MCU_ON_MASK 0x11392#define IRQ18_MCU_ON_MASK_SFT BIT(18)1393#define IRQ17_MCU_ON_SFT 171394#define IRQ17_MCU_ON_MASK 0x11395#define IRQ17_MCU_ON_MASK_SFT BIT(17)1396#define IRQ16_MCU_ON_SFT 161397#define IRQ16_MCU_ON_MASK 0x11398#define IRQ16_MCU_ON_MASK_SFT BIT(16)1399#define IRQ15_MCU_ON_SFT 151400#define IRQ15_MCU_ON_MASK 0x11401#define IRQ15_MCU_ON_MASK_SFT BIT(15)1402#define IRQ14_MCU_ON_SFT 141403#define IRQ14_MCU_ON_MASK 0x11404#define IRQ14_MCU_ON_MASK_SFT BIT(14)1405#define IRQ13_MCU_ON_SFT 131406#define IRQ13_MCU_ON_MASK 0x11407#define IRQ13_MCU_ON_MASK_SFT BIT(13)1408#define IRQ12_MCU_ON_SFT 121409#define IRQ12_MCU_ON_MASK 0x11410#define IRQ12_MCU_ON_MASK_SFT BIT(12)1411#define IRQ11_MCU_ON_SFT 111412#define IRQ11_MCU_ON_MASK 0x11413#define IRQ11_MCU_ON_MASK_SFT BIT(11)1414#define IRQ10_MCU_ON_SFT 101415#define IRQ10_MCU_ON_MASK 0x11416#define IRQ10_MCU_ON_MASK_SFT BIT(10)1417#define IRQ9_MCU_ON_SFT 91418#define IRQ9_MCU_ON_MASK 0x11419#define IRQ9_MCU_ON_MASK_SFT BIT(9)1420#define IRQ8_MCU_ON_SFT 81421#define IRQ8_MCU_ON_MASK 0x11422#define IRQ8_MCU_ON_MASK_SFT BIT(8)1423#define IRQ7_MCU_ON_SFT 71424#define IRQ7_MCU_ON_MASK 0x11425#define IRQ7_MCU_ON_MASK_SFT BIT(7)1426#define IRQ6_MCU_ON_SFT 61427#define IRQ6_MCU_ON_MASK 0x11428#define IRQ6_MCU_ON_MASK_SFT BIT(6)1429#define IRQ5_MCU_ON_SFT 51430#define IRQ5_MCU_ON_MASK 0x11431#define IRQ5_MCU_ON_MASK_SFT BIT(5)1432#define IRQ4_MCU_ON_SFT 41433#define IRQ4_MCU_ON_MASK 0x11434#define IRQ4_MCU_ON_MASK_SFT BIT(4)1435#define IRQ3_MCU_ON_SFT 31436#define IRQ3_MCU_ON_MASK 0x11437#define IRQ3_MCU_ON_MASK_SFT BIT(3)1438#define IRQ2_MCU_ON_SFT 21439#define IRQ2_MCU_ON_MASK 0x11440#define IRQ2_MCU_ON_MASK_SFT BIT(2)1441#define IRQ1_MCU_ON_SFT 11442#define IRQ1_MCU_ON_MASK 0x11443#define IRQ1_MCU_ON_MASK_SFT BIT(1)1444#define IRQ0_MCU_ON_SFT 01445#define IRQ0_MCU_ON_MASK 0x11446#define IRQ0_MCU_ON_MASK_SFT BIT(0)1447 1448/* AFE_IRQ_MCU_CON1 */1449#define IRQ7_MCU_MODE_SFT 281450#define IRQ7_MCU_MODE_MASK 0xf1451#define IRQ7_MCU_MODE_MASK_SFT GENMASK(31, 28)1452#define IRQ6_MCU_MODE_SFT 241453#define IRQ6_MCU_MODE_MASK 0xf1454#define IRQ6_MCU_MODE_MASK_SFT GENMASK(27, 24)1455#define IRQ5_MCU_MODE_SFT 201456#define IRQ5_MCU_MODE_MASK 0xf1457#define IRQ5_MCU_MODE_MASK_SFT GENMASK(23, 20)1458#define IRQ4_MCU_MODE_SFT 161459#define IRQ4_MCU_MODE_MASK 0xf1460#define IRQ4_MCU_MODE_MASK_SFT GENMASK(19, 16)1461#define IRQ3_MCU_MODE_SFT 121462#define IRQ3_MCU_MODE_MASK 0xf1463#define IRQ3_MCU_MODE_MASK_SFT GENMASK(15, 12)1464#define IRQ2_MCU_MODE_SFT 81465#define IRQ2_MCU_MODE_MASK 0xf1466#define IRQ2_MCU_MODE_MASK_SFT GENMASK(11, 8)1467#define IRQ1_MCU_MODE_SFT 41468#define IRQ1_MCU_MODE_MASK 0xf1469#define IRQ1_MCU_MODE_MASK_SFT GENMASK(7, 4)1470#define IRQ0_MCU_MODE_SFT 01471#define IRQ0_MCU_MODE_MASK 0xf1472#define IRQ0_MCU_MODE_MASK_SFT GENMASK(3, 0)1473 1474/* AFE_IRQ_MCU_CON2 */1475#define IRQ15_MCU_MODE_SFT 281476#define IRQ15_MCU_MODE_MASK 0xf1477#define IRQ15_MCU_MODE_MASK_SFT GENMASK(31, 28)1478#define IRQ14_MCU_MODE_SFT 241479#define IRQ14_MCU_MODE_MASK 0xf1480#define IRQ14_MCU_MODE_MASK_SFT GENMASK(27, 24)1481#define IRQ13_MCU_MODE_SFT 201482#define IRQ13_MCU_MODE_MASK 0xf1483#define IRQ13_MCU_MODE_MASK_SFT GENMASK(23, 20)1484#define IRQ12_MCU_MODE_SFT 161485#define IRQ12_MCU_MODE_MASK 0xf1486#define IRQ12_MCU_MODE_MASK_SFT GENMASK(19, 16)1487#define IRQ11_MCU_MODE_SFT 121488#define IRQ11_MCU_MODE_MASK 0xf1489#define IRQ11_MCU_MODE_MASK_SFT GENMASK(15, 12)1490#define IRQ10_MCU_MODE_SFT 81491#define IRQ10_MCU_MODE_MASK 0xf1492#define IRQ10_MCU_MODE_MASK_SFT GENMASK(11, 8)1493#define IRQ9_MCU_MODE_SFT 41494#define IRQ9_MCU_MODE_MASK 0xf1495#define IRQ9_MCU_MODE_MASK_SFT GENMASK(7, 4)1496#define IRQ8_MCU_MODE_SFT 01497#define IRQ8_MCU_MODE_MASK 0xf1498#define IRQ8_MCU_MODE_MASK_SFT GENMASK(3, 0)1499 1500/* AFE_IRQ_MCU_CON3 */1501#define IRQ23_MCU_MODE_SFT 281502#define IRQ23_MCU_MODE_MASK 0xf1503#define IRQ23_MCU_MODE_MASK_SFT GENMASK(31, 28)1504#define IRQ22_MCU_MODE_SFT 241505#define IRQ22_MCU_MODE_MASK 0xf1506#define IRQ22_MCU_MODE_MASK_SFT GENMASK(27, 24)1507#define IRQ21_MCU_MODE_SFT 201508#define IRQ21_MCU_MODE_MASK 0xf1509#define IRQ21_MCU_MODE_MASK_SFT GENMASK(23, 20)1510#define IRQ20_MCU_MODE_SFT 161511#define IRQ20_MCU_MODE_MASK 0xf1512#define IRQ20_MCU_MODE_MASK_SFT GENMASK(19, 16)1513#define IRQ19_MCU_MODE_SFT 121514#define IRQ19_MCU_MODE_MASK 0xf1515#define IRQ19_MCU_MODE_MASK_SFT GENMASK(15, 12)1516#define IRQ18_MCU_MODE_SFT 81517#define IRQ18_MCU_MODE_MASK 0xf1518#define IRQ18_MCU_MODE_MASK_SFT GENMASK(11, 8)1519#define IRQ17_MCU_MODE_SFT 41520#define IRQ17_MCU_MODE_MASK 0xf1521#define IRQ17_MCU_MODE_MASK_SFT GENMASK(7, 4)1522#define IRQ16_MCU_MODE_SFT 01523#define IRQ16_MCU_MODE_MASK 0xf1524#define IRQ16_MCU_MODE_MASK_SFT GENMASK(3, 0)1525 1526/* AFE_IRQ_MCU_CON4 */1527#define IRQ26_MCU_MODE_SFT 81528#define IRQ26_MCU_MODE_MASK 0xf1529#define IRQ26_MCU_MODE_MASK_SFT GENMASK(11, 8)1530#define IRQ25_MCU_MODE_SFT 41531#define IRQ25_MCU_MODE_MASK 0xf1532#define IRQ25_MCU_MODE_MASK_SFT GENMASK(7, 4)1533#define IRQ24_MCU_MODE_SFT 01534#define IRQ24_MCU_MODE_MASK 0xf1535#define IRQ24_MCU_MODE_MASK_SFT GENMASK(3, 0)1536 1537/* AFE_IRQ_MCU_CLR */1538#define IRQ31_MCU_CLR_SFT 311539#define IRQ31_MCU_CLR_MASK_SFT BIT(31)1540#define IRQ26_MCU_CLR_SFT 261541#define IRQ26_MCU_CLR_MASK_SFT BIT(26)1542#define IRQ25_MCU_CLR_SFT 251543#define IRQ25_MCU_CLR_MASK_SFT BIT(25)1544#define IRQ24_MCU_CLR_SFT 241545#define IRQ24_MCU_CLR_MASK_SFT BIT(24)1546#define IRQ23_MCU_CLR_SFT 231547#define IRQ23_MCU_CLR_MASK_SFT BIT(23)1548#define IRQ22_MCU_CLR_SFT 221549#define IRQ22_MCU_CLR_MASK_SFT BIT(22)1550#define IRQ21_MCU_CLR_SFT 211551#define IRQ21_MCU_CLR_MASK_SFT BIT(21)1552#define IRQ20_MCU_CLR_SFT 201553#define IRQ20_MCU_CLR_MASK_SFT BIT(20)1554#define IRQ19_MCU_CLR_SFT 191555#define IRQ19_MCU_CLR_MASK_SFT BIT(19)1556#define IRQ18_MCU_CLR_SFT 181557#define IRQ18_MCU_CLR_MASK_SFT BIT(18)1558#define IRQ17_MCU_CLR_SFT 171559#define IRQ17_MCU_CLR_MASK_SFT BIT(17)1560#define IRQ16_MCU_CLR_SFT 161561#define IRQ16_MCU_CLR_MASK_SFT BIT(16)1562#define IRQ15_MCU_CLR_SFT 151563#define IRQ15_MCU_CLR_MASK_SFT BIT(15)1564#define IRQ14_MCU_CLR_SFT 141565#define IRQ14_MCU_CLR_MASK_SFT BIT(14)1566#define IRQ13_MCU_CLR_SFT 131567#define IRQ13_MCU_CLR_MASK_SFT BIT(13)1568#define IRQ12_MCU_CLR_SFT 121569#define IRQ12_MCU_CLR_MASK_SFT BIT(12)1570#define IRQ11_MCU_CLR_SFT 111571#define IRQ11_MCU_CLR_MASK_SFT BIT(11)1572#define IRQ10_MCU_CLR_SFT 101573#define IRQ10_MCU_CLR_MASK_SFT BIT(10)1574#define IRQ9_MCU_CLR_SFT 91575#define IRQ9_MCU_CLR_MASK_SFT BIT(9)1576#define IRQ8_MCU_CLR_SFT 81577#define IRQ8_MCU_CLR_MASK_SFT BIT(8)1578#define IRQ7_MCU_CLR_SFT 71579#define IRQ7_MCU_CLR_MASK_SFT BIT(7)1580#define IRQ6_MCU_CLR_SFT 61581#define IRQ6_MCU_CLR_MASK_SFT BIT(6)1582#define IRQ5_MCU_CLR_SFT 51583#define IRQ5_MCU_CLR_MASK_SFT BIT(5)1584#define IRQ4_MCU_CLR_SFT 41585#define IRQ4_MCU_CLR_MASK_SFT BIT(4)1586#define IRQ3_MCU_CLR_SFT 31587#define IRQ3_MCU_CLR_MASK_SFT BIT(3)1588#define IRQ2_MCU_CLR_SFT 21589#define IRQ2_MCU_CLR_MASK_SFT BIT(2)1590#define IRQ1_MCU_CLR_SFT 11591#define IRQ1_MCU_CLR_MASK_SFT BIT(1)1592#define IRQ0_MCU_CLR_SFT 01593#define IRQ0_MCU_CLR_MASK_SFT BIT(0)1594 1595/* AFE_IRQ_MCU_EN */1596#define IRQ31_MCU_EN_SFT 311597#define IRQ30_MCU_EN_SFT 301598#define IRQ29_MCU_EN_SFT 291599#define IRQ28_MCU_EN_SFT 281600#define IRQ27_MCU_EN_SFT 271601#define IRQ26_MCU_EN_SFT 261602#define IRQ25_MCU_EN_SFT 251603#define IRQ24_MCU_EN_SFT 241604#define IRQ23_MCU_EN_SFT 231605#define IRQ22_MCU_EN_SFT 221606#define IRQ21_MCU_EN_SFT 211607#define IRQ20_MCU_EN_SFT 201608#define IRQ19_MCU_EN_SFT 191609#define IRQ18_MCU_EN_SFT 181610#define IRQ17_MCU_EN_SFT 171611#define IRQ16_MCU_EN_SFT 161612#define IRQ15_MCU_EN_SFT 151613#define IRQ14_MCU_EN_SFT 141614#define IRQ13_MCU_EN_SFT 131615#define IRQ12_MCU_EN_SFT 121616#define IRQ11_MCU_EN_SFT 111617#define IRQ10_MCU_EN_SFT 101618#define IRQ9_MCU_EN_SFT 91619#define IRQ8_MCU_EN_SFT 81620#define IRQ7_MCU_EN_SFT 71621#define IRQ6_MCU_EN_SFT 61622#define IRQ5_MCU_EN_SFT 51623#define IRQ4_MCU_EN_SFT 41624#define IRQ3_MCU_EN_SFT 31625#define IRQ2_MCU_EN_SFT 21626#define IRQ1_MCU_EN_SFT 11627#define IRQ0_MCU_EN_SFT 01628 1629/* AFE_IRQ_MCU_SCP_EN */1630#define IRQ31_MCU_SCP_EN_SFT 311631#define IRQ30_MCU_SCP_EN_SFT 301632#define IRQ29_MCU_SCP_EN_SFT 291633#define IRQ28_MCU_SCP_EN_SFT 281634#define IRQ27_MCU_SCP_EN_SFT 271635#define IRQ26_MCU_SCP_EN_SFT 261636#define IRQ25_MCU_SCP_EN_SFT 251637#define IRQ24_MCU_SCP_EN_SFT 241638#define IRQ23_MCU_SCP_EN_SFT 231639#define IRQ22_MCU_SCP_EN_SFT 221640#define IRQ21_MCU_SCP_EN_SFT 211641#define IRQ20_MCU_SCP_EN_SFT 201642#define IRQ19_MCU_SCP_EN_SFT 191643#define IRQ18_MCU_SCP_EN_SFT 181644#define IRQ17_MCU_SCP_EN_SFT 171645#define IRQ16_MCU_SCP_EN_SFT 161646#define IRQ15_MCU_SCP_EN_SFT 151647#define IRQ14_MCU_SCP_EN_SFT 141648#define IRQ13_MCU_SCP_EN_SFT 131649#define IRQ12_MCU_SCP_EN_SFT 121650#define IRQ11_MCU_SCP_EN_SFT 111651#define IRQ10_MCU_SCP_EN_SFT 101652#define IRQ9_MCU_SCP_EN_SFT 91653#define IRQ8_MCU_SCP_EN_SFT 81654#define IRQ7_MCU_SCP_EN_SFT 71655#define IRQ6_MCU_SCP_EN_SFT 61656#define IRQ5_MCU_SCP_EN_SFT 51657#define IRQ4_MCU_SCP_EN_SFT 41658#define IRQ3_MCU_SCP_EN_SFT 31659#define IRQ2_MCU_SCP_EN_SFT 21660#define IRQ1_MCU_SCP_EN_SFT 11661#define IRQ0_MCU_SCP_EN_SFT 01662 1663/* AFE_IRQ_MCU_DSP_EN */1664#define IRQ31_MCU_DSP_EN_SFT 311665#define IRQ30_MCU_DSP_EN_SFT 301666#define IRQ29_MCU_DSP_EN_SFT 291667#define IRQ28_MCU_DSP_EN_SFT 281668#define IRQ27_MCU_DSP_EN_SFT 271669#define IRQ26_MCU_DSP_EN_SFT 261670#define IRQ25_MCU_DSP_EN_SFT 251671#define IRQ24_MCU_DSP_EN_SFT 241672#define IRQ23_MCU_DSP_EN_SFT 231673#define IRQ22_MCU_DSP_EN_SFT 221674#define IRQ21_MCU_DSP_EN_SFT 211675#define IRQ20_MCU_DSP_EN_SFT 201676#define IRQ19_MCU_DSP_EN_SFT 191677#define IRQ18_MCU_DSP_EN_SFT 181678#define IRQ17_MCU_DSP_EN_SFT 171679#define IRQ16_MCU_DSP_EN_SFT 161680#define IRQ15_MCU_DSP_EN_SFT 151681#define IRQ14_MCU_DSP_EN_SFT 141682#define IRQ13_MCU_DSP_EN_SFT 131683#define IRQ12_MCU_DSP_EN_SFT 121684#define IRQ11_MCU_DSP_EN_SFT 111685#define IRQ10_MCU_DSP_EN_SFT 101686#define IRQ9_MCU_DSP_EN_SFT 91687#define IRQ8_MCU_DSP_EN_SFT 81688#define IRQ7_MCU_DSP_EN_SFT 71689#define IRQ6_MCU_DSP_EN_SFT 61690#define IRQ5_MCU_DSP_EN_SFT 51691#define IRQ4_MCU_DSP_EN_SFT 41692#define IRQ3_MCU_DSP_EN_SFT 31693#define IRQ2_MCU_DSP_EN_SFT 21694#define IRQ1_MCU_DSP_EN_SFT 11695#define IRQ0_MCU_DSP_EN_SFT 01696 1697/* AFE_AUD_PAD_TOP */1698#define AUD_PAD_TOP_MON_SFT 151699#define AUD_PAD_TOP_MON_MASK_SFT GENMASK(31, 15)1700#define AUD_PAD_TOP_FIFO_RSP_SFT 41701#define AUD_PAD_TOP_FIFO_RSP_MASK_SFT GENMASK(7, 4)1702#define RG_RX_PROTOCOL2_SFT 31703#define RG_RX_PROTOCOL2_MASK_SFT BIT(3)1704#define RESERVDED_01_SFT 11705#define RESERVDED_01_MASK_SFT GENMASK(2, 1)1706#define RG_RX_FIFO_ON_SFT 01707#define RG_RX_FIFO_ON_MASK_SFT BIT(0)1708 1709/* AFE_ADDA_MTKAIF_SYNCWORD_CFG */1710#define RG_ADDA6_MTKAIF_RX_SYNC_WORD2_DISABLE_SFT 231711#define RG_ADDA6_MTKAIF_RX_SYNC_WORD2_DISABLE_MASK_SFT BIT(23)1712 1713/* AFE_ADDA_MTKAIF_RX_CFG0 */1714#define MTKAIF_RXIF_VOICE_MODE_SFT 201715#define MTKAIF_RXIF_VOICE_MODE_MASK_SFT GENMASK(23, 20)1716#define MTKAIF_RXIF_DETECT_ON_SFT 161717#define MTKAIF_RXIF_DETECT_ON_MASK_SFT BIT(16)1718#define MTKAIF_RXIF_DATA_BIT_SFT 81719#define MTKAIF_RXIF_DATA_BIT_MASK_SFT GENMASK(10, 8)1720#define MTKAIF_RXIF_FIFO_RSP_SFT 41721#define MTKAIF_RXIF_FIFO_RSP_MASK_SFT GENMASK(6, 4)1722#define MTKAIF_RXIF_DATA_MODE_SFT 01723#define MTKAIF_RXIF_DATA_MODE_MASK_SFT BIT(0)1724 1725/* GENERAL_ASRC_MODE */1726#define GENERAL2_ASRCOUT_MODE_SFT 121727#define GENERAL2_ASRCOUT_MODE_MASK 0xf1728#define GENERAL2_ASRCOUT_MODE_MASK_SFT GENMASK(15, 12)1729#define GENERAL2_ASRCIN_MODE_SFT 81730#define GENERAL2_ASRCIN_MODE_MASK 0xf1731#define GENERAL2_ASRCIN_MODE_MASK_SFT GENMASK(11, 8)1732#define GENERAL1_ASRCOUT_MODE_SFT 41733#define GENERAL1_ASRCOUT_MODE_MASK 0xf1734#define GENERAL1_ASRCOUT_MODE_MASK_SFT GENMASK(7, 4)1735#define GENERAL1_ASRCIN_MODE_SFT 01736#define GENERAL1_ASRCIN_MODE_MASK 0xf1737#define GENERAL1_ASRCIN_MODE_MASK_SFT GENMASK(3, 0)1738 1739/* GENERAL_ASRC_EN_ON */1740#define GENERAL2_ASRC_EN_ON_SFT 11741#define GENERAL2_ASRC_EN_ON_MASK_SFT BIT(1)1742#define GENERAL1_ASRC_EN_ON_SFT 01743#define GENERAL1_ASRC_EN_ON_MASK_SFT BIT(0)1744 1745/* AFE_GENERAL1_ASRC_2CH_CON0 */1746#define G_SRC_CHSET_STR_CLR_SFT 41747#define G_SRC_CHSET_STR_CLR_MASK_SFT BIT(4)1748#define G_SRC_CHSET_ON_SFT 21749#define G_SRC_CHSET_ON_MASK_SFT BIT(2)1750#define G_SRC_COEFF_SRAM_CTRL_SFT 11751#define G_SRC_COEFF_SRAM_CTRL_MASK_SFT BIT(1)1752#define G_SRC_ASM_ON_SFT 01753#define G_SRC_ASM_ON_MASK_SFT BIT(0)1754 1755/* AFE_GENERAL1_ASRC_2CH_CON3 */1756#define G_SRC_ASM_FREQ_4_SFT 01757#define G_SRC_ASM_FREQ_4_MASK_SFT GENMASK(23, 0)1758 1759/* AFE_GENERAL1_ASRC_2CH_CON4 */1760#define G_SRC_ASM_FREQ_5_SFT 01761#define G_SRC_ASM_FREQ_5_MASK_SFT GENMASK(23, 0)1762 1763/* AFE_GENERAL1_ASRC_2CH_CON13 */1764#define G_SRC_COEFF_SRAM_ADR_SFT 01765#define G_SRC_COEFF_SRAM_ADR_MASK_SFT GENMASK(5, 0)1766 1767/* AFE_GENERAL1_ASRC_2CH_CON2 */1768#define G_SRC_CHSET_O16BIT_SFT 191769#define G_SRC_CHSET_O16BIT_MASK_SFT BIT(19)1770#define G_SRC_CHSET_CLR_IIR_HISTORY_SFT 171771#define G_SRC_CHSET_CLR_IIR_HISTORY_MASK_SFT BIT(17)1772#define G_SRC_CHSET_IS_MONO_SFT 161773#define G_SRC_CHSET_IS_MONO_MASK_SFT BIT(16)1774#define G_SRC_CHSET_IIR_EN_SFT 111775#define G_SRC_CHSET_IIR_EN_MASK_SFT BIT(11)1776#define G_SRC_CHSET_IIR_STAGE_SFT 81777#define G_SRC_CHSET_IIR_STAGE_MASK_SFT GENMASK(10, 8)1778#define G_SRC_CHSET_STR_CLR_RU_SFT 51779#define G_SRC_CHSET_STR_CLR_RU_MASK_SFT BIT(5)1780#define G_SRC_CHSET_ON_SFT 21781#define G_SRC_CHSET_ON_MASK_SFT BIT(2)1782#define G_SRC_COEFF_SRAM_CTRL_SFT 11783#define G_SRC_COEFF_SRAM_CTRL_MASK_SFT BIT(1)1784#define G_SRC_ASM_ON_SFT 01785#define G_SRC_ASM_ON_MASK_SFT BIT(0)1786 1787/* AFE_ADDA_DL_SDM_DITHER_CON */1788#define AFE_DL_SDM_DITHER_64TAP_EN_SFT 201789#define AFE_DL_SDM_DITHER_64TAP_EN_MASK_SFT BIT(20)1790#define AFE_DL_SDM_DITHER_EN_SFT 161791#define AFE_DL_SDM_DITHER_EN_MASK_SFT BIT(16)1792#define AFE_DL_SDM_DITHER_GAIN_SFT 01793#define AFE_DL_SDM_DITHER_GAIN_MASK_SFT GENMASK(7, 0)1794 1795/* AFE_ADDA_DL_SDM_AUTO_RESET_CON */1796#define SDM_AUTO_RESET_TEST_ON_SFT 311797#define SDM_AUTO_RESET_TEST_ON_MASK_SFT BIT(31)1798#define AFE_DL_USE_NEW_2ND_SDM_SFT 281799#define AFE_DL_USE_NEW_2ND_SDM_MASK_SFT BIT(28)1800#define SDM_AUTO_RESET_COUNT_TH_SFT 01801#define SDM_AUTO_RESET_COUNT_TH_MASK_SFT GENMASK(23, 0)1802 1803/* AFE_ASRC_2CH_CON0 */1804#define CON0_CHSET_STR_CLR_SFT 41805#define CON0_CHSET_STR_CLR_MASK_SFT BIT(4)1806#define CON0_ASM_ON_SFT 01807#define CON0_ASM_ON_MASK_SFT BIT(0)1808 1809/* AFE_ASRC_2CH_CON5 */1810#define CALI_EN_SFT 01811#define CALI_EN_MASK_SFT BIT(0)1812 1813/* FPGA_CFG4 */1814#define IRQ_COUNTER_SFT 31815#define IRQ_COUNTER_MASK_SFT GENMASK(31, 3)1816#define IRQ_CLK_COUNTER_CLEAN_SFT 21817#define IRQ_CLK_COUNTER_CLEAN_MASK_SFT BIT(2)1818#define IRQ_CLK_COUNTER_PAUSE_SFT 11819#define IRQ_CLK_COUNTER_PAUSE_MASK_SFT BIT(1)1820#define IRQ_CLK_COUNTER_ON_SFT 01821#define IRQ_CLK_COUNTER_ON_MASK_SFT BIT(0)1822 1823/* FPGA_CFG5 */1824#define WR_MSTR_ON_SFT 161825#define WR_MSTR_ON_MASK_SFT GENMASK(28, 16)1826#define WR_AG_SEL_SFT 01827#define WR_AG_SEL_MASK_SFT GENMASK(12, 0)1828 1829/* FPGA_CFG6 */1830#define WR_MSTR_REQ_REAL_SFT 161831#define WR_MSTR_REQ_REAL_MASK_SFT GENMASK(28, 16)1832#define WR_MSTR_REQ_IN_SFT 01833#define WR_MSTR_REQ_IN_MASK_SFT GENMASK(12, 0)1834 1835/* FPGA_CFG7 */1836#define MEM1_WDATA_MON0_SFT 01837#define MEM1_WDATA_MON0_MASK_SFT GENMASK(31, 0)1838 1839/* FPGA_CFG8 */1840#define MEM1_WDATA_MON1_SFT 01841#define MEM1_WDATA_MON1_MASK_SFT GENMASK(31, 0)1842 1843/* FPGA_CFG9 */1844#define MEM_WE_SFT 311845#define MEM_WE_MASK_SFT BIT(31)1846#define AFE_HREADY_SFT 301847#define AFE_HREADY_MASK_SFT BIT(30)1848#define MEM_WR_REQ_SFT 291849#define MEM_WR_REQ_MASK_SFT BIT(29)1850#define WR_AG_REG_MON_SFT 161851#define WR_AG_REG_MON_MASK_SFT GENMASK(28, 16)1852#define HCLK_CK_SFT 151853#define HCLK_CK_MASK_SFT BIT(15)1854#define MEM_RD_REQ_SFT 141855#define MEM_RD_REQ_MASK_SFT BIT(14)1856#define RD_AG_REQ_MON_SFT 01857#define RD_AG_REQ_MON_MASK_SFT GENMASK(13, 0)1858 1859/* FPGA_CFG10 */1860#define MEM_BYTE_0_SFT 01861#define MEM_BYTE_0_MASK_SFT GENMASK(31, 0)1862 1863/* FPGA_CFG11 */1864#define MEM_BYTE_1_SFT 01865#define MEM_BYTE_1_MASK_SFT GENMASK(31, 0)1866 1867/* FPGA_CFG12 */1868#define RDATA_CNT_SFT 301869#define RDATA_CNT_MASK_SFT GENMASK(31, 30)1870#define MS2_HREADY_SFT 291871#define MS2_HREADY_MASK_SFT BIT(29)1872#define MS1_HREADY_SFT 281873#define MS1_HREADY_MASK_SFT BIT(28)1874#define AG_SEL_SFT 01875#define AG_SEL_MASK_SFT GENMASK(25, 0)1876 1877/* FPGA_CFG13 */1878#define AFE_ST_SFT 271879#define AFE_ST_MASK_SFT GENMASK(31, 27)1880#define AG_IN_SERVICE_SFT 01881#define AG_IN_SERVICE_MASK_SFT GENMASK(25, 0)1882 1883/* ETDM_IN1_CON0 */1884#define ETDM_IN1_CON0_REG_ETDM_IN_EN_SFT 01885#define ETDM_IN1_CON0_REG_ETDM_IN_EN_MASK_SFT BIT(0)1886#define ETDM_IN1_CON0_REG_SYNC_MODE_SFT 11887#define ETDM_IN1_CON0_REG_SYNC_MODE_MASK_SFT BIT(1)1888#define ETDM_IN1_CON0_REG_LSB_FIRST_SFT 31889#define ETDM_IN1_CON0_REG_LSB_FIRST_MASK_SFT BIT(3)1890#define ETDM_IN1_CON0_REG_SOFT_RST_SFT 41891#define ETDM_IN1_CON0_REG_SOFT_RST_MASK_SFT BIT(4)1892#define ETDM_IN1_CON0_REG_SLAVE_MODE_SFT 51893#define ETDM_IN1_CON0_REG_SLAVE_MODE_MASK_SFT BIT(5)1894#define ETDM_IN1_CON0_REG_FMT_SFT 61895#define ETDM_IN1_CON0_REG_FMT_MASK_SFT GENMASK(8, 6)1896#define ETDM_IN1_CON0_REG_LRCK_EDGE_SEL_SFT 101897#define ETDM_IN1_CON0_REG_LRCK_EDGE_SEL_MASK_SFT BIT(10)1898#define ETDM_IN1_CON0_REG_BIT_LENGTH_SFT 111899#define ETDM_IN1_CON0_REG_BIT_LENGTH_MASK_SFT GENMASK(15, 11)1900#define ETDM_IN1_CON0_REG_WORD_LENGTH_SFT 161901#define ETDM_IN1_CON0_REG_WORD_LENGTH_MASK_SFT GENMASK(20, 16)1902#define ETDM_IN1_CON0_REG_CH_NUM_SFT 231903#define ETDM_IN1_CON0_REG_CH_NUM_MASK_SFT GENMASK(27, 23)1904#define ETDM_IN1_CON0_REG_RELATCH_1X_EN_SEL_DOMAIN_SFT 281905#define ETDM_IN1_CON0_REG_RELATCH_1X_EN_SEL_DOMAIN_MASK_SFT GENMASK(31, 28)1906#define ETDM_IN1_CON0_REG_VALID_TOGETHER_SFT 311907#define ETDM_IN1_CON0_REG_VALID_TOGETHER_MASK_SFT BIT(31)1908#define ETDM_IN_CON0_CTRL_MASK 0x1f9ff9e21909 1910/* ETDM_IN1_CON1 */1911#define ETDM_IN1_CON1_REG_INITIAL_COUNT_SFT 01912#define ETDM_IN1_CON1_REG_INITIAL_COUNT_MASK_SFT GENMASK(4, 0)1913#define ETDM_IN1_CON1_REG_INITIAL_POINT_SFT 51914#define ETDM_IN1_CON1_REG_INITIAL_POINT_MASK_SFT GENMASK(9, 5)1915#define ETDM_IN1_CON1_REG_LRCK_AUTO_OFF_SFT 101916#define ETDM_IN1_CON1_REG_LRCK_AUTO_OFF_MASK_SFT BIT(10)1917#define ETDM_IN1_CON1_REG_BCK_AUTO_OFF_SFT 111918#define ETDM_IN1_CON1_REG_BCK_AUTO_OFF_MASK_SFT BIT(11)1919#define ETDM_IN1_CON1_REG_INITIAL_LRCK_SFT 131920#define ETDM_IN1_CON1_REG_INITIAL_LRCK_MASK_SFT BIT(13)1921#define ETDM_IN1_CON1_REG_LRCK_RESET_SFT 151922#define ETDM_IN1_CON1_REG_LRCK_RESET_MASK_SFT BIT(15)1923#define ETDM_IN1_CON1_PINMUX_MCLK_CTRL_OE_SFT 161924#define ETDM_IN1_CON1_PINMUX_MCLK_CTRL_OE_MASK_SFT BIT(16)1925#define ETDM_IN1_CON1_REG_OUTPUT_CR_EN_SFT 181926#define ETDM_IN1_CON1_REG_OUTPUT_CR_EN_MASK_SFT BIT(18)1927#define ETDM_IN1_CON1_REG_LR_ALIGN_SFT 191928#define ETDM_IN1_CON1_REG_LR_ALIGN_MASK_SFT BIT(19)1929#define ETDM_IN1_CON1_REG_LRCK_WIDTH_SFT 201930#define ETDM_IN1_CON1_REG_LRCK_WIDTH_MASK_SFT GENMASK(29, 20)1931#define ETDM_IN1_CON1_REG_DIRECT_INPUT_MASTER_BCK_SFT 301932#define ETDM_IN1_CON1_REG_DIRECT_INPUT_MASTER_BCK_MASK_SFT BIT(30)1933#define ETDM_IN1_CON1_REG_LRCK_AUTO_MODE_SFT 311934#define ETDM_IN1_CON1_REG_LRCK_AUTO_MODE_MASK_SFT BIT(31)1935#define ETDM_IN_CON1_CTRL_MASK 0xbff100001936 1937/* ETDM_IN1_CON2 */1938#define ETDM_IN1_CON2_REG_UPDATE_POINT_SFT 01939#define ETDM_IN1_CON2_REG_UPDATE_POINT_MASK_SFT GENMASK(4, 0)1940#define ETDM_IN1_CON2_REG_UPDATE_GAP_SFT 51941#define ETDM_IN1_CON2_REG_UPDATE_GAP_MASK_SFT GENMASK(9, 5)1942#define ETDM_IN1_CON2_REG_CLOCK_SOURCE_SEL_SFT 101943#define ETDM_IN1_CON2_REG_CLOCK_SOURCE_SEL_MASK_SFT GENMASK(12, 10)1944#define ETDM_IN1_CON2_REG_AGENT_USE_ETDM_BCK_SFT 131945#define ETDM_IN1_CON2_REG_AGENT_USE_ETDM_BCK_MASK_SFT BIT(13)1946#define ETDM_IN1_CON2_REG_CK_EN_SEL_AUTO_SFT 141947#define ETDM_IN1_CON2_REG_CK_EN_SEL_AUTO_MASK_SFT BIT(14)1948#define ETDM_IN1_CON2_REG_MULTI_IP_ONE_DATA_CH_NUM_SFT 151949#define ETDM_IN1_CON2_REG_MULTI_IP_ONE_DATA_CH_NUM_MASK_SFT GENMASK(19, 15)1950#define ETDM_IN1_CON2_REG_MASK_AUTO_SFT 201951#define ETDM_IN1_CON2_REG_MASK_AUTO_MASK_SFT BIT(20)1952#define ETDM_IN1_CON2_REG_MASK_NUM_SFT 211953#define ETDM_IN1_CON2_REG_MASK_NUM_MASK_SFT GENMASK(25, 21)1954#define ETDM_IN1_CON2_REG_UPDATE_POINT_AUTO_SFT 261955#define ETDM_IN1_CON2_REG_UPDATE_POINT_AUTO_MASK_SFT BIT(26)1956#define ETDM_IN1_CON2_REG_SDATA_DELAY_0P5T_EN_SFT 271957#define ETDM_IN1_CON2_REG_SDATA_DELAY_0P5T_EN_MASK_SFT BIT(27)1958#define ETDM_IN1_CON2_REG_SDATA_DELAY_BCK_INV_SFT 281959#define ETDM_IN1_CON2_REG_SDATA_DELAY_BCK_INV_MASK_SFT BIT(28)1960#define ETDM_IN1_CON2_REG_LRCK_DELAY_0P5T_EN_SFT 291961#define ETDM_IN1_CON2_REG_LRCK_DELAY_0P5T_EN_MASK_SFT BIT(29)1962#define ETDM_IN1_CON2_REG_LRCK_DELAY_BCK_INV_SFT 301963#define ETDM_IN1_CON2_REG_LRCK_DELAY_BCK_INV_MASK_SFT BIT(30)1964#define ETDM_IN1_CON2_REG_MULTI_IP_MODE_SFT 311965#define ETDM_IN1_CON2_REG_MULTI_IP_MODE_MASK_SFT BIT(31)1966#define ETDM_IN_CON2_CTRL_MASK 0x800f80001967#define ETDM_IN_CON2_MULTI_IP_CH(x) (((x) - 1) << 15)1968#define ETDM_IN_CON2_MULTI_IP_2CH_MODE BIT(31)1969 1970/* ETDM_IN1_CON3 */1971#define ETDM_IN1_CON3_REG_DISABLE_OUT_0_SFT 01972#define ETDM_IN1_CON3_REG_DISABLE_OUT_0_MASK_SFT BIT(0)1973#define ETDM_IN1_CON3_REG_DISABLE_OUT_1_SFT 11974#define ETDM_IN1_CON3_REG_DISABLE_OUT_1_MASK_SFT BIT(1)1975#define ETDM_IN1_CON3_REG_DISABLE_OUT_2_SFT 21976#define ETDM_IN1_CON3_REG_DISABLE_OUT_2_MASK_SFT BIT(2)1977#define ETDM_IN1_CON3_REG_DISABLE_OUT_3_SFT 31978#define ETDM_IN1_CON3_REG_DISABLE_OUT_3_MASK_SFT BIT(3)1979#define ETDM_IN1_CON3_REG_DISABLE_OUT_4_SFT 41980#define ETDM_IN1_CON3_REG_DISABLE_OUT_4_MASK_SFT BIT(4)1981#define ETDM_IN1_CON3_REG_DISABLE_OUT_5_SFT 51982#define ETDM_IN1_CON3_REG_DISABLE_OUT_5_MASK_SFT BIT(5)1983#define ETDM_IN1_CON3_REG_DISABLE_OUT_6_SFT 61984#define ETDM_IN1_CON3_REG_DISABLE_OUT_6_MASK_SFT BIT(6)1985#define ETDM_IN1_CON3_REG_DISABLE_OUT_7_SFT 71986#define ETDM_IN1_CON3_REG_DISABLE_OUT_7_MASK_SFT BIT(7)1987#define ETDM_IN1_CON3_REG_DISABLE_OUT_8_SFT 81988#define ETDM_IN1_CON3_REG_DISABLE_OUT_8_MASK_SFT BIT(8)1989#define ETDM_IN1_CON3_REG_DISABLE_OUT_9_SFT 91990#define ETDM_IN1_CON3_REG_DISABLE_OUT_9_MASK_SFT BIT(9)1991#define ETDM_IN1_CON3_REG_DISABLE_OUT_10_SFT 101992#define ETDM_IN1_CON3_REG_DISABLE_OUT_10_MASK_SFT BIT(10)1993#define ETDM_IN1_CON3_REG_DISABLE_OUT_11_SFT 111994#define ETDM_IN1_CON3_REG_DISABLE_OUT_11_MASK_SFT BIT(11)1995#define ETDM_IN1_CON3_REG_DISABLE_OUT_12_SFT 121996#define ETDM_IN1_CON3_REG_DISABLE_OUT_12_MASK_SFT BIT(12)1997#define ETDM_IN1_CON3_REG_DISABLE_OUT_13_SFT 131998#define ETDM_IN1_CON3_REG_DISABLE_OUT_13_MASK_SFT BIT(13)1999#define ETDM_IN1_CON3_REG_DISABLE_OUT_14_SFT 142000#define ETDM_IN1_CON3_REG_DISABLE_OUT_14_MASK_SFT BIT(14)2001#define ETDM_IN1_CON3_REG_DISABLE_OUT_15_SFT 152002#define ETDM_IN1_CON3_REG_DISABLE_OUT_15_MASK_SFT BIT(15)2003#define ETDM_IN1_CON3_REG_RJ_DATA_RIGHT_ALIGN_SFT 162004#define ETDM_IN1_CON3_REG_RJ_DATA_RIGHT_ALIGN_MASK_SFT BIT(16)2005#define ETDM_IN1_CON3_REG_MONITOR_SEL_SFT 172006#define ETDM_IN1_CON3_REG_MONITOR_SEL_MASK_SFT GENMASK(18, 17)2007#define ETDM_IN1_CON3_REG_CNT_UPPER_LIMIT_SFT 192008#define ETDM_IN1_CON3_REG_CNT_UPPER_LIMIT_MASK_SFT GENMASK(24, 19)2009#define ETDM_IN1_CON3_REG_COMPACT_SAMPLE_END_DIS_SFT 252010#define ETDM_IN1_CON3_REG_COMPACT_SAMPLE_END_DIS_MASK_SFT BIT(25)2011#define ETDM_IN1_CON3_REG_FS_TIMING_SEL_SFT 262012#define ETDM_IN1_CON3_REG_FS_TIMING_SEL_MASK_SFT GENMASK(30, 26)2013#define ETDM_IN1_CON3_REG_SAMPLE_END_MODE_SFT 312014#define ETDM_IN1_CON3_REG_SAMPLE_END_MODE_MASK_SFT BIT(31)2015#define ETDM_IN_CON3_CTRL_MASK (0x7c000000)2016#define ETDM_IN_CON3_FS(x) (((x) & 0x1f) << 26)2017 2018/* ETDM_IN1_CON4 */2019#define ETDM_IN1_CON4_REG_DSD_MODE_SFT 02020#define ETDM_IN1_CON4_REG_DSD_MODE_MASK_SFT GENMASK(5, 0)2021#define ETDM_IN1_CON4_REG_DSD_REPACK_AUTO_MODE_SFT 82022#define ETDM_IN1_CON4_REG_DSD_REPACK_AUTO_MODE_MASK_SFT BIT(8)2023#define ETDM_IN1_CON4_REG_REPACK_WORD_LENGTH_SFT 92024#define ETDM_IN1_CON4_REG_REPACK_WORD_LENGTH_MASK_SFT GENMASK(10, 9)2025#define ETDM_IN1_CON4_REG_ASYNC_RESET_SFT 112026#define ETDM_IN1_CON4_REG_ASYNC_RESET_MASK_SFT BIT(11)2027#define ETDM_IN1_CON4_REG_DSD_CHNUM_SFT 122028#define ETDM_IN1_CON4_REG_DSD_CHNUM_MASK_SFT GENMASK(15, 12)2029#define ETDM_IN1_CON4_REG_SLAVE_BCK_INV_SFT 162030#define ETDM_IN1_CON4_REG_SLAVE_BCK_INV_MASK_SFT BIT(16)2031#define ETDM_IN1_CON4_REG_SLAVE_LRCK_INV_SFT 172032#define ETDM_IN1_CON4_REG_SLAVE_LRCK_INV_MASK_SFT BIT(17)2033#define ETDM_IN1_CON4_REG_MASTER_BCK_INV_SFT 182034#define ETDM_IN1_CON4_REG_MASTER_BCK_INV_MASK_SFT BIT(18)2035#define ETDM_IN1_CON4_REG_MASTER_LRCK_INV_SFT 192036#define ETDM_IN1_CON4_REG_MASTER_LRCK_INV_MASK_SFT BIT(19)2037#define ETDM_IN1_CON4_REG_RELATCH_1X_EN_SEL_SFT 202038#define ETDM_IN1_CON4_REG_RELATCH_1X_EN_SEL_MASK_SFT GENMASK(24, 20)2039#define ETDM_IN1_CON4_REG_SAMPLE_END_POINT_SFT 252040#define ETDM_IN1_CON4_REG_SAMPLE_END_POINT_MASK_SFT GENMASK(29, 25)2041#define ETDM_IN1_CON4_REG_WAIT_LAST_SAMPLE_SFT 302042#define ETDM_IN1_CON4_REG_WAIT_LAST_SAMPLE_MASK_SFT BIT(30)2043#define ETDM_IN1_CON4_REG_MASTER_BCK_FORCE_ON_SFT 312044#define ETDM_IN1_CON4_REG_MASTER_BCK_FORCE_ON_MASK_SFT BIT(31)2045#define ETDM_IN_CON4_CTRL_MASK 0x1ff00002046#define ETDM_IN_CON4_FS(x) (((x) & 0x1f) << 20)2047#define ETDM_IN_CON4_CON0_MASTER_LRCK_INV BIT(19)2048#define ETDM_IN_CON4_CON0_MASTER_BCK_INV BIT(18)2049#define ETDM_IN_CON4_CON0_SLAVE_LRCK_INV BIT(17)2050#define ETDM_IN_CON4_CON0_SLAVE_BCK_INV BIT(16)2051 2052/* ETDM_IN1_CON5 */2053#define ETDM_IN1_CON5_REG_ODD_FLAG_EN_0_SFT 02054#define ETDM_IN1_CON5_REG_ODD_FLAG_EN_0_MASK_SFT BIT(0)2055#define ETDM_IN1_CON5_REG_ODD_FLAG_EN_1_SFT 12056#define ETDM_IN1_CON5_REG_ODD_FLAG_EN_1_MASK_SFT BIT(1)2057#define ETDM_IN1_CON5_REG_ODD_FLAG_EN_2_SFT 22058#define ETDM_IN1_CON5_REG_ODD_FLAG_EN_2_MASK_SFT BIT(2)2059#define ETDM_IN1_CON5_REG_ODD_FLAG_EN_3_SFT 32060#define ETDM_IN1_CON5_REG_ODD_FLAG_EN_3_MASK_SFT BIT(3)2061#define ETDM_IN1_CON5_REG_ODD_FLAG_EN_4_SFT 42062#define ETDM_IN1_CON5_REG_ODD_FLAG_EN_4_MASK_SFT BIT(4)2063#define ETDM_IN1_CON5_REG_ODD_FLAG_EN_5_SFT 52064#define ETDM_IN1_CON5_REG_ODD_FLAG_EN_5_MASK_SFT BIT(5)2065#define ETDM_IN1_CON5_REG_ODD_FLAG_EN_6_SFT 62066#define ETDM_IN1_CON5_REG_ODD_FLAG_EN_6_MASK_SFT BIT(6)2067#define ETDM_IN1_CON5_REG_ODD_FLAG_EN_7_SFT 72068#define ETDM_IN1_CON5_REG_ODD_FLAG_EN_7_MASK_SFT BIT(7)2069#define ETDM_IN1_CON5_REG_ODD_FLAG_EN_8_SFT 82070#define ETDM_IN1_CON5_REG_ODD_FLAG_EN_8_MASK_SFT BIT(8)2071#define ETDM_IN1_CON5_REG_ODD_FLAG_EN_9_SFT 92072#define ETDM_IN1_CON5_REG_ODD_FLAG_EN_9_MASK_SFT BIT(9)2073#define ETDM_IN1_CON5_REG_ODD_FLAG_EN_10_SFT 102074#define ETDM_IN1_CON5_REG_ODD_FLAG_EN_10_MASK_SFT BIT(10)2075#define ETDM_IN1_CON5_REG_ODD_FLAG_EN_11_SFT 112076#define ETDM_IN1_CON5_REG_ODD_FLAG_EN_11_MASK_SFT BIT(11)2077#define ETDM_IN1_CON5_REG_ODD_FLAG_EN_12_SFT 122078#define ETDM_IN1_CON5_REG_ODD_FLAG_EN_12_MASK_SFT BIT(12)2079#define ETDM_IN1_CON5_REG_ODD_FLAG_EN_13_SFT 132080#define ETDM_IN1_CON5_REG_ODD_FLAG_EN_13_MASK_SFT BIT(13)2081#define ETDM_IN1_CON5_REG_ODD_FLAG_EN_14_SFT 142082#define ETDM_IN1_CON5_REG_ODD_FLAG_EN_14_MASK_SFT BIT(14)2083#define ETDM_IN1_CON5_REG_ODD_FLAG_EN_15_SFT 152084#define ETDM_IN1_CON5_REG_ODD_FLAG_EN_15_MASK_SFT BIT(15)2085#define ETDM_IN1_CON5_REG_LR_SWAP_0_SFT 162086#define ETDM_IN1_CON5_REG_LR_SWAP_0_MASK_SFT BIT(16)2087#define ETDM_IN1_CON5_REG_LR_SWAP_1_SFT 172088#define ETDM_IN1_CON5_REG_LR_SWAP_1_MASK_SFT BIT(17)2089#define ETDM_IN1_CON5_REG_LR_SWAP_2_SFT 182090#define ETDM_IN1_CON5_REG_LR_SWAP_2_MASK_SFT BIT(18)2091#define ETDM_IN1_CON5_REG_LR_SWAP_3_SFT 192092#define ETDM_IN1_CON5_REG_LR_SWAP_3_MASK_SFT BIT(19)2093#define ETDM_IN1_CON5_REG_LR_SWAP_4_SFT 202094#define ETDM_IN1_CON5_REG_LR_SWAP_4_MASK_SFT BIT(20)2095#define ETDM_IN1_CON5_REG_LR_SWAP_5_SFT 212096#define ETDM_IN1_CON5_REG_LR_SWAP_5_MASK_SFT BIT(21)2097#define ETDM_IN1_CON5_REG_LR_SWAP_6_SFT 222098#define ETDM_IN1_CON5_REG_LR_SWAP_6_MASK_SFT BIT(22)2099#define ETDM_IN1_CON5_REG_LR_SWAP_7_SFT 232100#define ETDM_IN1_CON5_REG_LR_SWAP_7_MASK_SFT BIT(23)2101#define ETDM_IN1_CON5_REG_LR_SWAP_8_SFT 242102#define ETDM_IN1_CON5_REG_LR_SWAP_8_MASK_SFT BIT(24)2103#define ETDM_IN1_CON5_REG_LR_SWAP_9_SFT 252104#define ETDM_IN1_CON5_REG_LR_SWAP_9_MASK_SFT BIT(25)2105#define ETDM_IN1_CON5_REG_LR_SWAP_10_SFT 262106#define ETDM_IN1_CON5_REG_LR_SWAP_10_MASK_SFT BIT(26)2107#define ETDM_IN1_CON5_REG_LR_SWAP_11_SFT 272108#define ETDM_IN1_CON5_REG_LR_SWAP_11_MASK_SFT BIT(27)2109#define ETDM_IN1_CON5_REG_LR_SWAP_12_SFT 282110#define ETDM_IN1_CON5_REG_LR_SWAP_12_MASK_SFT BIT(28)2111#define ETDM_IN1_CON5_REG_LR_SWAP_13_SFT 292112#define ETDM_IN1_CON5_REG_LR_SWAP_13_MASK_SFT BIT(29)2113#define ETDM_IN1_CON5_REG_LR_SWAP_14_SFT 302114#define ETDM_IN1_CON5_REG_LR_SWAP_14_MASK_SFT BIT(30)2115#define ETDM_IN1_CON5_REG_LR_SWAP_15_SFT 312116#define ETDM_IN1_CON5_REG_LR_SWAP_15_MASK_SFT BIT(31)2117 2118/* ETDM_IN1_CON6 */2119#define ETDM_IN1_CON6_LCH_DATA_REG_SFT 02120#define ETDM_IN1_CON6_LCH_DATA_REG_MASK_SFT GENMASK(31, 0)2121 2122/* ETDM_IN1_CON7 */2123#define ETDM_IN1_CON7_RCH_DATA_REG_SFT 02124#define ETDM_IN1_CON7_RCH_DATA_REG_MASK_SFT GENMASK(31, 0)2125 2126/* ETDM_IN1_CON8 */2127#define ETDM_IN1_CON8_REG_AFIFO_THRESHOLD_SFT 292128#define ETDM_IN1_CON8_REG_AFIFO_THRESHOLD_MASK_SFT GENMASK(30, 29)2129#define ETDM_IN1_CON8_REG_CK_EN_SEL_MANUAL_SFT 162130#define ETDM_IN1_CON8_REG_CK_EN_SEL_MANUAL_MASK_SFT GENMASK(25, 16)2131#define ETDM_IN1_CON8_REG_AFIFO_SW_RESET_SFT 152132#define ETDM_IN1_CON8_REG_AFIFO_SW_RESET_MASK_SFT BIT(15)2133#define ETDM_IN1_CON8_REG_AFIFO_RESET_SEL_SFT 142134#define ETDM_IN1_CON8_REG_AFIFO_RESET_SEL_MASK_SFT BIT(14)2135#define ETDM_IN1_CON8_REG_AFIFO_AUTO_RESET_DIS_SFT 92136#define ETDM_IN1_CON8_REG_AFIFO_AUTO_RESET_DIS_MASK_SFT BIT(9)2137#define ETDM_IN1_CON8_REG_ETDM_USE_AFIFO_SFT 82138#define ETDM_IN1_CON8_REG_ETDM_USE_AFIFO_MASK_SFT BIT(8)2139#define ETDM_IN1_CON8_REG_AFIFO_CLOCK_DOMAIN_SEL_SFT 52140#define ETDM_IN1_CON8_REG_AFIFO_CLOCK_DOMAIN_SEL_MASK_SFT GENMASK(7, 5)2141#define ETDM_IN1_CON8_REG_AFIFO_MODE_SFT 02142#define ETDM_IN1_CON8_REG_AFIFO_MODE_MASK_SFT GENMASK(4, 0)2143#define ETDM_IN_CON8_FS(x) (((x) & 0x1f) << 0)2144#define ETDM_IN_CON8_CTRL_MASK 0x13f2145 2146#define AUDIO_TOP_CON0 0x00002147#define AUDIO_TOP_CON1 0x00042148#define AUDIO_TOP_CON2 0x00082149#define AUDIO_TOP_CON3 0x000c2150#define AFE_DAC_CON0 0x00102151#define AFE_I2S_CON 0x00182152#define AFE_CONN0 0x00202153#define AFE_CONN1 0x00242154#define AFE_CONN2 0x00282155#define AFE_CONN3 0x002c2156#define AFE_CONN4 0x00302157#define AFE_I2S_CON1 0x00342158#define AFE_I2S_CON2 0x00382159#define AFE_I2S_CON3 0x00402160#define AFE_CONN5 0x00442161#define AFE_CONN_24BIT 0x00482162#define AFE_DL1_CON0 0x004c2163#define AFE_DL1_BASE_MSB 0x00502164#define AFE_DL1_BASE 0x00542165#define AFE_DL1_CUR_MSB 0x00582166#define AFE_DL1_CUR 0x005c2167#define AFE_DL1_END_MSB 0x00602168#define AFE_DL1_END 0x00642169#define AFE_DL2_CON0 0x00682170#define AFE_DL2_BASE_MSB 0x006c2171#define AFE_DL2_BASE 0x00702172#define AFE_DL2_CUR_MSB 0x00742173#define AFE_DL2_CUR 0x00782174#define AFE_DL2_END_MSB 0x007c2175#define AFE_DL2_END 0x00802176#define AFE_DL3_CON0 0x00842177#define AFE_DL3_BASE_MSB 0x00882178#define AFE_DL3_BASE 0x008c2179#define AFE_DL3_CUR_MSB 0x00902180#define AFE_DL3_CUR 0x00942181#define AFE_DL3_END_MSB 0x00982182#define AFE_DL3_END 0x009c2183#define AFE_CONN6 0x00bc2184#define AFE_DL4_CON0 0x00cc2185#define AFE_DL4_BASE_MSB 0x00d02186#define AFE_DL4_BASE 0x00d42187#define AFE_DL4_CUR_MSB 0x00d82188#define AFE_DL4_CUR 0x00dc2189#define AFE_DL4_END_MSB 0x00e02190#define AFE_DL4_END 0x00e42191#define AFE_DL12_CON0 0x00e82192#define AFE_DL12_BASE_MSB 0x00ec2193#define AFE_DL12_BASE 0x00f02194#define AFE_DL12_CUR_MSB 0x00f42195#define AFE_DL12_CUR 0x00f82196#define AFE_DL12_END_MSB 0x00fc2197#define AFE_DL12_END 0x01002198#define AFE_ADDA_DL_SRC2_CON0 0x01082199#define AFE_ADDA_DL_SRC2_CON1 0x010c2200#define AFE_ADDA_UL_SRC_CON0 0x01142201#define AFE_ADDA_UL_SRC_CON1 0x01182202#define AFE_ADDA_TOP_CON0 0x01202203#define AFE_ADDA_UL_DL_CON0 0x01242204#define AFE_ADDA_SRC_DEBUG 0x012c2205#define AFE_ADDA_SRC_DEBUG_MON0 0x01302206#define AFE_ADDA_SRC_DEBUG_MON1 0x01342207#define AFE_ADDA_UL_SRC_MON0 0x01482208#define AFE_ADDA_UL_SRC_MON1 0x014c2209#define AFE_SECURE_CON0 0x01502210#define AFE_SRAM_BOUND 0x01542211#define AFE_SECURE_CON1 0x01582212#define AFE_SECURE_CONN0 0x015c2213#define AFE_VUL_CON0 0x01702214#define AFE_VUL_BASE_MSB 0x01742215#define AFE_VUL_BASE 0x01782216#define AFE_VUL_CUR_MSB 0x017c2217#define AFE_VUL_CUR 0x01802218#define AFE_VUL_END_MSB 0x01842219#define AFE_VUL_END 0x01882220#define AFE_SIDETONE_DEBUG 0x01d02221#define AFE_SIDETONE_MON 0x01d42222#define AFE_SINEGEN_CON2 0x01dc2223#define AFE_SIDETONE_CON0 0x01e02224#define AFE_SIDETONE_COEFF 0x01e42225#define AFE_SIDETONE_CON1 0x01e82226#define AFE_SIDETONE_GAIN 0x01ec2227#define AFE_SINEGEN_CON0 0x01f02228#define AFE_TOP_CON0 0x02002229#define AFE_VUL2_CON0 0x020c2230#define AFE_VUL2_BASE_MSB 0x02102231#define AFE_VUL2_BASE 0x02142232#define AFE_VUL2_CUR_MSB 0x02182233#define AFE_VUL2_CUR 0x021c2234#define AFE_VUL2_END_MSB 0x02202235#define AFE_VUL2_END 0x02242236#define AFE_VUL3_CON0 0x02282237#define AFE_VUL3_BASE_MSB 0x022c2238#define AFE_VUL3_BASE 0x02302239#define AFE_VUL3_CUR_MSB 0x02342240#define AFE_VUL3_CUR 0x02382241#define AFE_VUL3_END_MSB 0x023c2242#define AFE_VUL3_END 0x02402243#define AFE_BUSY 0x02442244#define AFE_BUS_CFG 0x02502245#define AFE_ADDA_PREDIS_CON0 0x02602246#define AFE_ADDA_PREDIS_CON1 0x02642247#define AFE_I2S_MON 0x027c2248#define AFE_ADDA_IIR_COEF_02_01 0x02902249#define AFE_ADDA_IIR_COEF_04_03 0x02942250#define AFE_ADDA_IIR_COEF_06_05 0x02982251#define AFE_ADDA_IIR_COEF_08_07 0x029c2252#define AFE_ADDA_IIR_COEF_10_09 0x02a02253#define AFE_IRQ_MCU_CON1 0x02e42254#define AFE_IRQ_MCU_CON2 0x02e82255#define AFE_DAC_MON 0x02ec2256#define AFE_IRQ_MCU_CON3 0x02f02257#define AFE_IRQ_MCU_CON4 0x02f42258#define AFE_IRQ_MCU_CNT0 0x03002259#define AFE_IRQ_MCU_CNT6 0x03042260#define AFE_IRQ_MCU_CNT8 0x03082261#define AFE_IRQ_MCU_DSP2_EN 0x030c2262#define AFE_IRQ0_MCU_CNT_MON 0x03102263#define AFE_IRQ6_MCU_CNT_MON 0x03142264#define AFE_VUL4_CON0 0x03582265#define AFE_VUL4_BASE_MSB 0x035c2266#define AFE_VUL4_BASE 0x03602267#define AFE_VUL4_CUR_MSB 0x03642268#define AFE_VUL4_CUR 0x03682269#define AFE_VUL4_END_MSB 0x036c2270#define AFE_VUL4_END 0x03702271#define AFE_VUL12_CON0 0x03742272#define AFE_VUL12_BASE_MSB 0x03782273#define AFE_VUL12_BASE 0x037c2274#define AFE_VUL12_CUR_MSB 0x03802275#define AFE_VUL12_CUR 0x03842276#define AFE_VUL12_END_MSB 0x03882277#define AFE_VUL12_END 0x038c2278#define AFE_IRQ3_MCU_CNT_MON 0x03982279#define AFE_IRQ4_MCU_CNT_MON 0x039c2280#define AFE_IRQ_MCU_CON0 0x03a02281#define AFE_IRQ_MCU_STATUS 0x03a42282#define AFE_IRQ_MCU_CLR 0x03a82283#define AFE_IRQ_MCU_CNT1 0x03ac2284#define AFE_IRQ_MCU_CNT2 0x03b02285#define AFE_IRQ_MCU_EN 0x03b42286#define AFE_IRQ_MCU_MON2 0x03b82287#define AFE_IRQ_MCU_CNT5 0x03bc2288#define AFE_IRQ1_MCU_CNT_MON 0x03c02289#define AFE_IRQ2_MCU_CNT_MON 0x03c42290#define AFE_IRQ5_MCU_CNT_MON 0x03cc2291#define AFE_IRQ_MCU_DSP_EN 0x03d02292#define AFE_IRQ_MCU_SCP_EN 0x03d42293#define AFE_IRQ_MCU_CNT7 0x03dc2294#define AFE_IRQ7_MCU_CNT_MON 0x03e02295#define AFE_IRQ_MCU_CNT3 0x03e42296#define AFE_IRQ_MCU_CNT4 0x03e82297#define AFE_IRQ_MCU_CNT11 0x03ec2298#define AFE_APLL1_TUNER_CFG 0x03f02299#define AFE_APLL2_TUNER_CFG 0x03f42300#define AFE_IRQ_MCU_MISS_CLR 0x03f82301#define AFE_CONN33 0x04082302#define AFE_IRQ_MCU_CNT12 0x040c2303#define AFE_GAIN1_CON0 0x04102304#define AFE_GAIN1_CON1 0x04142305#define AFE_GAIN1_CON2 0x04182306#define AFE_GAIN1_CON3 0x041c2307#define AFE_CONN7 0x04202308#define AFE_GAIN1_CUR 0x04242309#define AFE_GAIN2_CON0 0x04282310#define AFE_GAIN2_CON1 0x042c2311#define AFE_GAIN2_CON2 0x04302312#define AFE_GAIN2_CON3 0x04342313#define AFE_CONN8 0x04382314#define AFE_GAIN2_CUR 0x043c2315#define AFE_CONN9 0x04402316#define AFE_CONN10 0x04442317#define AFE_CONN11 0x04482318#define AFE_CONN12 0x044c2319#define AFE_CONN13 0x04502320#define AFE_CONN14 0x04542321#define AFE_CONN15 0x04582322#define AFE_CONN16 0x045c2323#define AFE_CONN17 0x04602324#define AFE_CONN18 0x04642325#define AFE_CONN19 0x04682326#define AFE_CONN20 0x046c2327#define AFE_CONN21 0x04702328#define AFE_CONN22 0x04742329#define AFE_CONN23 0x04782330#define AFE_CONN24 0x047c2331#define AFE_CONN_RS 0x04942332#define AFE_CONN_DI 0x04982333#define AFE_CONN25 0x04b02334#define AFE_CONN26 0x04b42335#define AFE_CONN27 0x04b82336#define AFE_CONN28 0x04bc2337#define AFE_CONN29 0x04c02338#define AFE_CONN30 0x04c42339#define AFE_CONN31 0x04c82340#define AFE_CONN32 0x04cc2341#define AFE_SRAM_DELSEL_CON1 0x04f42342#define AFE_CONN56 0x05002343#define AFE_CONN57 0x05042344#define AFE_CONN58 0x05082345#define AFE_CONN59 0x050c2346#define AFE_CONN56_1 0x05102347#define AFE_CONN57_1 0x05142348#define AFE_CONN58_1 0x05182349#define AFE_CONN59_1 0x051c2350#define PCM_INTF_CON1 0x05302351#define PCM_INTF_CON2 0x05382352#define PCM2_INTF_CON 0x053c2353#define AFE_CM1_CON 0x05502354#define AFE_CONN34 0x05802355#define FPGA_CFG0 0x05b02356#define FPGA_CFG1 0x05b42357#define FPGA_CFG2 0x05c02358#define FPGA_CFG3 0x05c42359#define AUDIO_TOP_DBG_CON 0x05c82360#define AUDIO_TOP_DBG_MON0 0x05cc2361#define AUDIO_TOP_DBG_MON1 0x05d02362#define AFE_IRQ8_MCU_CNT_MON 0x05e42363#define AFE_IRQ11_MCU_CNT_MON 0x05e82364#define AFE_IRQ12_MCU_CNT_MON 0x05ec2365#define AFE_IRQ_MCU_CNT9 0x06002366#define AFE_IRQ_MCU_CNT10 0x06042367#define AFE_IRQ_MCU_CNT13 0x06082368#define AFE_IRQ_MCU_CNT14 0x060c2369#define AFE_IRQ_MCU_CNT15 0x06102370#define AFE_IRQ_MCU_CNT16 0x06142371#define AFE_IRQ_MCU_CNT17 0x06182372#define AFE_IRQ_MCU_CNT18 0x061c2373#define AFE_IRQ_MCU_CNT19 0x06202374#define AFE_IRQ_MCU_CNT20 0x06242375#define AFE_IRQ_MCU_CNT21 0x06282376#define AFE_IRQ_MCU_CNT22 0x062c2377#define AFE_IRQ_MCU_CNT23 0x06302378#define AFE_IRQ_MCU_CNT24 0x06342379#define AFE_IRQ_MCU_CNT25 0x06382380#define AFE_IRQ_MCU_CNT26 0x063c2381#define AFE_IRQ9_MCU_CNT_MON 0x06602382#define AFE_IRQ10_MCU_CNT_MON 0x06642383#define AFE_IRQ13_MCU_CNT_MON 0x06682384#define AFE_IRQ14_MCU_CNT_MON 0x066c2385#define AFE_IRQ15_MCU_CNT_MON 0x06702386#define AFE_IRQ16_MCU_CNT_MON 0x06742387#define AFE_IRQ17_MCU_CNT_MON 0x06782388#define AFE_IRQ18_MCU_CNT_MON 0x067c2389#define AFE_IRQ19_MCU_CNT_MON 0x06802390#define AFE_IRQ20_MCU_CNT_MON 0x06842391#define AFE_IRQ21_MCU_CNT_MON 0x06882392#define AFE_IRQ22_MCU_CNT_MON 0x068c2393#define AFE_IRQ23_MCU_CNT_MON 0x06902394#define AFE_IRQ24_MCU_CNT_MON 0x06942395#define AFE_IRQ25_MCU_CNT_MON 0x06982396#define AFE_IRQ26_MCU_CNT_MON 0x069c2397#define AFE_IRQ31_MCU_CNT_MON 0x06a02398#define AFE_GENERAL_REG0 0x08002399#define AFE_GENERAL_REG1 0x08042400#define AFE_GENERAL_REG2 0x08082401#define AFE_GENERAL_REG3 0x080c2402#define AFE_GENERAL_REG4 0x08102403#define AFE_GENERAL_REG5 0x08142404#define AFE_GENERAL_REG6 0x08182405#define AFE_GENERAL_REG7 0x081c2406#define AFE_GENERAL_REG8 0x08202407#define AFE_GENERAL_REG9 0x08242408#define AFE_GENERAL_REG10 0x08282409#define AFE_GENERAL_REG11 0x082c2410#define AFE_GENERAL_REG12 0x08302411#define AFE_GENERAL_REG13 0x08342412#define AFE_GENERAL_REG14 0x08382413#define AFE_GENERAL_REG15 0x083c2414#define AFE_CBIP_CFG0 0x08402415#define AFE_CBIP_MON0 0x08442416#define AFE_CBIP_SLV_MUX_MON0 0x08482417#define AFE_CBIP_SLV_DECODER_MON0 0x084c2418#define AFE_ADDA6_MTKAIF_MON0 0x08542419#define AFE_ADDA6_MTKAIF_MON1 0x08582420#define AFE_AWB_CON0 0x085c2421#define AFE_AWB_BASE_MSB 0x08602422#define AFE_AWB_BASE 0x08642423#define AFE_AWB_CUR_MSB 0x08682424#define AFE_AWB_CUR 0x086c2425#define AFE_AWB_END_MSB 0x08702426#define AFE_AWB_END 0x08742427#define AFE_AWB2_CON0 0x08782428#define AFE_AWB2_BASE_MSB 0x087c2429#define AFE_AWB2_BASE 0x08802430#define AFE_AWB2_CUR_MSB 0x08842431#define AFE_AWB2_CUR 0x08882432#define AFE_AWB2_END_MSB 0x088c2433#define AFE_AWB2_END 0x08902434#define AFE_DAI_CON0 0x08942435#define AFE_DAI_BASE_MSB 0x08982436#define AFE_DAI_BASE 0x089c2437#define AFE_DAI_CUR_MSB 0x08a02438#define AFE_DAI_CUR 0x08a42439#define AFE_DAI_END_MSB 0x08a82440#define AFE_DAI_END 0x08ac2441#define AFE_DAI2_CON0 0x08b02442#define AFE_DAI2_BASE_MSB 0x08b42443#define AFE_DAI2_BASE 0x08b82444#define AFE_DAI2_CUR_MSB 0x08bc2445#define AFE_DAI2_CUR 0x08c02446#define AFE_DAI2_END_MSB 0x08c42447#define AFE_DAI2_END 0x08c82448#define AFE_MEMIF_CON0 0x08cc2449#define AFE_CONN0_1 0x09002450#define AFE_CONN1_1 0x09042451#define AFE_CONN2_1 0x09082452#define AFE_CONN3_1 0x090c2453#define AFE_CONN4_1 0x09102454#define AFE_CONN5_1 0x09142455#define AFE_CONN6_1 0x09182456#define AFE_CONN7_1 0x091c2457#define AFE_CONN8_1 0x09202458#define AFE_CONN9_1 0x09242459#define AFE_CONN10_1 0x09282460#define AFE_CONN11_1 0x092c2461#define AFE_CONN12_1 0x09302462#define AFE_CONN13_1 0x09342463#define AFE_CONN14_1 0x09382464#define AFE_CONN15_1 0x093c2465#define AFE_CONN16_1 0x09402466#define AFE_CONN17_1 0x09442467#define AFE_CONN18_1 0x09482468#define AFE_CONN19_1 0x094c2469#define AFE_CONN20_1 0x09502470#define AFE_CONN21_1 0x09542471#define AFE_CONN22_1 0x09582472#define AFE_CONN23_1 0x095c2473#define AFE_CONN24_1 0x09602474#define AFE_CONN25_1 0x09642475#define AFE_CONN26_1 0x09682476#define AFE_CONN27_1 0x096c2477#define AFE_CONN28_1 0x09702478#define AFE_CONN29_1 0x09742479#define AFE_CONN30_1 0x09782480#define AFE_CONN31_1 0x097c2481#define AFE_CONN32_1 0x09802482#define AFE_CONN33_1 0x09842483#define AFE_CONN34_1 0x09882484#define AFE_CONN_RS_1 0x098c2485#define AFE_CONN_DI_1 0x09902486#define AFE_CONN_24BIT_1 0x09942487#define AFE_CONN_REG 0x09982488#define AFE_CONN35 0x09a02489#define AFE_CONN36 0x09a42490#define AFE_CONN37 0x09a82491#define AFE_CONN38 0x09ac2492#define AFE_CONN35_1 0x09b02493#define AFE_CONN36_1 0x09b42494#define AFE_CONN37_1 0x09b82495#define AFE_CONN38_1 0x09bc2496#define AFE_CONN39 0x09c02497#define AFE_CONN40 0x09c42498#define AFE_CONN41 0x09c82499#define AFE_CONN42 0x09cc2500#define AFE_CONN39_1 0x09e02501#define AFE_CONN40_1 0x09e42502#define AFE_CONN41_1 0x09e82503#define AFE_CONN42_1 0x09ec2504#define AFE_I2S_CON4 0x09f82505#define AFE_CONN60 0x0a642506#define AFE_CONN61 0x0a682507#define AFE_CONN62 0x0a6c2508#define AFE_CONN63 0x0a702509#define AFE_CONN64 0x0a742510#define AFE_CONN65 0x0a782511#define AFE_CONN66 0x0a7c2512#define AFE_ADDA6_TOP_CON0 0x0a802513#define AFE_ADDA6_UL_SRC_CON0 0x0a842514#define AFE_ADDA6_UL_SRC_CON1 0x0a882515#define AFE_ADDA6_SRC_DEBUG 0x0a8c2516#define AFE_ADDA6_SRC_DEBUG_MON0 0x0a902517#define AFE_ADDA6_ULCF_CFG_02_01 0x0aa02518#define AFE_ADDA6_ULCF_CFG_04_03 0x0aa42519#define AFE_ADDA6_ULCF_CFG_06_05 0x0aa82520#define AFE_ADDA6_ULCF_CFG_08_07 0x0aac2521#define AFE_ADDA6_ULCF_CFG_10_09 0x0ab02522#define AFE_ADDA6_ULCF_CFG_12_11 0x0ab42523#define AFE_ADDA6_ULCF_CFG_14_13 0x0ab82524#define AFE_ADDA6_ULCF_CFG_16_15 0x0abc2525#define AFE_ADDA6_ULCF_CFG_18_17 0x0ac02526#define AFE_ADDA6_ULCF_CFG_20_19 0x0ac42527#define AFE_ADDA6_ULCF_CFG_22_21 0x0ac82528#define AFE_ADDA6_ULCF_CFG_24_23 0x0acc2529#define AFE_ADDA6_ULCF_CFG_26_25 0x0ad02530#define AFE_ADDA6_ULCF_CFG_28_27 0x0ad42531#define AFE_ADDA6_ULCF_CFG_30_29 0x0ad82532#define AFE_ADD6A_UL_SRC_MON0 0x0ae42533#define AFE_ADDA6_UL_SRC_MON1 0x0ae82534#define AFE_CONN43 0x0af82535#define AFE_CONN43_1 0x0afc2536#define AFE_MOD_DAI_CON0 0x0b002537#define AFE_MOD_DAI_BASE_MSB 0x0b042538#define AFE_MOD_DAI_BASE 0x0b082539#define AFE_MOD_DAI_CUR_MSB 0x0b0c2540#define AFE_MOD_DAI_CUR 0x0b102541#define AFE_MOD_DAI_END_MSB 0x0b142542#define AFE_MOD_DAI_END 0x0b182543#define AFE_AWB_RCH_MON 0x0b702544#define AFE_AWB_LCH_MON 0x0b742545#define AFE_VUL_RCH_MON 0x0b782546#define AFE_VUL_LCH_MON 0x0b7c2547#define AFE_VUL12_RCH_MON 0x0b802548#define AFE_VUL12_LCH_MON 0x0b842549#define AFE_VUL2_RCH_MON 0x0b882550#define AFE_VUL2_LCH_MON 0x0b8c2551#define AFE_DAI_DATA_MON 0x0b902552#define AFE_MOD_DAI_DATA_MON 0x0b942553#define AFE_DAI2_DATA_MON 0x0b982554#define AFE_AWB2_RCH_MON 0x0b9c2555#define AFE_AWB2_LCH_MON 0x0ba02556#define AFE_VUL3_RCH_MON 0x0ba42557#define AFE_VUL3_LCH_MON 0x0ba82558#define AFE_VUL4_RCH_MON 0x0bac2559#define AFE_VUL4_LCH_MON 0x0bb02560#define AFE_VUL5_RCH_MON 0x0bb42561#define AFE_VUL5_LCH_MON 0x0bb82562#define AFE_VUL6_RCH_MON 0x0bbc2563#define AFE_VUL6_LCH_MON 0x0bc02564#define AFE_DL1_RCH_MON 0x0bc42565#define AFE_DL1_LCH_MON 0x0bc82566#define AFE_DL2_RCH_MON 0x0bcc2567#define AFE_DL2_LCH_MON 0x0bd02568#define AFE_DL12_RCH1_MON 0x0bd42569#define AFE_DL12_LCH1_MON 0x0bd82570#define AFE_DL12_RCH2_MON 0x0bdc2571#define AFE_DL12_LCH2_MON 0x0be02572#define AFE_DL3_RCH_MON 0x0be42573#define AFE_DL3_LCH_MON 0x0be82574#define AFE_DL4_RCH_MON 0x0bec2575#define AFE_DL4_LCH_MON 0x0bf02576#define AFE_DL5_RCH_MON 0x0bf42577#define AFE_DL5_LCH_MON 0x0bf82578#define AFE_DL6_RCH_MON 0x0bfc2579#define AFE_DL6_LCH_MON 0x0c002580#define AFE_DL7_RCH_MON 0x0c042581#define AFE_DL7_LCH_MON 0x0c082582#define AFE_DL8_RCH_MON 0x0c0c2583#define AFE_DL8_LCH_MON 0x0c102584#define AFE_VUL5_CON0 0x0c142585#define AFE_VUL5_BASE_MSB 0x0c182586#define AFE_VUL5_BASE 0x0c1c2587#define AFE_VUL5_CUR_MSB 0x0c202588#define AFE_VUL5_CUR 0x0c242589#define AFE_VUL5_END_MSB 0x0c282590#define AFE_VUL5_END 0x0c2c2591#define AFE_VUL6_CON0 0x0c302592#define AFE_VUL6_BASE_MSB 0x0c342593#define AFE_VUL6_BASE 0x0c382594#define AFE_VUL6_CUR_MSB 0x0c3c2595#define AFE_VUL6_CUR 0x0c402596#define AFE_VUL6_END_MSB 0x0c442597#define AFE_VUL6_END 0x0c482598#define AFE_ADDA_DL_SDM_DCCOMP_CON 0x0c502599#define AFE_ADDA_DL_SDM_TEST 0x0c542600#define AFE_ADDA_DL_DC_COMP_CFG0 0x0c582601#define AFE_ADDA_DL_DC_COMP_CFG1 0x0c5c2602#define AFE_ADDA_DL_SDM_FIFO_MON 0x0c602603#define AFE_ADDA_DL_SRC_LCH_MON 0x0c642604#define AFE_ADDA_DL_SRC_RCH_MON 0x0c682605#define AFE_ADDA_DL_SDM_OUT_MON 0x0c6c2606#define AFE_ADDA_DL_SDM_DITHER_CON 0x0c702607#define AFE_ADDA_DL_SDM_AUTO_RESET_CON 0x0c742608#define AFE_CONNSYS_I2S_CON 0x0c782609#define AFE_CONNSYS_I2S_MON 0x0c7c2610#define AFE_ASRC_2CH_CON0 0x0c802611#define AFE_ASRC_2CH_CON1 0x0c842612#define AFE_ASRC_2CH_CON2 0x0c882613#define AFE_ASRC_2CH_CON3 0x0c8c2614#define AFE_ASRC_2CH_CON4 0x0c902615#define AFE_ASRC_2CH_CON5 0x0c942616#define AFE_ASRC_2CH_CON6 0x0c982617#define AFE_ASRC_2CH_CON7 0x0c9c2618#define AFE_ASRC_2CH_CON8 0x0ca02619#define AFE_ASRC_2CH_CON9 0x0ca42620#define AFE_ASRC_2CH_CON10 0x0ca82621#define AFE_ASRC_2CH_CON12 0x0cb02622#define AFE_ASRC_2CH_CON13 0x0cb42623#define AFE_ADDA6_IIR_COEF_02_01 0x0ce02624#define AFE_ADDA6_IIR_COEF_04_03 0x0ce42625#define AFE_ADDA6_IIR_COEF_06_05 0x0ce82626#define AFE_ADDA6_IIR_COEF_08_07 0x0cec2627#define AFE_ADDA6_IIR_COEF_10_09 0x0cf02628#define AFE_CONN67 0x0cf42629#define AFE_CONN68 0x0cf82630#define AFE_CONN69 0x0cfc2631#define AFE_SE_PROT_SIDEBAND 0x0d382632#define AFE_SE_DOMAIN_SIDEBAND0 0x0d3c2633#define AFE_ADDA_PREDIS_CON2 0x0d402634#define AFE_ADDA_PREDIS_CON3 0x0d442635#define AFE_SE_DOMAIN_SIDEBAND1 0x0d542636#define AFE_SE_DOMAIN_SIDEBAND2 0x0d582637#define AFE_SE_DOMAIN_SIDEBAND3 0x0d5c2638#define AFE_CONN44 0x0d702639#define AFE_CONN45 0x0d742640#define AFE_CONN46 0x0d782641#define AFE_CONN47 0x0d7c2642#define AFE_CONN44_1 0x0d802643#define AFE_CONN45_1 0x0d842644#define AFE_CONN46_1 0x0d882645#define AFE_CONN47_1 0x0d8c2646#define AFE_HD_ENGEN_ENABLE 0x0dd02647#define AFE_ADDA_DL_NLE_FIFO_MON 0x0dfc2648#define AFE_ADDA_MTKAIF_CFG0 0x0e002649#define AFE_CONN67_1 0x0e042650#define AFE_CONN68_1 0x0e082651#define AFE_CONN69_1 0x0e0c2652#define AFE_ADDA_MTKAIF_SYNCWORD_CFG 0x0e142653#define AFE_ADDA_MTKAIF_RX_CFG0 0x0e202654#define AFE_ADDA_MTKAIF_RX_CFG1 0x0e242655#define AFE_ADDA_MTKAIF_RX_CFG2 0x0e282656#define AFE_ADDA_MTKAIF_MON0 0x0e342657#define AFE_ADDA_MTKAIF_MON1 0x0e382658#define AFE_AUD_PAD_TOP 0x0e402659#define AFE_DL_NLE_R_CFG0 0x0e442660#define AFE_DL_NLE_R_CFG1 0x0e482661#define AFE_DL_NLE_L_CFG0 0x0e4c2662#define AFE_DL_NLE_L_CFG1 0x0e502663#define AFE_DL_NLE_R_MON0 0x0e542664#define AFE_DL_NLE_R_MON1 0x0e582665#define AFE_DL_NLE_R_MON2 0x0e5c2666#define AFE_DL_NLE_L_MON0 0x0e602667#define AFE_DL_NLE_L_MON1 0x0e642668#define AFE_DL_NLE_L_MON2 0x0e682669#define AFE_DL_NLE_GAIN_CFG0 0x0e6c2670#define AFE_ADDA6_MTKAIF_CFG0 0x0e702671#define AFE_ADDA6_MTKAIF_RX_CFG0 0x0e742672#define AFE_ADDA6_MTKAIF_RX_CFG1 0x0e782673#define AFE_ADDA6_MTKAIF_RX_CFG2 0x0e7c2674#define AFE_GENERAL1_ASRC_2CH_CON0 0x0e802675#define AFE_GENERAL1_ASRC_2CH_CON1 0x0e842676#define AFE_GENERAL1_ASRC_2CH_CON2 0x0e882677#define AFE_GENERAL1_ASRC_2CH_CON3 0x0e8c2678#define AFE_GENERAL1_ASRC_2CH_CON4 0x0e902679#define AFE_GENERAL1_ASRC_2CH_CON5 0x0e942680#define AFE_GENERAL1_ASRC_2CH_CON6 0x0e982681#define AFE_GENERAL1_ASRC_2CH_CON7 0x0e9c2682#define AFE_GENERAL1_ASRC_2CH_CON8 0x0ea02683#define AFE_GENERAL1_ASRC_2CH_CON9 0x0ea42684#define AFE_GENERAL1_ASRC_2CH_CON10 0x0ea82685#define AFE_GENERAL1_ASRC_2CH_CON12 0x0eb02686#define AFE_GENERAL1_ASRC_2CH_CON13 0x0eb42687#define GENERAL_ASRC_MODE 0x0eb82688#define GENERAL_ASRC_EN_ON 0x0ebc2689#define AFE_CONN48 0x0ec02690#define AFE_CONN49 0x0ec42691#define AFE_CONN50 0x0ec82692#define AFE_CONN51 0x0ecc2693#define AFE_CONN52 0x0ed02694#define AFE_CONN53 0x0ed42695#define AFE_CONN54 0x0ed82696#define AFE_CONN55 0x0edc2697#define AFE_CONN48_1 0x0ee02698#define AFE_CONN49_1 0x0ee42699#define AFE_CONN50_1 0x0ee82700#define AFE_CONN51_1 0x0eec2701#define AFE_CONN52_1 0x0ef02702#define AFE_CONN53_1 0x0ef42703#define AFE_CONN54_1 0x0ef82704#define AFE_CONN55_1 0x0efc2705#define AFE_GENERAL2_ASRC_2CH_CON0 0x0f002706#define AFE_GENERAL2_ASRC_2CH_CON1 0x0f042707#define AFE_GENERAL2_ASRC_2CH_CON2 0x0f082708#define AFE_GENERAL2_ASRC_2CH_CON3 0x0f0c2709#define AFE_GENERAL2_ASRC_2CH_CON4 0x0f102710#define AFE_GENERAL2_ASRC_2CH_CON5 0x0f142711#define AFE_GENERAL2_ASRC_2CH_CON6 0x0f182712#define AFE_GENERAL2_ASRC_2CH_CON7 0x0f1c2713#define AFE_GENERAL2_ASRC_2CH_CON8 0x0f202714#define AFE_GENERAL2_ASRC_2CH_CON9 0x0f242715#define AFE_GENERAL2_ASRC_2CH_CON10 0x0f282716#define AFE_GENERAL2_ASRC_2CH_CON12 0x0f302717#define AFE_GENERAL2_ASRC_2CH_CON13 0x0f342718#define AFE_DL5_CON0 0x0f4c2719#define AFE_DL5_BASE_MSB 0x0f502720#define AFE_DL5_BASE 0x0f542721#define AFE_DL5_CUR_MSB 0x0f582722#define AFE_DL5_CUR 0x0f5c2723#define AFE_DL5_END_MSB 0x0f602724#define AFE_DL5_END 0x0f642725#define AFE_DL6_CON0 0x0f682726#define AFE_DL6_BASE_MSB 0x0f6c2727#define AFE_DL6_BASE 0x0f702728#define AFE_DL6_CUR_MSB 0x0f742729#define AFE_DL6_CUR 0x0f782730#define AFE_DL6_END_MSB 0x0f7c2731#define AFE_DL6_END 0x0f802732#define AFE_DL7_CON0 0x0f842733#define AFE_DL7_BASE_MSB 0x0f882734#define AFE_DL7_BASE 0x0f8c2735#define AFE_DL7_CUR_MSB 0x0f902736#define AFE_DL7_CUR 0x0f942737#define AFE_DL7_END_MSB 0x0f982738#define AFE_DL7_END 0x0f9c2739#define AFE_DL8_CON0 0x0fa02740#define AFE_DL8_BASE_MSB 0x0fa42741#define AFE_DL8_BASE 0x0fa82742#define AFE_DL8_CUR_MSB 0x0fac2743#define AFE_DL8_CUR 0x0fb02744#define AFE_DL8_END_MSB 0x0fb42745#define AFE_DL8_END 0x0fb82746#define AFE_SE_SECURE_CON 0x10042747#define AFE_PROT_SIDEBAND_MON 0x10082748#define AFE_DOMAIN_SIDEBAND0_MON 0x100c2749#define AFE_DOMAIN_SIDEBAND1_MON 0x10102750#define AFE_DOMAIN_SIDEBAND2_MON 0x10142751#define AFE_DOMAIN_SIDEBAND3_MON 0x10182752#define AFE_SECURE_MASK_CONN0 0x10202753#define AFE_SECURE_MASK_CONN1 0x10242754#define AFE_SECURE_MASK_CONN2 0x10282755#define AFE_SECURE_MASK_CONN3 0x102c2756#define AFE_SECURE_MASK_CONN4 0x10302757#define AFE_SECURE_MASK_CONN5 0x10342758#define AFE_SECURE_MASK_CONN6 0x10382759#define AFE_SECURE_MASK_CONN7 0x103c2760#define AFE_SECURE_MASK_CONN8 0x10402761#define AFE_SECURE_MASK_CONN9 0x10442762#define AFE_SECURE_MASK_CONN10 0x10482763#define AFE_SECURE_MASK_CONN11 0x104c2764#define AFE_SECURE_MASK_CONN12 0x10502765#define AFE_SECURE_MASK_CONN13 0x10542766#define AFE_SECURE_MASK_CONN14 0x10582767#define AFE_SECURE_MASK_CONN15 0x105c2768#define AFE_SECURE_MASK_CONN16 0x10602769#define AFE_SECURE_MASK_CONN17 0x10642770#define AFE_SECURE_MASK_CONN18 0x10682771#define AFE_SECURE_MASK_CONN19 0x106c2772#define AFE_SECURE_MASK_CONN20 0x10702773#define AFE_SECURE_MASK_CONN21 0x10742774#define AFE_SECURE_MASK_CONN22 0x10782775#define AFE_SECURE_MASK_CONN23 0x107c2776#define AFE_SECURE_MASK_CONN24 0x10802777#define AFE_SECURE_MASK_CONN25 0x10842778#define AFE_SECURE_MASK_CONN26 0x10882779#define AFE_SECURE_MASK_CONN27 0x108c2780#define AFE_SECURE_MASK_CONN28 0x10902781#define AFE_SECURE_MASK_CONN29 0x10942782#define AFE_SECURE_MASK_CONN30 0x10982783#define AFE_SECURE_MASK_CONN31 0x109c2784#define AFE_SECURE_MASK_CONN32 0x10a02785#define AFE_SECURE_MASK_CONN33 0x10a42786#define AFE_SECURE_MASK_CONN34 0x10a82787#define AFE_SECURE_MASK_CONN35 0x10ac2788#define AFE_SECURE_MASK_CONN36 0x10b02789#define AFE_SECURE_MASK_CONN37 0x10b42790#define AFE_SECURE_MASK_CONN38 0x10b82791#define AFE_SECURE_MASK_CONN39 0x10bc2792#define AFE_SECURE_MASK_CONN40 0x10c02793#define AFE_SECURE_MASK_CONN41 0x10c42794#define AFE_SECURE_MASK_CONN42 0x10c82795#define AFE_SECURE_MASK_CONN43 0x10cc2796#define AFE_SECURE_MASK_CONN44 0x10d02797#define AFE_SECURE_MASK_CONN45 0x10d42798#define AFE_SECURE_MASK_CONN46 0x10d82799#define AFE_SECURE_MASK_CONN47 0x10dc2800#define AFE_SECURE_MASK_CONN48 0x10e02801#define AFE_SECURE_MASK_CONN49 0x10e42802#define AFE_SECURE_MASK_CONN50 0x10e82803#define AFE_SECURE_MASK_CONN51 0x10ec2804#define AFE_SECURE_MASK_CONN52 0x10f02805#define AFE_SECURE_MASK_CONN53 0x10f42806#define AFE_SECURE_MASK_CONN54 0x10f82807#define AFE_SECURE_MASK_CONN55 0x10fc2808#define AFE_SECURE_MASK_CONN56 0x11002809#define AFE_SECURE_MASK_CONN57 0x11042810#define AFE_SECURE_MASK_CONN0_1 0x11082811#define AFE_SECURE_MASK_CONN1_1 0x110c2812#define AFE_SECURE_MASK_CONN2_1 0x11102813#define AFE_SECURE_MASK_CONN3_1 0x11142814#define AFE_SECURE_MASK_CONN4_1 0x11182815#define AFE_SECURE_MASK_CONN5_1 0x111c2816#define AFE_SECURE_MASK_CONN6_1 0x11202817#define AFE_SECURE_MASK_CONN7_1 0x11242818#define AFE_SECURE_MASK_CONN8_1 0x11282819#define AFE_SECURE_MASK_CONN9_1 0x112c2820#define AFE_SECURE_MASK_CONN10_1 0x11302821#define AFE_SECURE_MASK_CONN11_1 0x11342822#define AFE_SECURE_MASK_CONN12_1 0x11382823#define AFE_SECURE_MASK_CONN13_1 0x113c2824#define AFE_SECURE_MASK_CONN14_1 0x11402825#define AFE_SECURE_MASK_CONN15_1 0x11442826#define AFE_SECURE_MASK_CONN16_1 0x11482827#define AFE_SECURE_MASK_CONN17_1 0x114c2828#define AFE_SECURE_MASK_CONN18_1 0x11502829#define AFE_SECURE_MASK_CONN19_1 0x11542830#define AFE_SECURE_MASK_CONN20_1 0x11582831#define AFE_SECURE_MASK_CONN21_1 0x115c2832#define AFE_SECURE_MASK_CONN22_1 0x11602833#define AFE_SECURE_MASK_CONN23_1 0x11642834#define AFE_SECURE_MASK_CONN24_1 0x11682835#define AFE_SECURE_MASK_CONN25_1 0x116c2836#define AFE_SECURE_MASK_CONN26_1 0x11702837#define AFE_SECURE_MASK_CONN27_1 0x11742838#define AFE_SECURE_MASK_CONN28_1 0x11782839#define AFE_SECURE_MASK_CONN29_1 0x117c2840#define AFE_SECURE_MASK_CONN30_1 0x11802841#define AFE_SECURE_MASK_CONN31_1 0x11842842#define AFE_SECURE_MASK_CONN32_1 0x11882843#define AFE_SECURE_MASK_CONN33_1 0x118c2844#define AFE_SECURE_MASK_CONN34_1 0x11902845#define AFE_SECURE_MASK_CONN35_1 0x11942846#define AFE_SECURE_MASK_CONN36_1 0x11982847#define AFE_SECURE_MASK_CONN37_1 0x119c2848#define AFE_SECURE_MASK_CONN38_1 0x11a02849#define AFE_SECURE_MASK_CONN39_1 0x11a42850#define AFE_SECURE_MASK_CONN40_1 0x11a82851#define AFE_SECURE_MASK_CONN41_1 0x11ac2852#define AFE_SECURE_MASK_CONN42_1 0x11b02853#define AFE_SECURE_MASK_CONN43_1 0x11b42854#define AFE_SECURE_MASK_CONN44_1 0x11b82855#define AFE_SECURE_MASK_CONN45_1 0x11bc2856#define AFE_SECURE_MASK_CONN46_1 0x11c02857#define AFE_SECURE_MASK_CONN47_1 0x11c42858#define AFE_SECURE_MASK_CONN48_1 0x11c82859#define AFE_SECURE_MASK_CONN49_1 0x11cc2860#define AFE_SECURE_MASK_CONN50_1 0x11d02861#define AFE_SECURE_MASK_CONN51_1 0x11d42862#define AFE_SECURE_MASK_CONN52_1 0x11d82863#define AFE_SECURE_MASK_CONN53_1 0x11dc2864#define AFE_SECURE_MASK_CONN54_1 0x11e02865#define AFE_SECURE_MASK_CONN55_1 0x11e42866#define AFE_SECURE_MASK_CONN56_1 0x11e82867#define AFE_CONN60_1 0x11f02868#define AFE_CONN61_1 0x11f42869#define AFE_CONN62_1 0x11f82870#define AFE_CONN63_1 0x11fc2871#define AFE_CONN64_1 0x12202872#define AFE_CONN65_1 0x12242873#define AFE_CONN66_1 0x12282874#define FPGA_CFG4 0x12302875#define FPGA_CFG5 0x12342876#define FPGA_CFG6 0x12382877#define FPGA_CFG7 0x123c2878#define FPGA_CFG8 0x12402879#define FPGA_CFG9 0x12442880#define FPGA_CFG10 0x12482881#define FPGA_CFG11 0x124c2882#define FPGA_CFG12 0x12502883#define FPGA_CFG13 0x12542884#define ETDM_IN1_CON0 0x14302885#define ETDM_IN1_CON1 0x14342886#define ETDM_IN1_CON2 0x14382887#define ETDM_IN1_CON3 0x143c2888#define ETDM_IN1_CON4 0x14402889#define ETDM_IN1_CON5 0x14442890#define ETDM_IN1_CON6 0x14482891#define ETDM_IN1_CON7 0x144c2892#define ETDM_IN1_CON8 0x14502893#define ETDM_OUT1_CON0 0x14542894#define ETDM_OUT1_CON1 0x14582895#define ETDM_OUT1_CON2 0x145c2896#define ETDM_OUT1_CON3 0x14602897#define ETDM_OUT1_CON4 0x14642898#define ETDM_OUT1_CON5 0x14682899#define ETDM_OUT1_CON6 0x146c2900#define ETDM_OUT1_CON7 0x14702901#define ETDM_OUT1_CON8 0x14742902#define ETDM_IN1_MON 0x14782903#define ETDM_OUT1_MON 0x147c2904#define ETDM_0_3_COWORK_CON0 0x18b02905#define ETDM_0_3_COWORK_CON1 0x18b42906#define ETDM_0_3_COWORK_CON3 0x18bc2907 2908#define AFE_MAX_REGISTER ETDM_0_3_COWORK_CON32909 2910#define AFE_IRQ_STATUS_BITS 0x87FFFFFF2911#define AFE_IRQ_CNT_SHIFT 02912#define AFE_IRQ_CNT_MASK 0x3ffff2913#endif2914