748 lines · c
1// SPDX-License-Identifier: GPL-2.02/*3 * mt8188-afe-clk.c -- MediaTek 8188 afe clock ctrl4 *5 * Copyright (c) 2022 MediaTek Inc.6 * Author: Bicycle Tsai <bicycle.tsai@mediatek.com>7 * Trevor Wu <trevor.wu@mediatek.com>8 * Chun-Chia Chiu <chun-chia.chiu@mediatek.com>9 */10 11#include <linux/clk.h>12 13#include "mt8188-afe-common.h"14#include "mt8188-afe-clk.h"15#include "mt8188-audsys-clk.h"16#include "mt8188-reg.h"17 18static const char *aud_clks[MT8188_CLK_NUM] = {19 /* xtal */20 [MT8188_CLK_XTAL_26M] = "clk26m",21 22 /* pll */23 [MT8188_CLK_APMIXED_APLL1] = "apll1",24 [MT8188_CLK_APMIXED_APLL2] = "apll2",25 26 /* divider */27 [MT8188_CLK_TOP_APLL1_D4] = "apll1_d4",28 [MT8188_CLK_TOP_APLL2_D4] = "apll2_d4",29 [MT8188_CLK_TOP_APLL12_DIV0] = "apll12_div0",30 [MT8188_CLK_TOP_APLL12_DIV1] = "apll12_div1",31 [MT8188_CLK_TOP_APLL12_DIV2] = "apll12_div2",32 [MT8188_CLK_TOP_APLL12_DIV3] = "apll12_div3",33 [MT8188_CLK_TOP_APLL12_DIV4] = "apll12_div4",34 [MT8188_CLK_TOP_APLL12_DIV9] = "apll12_div9",35 36 /* mux */37 [MT8188_CLK_TOP_A1SYS_HP_SEL] = "top_a1sys_hp",38 [MT8188_CLK_TOP_A2SYS_SEL] = "top_a2sys",39 [MT8188_CLK_TOP_AUD_IEC_SEL] = "top_aud_iec",40 [MT8188_CLK_TOP_AUD_INTBUS_SEL] = "top_aud_intbus",41 [MT8188_CLK_TOP_AUDIO_H_SEL] = "top_audio_h",42 [MT8188_CLK_TOP_AUDIO_LOCAL_BUS_SEL] = "top_audio_local_bus",43 [MT8188_CLK_TOP_DPTX_M_SEL] = "top_dptx",44 [MT8188_CLK_TOP_I2SO1_M_SEL] = "top_i2so1",45 [MT8188_CLK_TOP_I2SO2_M_SEL] = "top_i2so2",46 [MT8188_CLK_TOP_I2SI1_M_SEL] = "top_i2si1",47 [MT8188_CLK_TOP_I2SI2_M_SEL] = "top_i2si2",48 49 /* clock gate */50 [MT8188_CLK_ADSP_AUDIO_26M] = "adsp_audio_26m",51 /* afe clock gate */52 [MT8188_CLK_AUD_AFE] = "aud_afe",53 [MT8188_CLK_AUD_APLL1_TUNER] = "aud_apll1_tuner",54 [MT8188_CLK_AUD_APLL2_TUNER] = "aud_apll2_tuner",55 [MT8188_CLK_AUD_APLL] = "aud_apll",56 [MT8188_CLK_AUD_APLL2] = "aud_apll2",57 [MT8188_CLK_AUD_DAC] = "aud_dac",58 [MT8188_CLK_AUD_ADC] = "aud_adc",59 [MT8188_CLK_AUD_DAC_HIRES] = "aud_dac_hires",60 [MT8188_CLK_AUD_A1SYS_HP] = "aud_a1sys_hp",61 [MT8188_CLK_AUD_ADC_HIRES] = "aud_adc_hires",62 [MT8188_CLK_AUD_I2SIN] = "aud_i2sin",63 [MT8188_CLK_AUD_TDM_IN] = "aud_tdm_in",64 [MT8188_CLK_AUD_I2S_OUT] = "aud_i2s_out",65 [MT8188_CLK_AUD_TDM_OUT] = "aud_tdm_out",66 [MT8188_CLK_AUD_HDMI_OUT] = "aud_hdmi_out",67 [MT8188_CLK_AUD_ASRC11] = "aud_asrc11",68 [MT8188_CLK_AUD_ASRC12] = "aud_asrc12",69 [MT8188_CLK_AUD_A1SYS] = "aud_a1sys",70 [MT8188_CLK_AUD_A2SYS] = "aud_a2sys",71 [MT8188_CLK_AUD_PCMIF] = "aud_pcmif",72 [MT8188_CLK_AUD_MEMIF_UL1] = "aud_memif_ul1",73 [MT8188_CLK_AUD_MEMIF_UL2] = "aud_memif_ul2",74 [MT8188_CLK_AUD_MEMIF_UL3] = "aud_memif_ul3",75 [MT8188_CLK_AUD_MEMIF_UL4] = "aud_memif_ul4",76 [MT8188_CLK_AUD_MEMIF_UL5] = "aud_memif_ul5",77 [MT8188_CLK_AUD_MEMIF_UL6] = "aud_memif_ul6",78 [MT8188_CLK_AUD_MEMIF_UL8] = "aud_memif_ul8",79 [MT8188_CLK_AUD_MEMIF_UL9] = "aud_memif_ul9",80 [MT8188_CLK_AUD_MEMIF_UL10] = "aud_memif_ul10",81 [MT8188_CLK_AUD_MEMIF_DL2] = "aud_memif_dl2",82 [MT8188_CLK_AUD_MEMIF_DL3] = "aud_memif_dl3",83 [MT8188_CLK_AUD_MEMIF_DL6] = "aud_memif_dl6",84 [MT8188_CLK_AUD_MEMIF_DL7] = "aud_memif_dl7",85 [MT8188_CLK_AUD_MEMIF_DL8] = "aud_memif_dl8",86 [MT8188_CLK_AUD_MEMIF_DL10] = "aud_memif_dl10",87 [MT8188_CLK_AUD_MEMIF_DL11] = "aud_memif_dl11",88};89 90struct mt8188_afe_tuner_cfg {91 unsigned int id;92 int apll_div_reg;93 unsigned int apll_div_shift;94 unsigned int apll_div_maskbit;95 unsigned int apll_div_default;96 int ref_ck_sel_reg;97 unsigned int ref_ck_sel_shift;98 unsigned int ref_ck_sel_maskbit;99 unsigned int ref_ck_sel_default;100 int tuner_en_reg;101 unsigned int tuner_en_shift;102 unsigned int tuner_en_maskbit;103 int upper_bound_reg;104 unsigned int upper_bound_shift;105 unsigned int upper_bound_maskbit;106 unsigned int upper_bound_default;107 spinlock_t ctrl_lock; /* lock for apll tuner ctrl*/108 int ref_cnt;109};110 111static struct mt8188_afe_tuner_cfg112 mt8188_afe_tuner_cfgs[MT8188_AUD_PLL_NUM] = {113 [MT8188_AUD_PLL1] = {114 .id = MT8188_AUD_PLL1,115 .apll_div_reg = AFE_APLL_TUNER_CFG,116 .apll_div_shift = 4,117 .apll_div_maskbit = 0xf,118 .apll_div_default = 0x7,119 .ref_ck_sel_reg = AFE_APLL_TUNER_CFG,120 .ref_ck_sel_shift = 1,121 .ref_ck_sel_maskbit = 0x3,122 .ref_ck_sel_default = 0x2,123 .tuner_en_reg = AFE_APLL_TUNER_CFG,124 .tuner_en_shift = 0,125 .tuner_en_maskbit = 0x1,126 .upper_bound_reg = AFE_APLL_TUNER_CFG,127 .upper_bound_shift = 8,128 .upper_bound_maskbit = 0xff,129 .upper_bound_default = 0x3,130 },131 [MT8188_AUD_PLL2] = {132 .id = MT8188_AUD_PLL2,133 .apll_div_reg = AFE_APLL_TUNER_CFG1,134 .apll_div_shift = 4,135 .apll_div_maskbit = 0xf,136 .apll_div_default = 0x7,137 .ref_ck_sel_reg = AFE_APLL_TUNER_CFG1,138 .ref_ck_sel_shift = 1,139 .ref_ck_sel_maskbit = 0x3,140 .ref_ck_sel_default = 0x1,141 .tuner_en_reg = AFE_APLL_TUNER_CFG1,142 .tuner_en_shift = 0,143 .tuner_en_maskbit = 0x1,144 .upper_bound_reg = AFE_APLL_TUNER_CFG1,145 .upper_bound_shift = 8,146 .upper_bound_maskbit = 0xff,147 .upper_bound_default = 0x3,148 },149 [MT8188_AUD_PLL3] = {150 .id = MT8188_AUD_PLL3,151 .apll_div_reg = AFE_EARC_APLL_TUNER_CFG,152 .apll_div_shift = 4,153 .apll_div_maskbit = 0x3f,154 .apll_div_default = 0x3,155 .ref_ck_sel_reg = AFE_EARC_APLL_TUNER_CFG,156 .ref_ck_sel_shift = 24,157 .ref_ck_sel_maskbit = 0x3,158 .ref_ck_sel_default = 0x0,159 .tuner_en_reg = AFE_EARC_APLL_TUNER_CFG,160 .tuner_en_shift = 0,161 .tuner_en_maskbit = 0x1,162 .upper_bound_reg = AFE_EARC_APLL_TUNER_CFG,163 .upper_bound_shift = 12,164 .upper_bound_maskbit = 0xff,165 .upper_bound_default = 0x4,166 },167 [MT8188_AUD_PLL4] = {168 .id = MT8188_AUD_PLL4,169 .apll_div_reg = AFE_SPDIFIN_APLL_TUNER_CFG,170 .apll_div_shift = 4,171 .apll_div_maskbit = 0x3f,172 .apll_div_default = 0x7,173 .ref_ck_sel_reg = AFE_SPDIFIN_APLL_TUNER_CFG1,174 .ref_ck_sel_shift = 8,175 .ref_ck_sel_maskbit = 0x1,176 .ref_ck_sel_default = 0,177 .tuner_en_reg = AFE_SPDIFIN_APLL_TUNER_CFG,178 .tuner_en_shift = 0,179 .tuner_en_maskbit = 0x1,180 .upper_bound_reg = AFE_SPDIFIN_APLL_TUNER_CFG,181 .upper_bound_shift = 12,182 .upper_bound_maskbit = 0xff,183 .upper_bound_default = 0x4,184 },185 [MT8188_AUD_PLL5] = {186 .id = MT8188_AUD_PLL5,187 .apll_div_reg = AFE_LINEIN_APLL_TUNER_CFG,188 .apll_div_shift = 4,189 .apll_div_maskbit = 0x3f,190 .apll_div_default = 0x3,191 .ref_ck_sel_reg = AFE_LINEIN_APLL_TUNER_CFG,192 .ref_ck_sel_shift = 24,193 .ref_ck_sel_maskbit = 0x1,194 .ref_ck_sel_default = 0,195 .tuner_en_reg = AFE_LINEIN_APLL_TUNER_CFG,196 .tuner_en_shift = 0,197 .tuner_en_maskbit = 0x1,198 .upper_bound_reg = AFE_LINEIN_APLL_TUNER_CFG,199 .upper_bound_shift = 12,200 .upper_bound_maskbit = 0xff,201 .upper_bound_default = 0x4,202 },203};204 205static struct mt8188_afe_tuner_cfg *mt8188_afe_found_apll_tuner(unsigned int id)206{207 if (id >= MT8188_AUD_PLL_NUM)208 return NULL;209 210 return &mt8188_afe_tuner_cfgs[id];211}212 213static int mt8188_afe_init_apll_tuner(unsigned int id)214{215 struct mt8188_afe_tuner_cfg *cfg = mt8188_afe_found_apll_tuner(id);216 217 if (!cfg)218 return -EINVAL;219 220 cfg->ref_cnt = 0;221 spin_lock_init(&cfg->ctrl_lock);222 223 return 0;224}225 226static int mt8188_afe_setup_apll_tuner(struct mtk_base_afe *afe, unsigned int id)227{228 const struct mt8188_afe_tuner_cfg *cfg = mt8188_afe_found_apll_tuner(id);229 230 if (!cfg)231 return -EINVAL;232 233 regmap_update_bits(afe->regmap,234 cfg->apll_div_reg,235 cfg->apll_div_maskbit << cfg->apll_div_shift,236 cfg->apll_div_default << cfg->apll_div_shift);237 238 regmap_update_bits(afe->regmap,239 cfg->ref_ck_sel_reg,240 cfg->ref_ck_sel_maskbit << cfg->ref_ck_sel_shift,241 cfg->ref_ck_sel_default << cfg->ref_ck_sel_shift);242 243 regmap_update_bits(afe->regmap,244 cfg->upper_bound_reg,245 cfg->upper_bound_maskbit << cfg->upper_bound_shift,246 cfg->upper_bound_default << cfg->upper_bound_shift);247 248 return 0;249}250 251static int mt8188_afe_enable_tuner_clk(struct mtk_base_afe *afe,252 unsigned int id)253{254 struct mt8188_afe_private *afe_priv = afe->platform_priv;255 256 switch (id) {257 case MT8188_AUD_PLL1:258 mt8188_afe_enable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_APLL]);259 mt8188_afe_enable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_APLL1_TUNER]);260 break;261 case MT8188_AUD_PLL2:262 mt8188_afe_enable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_APLL2]);263 mt8188_afe_enable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_APLL2_TUNER]);264 break;265 default:266 return -EINVAL;267 }268 269 return 0;270}271 272static int mt8188_afe_disable_tuner_clk(struct mtk_base_afe *afe,273 unsigned int id)274{275 struct mt8188_afe_private *afe_priv = afe->platform_priv;276 277 switch (id) {278 case MT8188_AUD_PLL1:279 mt8188_afe_disable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_APLL1_TUNER]);280 mt8188_afe_disable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_APLL]);281 break;282 case MT8188_AUD_PLL2:283 mt8188_afe_disable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_APLL2_TUNER]);284 mt8188_afe_disable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_APLL2]);285 break;286 default:287 return -EINVAL;288 }289 290 return 0;291}292 293static int mt8188_afe_enable_apll_tuner(struct mtk_base_afe *afe, unsigned int id)294{295 struct mt8188_afe_tuner_cfg *cfg = mt8188_afe_found_apll_tuner(id);296 unsigned long flags;297 int ret;298 299 if (!cfg)300 return -EINVAL;301 302 ret = mt8188_afe_setup_apll_tuner(afe, id);303 if (ret)304 return ret;305 306 ret = mt8188_afe_enable_tuner_clk(afe, id);307 if (ret)308 return ret;309 310 spin_lock_irqsave(&cfg->ctrl_lock, flags);311 312 cfg->ref_cnt++;313 if (cfg->ref_cnt == 1)314 regmap_update_bits(afe->regmap,315 cfg->tuner_en_reg,316 cfg->tuner_en_maskbit << cfg->tuner_en_shift,317 BIT(cfg->tuner_en_shift));318 319 spin_unlock_irqrestore(&cfg->ctrl_lock, flags);320 321 return 0;322}323 324static int mt8188_afe_disable_apll_tuner(struct mtk_base_afe *afe, unsigned int id)325{326 struct mt8188_afe_tuner_cfg *cfg = mt8188_afe_found_apll_tuner(id);327 unsigned long flags;328 int ret;329 330 if (!cfg)331 return -EINVAL;332 333 spin_lock_irqsave(&cfg->ctrl_lock, flags);334 335 cfg->ref_cnt--;336 if (cfg->ref_cnt == 0)337 regmap_update_bits(afe->regmap,338 cfg->tuner_en_reg,339 cfg->tuner_en_maskbit << cfg->tuner_en_shift,340 0 << cfg->tuner_en_shift);341 else if (cfg->ref_cnt < 0)342 cfg->ref_cnt = 0;343 344 spin_unlock_irqrestore(&cfg->ctrl_lock, flags);345 346 ret = mt8188_afe_disable_tuner_clk(afe, id);347 if (ret)348 return ret;349 350 return 0;351}352 353int mt8188_afe_get_mclk_source_clk_id(int sel)354{355 switch (sel) {356 case MT8188_MCK_SEL_26M:357 return MT8188_CLK_XTAL_26M;358 case MT8188_MCK_SEL_APLL1:359 return MT8188_CLK_APMIXED_APLL1;360 case MT8188_MCK_SEL_APLL2:361 return MT8188_CLK_APMIXED_APLL2;362 default:363 return -EINVAL;364 }365}366 367int mt8188_afe_get_mclk_source_rate(struct mtk_base_afe *afe, int apll)368{369 struct mt8188_afe_private *afe_priv = afe->platform_priv;370 int clk_id = mt8188_afe_get_mclk_source_clk_id(apll);371 372 if (clk_id < 0) {373 dev_dbg(afe->dev, "invalid clk id\n");374 return 0;375 }376 377 return clk_get_rate(afe_priv->clk[clk_id]);378}379 380int mt8188_afe_get_default_mclk_source_by_rate(int rate)381{382 return ((rate % 8000) == 0) ?383 MT8188_MCK_SEL_APLL1 : MT8188_MCK_SEL_APLL2;384}385 386int mt8188_get_apll_by_rate(struct mtk_base_afe *afe, int rate)387{388 return ((rate % 8000) == 0) ? MT8188_AUD_PLL1 : MT8188_AUD_PLL2;389}390 391int mt8188_get_apll_by_name(struct mtk_base_afe *afe, const char *name)392{393 if (strcmp(name, APLL1_W_NAME) == 0)394 return MT8188_AUD_PLL1;395 396 return MT8188_AUD_PLL2;397}398 399int mt8188_afe_init_clock(struct mtk_base_afe *afe)400{401 struct mt8188_afe_private *afe_priv = afe->platform_priv;402 int i, ret;403 404 ret = mt8188_audsys_clk_register(afe);405 if (ret) {406 dev_err(afe->dev, "register audsys clk fail %d\n", ret);407 return ret;408 }409 410 afe_priv->clk =411 devm_kcalloc(afe->dev, MT8188_CLK_NUM, sizeof(*afe_priv->clk),412 GFP_KERNEL);413 if (!afe_priv->clk)414 return -ENOMEM;415 416 for (i = 0; i < MT8188_CLK_NUM; i++) {417 afe_priv->clk[i] = devm_clk_get(afe->dev, aud_clks[i]);418 if (IS_ERR(afe_priv->clk[i])) {419 dev_err(afe->dev, "%s(), devm_clk_get %s fail, ret %ld\n",420 __func__, aud_clks[i],421 PTR_ERR(afe_priv->clk[i]));422 return PTR_ERR(afe_priv->clk[i]);423 }424 }425 426 /* initial tuner */427 for (i = 0; i < MT8188_AUD_PLL_NUM; i++) {428 ret = mt8188_afe_init_apll_tuner(i);429 if (ret) {430 dev_info(afe->dev, "%s(), init apll_tuner%d failed",431 __func__, (i + 1));432 return -EINVAL;433 }434 }435 436 return 0;437}438 439int mt8188_afe_enable_clk(struct mtk_base_afe *afe, struct clk *clk)440{441 int ret;442 443 if (clk) {444 ret = clk_prepare_enable(clk);445 if (ret) {446 dev_dbg(afe->dev, "%s(), failed to enable clk\n",447 __func__);448 return ret;449 }450 } else {451 dev_dbg(afe->dev, "NULL clk\n");452 }453 return 0;454}455EXPORT_SYMBOL_GPL(mt8188_afe_enable_clk);456 457void mt8188_afe_disable_clk(struct mtk_base_afe *afe, struct clk *clk)458{459 if (clk)460 clk_disable_unprepare(clk);461 else462 dev_dbg(afe->dev, "NULL clk\n");463}464EXPORT_SYMBOL_GPL(mt8188_afe_disable_clk);465 466int mt8188_afe_set_clk_rate(struct mtk_base_afe *afe, struct clk *clk,467 unsigned int rate)468{469 int ret;470 471 if (clk) {472 ret = clk_set_rate(clk, rate);473 if (ret) {474 dev_dbg(afe->dev, "%s(), failed to set clk rate\n",475 __func__);476 return ret;477 }478 }479 480 return 0;481}482 483int mt8188_afe_set_clk_parent(struct mtk_base_afe *afe, struct clk *clk,484 struct clk *parent)485{486 int ret;487 488 if (clk && parent) {489 ret = clk_set_parent(clk, parent);490 if (ret) {491 dev_dbg(afe->dev, "%s(), failed to set clk parent %d\n",492 __func__, ret);493 return ret;494 }495 }496 497 return 0;498}499 500static unsigned int get_top_cg_reg(unsigned int cg_type)501{502 switch (cg_type) {503 case MT8188_TOP_CG_A1SYS_TIMING:504 case MT8188_TOP_CG_A2SYS_TIMING:505 case MT8188_TOP_CG_26M_TIMING:506 return ASYS_TOP_CON;507 default:508 return 0;509 }510}511 512static unsigned int get_top_cg_mask(unsigned int cg_type)513{514 switch (cg_type) {515 case MT8188_TOP_CG_A1SYS_TIMING:516 return ASYS_TOP_CON_A1SYS_TIMING_ON;517 case MT8188_TOP_CG_A2SYS_TIMING:518 return ASYS_TOP_CON_A2SYS_TIMING_ON;519 case MT8188_TOP_CG_26M_TIMING:520 return ASYS_TOP_CON_26M_TIMING_ON;521 default:522 return 0;523 }524}525 526static unsigned int get_top_cg_on_val(unsigned int cg_type)527{528 switch (cg_type) {529 case MT8188_TOP_CG_A1SYS_TIMING:530 case MT8188_TOP_CG_A2SYS_TIMING:531 case MT8188_TOP_CG_26M_TIMING:532 return get_top_cg_mask(cg_type);533 default:534 return 0;535 }536}537 538static unsigned int get_top_cg_off_val(unsigned int cg_type)539{540 switch (cg_type) {541 case MT8188_TOP_CG_A1SYS_TIMING:542 case MT8188_TOP_CG_A2SYS_TIMING:543 case MT8188_TOP_CG_26M_TIMING:544 return 0;545 default:546 return get_top_cg_mask(cg_type);547 }548}549 550static int mt8188_afe_enable_top_cg(struct mtk_base_afe *afe, unsigned int cg_type)551{552 unsigned int reg = get_top_cg_reg(cg_type);553 unsigned int mask = get_top_cg_mask(cg_type);554 unsigned int val = get_top_cg_on_val(cg_type);555 556 regmap_update_bits(afe->regmap, reg, mask, val);557 558 return 0;559}560 561static int mt8188_afe_disable_top_cg(struct mtk_base_afe *afe, unsigned int cg_type)562{563 unsigned int reg = get_top_cg_reg(cg_type);564 unsigned int mask = get_top_cg_mask(cg_type);565 unsigned int val = get_top_cg_off_val(cg_type);566 567 regmap_update_bits(afe->regmap, reg, mask, val);568 569 return 0;570}571 572int mt8188_afe_enable_reg_rw_clk(struct mtk_base_afe *afe)573{574 struct mt8188_afe_private *afe_priv = afe->platform_priv;575 576 /* bus clock for AFE external access, like DRAM */577 mt8188_afe_enable_clk(afe, afe_priv->clk[MT8188_CLK_TOP_AUDIO_LOCAL_BUS_SEL]);578 579 /* bus clock for AFE internal access, like AFE SRAM */580 mt8188_afe_enable_clk(afe, afe_priv->clk[MT8188_CLK_TOP_AUD_INTBUS_SEL]);581 582 /* audio 26m clock source */583 mt8188_afe_enable_clk(afe, afe_priv->clk[MT8188_CLK_ADSP_AUDIO_26M]);584 585 /* AFE hw clock */586 mt8188_afe_enable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_AFE]);587 mt8188_afe_enable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_A1SYS_HP]);588 mt8188_afe_enable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_A1SYS]);589 590 return 0;591}592 593int mt8188_afe_disable_reg_rw_clk(struct mtk_base_afe *afe)594{595 struct mt8188_afe_private *afe_priv = afe->platform_priv;596 597 mt8188_afe_disable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_A1SYS]);598 mt8188_afe_disable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_A1SYS_HP]);599 mt8188_afe_disable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_AFE]);600 mt8188_afe_disable_clk(afe, afe_priv->clk[MT8188_CLK_ADSP_AUDIO_26M]);601 mt8188_afe_disable_clk(afe, afe_priv->clk[MT8188_CLK_TOP_AUD_INTBUS_SEL]);602 mt8188_afe_disable_clk(afe, afe_priv->clk[MT8188_CLK_TOP_AUDIO_LOCAL_BUS_SEL]);603 604 return 0;605}606 607static int mt8188_afe_enable_afe_on(struct mtk_base_afe *afe)608{609 regmap_update_bits(afe->regmap, AFE_DAC_CON0, 0x1, 0x1);610 return 0;611}612 613static int mt8188_afe_disable_afe_on(struct mtk_base_afe *afe)614{615 regmap_update_bits(afe->regmap, AFE_DAC_CON0, 0x1, 0x0);616 return 0;617}618 619static int mt8188_afe_enable_a1sys(struct mtk_base_afe *afe)620{621 struct mt8188_afe_private *afe_priv = afe->platform_priv;622 int ret;623 624 ret = mt8188_afe_enable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_A1SYS]);625 if (ret)626 return ret;627 628 return mt8188_afe_enable_top_cg(afe, MT8188_TOP_CG_A1SYS_TIMING);629}630 631static int mt8188_afe_disable_a1sys(struct mtk_base_afe *afe)632{633 struct mt8188_afe_private *afe_priv = afe->platform_priv;634 635 mt8188_afe_disable_top_cg(afe, MT8188_TOP_CG_A1SYS_TIMING);636 mt8188_afe_disable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_A1SYS]);637 return 0;638}639 640static int mt8188_afe_enable_a2sys(struct mtk_base_afe *afe)641{642 struct mt8188_afe_private *afe_priv = afe->platform_priv;643 int ret;644 645 ret = mt8188_afe_enable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_A2SYS]);646 if (ret)647 return ret;648 649 return mt8188_afe_enable_top_cg(afe, MT8188_TOP_CG_A2SYS_TIMING);650}651 652static int mt8188_afe_disable_a2sys(struct mtk_base_afe *afe)653{654 struct mt8188_afe_private *afe_priv = afe->platform_priv;655 656 mt8188_afe_disable_top_cg(afe, MT8188_TOP_CG_A2SYS_TIMING);657 mt8188_afe_disable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_A2SYS]);658 return 0;659}660 661int mt8188_apll1_enable(struct mtk_base_afe *afe)662{663 struct mt8188_afe_private *afe_priv = afe->platform_priv;664 int ret;665 666 ret = mt8188_afe_enable_clk(afe, afe_priv->clk[MT8188_CLK_TOP_APLL1_D4]);667 if (ret)668 return ret;669 670 ret = mt8188_afe_set_clk_parent(afe, afe_priv->clk[MT8188_CLK_TOP_A1SYS_HP_SEL],671 afe_priv->clk[MT8188_CLK_TOP_APLL1_D4]);672 if (ret)673 goto err_clk_parent;674 675 ret = mt8188_afe_enable_apll_tuner(afe, MT8188_AUD_PLL1);676 if (ret)677 goto err_apll_tuner;678 679 ret = mt8188_afe_enable_a1sys(afe);680 if (ret)681 goto err_a1sys;682 683 return 0;684 685err_a1sys:686 mt8188_afe_disable_apll_tuner(afe, MT8188_AUD_PLL1);687err_apll_tuner:688 mt8188_afe_set_clk_parent(afe, afe_priv->clk[MT8188_CLK_TOP_A1SYS_HP_SEL],689 afe_priv->clk[MT8188_CLK_XTAL_26M]);690err_clk_parent:691 mt8188_afe_disable_clk(afe, afe_priv->clk[MT8188_CLK_TOP_APLL1_D4]);692 693 return ret;694}695 696int mt8188_apll1_disable(struct mtk_base_afe *afe)697{698 struct mt8188_afe_private *afe_priv = afe->platform_priv;699 700 mt8188_afe_disable_a1sys(afe);701 mt8188_afe_disable_apll_tuner(afe, MT8188_AUD_PLL1);702 mt8188_afe_set_clk_parent(afe, afe_priv->clk[MT8188_CLK_TOP_A1SYS_HP_SEL],703 afe_priv->clk[MT8188_CLK_XTAL_26M]);704 mt8188_afe_disable_clk(afe, afe_priv->clk[MT8188_CLK_TOP_APLL1_D4]);705 706 return 0;707}708 709int mt8188_apll2_enable(struct mtk_base_afe *afe)710{711 int ret;712 713 ret = mt8188_afe_enable_apll_tuner(afe, MT8188_AUD_PLL2);714 if (ret)715 return ret;716 717 ret = mt8188_afe_enable_a2sys(afe);718 if (ret)719 goto err_a2sys;720 721 return 0;722err_a2sys:723 mt8188_afe_disable_apll_tuner(afe, MT8188_AUD_PLL2);724 725 return ret;726}727 728int mt8188_apll2_disable(struct mtk_base_afe *afe)729{730 mt8188_afe_disable_a2sys(afe);731 mt8188_afe_disable_apll_tuner(afe, MT8188_AUD_PLL2);732 return 0;733}734 735int mt8188_afe_enable_main_clock(struct mtk_base_afe *afe)736{737 mt8188_afe_enable_top_cg(afe, MT8188_TOP_CG_26M_TIMING);738 mt8188_afe_enable_afe_on(afe);739 return 0;740}741 742int mt8188_afe_disable_main_clock(struct mtk_base_afe *afe)743{744 mt8188_afe_disable_afe_on(afe);745 mt8188_afe_disable_top_cg(afe, MT8188_TOP_CG_26M_TIMING);746 return 0;747}748