brintos / linux-shallow public Read only

1// SPDX-License-Identifier: GPL-2.02/*3 * MediaTek ALSA SoC AFE platform driver for 81884 *5 * Copyright (c) 2022 MediaTek Inc.6 * Author: Bicycle Tsai <bicycle.tsai@mediatek.com>7 *         Trevor Wu <trevor.wu@mediatek.com>8 *         Chun-Chia Chiu <chun-chia.chiu@mediatek.com>9 */10 11#include <linux/arm-smccc.h>12#include <linux/delay.h>13#include <linux/dma-mapping.h>14#include <linux/module.h>15#include <linux/mfd/syscon.h>16#include <linux/of.h>17#include <linux/of_address.h>18#include <linux/of_platform.h>19#include <linux/of_reserved_mem.h>20#include <linux/pm_runtime.h>21#include <linux/soc/mediatek/infracfg.h>22#include <linux/reset.h>23#include <sound/pcm_params.h>24#include "mt8188-afe-common.h"25#include "mt8188-afe-clk.h"26#include "mt8188-reg.h"27#include "../common/mtk-afe-platform-driver.h"28#include "../common/mtk-afe-fe-dai.h"29 30#define MT8188_MEMIF_BUFFER_BYTES_ALIGN  (0x40)31#define MT8188_MEMIF_DL7_MAX_PERIOD_SIZE (0x3fff)32 33#define MEMIF_AXI_MINLEN 9 /* register default value */34 35struct mtk_dai_memif_priv {36	unsigned int asys_timing_sel;37	unsigned int fs_timing;38};39 40static const struct snd_pcm_hardware mt8188_afe_hardware = {41	.info = SNDRV_PCM_INFO_MMAP |42		SNDRV_PCM_INFO_INTERLEAVED |43		SNDRV_PCM_INFO_MMAP_VALID,44	.formats = SNDRV_PCM_FMTBIT_S16_LE |45		   SNDRV_PCM_FMTBIT_S24_LE |46		   SNDRV_PCM_FMTBIT_S32_LE,47	.period_bytes_min = 64,48	.period_bytes_max = 256 * 1024,49	.periods_min = 2,50	.periods_max = 256,51	.buffer_bytes_max = 256 * 2 * 1024,52};53 54struct mt8188_afe_rate {55	unsigned int rate;56	unsigned int reg_value;57};58 59static const struct mt8188_afe_rate mt8188_afe_rates[] = {60	{ .rate = 8000, .reg_value = 0, },61	{ .rate = 12000, .reg_value = 1, },62	{ .rate = 16000, .reg_value = 2, },63	{ .rate = 24000, .reg_value = 3, },64	{ .rate = 32000, .reg_value = 4, },65	{ .rate = 48000, .reg_value = 5, },66	{ .rate = 96000, .reg_value = 6, },67	{ .rate = 192000, .reg_value = 7, },68	{ .rate = 384000, .reg_value = 8, },69	{ .rate = 7350, .reg_value = 16, },70	{ .rate = 11025, .reg_value = 17, },71	{ .rate = 14700, .reg_value = 18, },72	{ .rate = 22050, .reg_value = 19, },73	{ .rate = 29400, .reg_value = 20, },74	{ .rate = 44100, .reg_value = 21, },75	{ .rate = 88200, .reg_value = 22, },76	{ .rate = 176400, .reg_value = 23, },77	{ .rate = 352800, .reg_value = 24, },78};79 80int mt8188_afe_fs_timing(unsigned int rate)81{82	int i;83 84	for (i = 0; i < ARRAY_SIZE(mt8188_afe_rates); i++)85		if (mt8188_afe_rates[i].rate == rate)86			return mt8188_afe_rates[i].reg_value;87 88	return -EINVAL;89}90 91static int mt8188_memif_fs(struct snd_pcm_substream *substream,92			   unsigned int rate)93{94	struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream);95	struct snd_soc_component *component = NULL;96	struct mtk_base_afe *afe = NULL;97	struct mt8188_afe_private *afe_priv = NULL;98	struct mtk_base_afe_memif *memif = NULL;99	struct mtk_dai_memif_priv *memif_priv = NULL;100	int fs = mt8188_afe_fs_timing(rate);101	int id = snd_soc_rtd_to_cpu(rtd, 0)->id;102 103	if (id < 0)104		return -EINVAL;105 106	component = snd_soc_rtdcom_lookup(rtd, AFE_PCM_NAME);107	if (!component)108		return -EINVAL;109 110	afe = snd_soc_component_get_drvdata(component);111	memif = &afe->memif[id];112 113	switch (memif->data->id) {114	case MT8188_AFE_MEMIF_DL10:115		fs = MT8188_ETDM_OUT3_1X_EN;116		break;117	case MT8188_AFE_MEMIF_UL8:118		fs = MT8188_ETDM_IN1_NX_EN;119		break;120	case MT8188_AFE_MEMIF_UL3:121		fs = MT8188_ETDM_IN2_NX_EN;122		break;123	default:124		afe_priv = afe->platform_priv;125		memif_priv = afe_priv->dai_priv[id];126		if (memif_priv->fs_timing)127			fs = memif_priv->fs_timing;128		break;129	}130 131	return fs;132}133 134static int mt8188_irq_fs(struct snd_pcm_substream *substream,135			 unsigned int rate)136{137	int fs = mt8188_memif_fs(substream, rate);138 139	switch (fs) {140	case MT8188_ETDM_IN1_NX_EN:141		fs = MT8188_ETDM_IN1_1X_EN;142		break;143	case MT8188_ETDM_IN2_NX_EN:144		fs = MT8188_ETDM_IN2_1X_EN;145		break;146	default:147		break;148	}149 150	return fs;151}152 153enum {154	MT8188_AFE_CM0,155	MT8188_AFE_CM1,156	MT8188_AFE_CM2,157	MT8188_AFE_CM_NUM,158};159 160struct mt8188_afe_channel_merge {161	int id;162	int reg;163	unsigned int sel_shift;164	unsigned int sel_maskbit;165	unsigned int sel_default;166	unsigned int ch_num_shift;167	unsigned int ch_num_maskbit;168	unsigned int en_shift;169	unsigned int en_maskbit;170	unsigned int update_cnt_shift;171	unsigned int update_cnt_maskbit;172	unsigned int update_cnt_default;173};174 175static const struct mt8188_afe_channel_merge176	mt8188_afe_cm[MT8188_AFE_CM_NUM] = {177	[MT8188_AFE_CM0] = {178		.id = MT8188_AFE_CM0,179		.reg = AFE_CM0_CON,180		.sel_shift = 30,181		.sel_maskbit = 0x1,182		.sel_default = 1,183		.ch_num_shift = 2,184		.ch_num_maskbit = 0x3f,185		.en_shift = 0,186		.en_maskbit = 0x1,187		.update_cnt_shift = 16,188		.update_cnt_maskbit = 0x1fff,189		.update_cnt_default = 0x3,190	},191	[MT8188_AFE_CM1] = {192		.id = MT8188_AFE_CM1,193		.reg = AFE_CM1_CON,194		.sel_shift = 30,195		.sel_maskbit = 0x1,196		.sel_default = 1,197		.ch_num_shift = 2,198		.ch_num_maskbit = 0x1f,199		.en_shift = 0,200		.en_maskbit = 0x1,201		.update_cnt_shift = 16,202		.update_cnt_maskbit = 0x1fff,203		.update_cnt_default = 0x3,204	},205	[MT8188_AFE_CM2] = {206		.id = MT8188_AFE_CM2,207		.reg = AFE_CM2_CON,208		.sel_shift = 30,209		.sel_maskbit = 0x1,210		.sel_default = 1,211		.ch_num_shift = 2,212		.ch_num_maskbit = 0x1f,213		.en_shift = 0,214		.en_maskbit = 0x1,215		.update_cnt_shift = 16,216		.update_cnt_maskbit = 0x1fff,217		.update_cnt_default = 0x3,218	},219};220 221static int mt8188_afe_memif_is_ul(int id)222{223	if (id >= MT8188_AFE_MEMIF_UL_START && id < MT8188_AFE_MEMIF_END)224		return 1;225	else226		return 0;227}228 229static const struct mt8188_afe_channel_merge *230	mt8188_afe_found_cm(struct snd_soc_dai *dai)231{232	struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);233	int id = -EINVAL;234 235	if (mt8188_afe_memif_is_ul(dai->id) == 0)236		return NULL;237 238	switch (dai->id) {239	case MT8188_AFE_MEMIF_UL9:240		id = MT8188_AFE_CM0;241		break;242	case MT8188_AFE_MEMIF_UL2:243		id = MT8188_AFE_CM1;244		break;245	case MT8188_AFE_MEMIF_UL10:246		id = MT8188_AFE_CM2;247		break;248	default:249		break;250	}251 252	if (id < 0) {253		dev_dbg(afe->dev, "%s, memif %d cannot find CM!\n", __func__, dai->id);254		return NULL;255	}256 257	return &mt8188_afe_cm[id];258}259 260static int mt8188_afe_config_cm(struct mtk_base_afe *afe,261				const struct mt8188_afe_channel_merge *cm,262				unsigned int channels)263{264	if (!cm)265		return -EINVAL;266 267	regmap_update_bits(afe->regmap,268			   cm->reg,269			   cm->sel_maskbit << cm->sel_shift,270			   cm->sel_default << cm->sel_shift);271 272	regmap_update_bits(afe->regmap,273			   cm->reg,274			   cm->ch_num_maskbit << cm->ch_num_shift,275			   (channels - 1) << cm->ch_num_shift);276 277	regmap_update_bits(afe->regmap,278			   cm->reg,279			   cm->update_cnt_maskbit << cm->update_cnt_shift,280			   cm->update_cnt_default << cm->update_cnt_shift);281 282	return 0;283}284 285static int mt8188_afe_enable_cm(struct mtk_base_afe *afe,286				const struct mt8188_afe_channel_merge *cm,287				bool enable)288{289	if (!cm)290		return -EINVAL;291 292	regmap_update_bits(afe->regmap,293			   cm->reg,294			   cm->en_maskbit << cm->en_shift,295			   enable << cm->en_shift);296 297	return 0;298}299 300static int mt8188_afe_fe_startup(struct snd_pcm_substream *substream,301				 struct snd_soc_dai *dai)302{303	struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream);304	struct snd_pcm_runtime *runtime = substream->runtime;305	struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);306	int id = snd_soc_rtd_to_cpu(rtd, 0)->id;307	int ret;308 309	ret = mtk_afe_fe_startup(substream, dai);310 311	snd_pcm_hw_constraint_step(runtime, 0,312				   SNDRV_PCM_HW_PARAM_BUFFER_BYTES,313				   MT8188_MEMIF_BUFFER_BYTES_ALIGN);314 315	if (id != MT8188_AFE_MEMIF_DL7)316		goto out;317 318	ret = snd_pcm_hw_constraint_minmax(runtime,319					   SNDRV_PCM_HW_PARAM_PERIOD_SIZE, 1,320					   MT8188_MEMIF_DL7_MAX_PERIOD_SIZE);321	if (ret < 0)322		dev_dbg(afe->dev, "hw_constraint_minmax failed\n");323out:324	return ret;325}326 327static void mt8188_afe_fe_shutdown(struct snd_pcm_substream *substream,328				   struct snd_soc_dai *dai)329{330	mtk_afe_fe_shutdown(substream, dai);331}332 333static int mt8188_afe_fe_hw_params(struct snd_pcm_substream *substream,334				   struct snd_pcm_hw_params *params,335				   struct snd_soc_dai *dai)336{337	struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream);338	struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);339	int id = snd_soc_rtd_to_cpu(rtd, 0)->id;340	struct mtk_base_afe_memif *memif = &afe->memif[id];341	const struct mtk_base_memif_data *data = memif->data;342	const struct mt8188_afe_channel_merge *cm = mt8188_afe_found_cm(dai);343	unsigned int channels = params_channels(params);344 345	mt8188_afe_config_cm(afe, cm, channels);346 347	if (data->ch_num_reg >= 0) {348		regmap_update_bits(afe->regmap, data->ch_num_reg,349				   data->ch_num_maskbit << data->ch_num_shift,350				   channels << data->ch_num_shift);351	}352 353	return mtk_afe_fe_hw_params(substream, params, dai);354}355 356static int mt8188_afe_fe_trigger(struct snd_pcm_substream *substream, int cmd,357				 struct snd_soc_dai *dai)358{359	struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);360	const struct mt8188_afe_channel_merge *cm = mt8188_afe_found_cm(dai);361	struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream);362	struct snd_pcm_runtime * const runtime = substream->runtime;363	int id = snd_soc_rtd_to_cpu(rtd, 0)->id;364	struct mtk_base_afe_memif *memif = &afe->memif[id];365	struct mtk_base_afe_irq *irqs = &afe->irqs[memif->irq_usage];366	const struct mtk_base_irq_data *irq_data = irqs->irq_data;367	unsigned int counter = runtime->period_size;368	int fs;369	int ret;370 371	switch (cmd) {372	case SNDRV_PCM_TRIGGER_START:373	case SNDRV_PCM_TRIGGER_RESUME:374		mt8188_afe_enable_cm(afe, cm, true);375 376		ret = mtk_memif_set_enable(afe, id);377		if (ret) {378			dev_err(afe->dev, "%s(), error, id %d, memif enable, ret %d\n",379				__func__, id, ret);380			return ret;381		}382 383		/* set irq counter */384		regmap_update_bits(afe->regmap, irq_data->irq_cnt_reg,385				   irq_data->irq_cnt_maskbit << irq_data->irq_cnt_shift,386				   counter << irq_data->irq_cnt_shift);387 388		/* set irq fs */389		fs = afe->irq_fs(substream, runtime->rate);390 391		if (fs < 0)392			return -EINVAL;393 394		if (irq_data->irq_fs_reg >= 0)395			regmap_update_bits(afe->regmap, irq_data->irq_fs_reg,396					   irq_data->irq_fs_maskbit << irq_data->irq_fs_shift,397					   fs << irq_data->irq_fs_shift);398 399		/* delay for uplink */400		if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {401			u32 sample_delay;402 403			sample_delay = ((MEMIF_AXI_MINLEN + 1) * 64 +404					(runtime->channels * runtime->sample_bits - 1)) /405					(runtime->channels * runtime->sample_bits) + 1;406 407			udelay(sample_delay * 1000000 / runtime->rate);408		}409 410		/* enable interrupt */411		regmap_set_bits(afe->regmap, irq_data->irq_en_reg,412				BIT(irq_data->irq_en_shift));413		return 0;414	case SNDRV_PCM_TRIGGER_STOP:415	case SNDRV_PCM_TRIGGER_SUSPEND:416		mt8188_afe_enable_cm(afe, cm, false);417 418		ret = mtk_memif_set_disable(afe, id);419		if (ret)420			dev_err(afe->dev, "%s(), error, id %d, memif enable, ret %d\n",421				__func__, id, ret);422 423		/* disable interrupt */424 425		regmap_clear_bits(afe->regmap, irq_data->irq_en_reg,426				  BIT(irq_data->irq_en_shift));427		/* and clear pending IRQ */428		regmap_write(afe->regmap, irq_data->irq_clr_reg,429			     BIT(irq_data->irq_clr_shift));430		return ret;431	default:432		return -EINVAL;433	}434}435 436static const struct snd_soc_dai_ops mt8188_afe_fe_dai_ops = {437	.startup	= mt8188_afe_fe_startup,438	.shutdown	= mt8188_afe_fe_shutdown,439	.hw_params	= mt8188_afe_fe_hw_params,440	.hw_free	= mtk_afe_fe_hw_free,441	.prepare	= mtk_afe_fe_prepare,442	.trigger	= mt8188_afe_fe_trigger,443};444 445#define MTK_PCM_RATES (SNDRV_PCM_RATE_8000_48000 |\446		       SNDRV_PCM_RATE_88200 |\447		       SNDRV_PCM_RATE_96000 |\448		       SNDRV_PCM_RATE_176400 |\449		       SNDRV_PCM_RATE_192000 |\450		       SNDRV_PCM_RATE_352800 |\451		       SNDRV_PCM_RATE_384000)452 453#define MTK_PCM_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\454			 SNDRV_PCM_FMTBIT_S24_LE |\455			 SNDRV_PCM_FMTBIT_S32_LE)456 457static struct snd_soc_dai_driver mt8188_memif_dai_driver[] = {458	/* FE DAIs: memory intefaces to CPU */459	{460		.name = "DL2",461		.id = MT8188_AFE_MEMIF_DL2,462		.playback = {463			.stream_name = "DL2",464			.channels_min = 1,465			.channels_max = 2,466			.rates = MTK_PCM_RATES,467			.formats = MTK_PCM_FORMATS,468		},469		.ops = &mt8188_afe_fe_dai_ops,470	},471	{472		.name = "DL3",473		.id = MT8188_AFE_MEMIF_DL3,474		.playback = {475			.stream_name = "DL3",476			.channels_min = 1,477			.channels_max = 2,478			.rates = MTK_PCM_RATES,479			.formats = MTK_PCM_FORMATS,480		},481		.ops = &mt8188_afe_fe_dai_ops,482	},483	{484		.name = "DL6",485		.id = MT8188_AFE_MEMIF_DL6,486		.playback = {487			.stream_name = "DL6",488			.channels_min = 1,489			.channels_max = 2,490			.rates = MTK_PCM_RATES,491			.formats = MTK_PCM_FORMATS,492		},493		.ops = &mt8188_afe_fe_dai_ops,494	},495	{496		.name = "DL7",497		.id = MT8188_AFE_MEMIF_DL7,498		.playback = {499			.stream_name = "DL7",500			.channels_min = 1,501			.channels_max = 2,502			.rates = MTK_PCM_RATES,503			.formats = MTK_PCM_FORMATS,504		},505		.ops = &mt8188_afe_fe_dai_ops,506	},507	{508		.name = "DL8",509		.id = MT8188_AFE_MEMIF_DL8,510		.playback = {511			.stream_name = "DL8",512			.channels_min = 1,513			.channels_max = 16,514			.rates = MTK_PCM_RATES,515			.formats = MTK_PCM_FORMATS,516		},517		.ops = &mt8188_afe_fe_dai_ops,518	},519	{520		.name = "DL10",521		.id = MT8188_AFE_MEMIF_DL10,522		.playback = {523			.stream_name = "DL10",524			.channels_min = 1,525			.channels_max = 8,526			.rates = MTK_PCM_RATES,527			.formats = MTK_PCM_FORMATS,528		},529		.ops = &mt8188_afe_fe_dai_ops,530	},531	{532		.name = "DL11",533		.id = MT8188_AFE_MEMIF_DL11,534		.playback = {535			.stream_name = "DL11",536			.channels_min = 1,537			.channels_max = 32,538			.rates = MTK_PCM_RATES,539			.formats = MTK_PCM_FORMATS,540		},541		.ops = &mt8188_afe_fe_dai_ops,542	},543	{544		.name = "UL1",545		.id = MT8188_AFE_MEMIF_UL1,546		.capture = {547			.stream_name = "UL1",548			.channels_min = 1,549			.channels_max = 8,550			.rates = MTK_PCM_RATES,551			.formats = MTK_PCM_FORMATS,552		},553		.ops = &mt8188_afe_fe_dai_ops,554	},555	{556		.name = "UL2",557		.id = MT8188_AFE_MEMIF_UL2,558		.capture = {559			.stream_name = "UL2",560			.channels_min = 1,561			.channels_max = 8,562			.rates = MTK_PCM_RATES,563			.formats = MTK_PCM_FORMATS,564		},565		.ops = &mt8188_afe_fe_dai_ops,566	},567	{568		.name = "UL3",569		.id = MT8188_AFE_MEMIF_UL3,570		.capture = {571			.stream_name = "UL3",572			.channels_min = 1,573			.channels_max = 16,574			.rates = MTK_PCM_RATES,575			.formats = MTK_PCM_FORMATS,576		},577		.ops = &mt8188_afe_fe_dai_ops,578	},579	{580		.name = "UL4",581		.id = MT8188_AFE_MEMIF_UL4,582		.capture = {583			.stream_name = "UL4",584			.channels_min = 1,585			.channels_max = 2,586			.rates = MTK_PCM_RATES,587			.formats = MTK_PCM_FORMATS,588		},589		.ops = &mt8188_afe_fe_dai_ops,590	},591	{592		.name = "UL5",593		.id = MT8188_AFE_MEMIF_UL5,594		.capture = {595			.stream_name = "UL5",596			.channels_min = 1,597			.channels_max = 2,598			.rates = MTK_PCM_RATES,599			.formats = MTK_PCM_FORMATS,600		},601		.ops = &mt8188_afe_fe_dai_ops,602	},603	{604		.name = "UL6",605		.id = MT8188_AFE_MEMIF_UL6,606		.capture = {607			.stream_name = "UL6",608			.channels_min = 1,609			.channels_max = 8,610			.rates = MTK_PCM_RATES,611			.formats = MTK_PCM_FORMATS,612		},613		.ops = &mt8188_afe_fe_dai_ops,614	},615	{616		.name = "UL8",617		.id = MT8188_AFE_MEMIF_UL8,618		.capture = {619			.stream_name = "UL8",620			.channels_min = 1,621			.channels_max = 24,622			.rates = MTK_PCM_RATES,623			.formats = MTK_PCM_FORMATS,624		},625		.ops = &mt8188_afe_fe_dai_ops,626	},627	{628		.name = "UL9",629		.id = MT8188_AFE_MEMIF_UL9,630		.capture = {631			.stream_name = "UL9",632			.channels_min = 1,633			.channels_max = 32,634			.rates = MTK_PCM_RATES,635			.formats = MTK_PCM_FORMATS,636		},637		.ops = &mt8188_afe_fe_dai_ops,638	},639	{640		.name = "UL10",641		.id = MT8188_AFE_MEMIF_UL10,642		.capture = {643			.stream_name = "UL10",644			.channels_min = 1,645			.channels_max = 4,646			.rates = MTK_PCM_RATES,647			.formats = MTK_PCM_FORMATS,648		},649		.ops = &mt8188_afe_fe_dai_ops,650	},651};652 653static const struct snd_kcontrol_new o002_mix[] = {654	SOC_DAPM_SINGLE_AUTODISABLE("I000 Switch", AFE_CONN2, 0, 1, 0),655	SOC_DAPM_SINGLE_AUTODISABLE("I012 Switch", AFE_CONN2, 12, 1, 0),656	SOC_DAPM_SINGLE_AUTODISABLE("I020 Switch", AFE_CONN2, 20, 1, 0),657	SOC_DAPM_SINGLE_AUTODISABLE("I022 Switch", AFE_CONN2, 22, 1, 0),658	SOC_DAPM_SINGLE_AUTODISABLE("I070 Switch", AFE_CONN2_2, 6, 1, 0),659	SOC_DAPM_SINGLE_AUTODISABLE("I072 Switch", AFE_CONN2_2, 8, 1, 0),660	SOC_DAPM_SINGLE_AUTODISABLE("I168 Switch", AFE_CONN2_5, 8, 1, 0),661};662 663static const struct snd_kcontrol_new o003_mix[] = {664	SOC_DAPM_SINGLE_AUTODISABLE("I001 Switch", AFE_CONN3, 1, 1, 0),665	SOC_DAPM_SINGLE_AUTODISABLE("I013 Switch", AFE_CONN3, 13, 1, 0),666	SOC_DAPM_SINGLE_AUTODISABLE("I021 Switch", AFE_CONN3, 21, 1, 0),667	SOC_DAPM_SINGLE_AUTODISABLE("I023 Switch", AFE_CONN3, 23, 1, 0),668	SOC_DAPM_SINGLE_AUTODISABLE("I071 Switch", AFE_CONN3_2, 7, 1, 0),669	SOC_DAPM_SINGLE_AUTODISABLE("I073 Switch", AFE_CONN3_2, 9, 1, 0),670	SOC_DAPM_SINGLE_AUTODISABLE("I169 Switch", AFE_CONN3_5, 9, 1, 0),671};672 673static const struct snd_kcontrol_new o004_mix[] = {674	SOC_DAPM_SINGLE_AUTODISABLE("I000 Switch", AFE_CONN4, 0, 1, 0),675	SOC_DAPM_SINGLE_AUTODISABLE("I014 Switch", AFE_CONN4, 14, 1, 0),676	SOC_DAPM_SINGLE_AUTODISABLE("I024 Switch", AFE_CONN4, 24, 1, 0),677	SOC_DAPM_SINGLE_AUTODISABLE("I074 Switch", AFE_CONN4_2, 10, 1, 0),678};679 680static const struct snd_kcontrol_new o005_mix[] = {681	SOC_DAPM_SINGLE_AUTODISABLE("I001 Switch", AFE_CONN5, 1, 1, 0),682	SOC_DAPM_SINGLE_AUTODISABLE("I015 Switch", AFE_CONN5, 15, 1, 0),683	SOC_DAPM_SINGLE_AUTODISABLE("I025 Switch", AFE_CONN5, 25, 1, 0),684	SOC_DAPM_SINGLE_AUTODISABLE("I075 Switch", AFE_CONN5_2, 11, 1, 0),685};686 687static const struct snd_kcontrol_new o006_mix[] = {688	SOC_DAPM_SINGLE_AUTODISABLE("I000 Switch", AFE_CONN6, 0, 1, 0),689	SOC_DAPM_SINGLE_AUTODISABLE("I016 Switch", AFE_CONN6, 16, 1, 0),690	SOC_DAPM_SINGLE_AUTODISABLE("I026 Switch", AFE_CONN6, 26, 1, 0),691	SOC_DAPM_SINGLE_AUTODISABLE("I076 Switch", AFE_CONN6_2, 12, 1, 0),692};693 694static const struct snd_kcontrol_new o007_mix[] = {695	SOC_DAPM_SINGLE_AUTODISABLE("I001 Switch", AFE_CONN7, 1, 1, 0),696	SOC_DAPM_SINGLE_AUTODISABLE("I017 Switch", AFE_CONN7, 17, 1, 0),697	SOC_DAPM_SINGLE_AUTODISABLE("I027 Switch", AFE_CONN7, 27, 1, 0),698	SOC_DAPM_SINGLE_AUTODISABLE("I077 Switch", AFE_CONN7_2, 13, 1, 0),699};700 701static const struct snd_kcontrol_new o008_mix[] = {702	SOC_DAPM_SINGLE_AUTODISABLE("I018 Switch", AFE_CONN8, 18, 1, 0),703	SOC_DAPM_SINGLE_AUTODISABLE("I028 Switch", AFE_CONN8, 28, 1, 0),704	SOC_DAPM_SINGLE_AUTODISABLE("I078 Switch", AFE_CONN8_2, 14, 1, 0),705};706 707static const struct snd_kcontrol_new o009_mix[] = {708	SOC_DAPM_SINGLE_AUTODISABLE("I019 Switch", AFE_CONN9, 19, 1, 0),709	SOC_DAPM_SINGLE_AUTODISABLE("I029 Switch", AFE_CONN9, 29, 1, 0),710	SOC_DAPM_SINGLE_AUTODISABLE("I079 Switch", AFE_CONN9_2, 15, 1, 0),711};712 713static const struct snd_kcontrol_new o010_mix[] = {714	SOC_DAPM_SINGLE_AUTODISABLE("I022 Switch", AFE_CONN10, 22, 1, 0),715	SOC_DAPM_SINGLE_AUTODISABLE("I030 Switch", AFE_CONN10, 30, 1, 0),716	SOC_DAPM_SINGLE_AUTODISABLE("I046 Switch", AFE_CONN10_1, 14, 1, 0),717	SOC_DAPM_SINGLE_AUTODISABLE("I072 Switch", AFE_CONN10_2, 8, 1, 0),718	SOC_DAPM_SINGLE_AUTODISABLE("I080 Switch", AFE_CONN10_2, 16, 1, 0),719	SOC_DAPM_SINGLE_AUTODISABLE("I188 Switch", AFE_CONN10_5, 28, 1, 0),720};721 722static const struct snd_kcontrol_new o011_mix[] = {723	SOC_DAPM_SINGLE_AUTODISABLE("I023 Switch", AFE_CONN11, 23, 1, 0),724	SOC_DAPM_SINGLE_AUTODISABLE("I031 Switch", AFE_CONN11, 31, 1, 0),725	SOC_DAPM_SINGLE_AUTODISABLE("I047 Switch", AFE_CONN11_1, 15, 1, 0),726	SOC_DAPM_SINGLE_AUTODISABLE("I073 Switch", AFE_CONN11_2, 9, 1, 0),727	SOC_DAPM_SINGLE_AUTODISABLE("I081 Switch", AFE_CONN11_2, 17, 1, 0),728	SOC_DAPM_SINGLE_AUTODISABLE("I189 Switch", AFE_CONN11_5, 29, 1, 0),729};730 731static const struct snd_kcontrol_new o012_mix[] = {732	SOC_DAPM_SINGLE_AUTODISABLE("I024 Switch", AFE_CONN12, 24, 1, 0),733	SOC_DAPM_SINGLE_AUTODISABLE("I032 Switch", AFE_CONN12_1, 0, 1, 0),734	SOC_DAPM_SINGLE_AUTODISABLE("I048 Switch", AFE_CONN12_1, 16, 1, 0),735	SOC_DAPM_SINGLE_AUTODISABLE("I074 Switch", AFE_CONN12_2, 10, 1, 0),736	SOC_DAPM_SINGLE_AUTODISABLE("I082 Switch", AFE_CONN12_2, 18, 1, 0),737	SOC_DAPM_SINGLE_AUTODISABLE("I190 Switch", AFE_CONN12_5, 30, 1, 0),738};739 740static const struct snd_kcontrol_new o013_mix[] = {741	SOC_DAPM_SINGLE_AUTODISABLE("I025 Switch", AFE_CONN13, 25, 1, 0),742	SOC_DAPM_SINGLE_AUTODISABLE("I033 Switch", AFE_CONN13_1, 1, 1, 0),743	SOC_DAPM_SINGLE_AUTODISABLE("I049 Switch", AFE_CONN13_1, 17, 1, 0),744	SOC_DAPM_SINGLE_AUTODISABLE("I075 Switch", AFE_CONN13_2, 11, 1, 0),745	SOC_DAPM_SINGLE_AUTODISABLE("I083 Switch", AFE_CONN13_2, 19, 1, 0),746	SOC_DAPM_SINGLE_AUTODISABLE("I191 Switch", AFE_CONN13_5, 31, 1, 0),747};748 749static const struct snd_kcontrol_new o014_mix[] = {750	SOC_DAPM_SINGLE_AUTODISABLE("I026 Switch", AFE_CONN14, 26, 1, 0),751	SOC_DAPM_SINGLE_AUTODISABLE("I034 Switch", AFE_CONN14_1, 2, 1, 0),752	SOC_DAPM_SINGLE_AUTODISABLE("I050 Switch", AFE_CONN14_1, 18, 1, 0),753	SOC_DAPM_SINGLE_AUTODISABLE("I076 Switch", AFE_CONN14_2, 12, 1, 0),754	SOC_DAPM_SINGLE_AUTODISABLE("I084 Switch", AFE_CONN14_2, 20, 1, 0),755	SOC_DAPM_SINGLE_AUTODISABLE("I192 Switch", AFE_CONN14_6, 0, 1, 0),756};757 758static const struct snd_kcontrol_new o015_mix[] = {759	SOC_DAPM_SINGLE_AUTODISABLE("I027 Switch", AFE_CONN15, 27, 1, 0),760	SOC_DAPM_SINGLE_AUTODISABLE("I035 Switch", AFE_CONN15_1, 3, 1, 0),761	SOC_DAPM_SINGLE_AUTODISABLE("I051 Switch", AFE_CONN15_1, 19, 1, 0),762	SOC_DAPM_SINGLE_AUTODISABLE("I077 Switch", AFE_CONN15_2, 13, 1, 0),763	SOC_DAPM_SINGLE_AUTODISABLE("I085 Switch", AFE_CONN15_2, 21, 1, 0),764	SOC_DAPM_SINGLE_AUTODISABLE("I193 Switch", AFE_CONN15_6, 1, 1, 0),765};766 767static const struct snd_kcontrol_new o016_mix[] = {768	SOC_DAPM_SINGLE_AUTODISABLE("I028 Switch", AFE_CONN16, 28, 1, 0),769	SOC_DAPM_SINGLE_AUTODISABLE("I036 Switch", AFE_CONN16_1, 4, 1, 0),770	SOC_DAPM_SINGLE_AUTODISABLE("I052 Switch", AFE_CONN16_1, 20, 1, 0),771	SOC_DAPM_SINGLE_AUTODISABLE("I078 Switch", AFE_CONN16_2, 14, 1, 0),772	SOC_DAPM_SINGLE_AUTODISABLE("I086 Switch", AFE_CONN16_2, 22, 1, 0),773	SOC_DAPM_SINGLE_AUTODISABLE("I194 Switch", AFE_CONN16_6, 2, 1, 0),774};775 776static const struct snd_kcontrol_new o017_mix[] = {777	SOC_DAPM_SINGLE_AUTODISABLE("I029 Switch", AFE_CONN17, 29, 1, 0),778	SOC_DAPM_SINGLE_AUTODISABLE("I037 Switch", AFE_CONN17_1, 5, 1, 0),779	SOC_DAPM_SINGLE_AUTODISABLE("I053 Switch", AFE_CONN17_1, 21, 1, 0),780	SOC_DAPM_SINGLE_AUTODISABLE("I079 Switch", AFE_CONN17_2, 15, 1, 0),781	SOC_DAPM_SINGLE_AUTODISABLE("I087 Switch", AFE_CONN17_2, 23, 1, 0),782	SOC_DAPM_SINGLE_AUTODISABLE("I195 Switch", AFE_CONN17_6, 3, 1, 0),783};784 785static const struct snd_kcontrol_new o018_mix[] = {786	SOC_DAPM_SINGLE_AUTODISABLE("I080 Switch", AFE_CONN18_2, 16, 1, 0),787};788 789static const struct snd_kcontrol_new o019_mix[] = {790	SOC_DAPM_SINGLE_AUTODISABLE("I081 Switch", AFE_CONN19_2, 17, 1, 0),791};792 793static const struct snd_kcontrol_new o020_mix[] = {794	SOC_DAPM_SINGLE_AUTODISABLE("I082 Switch", AFE_CONN20_2, 18, 1, 0),795};796 797static const struct snd_kcontrol_new o021_mix[] = {798	SOC_DAPM_SINGLE_AUTODISABLE("I083 Switch", AFE_CONN21_2, 19, 1, 0),799};800 801static const struct snd_kcontrol_new o022_mix[] = {802	SOC_DAPM_SINGLE_AUTODISABLE("I084 Switch", AFE_CONN22_2, 20, 1, 0),803};804 805static const struct snd_kcontrol_new o023_mix[] = {806	SOC_DAPM_SINGLE_AUTODISABLE("I085 Switch", AFE_CONN23_2, 21, 1, 0),807};808 809static const struct snd_kcontrol_new o024_mix[] = {810	SOC_DAPM_SINGLE_AUTODISABLE("I086 Switch", AFE_CONN24_2, 22, 1, 0),811};812 813static const struct snd_kcontrol_new o025_mix[] = {814	SOC_DAPM_SINGLE_AUTODISABLE("I087 Switch", AFE_CONN25_2, 23, 1, 0),815};816 817static const struct snd_kcontrol_new o026_mix[] = {818	SOC_DAPM_SINGLE_AUTODISABLE("I046 Switch", AFE_CONN26_1, 14, 1, 0),819};820 821static const struct snd_kcontrol_new o027_mix[] = {822	SOC_DAPM_SINGLE_AUTODISABLE("I047 Switch", AFE_CONN27_1, 15, 1, 0),823};824 825static const struct snd_kcontrol_new o028_mix[] = {826	SOC_DAPM_SINGLE_AUTODISABLE("I048 Switch", AFE_CONN28_1, 16, 1, 0),827};828 829static const struct snd_kcontrol_new o029_mix[] = {830	SOC_DAPM_SINGLE_AUTODISABLE("I049 Switch", AFE_CONN29_1, 17, 1, 0),831};832 833static const struct snd_kcontrol_new o030_mix[] = {834	SOC_DAPM_SINGLE_AUTODISABLE("I050 Switch", AFE_CONN30_1, 18, 1, 0),835};836 837static const struct snd_kcontrol_new o031_mix[] = {838	SOC_DAPM_SINGLE_AUTODISABLE("I051 Switch", AFE_CONN31_1, 19, 1, 0),839};840 841static const struct snd_kcontrol_new o032_mix[] = {842	SOC_DAPM_SINGLE_AUTODISABLE("I052 Switch", AFE_CONN32_1, 20, 1, 0),843};844 845static const struct snd_kcontrol_new o033_mix[] = {846	SOC_DAPM_SINGLE_AUTODISABLE("I053 Switch", AFE_CONN33_1, 21, 1, 0),847};848 849static const struct snd_kcontrol_new o034_mix[] = {850	SOC_DAPM_SINGLE_AUTODISABLE("I000 Switch", AFE_CONN34, 0, 1, 0),851	SOC_DAPM_SINGLE_AUTODISABLE("I002 Switch", AFE_CONN34, 2, 1, 0),852	SOC_DAPM_SINGLE_AUTODISABLE("I012 Switch", AFE_CONN34, 12, 1, 0),853	SOC_DAPM_SINGLE_AUTODISABLE("I020 Switch", AFE_CONN34, 20, 1, 0),854	SOC_DAPM_SINGLE_AUTODISABLE("I070 Switch", AFE_CONN34_2, 6, 1, 0),855	SOC_DAPM_SINGLE_AUTODISABLE("I072 Switch", AFE_CONN34_2, 8, 1, 0),856	SOC_DAPM_SINGLE_AUTODISABLE("I168 Switch", AFE_CONN34_5, 8, 1, 0),857};858 859static const struct snd_kcontrol_new o035_mix[] = {860	SOC_DAPM_SINGLE_AUTODISABLE("I001 Switch", AFE_CONN35, 1, 1, 0),861	SOC_DAPM_SINGLE_AUTODISABLE("I003 Switch", AFE_CONN35, 3, 1, 0),862	SOC_DAPM_SINGLE_AUTODISABLE("I013 Switch", AFE_CONN35, 13, 1, 0),863	SOC_DAPM_SINGLE_AUTODISABLE("I021 Switch", AFE_CONN35, 21, 1, 0),864	SOC_DAPM_SINGLE_AUTODISABLE("I071 Switch", AFE_CONN35_2, 7, 1, 0),865	SOC_DAPM_SINGLE_AUTODISABLE("I073 Switch", AFE_CONN35_2, 9, 1, 0),866	SOC_DAPM_SINGLE_AUTODISABLE("I168 Switch", AFE_CONN35_5, 8, 1, 0),867	SOC_DAPM_SINGLE_AUTODISABLE("I169 Switch", AFE_CONN35_5, 9, 1, 0),868};869 870static const struct snd_kcontrol_new o036_mix[] = {871	SOC_DAPM_SINGLE_AUTODISABLE("I000 Switch", AFE_CONN36, 0, 1, 0),872	SOC_DAPM_SINGLE_AUTODISABLE("I012 Switch", AFE_CONN36, 12, 1, 0),873	SOC_DAPM_SINGLE_AUTODISABLE("I020 Switch", AFE_CONN36, 20, 1, 0),874	SOC_DAPM_SINGLE_AUTODISABLE("I070 Switch", AFE_CONN36_2, 6, 1, 0),875	SOC_DAPM_SINGLE_AUTODISABLE("I168 Switch", AFE_CONN36_5, 8, 1, 0),876};877 878static const struct snd_kcontrol_new o037_mix[] = {879	SOC_DAPM_SINGLE_AUTODISABLE("I001 Switch", AFE_CONN37, 1, 1, 0),880	SOC_DAPM_SINGLE_AUTODISABLE("I013 Switch", AFE_CONN37, 13, 1, 0),881	SOC_DAPM_SINGLE_AUTODISABLE("I021 Switch", AFE_CONN37, 21, 1, 0),882	SOC_DAPM_SINGLE_AUTODISABLE("I071 Switch", AFE_CONN37_2, 7, 1, 0),883	SOC_DAPM_SINGLE_AUTODISABLE("I169 Switch", AFE_CONN37_5, 9, 1, 0),884};885 886static const struct snd_kcontrol_new o038_mix[] = {887	SOC_DAPM_SINGLE_AUTODISABLE("I022 Switch", AFE_CONN38, 22, 1, 0),888	SOC_DAPM_SINGLE_AUTODISABLE("I168 Switch", AFE_CONN38_5, 8, 1, 0),889};890 891static const struct snd_kcontrol_new o039_mix[] = {892	SOC_DAPM_SINGLE_AUTODISABLE("I023 Switch", AFE_CONN39, 23, 1, 0),893	SOC_DAPM_SINGLE_AUTODISABLE("I169 Switch", AFE_CONN39_5, 9, 1, 0),894};895 896static const struct snd_kcontrol_new o040_mix[] = {897	SOC_DAPM_SINGLE_AUTODISABLE("I002 Switch", AFE_CONN40, 2, 1, 0),898	SOC_DAPM_SINGLE_AUTODISABLE("I012 Switch", AFE_CONN40, 12, 1, 0),899	SOC_DAPM_SINGLE_AUTODISABLE("I022 Switch", AFE_CONN40, 22, 1, 0),900	SOC_DAPM_SINGLE_AUTODISABLE("I168 Switch", AFE_CONN40_5, 8, 1, 0),901};902 903static const struct snd_kcontrol_new o041_mix[] = {904	SOC_DAPM_SINGLE_AUTODISABLE("I003 Switch", AFE_CONN41, 3, 1, 0),905	SOC_DAPM_SINGLE_AUTODISABLE("I013 Switch", AFE_CONN41, 13, 1, 0),906	SOC_DAPM_SINGLE_AUTODISABLE("I023 Switch", AFE_CONN41, 23, 1, 0),907	SOC_DAPM_SINGLE_AUTODISABLE("I169 Switch", AFE_CONN41_5, 9, 1, 0),908};909 910static const struct snd_kcontrol_new o042_mix[] = {911	SOC_DAPM_SINGLE_AUTODISABLE("I014 Switch", AFE_CONN42, 14, 1, 0),912	SOC_DAPM_SINGLE_AUTODISABLE("I024 Switch", AFE_CONN42, 24, 1, 0),913};914 915static const struct snd_kcontrol_new o043_mix[] = {916	SOC_DAPM_SINGLE_AUTODISABLE("I015 Switch", AFE_CONN43, 15, 1, 0),917	SOC_DAPM_SINGLE_AUTODISABLE("I025 Switch", AFE_CONN43, 25, 1, 0),918};919 920static const struct snd_kcontrol_new o044_mix[] = {921	SOC_DAPM_SINGLE_AUTODISABLE("I016 Switch", AFE_CONN44, 16, 1, 0),922	SOC_DAPM_SINGLE_AUTODISABLE("I026 Switch", AFE_CONN44, 26, 1, 0),923};924 925static const struct snd_kcontrol_new o045_mix[] = {926	SOC_DAPM_SINGLE_AUTODISABLE("I017 Switch", AFE_CONN45, 17, 1, 0),927	SOC_DAPM_SINGLE_AUTODISABLE("I027 Switch", AFE_CONN45, 27, 1, 0),928};929 930static const struct snd_kcontrol_new o046_mix[] = {931	SOC_DAPM_SINGLE_AUTODISABLE("I018 Switch", AFE_CONN46, 18, 1, 0),932	SOC_DAPM_SINGLE_AUTODISABLE("I028 Switch", AFE_CONN46, 28, 1, 0),933};934 935static const struct snd_kcontrol_new o047_mix[] = {936	SOC_DAPM_SINGLE_AUTODISABLE("I019 Switch", AFE_CONN47, 19, 1, 0),937	SOC_DAPM_SINGLE_AUTODISABLE("I029 Switch", AFE_CONN47, 29, 1, 0),938};939 940static const struct snd_kcontrol_new o182_mix[] = {941	SOC_DAPM_SINGLE_AUTODISABLE("I020 Switch", AFE_CONN182, 20, 1, 0),942	SOC_DAPM_SINGLE_AUTODISABLE("I022 Switch", AFE_CONN182, 22, 1, 0),943	SOC_DAPM_SINGLE_AUTODISABLE("I024 Switch", AFE_CONN182, 24, 1, 0),944};945 946static const struct snd_kcontrol_new o183_mix[] = {947	SOC_DAPM_SINGLE_AUTODISABLE("I021 Switch", AFE_CONN183, 21, 1, 0),948	SOC_DAPM_SINGLE_AUTODISABLE("I023 Switch", AFE_CONN183, 23, 1, 0),949	SOC_DAPM_SINGLE_AUTODISABLE("I025 Switch", AFE_CONN183, 25, 1, 0),950};951 952static const char * const dl8_dl11_data_sel_mux_text[] = {953	"dl8", "dl11",954};955 956static SOC_ENUM_SINGLE_DECL(dl8_dl11_data_sel_mux_enum,957			    AFE_DAC_CON2, 0, dl8_dl11_data_sel_mux_text);958 959static const struct snd_kcontrol_new dl8_dl11_data_sel_mux =960	SOC_DAPM_ENUM("DL8_DL11 Sink",961		      dl8_dl11_data_sel_mux_enum);962 963static const struct snd_soc_dapm_widget mt8188_memif_widgets[] = {964	/* DL6 */965	SND_SOC_DAPM_MIXER("I000", SND_SOC_NOPM, 0, 0, NULL, 0),966	SND_SOC_DAPM_MIXER("I001", SND_SOC_NOPM, 0, 0, NULL, 0),967 968	/* DL3 */969	SND_SOC_DAPM_MIXER("I020", SND_SOC_NOPM, 0, 0, NULL, 0),970	SND_SOC_DAPM_MIXER("I021", SND_SOC_NOPM, 0, 0, NULL, 0),971 972	/* DL11 */973	SND_SOC_DAPM_MIXER("I022", SND_SOC_NOPM, 0, 0, NULL, 0),974	SND_SOC_DAPM_MIXER("I023", SND_SOC_NOPM, 0, 0, NULL, 0),975	SND_SOC_DAPM_MIXER("I024", SND_SOC_NOPM, 0, 0, NULL, 0),976	SND_SOC_DAPM_MIXER("I025", SND_SOC_NOPM, 0, 0, NULL, 0),977	SND_SOC_DAPM_MIXER("I026", SND_SOC_NOPM, 0, 0, NULL, 0),978	SND_SOC_DAPM_MIXER("I027", SND_SOC_NOPM, 0, 0, NULL, 0),979	SND_SOC_DAPM_MIXER("I028", SND_SOC_NOPM, 0, 0, NULL, 0),980	SND_SOC_DAPM_MIXER("I029", SND_SOC_NOPM, 0, 0, NULL, 0),981	SND_SOC_DAPM_MIXER("I030", SND_SOC_NOPM, 0, 0, NULL, 0),982	SND_SOC_DAPM_MIXER("I031", SND_SOC_NOPM, 0, 0, NULL, 0),983	SND_SOC_DAPM_MIXER("I032", SND_SOC_NOPM, 0, 0, NULL, 0),984	SND_SOC_DAPM_MIXER("I033", SND_SOC_NOPM, 0, 0, NULL, 0),985	SND_SOC_DAPM_MIXER("I034", SND_SOC_NOPM, 0, 0, NULL, 0),986	SND_SOC_DAPM_MIXER("I035", SND_SOC_NOPM, 0, 0, NULL, 0),987	SND_SOC_DAPM_MIXER("I036", SND_SOC_NOPM, 0, 0, NULL, 0),988	SND_SOC_DAPM_MIXER("I037", SND_SOC_NOPM, 0, 0, NULL, 0),989 990	/* DL11/DL8 */991	SND_SOC_DAPM_MIXER("I046", SND_SOC_NOPM, 0, 0, NULL, 0),992	SND_SOC_DAPM_MIXER("I047", SND_SOC_NOPM, 0, 0, NULL, 0),993	SND_SOC_DAPM_MIXER("I048", SND_SOC_NOPM, 0, 0, NULL, 0),994	SND_SOC_DAPM_MIXER("I049", SND_SOC_NOPM, 0, 0, NULL, 0),995	SND_SOC_DAPM_MIXER("I050", SND_SOC_NOPM, 0, 0, NULL, 0),996	SND_SOC_DAPM_MIXER("I051", SND_SOC_NOPM, 0, 0, NULL, 0),997	SND_SOC_DAPM_MIXER("I052", SND_SOC_NOPM, 0, 0, NULL, 0),998	SND_SOC_DAPM_MIXER("I053", SND_SOC_NOPM, 0, 0, NULL, 0),999	SND_SOC_DAPM_MIXER("I054", SND_SOC_NOPM, 0, 0, NULL, 0),1000	SND_SOC_DAPM_MIXER("I055", SND_SOC_NOPM, 0, 0, NULL, 0),1001	SND_SOC_DAPM_MIXER("I056", SND_SOC_NOPM, 0, 0, NULL, 0),1002	SND_SOC_DAPM_MIXER("I057", SND_SOC_NOPM, 0, 0, NULL, 0),1003	SND_SOC_DAPM_MIXER("I058", SND_SOC_NOPM, 0, 0, NULL, 0),1004	SND_SOC_DAPM_MIXER("I059", SND_SOC_NOPM, 0, 0, NULL, 0),1005	SND_SOC_DAPM_MIXER("I060", SND_SOC_NOPM, 0, 0, NULL, 0),1006	SND_SOC_DAPM_MIXER("I061", SND_SOC_NOPM, 0, 0, NULL, 0),1007 1008	/* DL2 */1009	SND_SOC_DAPM_MIXER("I070", SND_SOC_NOPM, 0, 0, NULL, 0),1010	SND_SOC_DAPM_MIXER("I071", SND_SOC_NOPM, 0, 0, NULL, 0),1011 1012	SND_SOC_DAPM_MUX("DL8_DL11 Mux",1013			 SND_SOC_NOPM, 0, 0, &dl8_dl11_data_sel_mux),1014 1015	/* UL9 */1016	SND_SOC_DAPM_MIXER("O002", SND_SOC_NOPM, 0, 0,1017			   o002_mix, ARRAY_SIZE(o002_mix)),1018	SND_SOC_DAPM_MIXER("O003", SND_SOC_NOPM, 0, 0,1019			   o003_mix, ARRAY_SIZE(o003_mix)),1020	SND_SOC_DAPM_MIXER("O004", SND_SOC_NOPM, 0, 0,1021			   o004_mix, ARRAY_SIZE(o004_mix)),1022	SND_SOC_DAPM_MIXER("O005", SND_SOC_NOPM, 0, 0,1023			   o005_mix, ARRAY_SIZE(o005_mix)),1024	SND_SOC_DAPM_MIXER("O006", SND_SOC_NOPM, 0, 0,1025			   o006_mix, ARRAY_SIZE(o006_mix)),1026	SND_SOC_DAPM_MIXER("O007", SND_SOC_NOPM, 0, 0,1027			   o007_mix, ARRAY_SIZE(o007_mix)),1028	SND_SOC_DAPM_MIXER("O008", SND_SOC_NOPM, 0, 0,1029			   o008_mix, ARRAY_SIZE(o008_mix)),1030	SND_SOC_DAPM_MIXER("O009", SND_SOC_NOPM, 0, 0,1031			   o009_mix, ARRAY_SIZE(o009_mix)),1032	SND_SOC_DAPM_MIXER("O010", SND_SOC_NOPM, 0, 0,1033			   o010_mix, ARRAY_SIZE(o010_mix)),1034	SND_SOC_DAPM_MIXER("O011", SND_SOC_NOPM, 0, 0,1035			   o011_mix, ARRAY_SIZE(o011_mix)),1036	SND_SOC_DAPM_MIXER("O012", SND_SOC_NOPM, 0, 0,1037			   o012_mix, ARRAY_SIZE(o012_mix)),1038	SND_SOC_DAPM_MIXER("O013", SND_SOC_NOPM, 0, 0,1039			   o013_mix, ARRAY_SIZE(o013_mix)),1040	SND_SOC_DAPM_MIXER("O014", SND_SOC_NOPM, 0, 0,1041			   o014_mix, ARRAY_SIZE(o014_mix)),1042	SND_SOC_DAPM_MIXER("O015", SND_SOC_NOPM, 0, 0,1043			   o015_mix, ARRAY_SIZE(o015_mix)),1044	SND_SOC_DAPM_MIXER("O016", SND_SOC_NOPM, 0, 0,1045			   o016_mix, ARRAY_SIZE(o016_mix)),1046	SND_SOC_DAPM_MIXER("O017", SND_SOC_NOPM, 0, 0,1047			   o017_mix, ARRAY_SIZE(o017_mix)),1048	SND_SOC_DAPM_MIXER("O018", SND_SOC_NOPM, 0, 0,1049			   o018_mix, ARRAY_SIZE(o018_mix)),1050	SND_SOC_DAPM_MIXER("O019", SND_SOC_NOPM, 0, 0,1051			   o019_mix, ARRAY_SIZE(o019_mix)),1052	SND_SOC_DAPM_MIXER("O020", SND_SOC_NOPM, 0, 0,1053			   o020_mix, ARRAY_SIZE(o020_mix)),1054	SND_SOC_DAPM_MIXER("O021", SND_SOC_NOPM, 0, 0,1055			   o021_mix, ARRAY_SIZE(o021_mix)),1056	SND_SOC_DAPM_MIXER("O022", SND_SOC_NOPM, 0, 0,1057			   o022_mix, ARRAY_SIZE(o022_mix)),1058	SND_SOC_DAPM_MIXER("O023", SND_SOC_NOPM, 0, 0,1059			   o023_mix, ARRAY_SIZE(o023_mix)),1060	SND_SOC_DAPM_MIXER("O024", SND_SOC_NOPM, 0, 0,1061			   o024_mix, ARRAY_SIZE(o024_mix)),1062	SND_SOC_DAPM_MIXER("O025", SND_SOC_NOPM, 0, 0,1063			   o025_mix, ARRAY_SIZE(o025_mix)),1064	SND_SOC_DAPM_MIXER("O026", SND_SOC_NOPM, 0, 0,1065			   o026_mix, ARRAY_SIZE(o026_mix)),1066	SND_SOC_DAPM_MIXER("O027", SND_SOC_NOPM, 0, 0,1067			   o027_mix, ARRAY_SIZE(o027_mix)),1068	SND_SOC_DAPM_MIXER("O028", SND_SOC_NOPM, 0, 0,1069			   o028_mix, ARRAY_SIZE(o028_mix)),1070	SND_SOC_DAPM_MIXER("O029", SND_SOC_NOPM, 0, 0,1071			   o029_mix, ARRAY_SIZE(o029_mix)),1072	SND_SOC_DAPM_MIXER("O030", SND_SOC_NOPM, 0, 0,1073			   o030_mix, ARRAY_SIZE(o030_mix)),1074	SND_SOC_DAPM_MIXER("O031", SND_SOC_NOPM, 0, 0,1075			   o031_mix, ARRAY_SIZE(o031_mix)),1076	SND_SOC_DAPM_MIXER("O032", SND_SOC_NOPM, 0, 0,1077			   o032_mix, ARRAY_SIZE(o032_mix)),1078	SND_SOC_DAPM_MIXER("O033", SND_SOC_NOPM, 0, 0,1079			   o033_mix, ARRAY_SIZE(o033_mix)),1080 1081	/* UL4 */1082	SND_SOC_DAPM_MIXER("O034", SND_SOC_NOPM, 0, 0,1083			   o034_mix, ARRAY_SIZE(o034_mix)),1084	SND_SOC_DAPM_MIXER("O035", SND_SOC_NOPM, 0, 0,1085			   o035_mix, ARRAY_SIZE(o035_mix)),1086 1087	/* UL5 */1088	SND_SOC_DAPM_MIXER("O036", SND_SOC_NOPM, 0, 0,1089			   o036_mix, ARRAY_SIZE(o036_mix)),1090	SND_SOC_DAPM_MIXER("O037", SND_SOC_NOPM, 0, 0,1091			   o037_mix, ARRAY_SIZE(o037_mix)),1092 1093	/* UL10 */1094	SND_SOC_DAPM_MIXER("O038", SND_SOC_NOPM, 0, 0,1095			   o038_mix, ARRAY_SIZE(o038_mix)),1096	SND_SOC_DAPM_MIXER("O039", SND_SOC_NOPM, 0, 0,1097			   o039_mix, ARRAY_SIZE(o039_mix)),1098	SND_SOC_DAPM_MIXER("O182", SND_SOC_NOPM, 0, 0,1099			   o182_mix, ARRAY_SIZE(o182_mix)),1100	SND_SOC_DAPM_MIXER("O183", SND_SOC_NOPM, 0, 0,1101			   o183_mix, ARRAY_SIZE(o183_mix)),1102 1103	/* UL2 */1104	SND_SOC_DAPM_MIXER("O040", SND_SOC_NOPM, 0, 0,1105			   o040_mix, ARRAY_SIZE(o040_mix)),1106	SND_SOC_DAPM_MIXER("O041", SND_SOC_NOPM, 0, 0,1107			   o041_mix, ARRAY_SIZE(o041_mix)),1108	SND_SOC_DAPM_MIXER("O042", SND_SOC_NOPM, 0, 0,1109			   o042_mix, ARRAY_SIZE(o042_mix)),1110	SND_SOC_DAPM_MIXER("O043", SND_SOC_NOPM, 0, 0,1111			   o043_mix, ARRAY_SIZE(o043_mix)),1112	SND_SOC_DAPM_MIXER("O044", SND_SOC_NOPM, 0, 0,1113			   o044_mix, ARRAY_SIZE(o044_mix)),1114	SND_SOC_DAPM_MIXER("O045", SND_SOC_NOPM, 0, 0,1115			   o045_mix, ARRAY_SIZE(o045_mix)),1116	SND_SOC_DAPM_MIXER("O046", SND_SOC_NOPM, 0, 0,1117			   o046_mix, ARRAY_SIZE(o046_mix)),1118	SND_SOC_DAPM_MIXER("O047", SND_SOC_NOPM, 0, 0,1119			   o047_mix, ARRAY_SIZE(o047_mix)),1120};1121 1122static const struct snd_soc_dapm_route mt8188_memif_routes[] = {1123	{"I000", NULL, "DL6"},1124	{"I001", NULL, "DL6"},1125 1126	{"I020", NULL, "DL3"},1127	{"I021", NULL, "DL3"},1128 1129	{"I022", NULL, "DL11"},1130	{"I023", NULL, "DL11"},1131	{"I024", NULL, "DL11"},1132	{"I025", NULL, "DL11"},1133	{"I026", NULL, "DL11"},1134	{"I027", NULL, "DL11"},1135	{"I028", NULL, "DL11"},1136	{"I029", NULL, "DL11"},1137	{"I030", NULL, "DL11"},1138	{"I031", NULL, "DL11"},1139	{"I032", NULL, "DL11"},1140	{"I033", NULL, "DL11"},1141	{"I034", NULL, "DL11"},1142	{"I035", NULL, "DL11"},1143	{"I036", NULL, "DL11"},1144	{"I037", NULL, "DL11"},1145 1146	{"DL8_DL11 Mux", "dl8", "DL8"},1147	{"DL8_DL11 Mux", "dl11", "DL11"},1148 1149	{"I046", NULL, "DL8_DL11 Mux"},1150	{"I047", NULL, "DL8_DL11 Mux"},1151	{"I048", NULL, "DL8_DL11 Mux"},1152	{"I049", NULL, "DL8_DL11 Mux"},1153	{"I050", NULL, "DL8_DL11 Mux"},1154	{"I051", NULL, "DL8_DL11 Mux"},1155	{"I052", NULL, "DL8_DL11 Mux"},1156	{"I053", NULL, "DL8_DL11 Mux"},1157	{"I054", NULL, "DL8_DL11 Mux"},1158	{"I055", NULL, "DL8_DL11 Mux"},1159	{"I056", NULL, "DL8_DL11 Mux"},1160	{"I057", NULL, "DL8_DL11 Mux"},1161	{"I058", NULL, "DL8_DL11 Mux"},1162	{"I059", NULL, "DL8_DL11 Mux"},1163	{"I060", NULL, "DL8_DL11 Mux"},1164	{"I061", NULL, "DL8_DL11 Mux"},1165 1166	{"I070", NULL, "DL2"},1167	{"I071", NULL, "DL2"},1168 1169	{"UL9", NULL, "O002"},1170	{"UL9", NULL, "O003"},1171	{"UL9", NULL, "O004"},1172	{"UL9", NULL, "O005"},1173	{"UL9", NULL, "O006"},1174	{"UL9", NULL, "O007"},1175	{"UL9", NULL, "O008"},1176	{"UL9", NULL, "O009"},1177	{"UL9", NULL, "O010"},1178	{"UL9", NULL, "O011"},1179	{"UL9", NULL, "O012"},1180	{"UL9", NULL, "O013"},1181	{"UL9", NULL, "O014"},1182	{"UL9", NULL, "O015"},1183	{"UL9", NULL, "O016"},1184	{"UL9", NULL, "O017"},1185	{"UL9", NULL, "O018"},1186	{"UL9", NULL, "O019"},1187	{"UL9", NULL, "O020"},1188	{"UL9", NULL, "O021"},1189	{"UL9", NULL, "O022"},1190	{"UL9", NULL, "O023"},1191	{"UL9", NULL, "O024"},1192	{"UL9", NULL, "O025"},1193	{"UL9", NULL, "O026"},1194	{"UL9", NULL, "O027"},1195	{"UL9", NULL, "O028"},1196	{"UL9", NULL, "O029"},1197	{"UL9", NULL, "O030"},1198	{"UL9", NULL, "O031"},1199	{"UL9", NULL, "O032"},1200	{"UL9", NULL, "O033"},1201 1202	{"UL4", NULL, "O034"},1203	{"UL4", NULL, "O035"},1204 1205	{"UL5", NULL, "O036"},1206	{"UL5", NULL, "O037"},1207 1208	{"UL10", NULL, "O038"},1209	{"UL10", NULL, "O039"},1210	{"UL10", NULL, "O182"},1211	{"UL10", NULL, "O183"},1212 1213	{"UL2", NULL, "O040"},1214	{"UL2", NULL, "O041"},1215	{"UL2", NULL, "O042"},1216	{"UL2", NULL, "O043"},1217	{"UL2", NULL, "O044"},1218	{"UL2", NULL, "O045"},1219	{"UL2", NULL, "O046"},1220	{"UL2", NULL, "O047"},1221 1222	{"O004", "I000 Switch", "I000"},1223	{"O005", "I001 Switch", "I001"},1224 1225	{"O006", "I000 Switch", "I000"},1226	{"O007", "I001 Switch", "I001"},1227 1228	{"O010", "I022 Switch", "I022"},1229	{"O011", "I023 Switch", "I023"},1230	{"O012", "I024 Switch", "I024"},1231	{"O013", "I025 Switch", "I025"},1232	{"O014", "I026 Switch", "I026"},1233	{"O015", "I027 Switch", "I027"},1234	{"O016", "I028 Switch", "I028"},1235	{"O017", "I029 Switch", "I029"},1236 1237	{"O010", "I046 Switch", "I046"},1238	{"O011", "I047 Switch", "I047"},1239	{"O012", "I048 Switch", "I048"},1240	{"O013", "I049 Switch", "I049"},1241	{"O014", "I050 Switch", "I050"},1242	{"O015", "I051 Switch", "I051"},1243	{"O016", "I052 Switch", "I052"},1244	{"O017", "I053 Switch", "I053"},1245 1246	{"O002", "I022 Switch", "I022"},1247	{"O003", "I023 Switch", "I023"},1248	{"O004", "I024 Switch", "I024"},1249	{"O005", "I025 Switch", "I025"},1250	{"O006", "I026 Switch", "I026"},1251	{"O007", "I027 Switch", "I027"},1252	{"O008", "I028 Switch", "I028"},1253	{"O009", "I029 Switch", "I029"},1254	{"O010", "I030 Switch", "I030"},1255	{"O011", "I031 Switch", "I031"},1256	{"O012", "I032 Switch", "I032"},1257	{"O013", "I033 Switch", "I033"},1258	{"O014", "I034 Switch", "I034"},1259	{"O015", "I035 Switch", "I035"},1260	{"O016", "I036 Switch", "I036"},1261	{"O017", "I037 Switch", "I037"},1262	{"O026", "I046 Switch", "I046"},1263	{"O027", "I047 Switch", "I047"},1264	{"O028", "I048 Switch", "I048"},1265	{"O029", "I049 Switch", "I049"},1266	{"O030", "I050 Switch", "I050"},1267	{"O031", "I051 Switch", "I051"},1268	{"O032", "I052 Switch", "I052"},1269	{"O033", "I053 Switch", "I053"},1270 1271	{"O002", "I000 Switch", "I000"},1272	{"O003", "I001 Switch", "I001"},1273	{"O002", "I020 Switch", "I020"},1274	{"O003", "I021 Switch", "I021"},1275	{"O002", "I070 Switch", "I070"},1276	{"O003", "I071 Switch", "I071"},1277 1278	{"O034", "I000 Switch", "I000"},1279	{"O035", "I001 Switch", "I001"},1280	{"O034", "I002 Switch", "I002"},1281	{"O035", "I003 Switch", "I003"},1282	{"O034", "I012 Switch", "I012"},1283	{"O035", "I013 Switch", "I013"},1284	{"O034", "I020 Switch", "I020"},1285	{"O035", "I021 Switch", "I021"},1286	{"O034", "I070 Switch", "I070"},1287	{"O035", "I071 Switch", "I071"},1288	{"O034", "I072 Switch", "I072"},1289	{"O035", "I073 Switch", "I073"},1290 1291	{"O036", "I000 Switch", "I000"},1292	{"O037", "I001 Switch", "I001"},1293	{"O036", "I012 Switch", "I012"},1294	{"O037", "I013 Switch", "I013"},1295	{"O036", "I020 Switch", "I020"},1296	{"O037", "I021 Switch", "I021"},1297	{"O036", "I070 Switch", "I070"},1298	{"O037", "I071 Switch", "I071"},1299	{"O036", "I168 Switch", "I168"},1300	{"O037", "I169 Switch", "I169"},1301 1302	{"O038", "I022 Switch", "I022"},1303	{"O039", "I023 Switch", "I023"},1304	{"O182", "I024 Switch", "I024"},1305	{"O183", "I025 Switch", "I025"},1306 1307	{"O038", "I168 Switch", "I168"},1308	{"O039", "I169 Switch", "I169"},1309 1310	{"O182", "I020 Switch", "I020"},1311	{"O183", "I021 Switch", "I021"},1312 1313	{"O182", "I022 Switch", "I022"},1314	{"O183", "I023 Switch", "I023"},1315 1316	{"O040", "I022 Switch", "I022"},1317	{"O041", "I023 Switch", "I023"},1318	{"O042", "I024 Switch", "I024"},1319	{"O043", "I025 Switch", "I025"},1320	{"O044", "I026 Switch", "I026"},1321	{"O045", "I027 Switch", "I027"},1322	{"O046", "I028 Switch", "I028"},1323	{"O047", "I029 Switch", "I029"},1324 1325	{"O040", "I002 Switch", "I002"},1326	{"O041", "I003 Switch", "I003"},1327 1328	{"O002", "I012 Switch", "I012"},1329	{"O003", "I013 Switch", "I013"},1330	{"O004", "I014 Switch", "I014"},1331	{"O005", "I015 Switch", "I015"},1332	{"O006", "I016 Switch", "I016"},1333	{"O007", "I017 Switch", "I017"},1334	{"O008", "I018 Switch", "I018"},1335	{"O009", "I019 Switch", "I019"},1336	{"O010", "I188 Switch", "I188"},1337	{"O011", "I189 Switch", "I189"},1338	{"O012", "I190 Switch", "I190"},1339	{"O013", "I191 Switch", "I191"},1340	{"O014", "I192 Switch", "I192"},1341	{"O015", "I193 Switch", "I193"},1342	{"O016", "I194 Switch", "I194"},1343	{"O017", "I195 Switch", "I195"},1344 1345	{"O040", "I012 Switch", "I012"},1346	{"O041", "I013 Switch", "I013"},1347	{"O042", "I014 Switch", "I014"},1348	{"O043", "I015 Switch", "I015"},1349	{"O044", "I016 Switch", "I016"},1350	{"O045", "I017 Switch", "I017"},1351	{"O046", "I018 Switch", "I018"},1352	{"O047", "I019 Switch", "I019"},1353 1354	{"O002", "I072 Switch", "I072"},1355	{"O003", "I073 Switch", "I073"},1356	{"O004", "I074 Switch", "I074"},1357	{"O005", "I075 Switch", "I075"},1358	{"O006", "I076 Switch", "I076"},1359	{"O007", "I077 Switch", "I077"},1360	{"O008", "I078 Switch", "I078"},1361	{"O009", "I079 Switch", "I079"},1362	{"O010", "I080 Switch", "I080"},1363	{"O011", "I081 Switch", "I081"},1364	{"O012", "I082 Switch", "I082"},1365	{"O013", "I083 Switch", "I083"},1366	{"O014", "I084 Switch", "I084"},1367	{"O015", "I085 Switch", "I085"},1368	{"O016", "I086 Switch", "I086"},1369	{"O017", "I087 Switch", "I087"},1370 1371	{"O010", "I072 Switch", "I072"},1372	{"O011", "I073 Switch", "I073"},1373	{"O012", "I074 Switch", "I074"},1374	{"O013", "I075 Switch", "I075"},1375	{"O014", "I076 Switch", "I076"},1376	{"O015", "I077 Switch", "I077"},1377	{"O016", "I078 Switch", "I078"},1378	{"O017", "I079 Switch", "I079"},1379	{"O018", "I080 Switch", "I080"},1380	{"O019", "I081 Switch", "I081"},1381	{"O020", "I082 Switch", "I082"},1382	{"O021", "I083 Switch", "I083"},1383	{"O022", "I084 Switch", "I084"},1384	{"O023", "I085 Switch", "I085"},1385	{"O024", "I086 Switch", "I086"},1386	{"O025", "I087 Switch", "I087"},1387 1388	{"O002", "I168 Switch", "I168"},1389	{"O003", "I169 Switch", "I169"},1390 1391	{"O034", "I168 Switch", "I168"},1392	{"O035", "I168 Switch", "I168"},1393	{"O035", "I169 Switch", "I169"},1394 1395	{"O040", "I168 Switch", "I168"},1396	{"O041", "I169 Switch", "I169"},1397};1398 1399static const char * const mt8188_afe_1x_en_sel_text[] = {1400	"a1sys_a2sys", "a3sys", "a4sys",1401};1402 1403static const unsigned int mt8188_afe_1x_en_sel_values[] = {1404	0, 1, 2,1405};1406 1407static SOC_VALUE_ENUM_SINGLE_DECL(dl2_1x_en_sel_enum,1408				  A3_A4_TIMING_SEL1, 18, 0x3,1409				  mt8188_afe_1x_en_sel_text,1410				  mt8188_afe_1x_en_sel_values);1411static SOC_VALUE_ENUM_SINGLE_DECL(dl3_1x_en_sel_enum,1412				  A3_A4_TIMING_SEL1, 20, 0x3,1413				  mt8188_afe_1x_en_sel_text,1414				  mt8188_afe_1x_en_sel_values);1415static SOC_VALUE_ENUM_SINGLE_DECL(dl6_1x_en_sel_enum,1416				  A3_A4_TIMING_SEL1, 22, 0x3,1417				  mt8188_afe_1x_en_sel_text,1418				  mt8188_afe_1x_en_sel_values);1419static SOC_VALUE_ENUM_SINGLE_DECL(dl7_1x_en_sel_enum,1420				  A3_A4_TIMING_SEL1, 24, 0x3,1421				  mt8188_afe_1x_en_sel_text,1422				  mt8188_afe_1x_en_sel_values);1423static SOC_VALUE_ENUM_SINGLE_DECL(dl8_1x_en_sel_enum,1424				  A3_A4_TIMING_SEL1, 26, 0x3,1425				  mt8188_afe_1x_en_sel_text,1426				  mt8188_afe_1x_en_sel_values);1427static SOC_VALUE_ENUM_SINGLE_DECL(dl10_1x_en_sel_enum,1428				  A3_A4_TIMING_SEL1, 28, 0x3,1429				  mt8188_afe_1x_en_sel_text,1430				  mt8188_afe_1x_en_sel_values);1431static SOC_VALUE_ENUM_SINGLE_DECL(dl11_1x_en_sel_enum,1432				  A3_A4_TIMING_SEL1, 30, 0x3,1433				  mt8188_afe_1x_en_sel_text,1434				  mt8188_afe_1x_en_sel_values);1435static SOC_VALUE_ENUM_SINGLE_DECL(ul1_1x_en_sel_enum,1436				  A3_A4_TIMING_SEL1, 0, 0x3,1437				  mt8188_afe_1x_en_sel_text,1438				  mt8188_afe_1x_en_sel_values);1439static SOC_VALUE_ENUM_SINGLE_DECL(ul2_1x_en_sel_enum,1440				  A3_A4_TIMING_SEL1, 2, 0x3,1441				  mt8188_afe_1x_en_sel_text,1442				  mt8188_afe_1x_en_sel_values);1443static SOC_VALUE_ENUM_SINGLE_DECL(ul3_1x_en_sel_enum,1444				  A3_A4_TIMING_SEL1, 4, 0x3,1445				  mt8188_afe_1x_en_sel_text,1446				  mt8188_afe_1x_en_sel_values);1447static SOC_VALUE_ENUM_SINGLE_DECL(ul4_1x_en_sel_enum,1448				  A3_A4_TIMING_SEL1, 6, 0x3,1449				  mt8188_afe_1x_en_sel_text,1450				  mt8188_afe_1x_en_sel_values);1451static SOC_VALUE_ENUM_SINGLE_DECL(ul5_1x_en_sel_enum,1452				  A3_A4_TIMING_SEL1, 8, 0x3,1453				  mt8188_afe_1x_en_sel_text,1454				  mt8188_afe_1x_en_sel_values);1455static SOC_VALUE_ENUM_SINGLE_DECL(ul6_1x_en_sel_enum,1456				  A3_A4_TIMING_SEL1, 10, 0x3,1457				  mt8188_afe_1x_en_sel_text,1458				  mt8188_afe_1x_en_sel_values);1459static SOC_VALUE_ENUM_SINGLE_DECL(ul8_1x_en_sel_enum,1460				  A3_A4_TIMING_SEL1, 12, 0x3,1461				  mt8188_afe_1x_en_sel_text,1462				  mt8188_afe_1x_en_sel_values);1463static SOC_VALUE_ENUM_SINGLE_DECL(ul9_1x_en_sel_enum,1464				  A3_A4_TIMING_SEL1, 14, 0x3,1465				  mt8188_afe_1x_en_sel_text,1466				  mt8188_afe_1x_en_sel_values);1467static SOC_VALUE_ENUM_SINGLE_DECL(ul10_1x_en_sel_enum,1468				  A3_A4_TIMING_SEL1, 16, 0x3,1469				  mt8188_afe_1x_en_sel_text,1470				  mt8188_afe_1x_en_sel_values);1471 1472static SOC_VALUE_ENUM_SINGLE_DECL(asys_irq1_1x_en_sel_enum,1473				  A3_A4_TIMING_SEL6, 0, 0x3,1474				  mt8188_afe_1x_en_sel_text,1475				  mt8188_afe_1x_en_sel_values);1476static SOC_VALUE_ENUM_SINGLE_DECL(asys_irq2_1x_en_sel_enum,1477				  A3_A4_TIMING_SEL6, 2, 0x3,1478				  mt8188_afe_1x_en_sel_text,1479				  mt8188_afe_1x_en_sel_values);1480static SOC_VALUE_ENUM_SINGLE_DECL(asys_irq3_1x_en_sel_enum,1481				  A3_A4_TIMING_SEL6, 4, 0x3,1482				  mt8188_afe_1x_en_sel_text,1483				  mt8188_afe_1x_en_sel_values);1484static SOC_VALUE_ENUM_SINGLE_DECL(asys_irq4_1x_en_sel_enum,1485				  A3_A4_TIMING_SEL6, 6, 0x3,1486				  mt8188_afe_1x_en_sel_text,1487				  mt8188_afe_1x_en_sel_values);1488static SOC_VALUE_ENUM_SINGLE_DECL(asys_irq5_1x_en_sel_enum,1489				  A3_A4_TIMING_SEL6, 8, 0x3,1490				  mt8188_afe_1x_en_sel_text,1491				  mt8188_afe_1x_en_sel_values);1492static SOC_VALUE_ENUM_SINGLE_DECL(asys_irq6_1x_en_sel_enum,1493				  A3_A4_TIMING_SEL6, 10, 0x3,1494				  mt8188_afe_1x_en_sel_text,1495				  mt8188_afe_1x_en_sel_values);1496static SOC_VALUE_ENUM_SINGLE_DECL(asys_irq7_1x_en_sel_enum,1497				  A3_A4_TIMING_SEL6, 12, 0x3,1498				  mt8188_afe_1x_en_sel_text,1499				  mt8188_afe_1x_en_sel_values);1500static SOC_VALUE_ENUM_SINGLE_DECL(asys_irq8_1x_en_sel_enum,1501				  A3_A4_TIMING_SEL6, 14, 0x3,1502				  mt8188_afe_1x_en_sel_text,1503				  mt8188_afe_1x_en_sel_values);1504static SOC_VALUE_ENUM_SINGLE_DECL(asys_irq9_1x_en_sel_enum,1505				  A3_A4_TIMING_SEL6, 16, 0x3,1506				  mt8188_afe_1x_en_sel_text,1507				  mt8188_afe_1x_en_sel_values);1508static SOC_VALUE_ENUM_SINGLE_DECL(asys_irq10_1x_en_sel_enum,1509				  A3_A4_TIMING_SEL6, 18, 0x3,1510				  mt8188_afe_1x_en_sel_text,1511				  mt8188_afe_1x_en_sel_values);1512static SOC_VALUE_ENUM_SINGLE_DECL(asys_irq11_1x_en_sel_enum,1513				  A3_A4_TIMING_SEL6, 20, 0x3,1514				  mt8188_afe_1x_en_sel_text,1515				  mt8188_afe_1x_en_sel_values);1516static SOC_VALUE_ENUM_SINGLE_DECL(asys_irq12_1x_en_sel_enum,1517				  A3_A4_TIMING_SEL6, 22, 0x3,1518				  mt8188_afe_1x_en_sel_text,1519				  mt8188_afe_1x_en_sel_values);1520static SOC_VALUE_ENUM_SINGLE_DECL(asys_irq13_1x_en_sel_enum,1521				  A3_A4_TIMING_SEL6, 24, 0x3,1522				  mt8188_afe_1x_en_sel_text,1523				  mt8188_afe_1x_en_sel_values);1524static SOC_VALUE_ENUM_SINGLE_DECL(asys_irq14_1x_en_sel_enum,1525				  A3_A4_TIMING_SEL6, 26, 0x3,1526				  mt8188_afe_1x_en_sel_text,1527				  mt8188_afe_1x_en_sel_values);1528static SOC_VALUE_ENUM_SINGLE_DECL(asys_irq15_1x_en_sel_enum,1529				  A3_A4_TIMING_SEL6, 28, 0x3,1530				  mt8188_afe_1x_en_sel_text,1531				  mt8188_afe_1x_en_sel_values);1532static SOC_VALUE_ENUM_SINGLE_DECL(asys_irq16_1x_en_sel_enum,1533				  A3_A4_TIMING_SEL6, 30, 0x3,1534				  mt8188_afe_1x_en_sel_text,1535				  mt8188_afe_1x_en_sel_values);1536 1537static const char * const mt8188_afe_fs_timing_sel_text[] = {1538	"asys",1539	"etdmout1_1x_en",1540	"etdmout2_1x_en",1541	"etdmout3_1x_en",1542	"etdmin1_1x_en",1543	"etdmin2_1x_en",1544	"etdmin1_nx_en",1545	"etdmin2_nx_en",1546};1547 1548static const unsigned int mt8188_afe_fs_timing_sel_values[] = {1549	0,1550	MT8188_ETDM_OUT1_1X_EN,1551	MT8188_ETDM_OUT2_1X_EN,1552	MT8188_ETDM_OUT3_1X_EN,1553	MT8188_ETDM_IN1_1X_EN,1554	MT8188_ETDM_IN2_1X_EN,1555	MT8188_ETDM_IN1_NX_EN,1556	MT8188_ETDM_IN2_NX_EN,1557};1558 1559static SOC_VALUE_ENUM_SINGLE_DECL(dl2_fs_timing_sel_enum,1560				  SND_SOC_NOPM, 0, 0,1561				  mt8188_afe_fs_timing_sel_text,1562				  mt8188_afe_fs_timing_sel_values);1563static SOC_VALUE_ENUM_SINGLE_DECL(dl3_fs_timing_sel_enum,1564				  SND_SOC_NOPM, 0, 0,1565				  mt8188_afe_fs_timing_sel_text,1566				  mt8188_afe_fs_timing_sel_values);1567static SOC_VALUE_ENUM_SINGLE_DECL(dl6_fs_timing_sel_enum,1568				  SND_SOC_NOPM, 0, 0,1569				  mt8188_afe_fs_timing_sel_text,1570				  mt8188_afe_fs_timing_sel_values);1571static SOC_VALUE_ENUM_SINGLE_DECL(dl8_fs_timing_sel_enum,1572				  SND_SOC_NOPM, 0, 0,1573				  mt8188_afe_fs_timing_sel_text,1574				  mt8188_afe_fs_timing_sel_values);1575static SOC_VALUE_ENUM_SINGLE_DECL(dl11_fs_timing_sel_enum,1576				  SND_SOC_NOPM, 0, 0,1577				  mt8188_afe_fs_timing_sel_text,1578				  mt8188_afe_fs_timing_sel_values);1579static SOC_VALUE_ENUM_SINGLE_DECL(ul2_fs_timing_sel_enum,1580				  SND_SOC_NOPM, 0, 0,1581				  mt8188_afe_fs_timing_sel_text,1582				  mt8188_afe_fs_timing_sel_values);1583static SOC_VALUE_ENUM_SINGLE_DECL(ul4_fs_timing_sel_enum,1584				  SND_SOC_NOPM, 0, 0,1585				  mt8188_afe_fs_timing_sel_text,1586				  mt8188_afe_fs_timing_sel_values);1587static SOC_VALUE_ENUM_SINGLE_DECL(ul5_fs_timing_sel_enum,1588				  SND_SOC_NOPM, 0, 0,1589				  mt8188_afe_fs_timing_sel_text,1590				  mt8188_afe_fs_timing_sel_values);1591static SOC_VALUE_ENUM_SINGLE_DECL(ul9_fs_timing_sel_enum,1592				  SND_SOC_NOPM, 0, 0,1593				  mt8188_afe_fs_timing_sel_text,1594				  mt8188_afe_fs_timing_sel_values);1595static SOC_VALUE_ENUM_SINGLE_DECL(ul10_fs_timing_sel_enum,1596				  SND_SOC_NOPM, 0, 0,1597				  mt8188_afe_fs_timing_sel_text,1598				  mt8188_afe_fs_timing_sel_values);1599 1600static int mt8188_memif_1x_en_sel_put(struct snd_kcontrol *kcontrol,1601				      struct snd_ctl_elem_value *ucontrol)1602{1603	struct snd_soc_component *component =1604		snd_soc_kcontrol_component(kcontrol);1605	struct mtk_base_afe *afe = snd_soc_component_get_drvdata(component);1606	struct mt8188_afe_private *afe_priv = afe->platform_priv;1607	struct mtk_dai_memif_priv *memif_priv;1608	unsigned int dai_id = kcontrol->id.device;1609	long val = ucontrol->value.integer.value[0];1610	int ret = 0;1611 1612	memif_priv = afe_priv->dai_priv[dai_id];1613 1614	if (val == memif_priv->asys_timing_sel)1615		return 0;1616 1617	ret = snd_soc_put_enum_double(kcontrol, ucontrol);1618 1619	memif_priv->asys_timing_sel = val;1620 1621	return ret;1622}1623 1624static int mt8188_asys_irq_1x_en_sel_put(struct snd_kcontrol *kcontrol,1625					 struct snd_ctl_elem_value *ucontrol)1626{1627	struct snd_soc_component *component =1628		snd_soc_kcontrol_component(kcontrol);1629	struct mtk_base_afe *afe = snd_soc_component_get_drvdata(component);1630	struct mt8188_afe_private *afe_priv = afe->platform_priv;1631	unsigned int id = kcontrol->id.device;1632	long val = ucontrol->value.integer.value[0];1633	int ret = 0;1634 1635	if (val == afe_priv->irq_priv[id].asys_timing_sel)1636		return 0;1637 1638	ret = snd_soc_put_enum_double(kcontrol, ucontrol);1639 1640	afe_priv->irq_priv[id].asys_timing_sel = val;1641 1642	return ret;1643}1644 1645static int mt8188_memif_fs_timing_sel_get(struct snd_kcontrol *kcontrol,1646					  struct snd_ctl_elem_value *ucontrol)1647{1648	struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);1649	struct mtk_base_afe *afe = snd_soc_component_get_drvdata(component);1650	struct mt8188_afe_private *afe_priv = afe->platform_priv;1651	struct mtk_dai_memif_priv *memif_priv;1652	unsigned int dai_id = kcontrol->id.device;1653	struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;1654 1655	memif_priv = afe_priv->dai_priv[dai_id];1656 1657	ucontrol->value.enumerated.item[0] =1658		snd_soc_enum_val_to_item(e, memif_priv->fs_timing);1659 1660	return 0;1661}1662 1663static int mt8188_memif_fs_timing_sel_put(struct snd_kcontrol *kcontrol,1664					  struct snd_ctl_elem_value *ucontrol)1665{1666	struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);1667	struct mtk_base_afe *afe = snd_soc_component_get_drvdata(component);1668	struct mt8188_afe_private *afe_priv = afe->platform_priv;1669	struct mtk_dai_memif_priv *memif_priv;1670	unsigned int dai_id = kcontrol->id.device;1671	struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;1672	unsigned int *item = ucontrol->value.enumerated.item;1673	unsigned int prev_item = 0;1674 1675	if (item[0] >= e->items)1676		return -EINVAL;1677 1678	memif_priv = afe_priv->dai_priv[dai_id];1679 1680	prev_item = snd_soc_enum_val_to_item(e, memif_priv->fs_timing);1681 1682	if (item[0] == prev_item)1683		return 0;1684 1685	memif_priv->fs_timing = snd_soc_enum_item_to_val(e, item[0]);1686 1687	return 1;1688}1689 1690static const struct snd_kcontrol_new mt8188_memif_controls[] = {1691	MT8188_SOC_ENUM_EXT("dl2_1x_en_sel",1692			    dl2_1x_en_sel_enum,1693			    snd_soc_get_enum_double,1694			    mt8188_memif_1x_en_sel_put,1695			    MT8188_AFE_MEMIF_DL2),1696	MT8188_SOC_ENUM_EXT("dl3_1x_en_sel",1697			    dl3_1x_en_sel_enum,1698			    snd_soc_get_enum_double,1699			    mt8188_memif_1x_en_sel_put,1700			    MT8188_AFE_MEMIF_DL3),1701	MT8188_SOC_ENUM_EXT("dl6_1x_en_sel",1702			    dl6_1x_en_sel_enum,1703			    snd_soc_get_enum_double,1704			    mt8188_memif_1x_en_sel_put,1705			    MT8188_AFE_MEMIF_DL6),1706	MT8188_SOC_ENUM_EXT("dl7_1x_en_sel",1707			    dl7_1x_en_sel_enum,1708			    snd_soc_get_enum_double,1709			    mt8188_memif_1x_en_sel_put,1710			    MT8188_AFE_MEMIF_DL7),1711	MT8188_SOC_ENUM_EXT("dl8_1x_en_sel",1712			    dl8_1x_en_sel_enum,1713			    snd_soc_get_enum_double,1714			    mt8188_memif_1x_en_sel_put,1715			    MT8188_AFE_MEMIF_DL8),1716	MT8188_SOC_ENUM_EXT("dl10_1x_en_sel",1717			    dl10_1x_en_sel_enum,1718			    snd_soc_get_enum_double,1719			    mt8188_memif_1x_en_sel_put,1720			    MT8188_AFE_MEMIF_DL10),1721	MT8188_SOC_ENUM_EXT("dl11_1x_en_sel",1722			    dl11_1x_en_sel_enum,1723			    snd_soc_get_enum_double,1724			    mt8188_memif_1x_en_sel_put,1725			    MT8188_AFE_MEMIF_DL11),1726	MT8188_SOC_ENUM_EXT("ul1_1x_en_sel",1727			    ul1_1x_en_sel_enum,1728			    snd_soc_get_enum_double,1729			    mt8188_memif_1x_en_sel_put,1730			    MT8188_AFE_MEMIF_UL1),1731	MT8188_SOC_ENUM_EXT("ul2_1x_en_sel",1732			    ul2_1x_en_sel_enum,1733			    snd_soc_get_enum_double,1734			    mt8188_memif_1x_en_sel_put,1735			    MT8188_AFE_MEMIF_UL2),1736	MT8188_SOC_ENUM_EXT("ul3_1x_en_sel",1737			    ul3_1x_en_sel_enum,1738			    snd_soc_get_enum_double,1739			    mt8188_memif_1x_en_sel_put,1740			    MT8188_AFE_MEMIF_UL3),1741	MT8188_SOC_ENUM_EXT("ul4_1x_en_sel",1742			    ul4_1x_en_sel_enum,1743			    snd_soc_get_enum_double,1744			    mt8188_memif_1x_en_sel_put,1745			    MT8188_AFE_MEMIF_UL4),1746	MT8188_SOC_ENUM_EXT("ul5_1x_en_sel",1747			    ul5_1x_en_sel_enum,1748			    snd_soc_get_enum_double,1749			    mt8188_memif_1x_en_sel_put,1750			    MT8188_AFE_MEMIF_UL5),1751	MT8188_SOC_ENUM_EXT("ul6_1x_en_sel",1752			    ul6_1x_en_sel_enum,1753			    snd_soc_get_enum_double,1754			    mt8188_memif_1x_en_sel_put,1755			    MT8188_AFE_MEMIF_UL6),1756	MT8188_SOC_ENUM_EXT("ul8_1x_en_sel",1757			    ul8_1x_en_sel_enum,1758			    snd_soc_get_enum_double,1759			    mt8188_memif_1x_en_sel_put,1760			    MT8188_AFE_MEMIF_UL8),1761	MT8188_SOC_ENUM_EXT("ul9_1x_en_sel",1762			    ul9_1x_en_sel_enum,1763			    snd_soc_get_enum_double,1764			    mt8188_memif_1x_en_sel_put,1765			    MT8188_AFE_MEMIF_UL9),1766	MT8188_SOC_ENUM_EXT("ul10_1x_en_sel",1767			    ul10_1x_en_sel_enum,1768			    snd_soc_get_enum_double,1769			    mt8188_memif_1x_en_sel_put,1770			    MT8188_AFE_MEMIF_UL10),1771	MT8188_SOC_ENUM_EXT("asys_irq1_1x_en_sel",1772			    asys_irq1_1x_en_sel_enum,1773			    snd_soc_get_enum_double,1774			    mt8188_asys_irq_1x_en_sel_put,1775			    MT8188_AFE_IRQ_13),1776	MT8188_SOC_ENUM_EXT("asys_irq2_1x_en_sel",1777			    asys_irq2_1x_en_sel_enum,1778			    snd_soc_get_enum_double,1779			    mt8188_asys_irq_1x_en_sel_put,1780			    MT8188_AFE_IRQ_14),1781	MT8188_SOC_ENUM_EXT("asys_irq3_1x_en_sel",1782			    asys_irq3_1x_en_sel_enum,1783			    snd_soc_get_enum_double,1784			    mt8188_asys_irq_1x_en_sel_put,1785			    MT8188_AFE_IRQ_15),1786	MT8188_SOC_ENUM_EXT("asys_irq4_1x_en_sel",1787			    asys_irq4_1x_en_sel_enum,1788			    snd_soc_get_enum_double,1789			    mt8188_asys_irq_1x_en_sel_put,1790			    MT8188_AFE_IRQ_16),1791	MT8188_SOC_ENUM_EXT("asys_irq5_1x_en_sel",1792			    asys_irq5_1x_en_sel_enum,1793			    snd_soc_get_enum_double,1794			    mt8188_asys_irq_1x_en_sel_put,1795			    MT8188_AFE_IRQ_17),1796	MT8188_SOC_ENUM_EXT("asys_irq6_1x_en_sel",1797			    asys_irq6_1x_en_sel_enum,1798			    snd_soc_get_enum_double,1799			    mt8188_asys_irq_1x_en_sel_put,1800			    MT8188_AFE_IRQ_18),1801	MT8188_SOC_ENUM_EXT("asys_irq7_1x_en_sel",1802			    asys_irq7_1x_en_sel_enum,1803			    snd_soc_get_enum_double,1804			    mt8188_asys_irq_1x_en_sel_put,1805			    MT8188_AFE_IRQ_19),1806	MT8188_SOC_ENUM_EXT("asys_irq8_1x_en_sel",1807			    asys_irq8_1x_en_sel_enum,1808			    snd_soc_get_enum_double,1809			    mt8188_asys_irq_1x_en_sel_put,1810			    MT8188_AFE_IRQ_20),1811	MT8188_SOC_ENUM_EXT("asys_irq9_1x_en_sel",1812			    asys_irq9_1x_en_sel_enum,1813			    snd_soc_get_enum_double,1814			    mt8188_asys_irq_1x_en_sel_put,1815			    MT8188_AFE_IRQ_21),1816	MT8188_SOC_ENUM_EXT("asys_irq10_1x_en_sel",1817			    asys_irq10_1x_en_sel_enum,1818			    snd_soc_get_enum_double,1819			    mt8188_asys_irq_1x_en_sel_put,1820			    MT8188_AFE_IRQ_22),1821	MT8188_SOC_ENUM_EXT("asys_irq11_1x_en_sel",1822			    asys_irq11_1x_en_sel_enum,1823			    snd_soc_get_enum_double,1824			    mt8188_asys_irq_1x_en_sel_put,1825			    MT8188_AFE_IRQ_23),1826	MT8188_SOC_ENUM_EXT("asys_irq12_1x_en_sel",1827			    asys_irq12_1x_en_sel_enum,1828			    snd_soc_get_enum_double,1829			    mt8188_asys_irq_1x_en_sel_put,1830			    MT8188_AFE_IRQ_24),1831	MT8188_SOC_ENUM_EXT("asys_irq13_1x_en_sel",1832			    asys_irq13_1x_en_sel_enum,1833			    snd_soc_get_enum_double,1834			    mt8188_asys_irq_1x_en_sel_put,1835			    MT8188_AFE_IRQ_25),1836	MT8188_SOC_ENUM_EXT("asys_irq14_1x_en_sel",1837			    asys_irq14_1x_en_sel_enum,1838			    snd_soc_get_enum_double,1839			    mt8188_asys_irq_1x_en_sel_put,1840			    MT8188_AFE_IRQ_26),1841	MT8188_SOC_ENUM_EXT("asys_irq15_1x_en_sel",1842			    asys_irq15_1x_en_sel_enum,1843			    snd_soc_get_enum_double,1844			    mt8188_asys_irq_1x_en_sel_put,1845			    MT8188_AFE_IRQ_27),1846	MT8188_SOC_ENUM_EXT("asys_irq16_1x_en_sel",1847			    asys_irq16_1x_en_sel_enum,1848			    snd_soc_get_enum_double,1849			    mt8188_asys_irq_1x_en_sel_put,1850			    MT8188_AFE_IRQ_28),1851	MT8188_SOC_ENUM_EXT("dl2_fs_timing_sel",1852			    dl2_fs_timing_sel_enum,1853			    mt8188_memif_fs_timing_sel_get,1854			    mt8188_memif_fs_timing_sel_put,1855			    MT8188_AFE_MEMIF_DL2),1856	MT8188_SOC_ENUM_EXT("dl3_fs_timing_sel",1857			    dl3_fs_timing_sel_enum,1858			    mt8188_memif_fs_timing_sel_get,1859			    mt8188_memif_fs_timing_sel_put,1860			    MT8188_AFE_MEMIF_DL3),1861	MT8188_SOC_ENUM_EXT("dl6_fs_timing_sel",1862			    dl6_fs_timing_sel_enum,1863			    mt8188_memif_fs_timing_sel_get,1864			    mt8188_memif_fs_timing_sel_put,1865			    MT8188_AFE_MEMIF_DL6),1866	MT8188_SOC_ENUM_EXT("dl8_fs_timing_sel",1867			    dl8_fs_timing_sel_enum,1868			    mt8188_memif_fs_timing_sel_get,1869			    mt8188_memif_fs_timing_sel_put,1870			    MT8188_AFE_MEMIF_DL8),1871	MT8188_SOC_ENUM_EXT("dl11_fs_timing_sel",1872			    dl11_fs_timing_sel_enum,1873			    mt8188_memif_fs_timing_sel_get,1874			    mt8188_memif_fs_timing_sel_put,1875			    MT8188_AFE_MEMIF_DL11),1876	MT8188_SOC_ENUM_EXT("ul2_fs_timing_sel",1877			    ul2_fs_timing_sel_enum,1878			    mt8188_memif_fs_timing_sel_get,1879			    mt8188_memif_fs_timing_sel_put,1880			    MT8188_AFE_MEMIF_UL2),1881	MT8188_SOC_ENUM_EXT("ul4_fs_timing_sel",1882			    ul4_fs_timing_sel_enum,1883			    mt8188_memif_fs_timing_sel_get,1884			    mt8188_memif_fs_timing_sel_put,1885			    MT8188_AFE_MEMIF_UL4),1886	MT8188_SOC_ENUM_EXT("ul5_fs_timing_sel",1887			    ul5_fs_timing_sel_enum,1888			    mt8188_memif_fs_timing_sel_get,1889			    mt8188_memif_fs_timing_sel_put,1890			    MT8188_AFE_MEMIF_UL5),1891	MT8188_SOC_ENUM_EXT("ul9_fs_timing_sel",1892			    ul9_fs_timing_sel_enum,1893			    mt8188_memif_fs_timing_sel_get,1894			    mt8188_memif_fs_timing_sel_put,1895			    MT8188_AFE_MEMIF_UL9),1896	MT8188_SOC_ENUM_EXT("ul10_fs_timing_sel",1897			    ul10_fs_timing_sel_enum,1898			    mt8188_memif_fs_timing_sel_get,1899			    mt8188_memif_fs_timing_sel_put,1900			    MT8188_AFE_MEMIF_UL10),1901};1902 1903static const struct mtk_base_memif_data memif_data[MT8188_AFE_MEMIF_NUM] = {1904	[MT8188_AFE_MEMIF_DL2] = {1905		.name = "DL2",1906		.id = MT8188_AFE_MEMIF_DL2,1907		.reg_ofs_base = AFE_DL2_BASE,1908		.reg_ofs_cur = AFE_DL2_CUR,1909		.reg_ofs_end = AFE_DL2_END,1910		.fs_reg = AFE_MEMIF_AGENT_FS_CON0,1911		.fs_shift = 10,1912		.fs_maskbit = 0x1f,1913		.mono_reg = -1,1914		.mono_shift = 0,1915		.int_odd_flag_reg = -1,1916		.int_odd_flag_shift = 0,1917		.enable_reg = AFE_DAC_CON0,1918		.enable_shift = 18,1919		.hd_reg = AFE_DL2_CON0,1920		.hd_shift = 5,1921		.agent_disable_reg = AUDIO_TOP_CON5,1922		.agent_disable_shift = 18,1923		.ch_num_reg = AFE_DL2_CON0,1924		.ch_num_shift = 0,1925		.ch_num_maskbit = 0x1f,1926		.msb_reg = AFE_NORMAL_BASE_ADR_MSB,1927		.msb_shift = 18,1928		.msb_end_reg = AFE_NORMAL_END_ADR_MSB,1929		.msb_end_shift = 18,1930	},1931	[MT8188_AFE_MEMIF_DL3] = {1932		.name = "DL3",1933		.id = MT8188_AFE_MEMIF_DL3,1934		.reg_ofs_base = AFE_DL3_BASE,1935		.reg_ofs_cur = AFE_DL3_CUR,1936		.reg_ofs_end = AFE_DL3_END,1937		.fs_reg = AFE_MEMIF_AGENT_FS_CON0,1938		.fs_shift = 15,1939		.fs_maskbit = 0x1f,1940		.mono_reg = -1,1941		.mono_shift = 0,1942		.int_odd_flag_reg = -1,1943		.int_odd_flag_shift = 0,1944		.enable_reg = AFE_DAC_CON0,1945		.enable_shift = 19,1946		.hd_reg = AFE_DL3_CON0,1947		.hd_shift = 5,1948		.agent_disable_reg = AUDIO_TOP_CON5,1949		.agent_disable_shift = 19,1950		.ch_num_reg = AFE_DL3_CON0,1951		.ch_num_shift = 0,1952		.ch_num_maskbit = 0x1f,1953		.msb_reg = AFE_NORMAL_BASE_ADR_MSB,1954		.msb_shift = 19,1955		.msb_end_reg = AFE_NORMAL_END_ADR_MSB,1956		.msb_end_shift = 19,1957	},1958	[MT8188_AFE_MEMIF_DL6] = {1959		.name = "DL6",1960		.id = MT8188_AFE_MEMIF_DL6,1961		.reg_ofs_base = AFE_DL6_BASE,1962		.reg_ofs_cur = AFE_DL6_CUR,1963		.reg_ofs_end = AFE_DL6_END,1964		.fs_reg = AFE_MEMIF_AGENT_FS_CON1,1965		.fs_shift = 0,1966		.fs_maskbit = 0x1f,1967		.mono_reg = -1,1968		.mono_shift = 0,1969		.int_odd_flag_reg = -1,1970		.int_odd_flag_shift = 0,1971		.enable_reg = AFE_DAC_CON0,1972		.enable_shift = 22,1973		.hd_reg = AFE_DL6_CON0,1974		.hd_shift = 5,1975		.agent_disable_reg = AUDIO_TOP_CON5,1976		.agent_disable_shift = 22,1977		.ch_num_reg = AFE_DL6_CON0,1978		.ch_num_shift = 0,1979		.ch_num_maskbit = 0x1f,1980		.msb_reg = AFE_NORMAL_BASE_ADR_MSB,1981		.msb_shift = 22,1982		.msb_end_reg = AFE_NORMAL_END_ADR_MSB,1983		.msb_end_shift = 22,1984	},1985	[MT8188_AFE_MEMIF_DL7] = {1986		.name = "DL7",1987		.id = MT8188_AFE_MEMIF_DL7,1988		.reg_ofs_base = AFE_DL7_BASE,1989		.reg_ofs_cur = AFE_DL7_CUR,1990		.reg_ofs_end = AFE_DL7_END,1991		.fs_reg = -1,1992		.fs_shift = 0,1993		.fs_maskbit = 0,1994		.mono_reg = -1,1995		.mono_shift = 0,1996		.int_odd_flag_reg = -1,1997		.int_odd_flag_shift = 0,1998		.enable_reg = AFE_DAC_CON0,1999		.enable_shift = 23,2000		.hd_reg = AFE_DL7_CON0,2001		.hd_shift = 5,2002		.agent_disable_reg = AUDIO_TOP_CON5,2003		.agent_disable_shift = 23,2004		.ch_num_reg = AFE_DL7_CON0,2005		.ch_num_shift = 0,2006		.ch_num_maskbit = 0x1f,2007		.msb_reg = AFE_NORMAL_BASE_ADR_MSB,2008		.msb_shift = 23,2009		.msb_end_reg = AFE_NORMAL_END_ADR_MSB,2010		.msb_end_shift = 23,2011	},2012	[MT8188_AFE_MEMIF_DL8] = {2013		.name = "DL8",2014		.id = MT8188_AFE_MEMIF_DL8,2015		.reg_ofs_base = AFE_DL8_BASE,2016		.reg_ofs_cur = AFE_DL8_CUR,2017		.reg_ofs_end = AFE_DL8_END,2018		.fs_reg = AFE_MEMIF_AGENT_FS_CON1,2019		.fs_shift = 10,2020		.fs_maskbit = 0x1f,2021		.mono_reg = -1,2022		.mono_shift = 0,2023		.int_odd_flag_reg = -1,2024		.int_odd_flag_shift = 0,2025		.enable_reg = AFE_DAC_CON0,2026		.enable_shift = 24,2027		.hd_reg = AFE_DL8_CON0,2028		.hd_shift = 6,2029		.agent_disable_reg = AUDIO_TOP_CON5,2030		.agent_disable_shift = 24,2031		.ch_num_reg = AFE_DL8_CON0,2032		.ch_num_shift = 0,2033		.ch_num_maskbit = 0x3f,2034		.msb_reg = AFE_NORMAL_BASE_ADR_MSB,2035		.msb_shift = 24,2036		.msb_end_reg = AFE_NORMAL_END_ADR_MSB,2037		.msb_end_shift = 24,2038	},2039	[MT8188_AFE_MEMIF_DL10] = {2040		.name = "DL10",2041		.id = MT8188_AFE_MEMIF_DL10,2042		.reg_ofs_base = AFE_DL10_BASE,2043		.reg_ofs_cur = AFE_DL10_CUR,2044		.reg_ofs_end = AFE_DL10_END,2045		.fs_reg = AFE_MEMIF_AGENT_FS_CON1,2046		.fs_shift = 20,2047		.fs_maskbit = 0x1f,2048		.mono_reg = -1,2049		.mono_shift = 0,2050		.int_odd_flag_reg = -1,2051		.int_odd_flag_shift = 0,2052		.enable_reg = AFE_DAC_CON0,2053		.enable_shift = 26,2054		.hd_reg = AFE_DL10_CON0,2055		.hd_shift = 5,2056		.agent_disable_reg = AUDIO_TOP_CON5,2057		.agent_disable_shift = 26,2058		.ch_num_reg = AFE_DL10_CON0,2059		.ch_num_shift = 0,2060		.ch_num_maskbit = 0x1f,2061		.msb_reg = AFE_NORMAL_BASE_ADR_MSB,2062		.msb_shift = 26,2063		.msb_end_reg = AFE_NORMAL_END_ADR_MSB,2064		.msb_end_shift = 26,2065	},2066	[MT8188_AFE_MEMIF_DL11] = {2067		.name = "DL11",2068		.id = MT8188_AFE_MEMIF_DL11,2069		.reg_ofs_base = AFE_DL11_BASE,2070		.reg_ofs_cur = AFE_DL11_CUR,2071		.reg_ofs_end = AFE_DL11_END,2072		.fs_reg = AFE_MEMIF_AGENT_FS_CON1,2073		.fs_shift = 25,2074		.fs_maskbit = 0x1f,2075		.mono_reg = -1,2076		.mono_shift = 0,2077		.int_odd_flag_reg = -1,2078		.int_odd_flag_shift = 0,2079		.enable_reg = AFE_DAC_CON0,2080		.enable_shift = 27,2081		.hd_reg = AFE_DL11_CON0,2082		.hd_shift = 7,2083		.agent_disable_reg = AUDIO_TOP_CON5,2084		.agent_disable_shift = 27,2085		.ch_num_reg = AFE_DL11_CON0,2086		.ch_num_shift = 0,2087		.ch_num_maskbit = 0x7f,2088		.msb_reg = AFE_NORMAL_BASE_ADR_MSB,2089		.msb_shift = 27,2090		.msb_end_reg = AFE_NORMAL_END_ADR_MSB,2091		.msb_end_shift = 27,2092	},2093	[MT8188_AFE_MEMIF_UL1] = {2094		.name = "UL1",2095		.id = MT8188_AFE_MEMIF_UL1,2096		.reg_ofs_base = AFE_UL1_BASE,2097		.reg_ofs_cur = AFE_UL1_CUR,2098		.reg_ofs_end = AFE_UL1_END,2099		.fs_reg = -1,2100		.fs_shift = 0,2101		.fs_maskbit = 0,2102		.mono_reg = AFE_UL1_CON0,2103		.mono_shift = 1,2104		.int_odd_flag_reg = AFE_UL1_CON0,2105		.int_odd_flag_shift = 0,2106		.enable_reg = AFE_DAC_CON0,2107		.enable_shift = 1,2108		.hd_reg = AFE_UL1_CON0,2109		.hd_shift = 5,2110		.agent_disable_reg = AUDIO_TOP_CON5,2111		.agent_disable_shift = 0,2112		.ch_num_reg = -1,2113		.ch_num_shift = 0,2114		.ch_num_maskbit = 0,2115		.msb_reg = AFE_NORMAL_BASE_ADR_MSB,2116		.msb_shift = 0,2117		.msb_end_reg = AFE_NORMAL_END_ADR_MSB,2118		.msb_end_shift = 0,2119	},2120	[MT8188_AFE_MEMIF_UL2] = {2121		.name = "UL2",2122		.id = MT8188_AFE_MEMIF_UL2,2123		.reg_ofs_base = AFE_UL2_BASE,2124		.reg_ofs_cur = AFE_UL2_CUR,2125		.reg_ofs_end = AFE_UL2_END,2126		.fs_reg = AFE_MEMIF_AGENT_FS_CON2,2127		.fs_shift = 5,2128		.fs_maskbit = 0x1f,2129		.mono_reg = AFE_UL2_CON0,2130		.mono_shift = 1,2131		.int_odd_flag_reg = AFE_UL2_CON0,2132		.int_odd_flag_shift = 0,2133		.enable_reg = AFE_DAC_CON0,2134		.enable_shift = 2,2135		.hd_reg = AFE_UL2_CON0,2136		.hd_shift = 5,2137		.agent_disable_reg = AUDIO_TOP_CON5,2138		.agent_disable_shift = 1,2139		.ch_num_reg = -1,2140		.ch_num_shift = 0,2141		.ch_num_maskbit = 0,2142		.msb_reg = AFE_NORMAL_BASE_ADR_MSB,2143		.msb_shift = 1,2144		.msb_end_reg = AFE_NORMAL_END_ADR_MSB,2145		.msb_end_shift = 1,2146	},2147	[MT8188_AFE_MEMIF_UL3] = {2148		.name = "UL3",2149		.id = MT8188_AFE_MEMIF_UL3,2150		.reg_ofs_base = AFE_UL3_BASE,2151		.reg_ofs_cur = AFE_UL3_CUR,2152		.reg_ofs_end = AFE_UL3_END,2153		.fs_reg = AFE_MEMIF_AGENT_FS_CON2,2154		.fs_shift = 10,2155		.fs_maskbit = 0x1f,2156		.mono_reg = AFE_UL3_CON0,2157		.mono_shift = 1,2158		.int_odd_flag_reg = AFE_UL3_CON0,2159		.int_odd_flag_shift = 0,2160		.enable_reg = AFE_DAC_CON0,2161		.enable_shift = 3,2162		.hd_reg = AFE_UL3_CON0,2163		.hd_shift = 5,2164		.agent_disable_reg = AUDIO_TOP_CON5,2165		.agent_disable_shift = 2,2166		.ch_num_reg = -1,2167		.ch_num_shift = 0,2168		.ch_num_maskbit = 0,2169		.msb_reg = AFE_NORMAL_BASE_ADR_MSB,2170		.msb_shift = 2,2171		.msb_end_reg = AFE_NORMAL_END_ADR_MSB,2172		.msb_end_shift = 2,2173	},2174	[MT8188_AFE_MEMIF_UL4] = {2175		.name = "UL4",2176		.id = MT8188_AFE_MEMIF_UL4,2177		.reg_ofs_base = AFE_UL4_BASE,2178		.reg_ofs_cur = AFE_UL4_CUR,2179		.reg_ofs_end = AFE_UL4_END,2180		.fs_reg = AFE_MEMIF_AGENT_FS_CON2,2181		.fs_shift = 15,2182		.fs_maskbit = 0x1f,2183		.mono_reg = AFE_UL4_CON0,2184		.mono_shift = 1,2185		.int_odd_flag_reg = AFE_UL4_CON0,2186		.int_odd_flag_shift = 0,2187		.enable_reg = AFE_DAC_CON0,2188		.enable_shift = 4,2189		.hd_reg = AFE_UL4_CON0,2190		.hd_shift = 5,2191		.agent_disable_reg = AUDIO_TOP_CON5,2192		.agent_disable_shift = 3,2193		.ch_num_reg = -1,2194		.ch_num_shift = 0,2195		.ch_num_maskbit = 0,2196		.msb_reg = AFE_NORMAL_BASE_ADR_MSB,2197		.msb_shift = 3,2198		.msb_end_reg = AFE_NORMAL_END_ADR_MSB,2199		.msb_end_shift = 3,2200	},2201	[MT8188_AFE_MEMIF_UL5] = {2202		.name = "UL5",2203		.id = MT8188_AFE_MEMIF_UL5,2204		.reg_ofs_base = AFE_UL5_BASE,2205		.reg_ofs_cur = AFE_UL5_CUR,2206		.reg_ofs_end = AFE_UL5_END,2207		.fs_reg = AFE_MEMIF_AGENT_FS_CON2,2208		.fs_shift = 20,2209		.fs_maskbit = 0x1f,2210		.mono_reg = AFE_UL5_CON0,2211		.mono_shift = 1,2212		.int_odd_flag_reg = AFE_UL5_CON0,2213		.int_odd_flag_shift = 0,2214		.enable_reg = AFE_DAC_CON0,2215		.enable_shift = 5,2216		.hd_reg = AFE_UL5_CON0,2217		.hd_shift = 5,2218		.agent_disable_reg = AUDIO_TOP_CON5,2219		.agent_disable_shift = 4,2220		.ch_num_reg = -1,2221		.ch_num_shift = 0,2222		.ch_num_maskbit = 0,2223		.msb_reg = AFE_NORMAL_BASE_ADR_MSB,2224		.msb_shift = 4,2225		.msb_end_reg = AFE_NORMAL_END_ADR_MSB,2226		.msb_end_shift = 4,2227	},2228	[MT8188_AFE_MEMIF_UL6] = {2229		.name = "UL6",2230		.id = MT8188_AFE_MEMIF_UL6,2231		.reg_ofs_base = AFE_UL6_BASE,2232		.reg_ofs_cur = AFE_UL6_CUR,2233		.reg_ofs_end = AFE_UL6_END,2234		.fs_reg = -1,2235		.fs_shift = 0,2236		.fs_maskbit = 0,2237		.mono_reg = AFE_UL6_CON0,2238		.mono_shift = 1,2239		.int_odd_flag_reg = AFE_UL6_CON0,2240		.int_odd_flag_shift = 0,2241		.enable_reg = AFE_DAC_CON0,2242		.enable_shift = 6,2243		.hd_reg = AFE_UL6_CON0,2244		.hd_shift = 5,2245		.agent_disable_reg = AUDIO_TOP_CON5,2246		.agent_disable_shift = 5,2247		.ch_num_reg = -1,2248		.ch_num_shift = 0,2249		.ch_num_maskbit = 0,2250		.msb_reg = AFE_NORMAL_BASE_ADR_MSB,2251		.msb_shift = 5,2252		.msb_end_reg = AFE_NORMAL_END_ADR_MSB,2253		.msb_end_shift = 5,2254	},2255	[MT8188_AFE_MEMIF_UL8] = {2256		.name = "UL8",2257		.id = MT8188_AFE_MEMIF_UL8,2258		.reg_ofs_base = AFE_UL8_BASE,2259		.reg_ofs_cur = AFE_UL8_CUR,2260		.reg_ofs_end = AFE_UL8_END,2261		.fs_reg = AFE_MEMIF_AGENT_FS_CON3,2262		.fs_shift = 5,2263		.fs_maskbit = 0x1f,2264		.mono_reg = AFE_UL8_CON0,2265		.mono_shift = 1,2266		.int_odd_flag_reg = AFE_UL8_CON0,2267		.int_odd_flag_shift = 0,2268		.enable_reg = AFE_DAC_CON0,2269		.enable_shift = 8,2270		.hd_reg = AFE_UL8_CON0,2271		.hd_shift = 5,2272		.agent_disable_reg = AUDIO_TOP_CON5,2273		.agent_disable_shift = 7,2274		.ch_num_reg = -1,2275		.ch_num_shift = 0,2276		.ch_num_maskbit = 0,2277		.msb_reg = AFE_NORMAL_BASE_ADR_MSB,2278		.msb_shift = 7,2279		.msb_end_reg = AFE_NORMAL_END_ADR_MSB,2280		.msb_end_shift = 7,2281	},2282	[MT8188_AFE_MEMIF_UL9] = {2283		.name = "UL9",2284		.id = MT8188_AFE_MEMIF_UL9,2285		.reg_ofs_base = AFE_UL9_BASE,2286		.reg_ofs_cur = AFE_UL9_CUR,2287		.reg_ofs_end = AFE_UL9_END,2288		.fs_reg = AFE_MEMIF_AGENT_FS_CON3,2289		.fs_shift = 10,2290		.fs_maskbit = 0x1f,2291		.mono_reg = AFE_UL9_CON0,2292		.mono_shift = 1,2293		.int_odd_flag_reg = AFE_UL9_CON0,2294		.int_odd_flag_shift = 0,2295		.enable_reg = AFE_DAC_CON0,2296		.enable_shift = 9,2297		.hd_reg = AFE_UL9_CON0,2298		.hd_shift = 5,2299		.agent_disable_reg = AUDIO_TOP_CON5,2300		.agent_disable_shift = 8,2301		.ch_num_reg = -1,2302		.ch_num_shift = 0,2303		.ch_num_maskbit = 0,2304		.msb_reg = AFE_NORMAL_BASE_ADR_MSB,2305		.msb_shift = 8,2306		.msb_end_reg = AFE_NORMAL_END_ADR_MSB,2307		.msb_end_shift = 8,2308	},2309	[MT8188_AFE_MEMIF_UL10] = {2310		.name = "UL10",2311		.id = MT8188_AFE_MEMIF_UL10,2312		.reg_ofs_base = AFE_UL10_BASE,2313		.reg_ofs_cur = AFE_UL10_CUR,2314		.reg_ofs_end = AFE_UL10_END,2315		.fs_reg = AFE_MEMIF_AGENT_FS_CON3,2316		.fs_shift = 15,2317		.fs_maskbit = 0x1f,2318		.mono_reg = AFE_UL10_CON0,2319		.mono_shift = 1,2320		.int_odd_flag_reg = AFE_UL10_CON0,2321		.int_odd_flag_shift = 0,2322		.enable_reg = AFE_DAC_CON0,2323		.enable_shift = 10,2324		.hd_reg = AFE_UL10_CON0,2325		.hd_shift = 5,2326		.agent_disable_reg = AUDIO_TOP_CON5,2327		.agent_disable_shift = 9,2328		.ch_num_reg = -1,2329		.ch_num_shift = 0,2330		.ch_num_maskbit = 0,2331		.msb_reg = AFE_NORMAL_BASE_ADR_MSB,2332		.msb_shift = 9,2333		.msb_end_reg = AFE_NORMAL_END_ADR_MSB,2334		.msb_end_shift = 9,2335	},2336};2337 2338static const struct mtk_base_irq_data irq_data[MT8188_AFE_IRQ_NUM] = {2339	[MT8188_AFE_IRQ_1] = {2340		.id = MT8188_AFE_IRQ_1,2341		.irq_cnt_reg = -1,2342		.irq_cnt_shift = 0,2343		.irq_cnt_maskbit = 0,2344		.irq_fs_reg = -1,2345		.irq_fs_shift = 0,2346		.irq_fs_maskbit = 0,2347		.irq_en_reg = AFE_IRQ1_CON,2348		.irq_en_shift = 31,2349		.irq_clr_reg = AFE_IRQ_MCU_CLR,2350		.irq_clr_shift = 0,2351		.irq_status_shift = 16,2352	},2353	[MT8188_AFE_IRQ_2] = {2354		.id = MT8188_AFE_IRQ_2,2355		.irq_cnt_reg = -1,2356		.irq_cnt_shift = 0,2357		.irq_cnt_maskbit = 0,2358		.irq_fs_reg = -1,2359		.irq_fs_shift = 0,2360		.irq_fs_maskbit = 0,2361		.irq_en_reg = AFE_IRQ2_CON,2362		.irq_en_shift = 31,2363		.irq_clr_reg = AFE_IRQ_MCU_CLR,2364		.irq_clr_shift = 1,2365		.irq_status_shift = 17,2366	},2367	[MT8188_AFE_IRQ_3] = {2368		.id = MT8188_AFE_IRQ_3,2369		.irq_cnt_reg = AFE_IRQ3_CON,2370		.irq_cnt_shift = 0,2371		.irq_cnt_maskbit = 0xffffff,2372		.irq_fs_reg = -1,2373		.irq_fs_shift = 0,2374		.irq_fs_maskbit = 0,2375		.irq_en_reg = AFE_IRQ3_CON,2376		.irq_en_shift = 31,2377		.irq_clr_reg = AFE_IRQ_MCU_CLR,2378		.irq_clr_shift = 2,2379		.irq_status_shift = 18,2380	},2381	[MT8188_AFE_IRQ_8] = {2382		.id = MT8188_AFE_IRQ_8,2383		.irq_cnt_reg = -1,2384		.irq_cnt_shift = 0,2385		.irq_cnt_maskbit = 0,2386		.irq_fs_reg = -1,2387		.irq_fs_shift = 0,2388		.irq_fs_maskbit = 0,2389		.irq_en_reg = AFE_IRQ8_CON,2390		.irq_en_shift = 31,2391		.irq_clr_reg = AFE_IRQ_MCU_CLR,2392		.irq_clr_shift = 7,2393		.irq_status_shift = 23,2394	},2395	[MT8188_AFE_IRQ_9] = {2396		.id = MT8188_AFE_IRQ_9,2397		.irq_cnt_reg = AFE_IRQ9_CON,2398		.irq_cnt_shift = 0,2399		.irq_cnt_maskbit = 0xffffff,2400		.irq_fs_reg = -1,2401		.irq_fs_shift = 0,2402		.irq_fs_maskbit = 0,2403		.irq_en_reg = AFE_IRQ9_CON,2404		.irq_en_shift = 31,2405		.irq_clr_reg = AFE_IRQ_MCU_CLR,2406		.irq_clr_shift = 8,2407		.irq_status_shift = 24,2408	},2409	[MT8188_AFE_IRQ_10] = {2410		.id = MT8188_AFE_IRQ_10,2411		.irq_cnt_reg = -1,2412		.irq_cnt_shift = 0,2413		.irq_cnt_maskbit = 0,2414		.irq_fs_reg = -1,2415		.irq_fs_shift = 0,2416		.irq_fs_maskbit = 0,2417		.irq_en_reg = AFE_IRQ10_CON,2418		.irq_en_shift = 31,2419		.irq_clr_reg = AFE_IRQ_MCU_CLR,2420		.irq_clr_shift = 9,2421		.irq_status_shift = 25,2422	},2423	[MT8188_AFE_IRQ_13] = {2424		.id = MT8188_AFE_IRQ_13,2425		.irq_cnt_reg = ASYS_IRQ1_CON,2426		.irq_cnt_shift = 0,2427		.irq_cnt_maskbit = 0xffffff,2428		.irq_fs_reg = ASYS_IRQ1_CON,2429		.irq_fs_shift = 24,2430		.irq_fs_maskbit = 0x1ffff,2431		.irq_en_reg = ASYS_IRQ1_CON,2432		.irq_en_shift = 31,2433		.irq_clr_reg =  ASYS_IRQ_CLR,2434		.irq_clr_shift = 0,2435		.irq_status_shift = 0,2436	},2437	[MT8188_AFE_IRQ_14] = {2438		.id = MT8188_AFE_IRQ_14,2439		.irq_cnt_reg = ASYS_IRQ2_CON,2440		.irq_cnt_shift = 0,2441		.irq_cnt_maskbit = 0xffffff,2442		.irq_fs_reg = ASYS_IRQ2_CON,2443		.irq_fs_shift = 24,2444		.irq_fs_maskbit = 0x1ffff,2445		.irq_en_reg = ASYS_IRQ2_CON,2446		.irq_en_shift = 31,2447		.irq_clr_reg =  ASYS_IRQ_CLR,2448		.irq_clr_shift = 1,2449		.irq_status_shift = 1,2450	},2451	[MT8188_AFE_IRQ_15] = {2452		.id = MT8188_AFE_IRQ_15,2453		.irq_cnt_reg = ASYS_IRQ3_CON,2454		.irq_cnt_shift = 0,2455		.irq_cnt_maskbit = 0xffffff,2456		.irq_fs_reg = ASYS_IRQ3_CON,2457		.irq_fs_shift = 24,2458		.irq_fs_maskbit = 0x1ffff,2459		.irq_en_reg = ASYS_IRQ3_CON,2460		.irq_en_shift = 31,2461		.irq_clr_reg =  ASYS_IRQ_CLR,2462		.irq_clr_shift = 2,2463		.irq_status_shift = 2,2464	},2465	[MT8188_AFE_IRQ_16] = {2466		.id = MT8188_AFE_IRQ_16,2467		.irq_cnt_reg = ASYS_IRQ4_CON,2468		.irq_cnt_shift = 0,2469		.irq_cnt_maskbit = 0xffffff,2470		.irq_fs_reg = ASYS_IRQ4_CON,2471		.irq_fs_shift = 24,2472		.irq_fs_maskbit = 0x1ffff,2473		.irq_en_reg = ASYS_IRQ4_CON,2474		.irq_en_shift = 31,2475		.irq_clr_reg =  ASYS_IRQ_CLR,2476		.irq_clr_shift = 3,2477		.irq_status_shift = 3,2478	},2479	[MT8188_AFE_IRQ_17] = {2480		.id = MT8188_AFE_IRQ_17,2481		.irq_cnt_reg = ASYS_IRQ5_CON,2482		.irq_cnt_shift = 0,2483		.irq_cnt_maskbit = 0xffffff,2484		.irq_fs_reg = ASYS_IRQ5_CON,2485		.irq_fs_shift = 24,2486		.irq_fs_maskbit = 0x1ffff,2487		.irq_en_reg = ASYS_IRQ5_CON,2488		.irq_en_shift = 31,2489		.irq_clr_reg =  ASYS_IRQ_CLR,2490		.irq_clr_shift = 4,2491		.irq_status_shift = 4,2492	},2493	[MT8188_AFE_IRQ_18] = {2494		.id = MT8188_AFE_IRQ_18,2495		.irq_cnt_reg = ASYS_IRQ6_CON,2496		.irq_cnt_shift = 0,2497		.irq_cnt_maskbit = 0xffffff,2498		.irq_fs_reg = ASYS_IRQ6_CON,2499		.irq_fs_shift = 24,2500		.irq_fs_maskbit = 0x1ffff,2501		.irq_en_reg = ASYS_IRQ6_CON,2502		.irq_en_shift = 31,2503		.irq_clr_reg =  ASYS_IRQ_CLR,2504		.irq_clr_shift = 5,2505		.irq_status_shift = 5,2506	},2507	[MT8188_AFE_IRQ_19] = {2508		.id = MT8188_AFE_IRQ_19,2509		.irq_cnt_reg = ASYS_IRQ7_CON,2510		.irq_cnt_shift = 0,2511		.irq_cnt_maskbit = 0xffffff,2512		.irq_fs_reg = ASYS_IRQ7_CON,2513		.irq_fs_shift = 24,2514		.irq_fs_maskbit = 0x1ffff,2515		.irq_en_reg = ASYS_IRQ7_CON,2516		.irq_en_shift = 31,2517		.irq_clr_reg =  ASYS_IRQ_CLR,2518		.irq_clr_shift = 6,2519		.irq_status_shift = 6,2520	},2521	[MT8188_AFE_IRQ_20] = {2522		.id = MT8188_AFE_IRQ_20,2523		.irq_cnt_reg = ASYS_IRQ8_CON,2524		.irq_cnt_shift = 0,2525		.irq_cnt_maskbit = 0xffffff,2526		.irq_fs_reg = ASYS_IRQ8_CON,2527		.irq_fs_shift = 24,2528		.irq_fs_maskbit = 0x1ffff,2529		.irq_en_reg = ASYS_IRQ8_CON,2530		.irq_en_shift = 31,2531		.irq_clr_reg =  ASYS_IRQ_CLR,2532		.irq_clr_shift = 7,2533		.irq_status_shift = 7,2534	},2535	[MT8188_AFE_IRQ_21] = {2536		.id = MT8188_AFE_IRQ_21,2537		.irq_cnt_reg = ASYS_IRQ9_CON,2538		.irq_cnt_shift = 0,2539		.irq_cnt_maskbit = 0xffffff,2540		.irq_fs_reg = ASYS_IRQ9_CON,2541		.irq_fs_shift = 24,2542		.irq_fs_maskbit = 0x1ffff,2543		.irq_en_reg = ASYS_IRQ9_CON,2544		.irq_en_shift = 31,2545		.irq_clr_reg =  ASYS_IRQ_CLR,2546		.irq_clr_shift = 8,2547		.irq_status_shift = 8,2548	},2549	[MT8188_AFE_IRQ_22] = {2550		.id = MT8188_AFE_IRQ_22,2551		.irq_cnt_reg = ASYS_IRQ10_CON,2552		.irq_cnt_shift = 0,2553		.irq_cnt_maskbit = 0xffffff,2554		.irq_fs_reg = ASYS_IRQ10_CON,2555		.irq_fs_shift = 24,2556		.irq_fs_maskbit = 0x1ffff,2557		.irq_en_reg = ASYS_IRQ10_CON,2558		.irq_en_shift = 31,2559		.irq_clr_reg =  ASYS_IRQ_CLR,2560		.irq_clr_shift = 9,2561		.irq_status_shift = 9,2562	},2563	[MT8188_AFE_IRQ_23] = {2564		.id = MT8188_AFE_IRQ_23,2565		.irq_cnt_reg = ASYS_IRQ11_CON,2566		.irq_cnt_shift = 0,2567		.irq_cnt_maskbit = 0xffffff,2568		.irq_fs_reg = ASYS_IRQ11_CON,2569		.irq_fs_shift = 24,2570		.irq_fs_maskbit = 0x1ffff,2571		.irq_en_reg = ASYS_IRQ11_CON,2572		.irq_en_shift = 31,2573		.irq_clr_reg =  ASYS_IRQ_CLR,2574		.irq_clr_shift = 10,2575		.irq_status_shift = 10,2576	},2577	[MT8188_AFE_IRQ_24] = {2578		.id = MT8188_AFE_IRQ_24,2579		.irq_cnt_reg = ASYS_IRQ12_CON,2580		.irq_cnt_shift = 0,2581		.irq_cnt_maskbit = 0xffffff,2582		.irq_fs_reg = ASYS_IRQ12_CON,2583		.irq_fs_shift = 24,2584		.irq_fs_maskbit = 0x1ffff,2585		.irq_en_reg = ASYS_IRQ12_CON,2586		.irq_en_shift = 31,2587		.irq_clr_reg =  ASYS_IRQ_CLR,2588		.irq_clr_shift = 11,2589		.irq_status_shift = 11,2590	},2591	[MT8188_AFE_IRQ_25] = {2592		.id = MT8188_AFE_IRQ_25,2593		.irq_cnt_reg = ASYS_IRQ13_CON,2594		.irq_cnt_shift = 0,2595		.irq_cnt_maskbit = 0xffffff,2596		.irq_fs_reg = ASYS_IRQ13_CON,2597		.irq_fs_shift = 24,2598		.irq_fs_maskbit = 0x1ffff,2599		.irq_en_reg = ASYS_IRQ13_CON,2600		.irq_en_shift = 31,2601		.irq_clr_reg =  ASYS_IRQ_CLR,2602		.irq_clr_shift = 12,2603		.irq_status_shift = 12,2604	},2605	[MT8188_AFE_IRQ_26] = {2606		.id = MT8188_AFE_IRQ_26,2607		.irq_cnt_reg = ASYS_IRQ14_CON,2608		.irq_cnt_shift = 0,2609		.irq_cnt_maskbit = 0xffffff,2610		.irq_fs_reg = ASYS_IRQ14_CON,2611		.irq_fs_shift = 24,2612		.irq_fs_maskbit = 0x1ffff,2613		.irq_en_reg = ASYS_IRQ14_CON,2614		.irq_en_shift = 31,2615		.irq_clr_reg =  ASYS_IRQ_CLR,2616		.irq_clr_shift = 13,2617		.irq_status_shift = 13,2618	},2619	[MT8188_AFE_IRQ_27] = {2620		.id = MT8188_AFE_IRQ_27,2621		.irq_cnt_reg = ASYS_IRQ15_CON,2622		.irq_cnt_shift = 0,2623		.irq_cnt_maskbit = 0xffffff,2624		.irq_fs_reg = ASYS_IRQ15_CON,2625		.irq_fs_shift = 24,2626		.irq_fs_maskbit = 0x1ffff,2627		.irq_en_reg = ASYS_IRQ15_CON,2628		.irq_en_shift = 31,2629		.irq_clr_reg =  ASYS_IRQ_CLR,2630		.irq_clr_shift = 14,2631		.irq_status_shift = 14,2632	},2633	[MT8188_AFE_IRQ_28] = {2634		.id = MT8188_AFE_IRQ_28,2635		.irq_cnt_reg = ASYS_IRQ16_CON,2636		.irq_cnt_shift = 0,2637		.irq_cnt_maskbit = 0xffffff,2638		.irq_fs_reg = ASYS_IRQ16_CON,2639		.irq_fs_shift = 24,2640		.irq_fs_maskbit = 0x1ffff,2641		.irq_en_reg = ASYS_IRQ16_CON,2642		.irq_en_shift = 31,2643		.irq_clr_reg =  ASYS_IRQ_CLR,2644		.irq_clr_shift = 15,2645		.irq_status_shift = 15,2646	},2647};2648 2649static const int mt8188_afe_memif_const_irqs[MT8188_AFE_MEMIF_NUM] = {2650	[MT8188_AFE_MEMIF_DL2] = MT8188_AFE_IRQ_13,2651	[MT8188_AFE_MEMIF_DL3] = MT8188_AFE_IRQ_14,2652	[MT8188_AFE_MEMIF_DL6] = MT8188_AFE_IRQ_15,2653	[MT8188_AFE_MEMIF_DL7] = MT8188_AFE_IRQ_1,2654	[MT8188_AFE_MEMIF_DL8] = MT8188_AFE_IRQ_16,2655	[MT8188_AFE_MEMIF_DL10] = MT8188_AFE_IRQ_17,2656	[MT8188_AFE_MEMIF_DL11] = MT8188_AFE_IRQ_18,2657	[MT8188_AFE_MEMIF_UL1] = MT8188_AFE_IRQ_3,2658	[MT8188_AFE_MEMIF_UL2] = MT8188_AFE_IRQ_19,2659	[MT8188_AFE_MEMIF_UL3] = MT8188_AFE_IRQ_20,2660	[MT8188_AFE_MEMIF_UL4] = MT8188_AFE_IRQ_21,2661	[MT8188_AFE_MEMIF_UL5] = MT8188_AFE_IRQ_22,2662	[MT8188_AFE_MEMIF_UL6] = MT8188_AFE_IRQ_9,2663	[MT8188_AFE_MEMIF_UL8] = MT8188_AFE_IRQ_23,2664	[MT8188_AFE_MEMIF_UL9] = MT8188_AFE_IRQ_24,2665	[MT8188_AFE_MEMIF_UL10] = MT8188_AFE_IRQ_25,2666};2667 2668static bool mt8188_is_volatile_reg(struct device *dev, unsigned int reg)2669{2670	/* these auto-gen reg has read-only bit, so put it as volatile */2671	/* volatile reg cannot be cached, so cannot be set when power off */2672	switch (reg) {2673	case AUDIO_TOP_CON0:2674	case AUDIO_TOP_CON1:2675	case AUDIO_TOP_CON3:2676	case AUDIO_TOP_CON4:2677	case AUDIO_TOP_CON5:2678	case AUDIO_TOP_CON6:2679	case ASYS_IRQ_CLR:2680	case ASYS_IRQ_STATUS:2681	case ASYS_IRQ_MON1:2682	case ASYS_IRQ_MON2:2683	case AFE_IRQ_MCU_CLR:2684	case AFE_IRQ_STATUS:2685	case AFE_IRQ3_CON_MON:2686	case AFE_IRQ_MCU_MON2:2687	case ADSP_IRQ_STATUS:2688	case AUDIO_TOP_STA0:2689	case AUDIO_TOP_STA1:2690	case AFE_GAIN1_CUR:2691	case AFE_GAIN2_CUR:2692	case AFE_IEC_BURST_INFO:2693	case AFE_IEC_CHL_STAT0:2694	case AFE_IEC_CHL_STAT1:2695	case AFE_IEC_CHR_STAT0:2696	case AFE_IEC_CHR_STAT1:2697	case AFE_SPDIFIN_CHSTS1:2698	case AFE_SPDIFIN_CHSTS2:2699	case AFE_SPDIFIN_CHSTS3:2700	case AFE_SPDIFIN_CHSTS4:2701	case AFE_SPDIFIN_CHSTS5:2702	case AFE_SPDIFIN_CHSTS6:2703	case AFE_SPDIFIN_DEBUG1:2704	case AFE_SPDIFIN_DEBUG2:2705	case AFE_SPDIFIN_DEBUG3:2706	case AFE_SPDIFIN_DEBUG4:2707	case AFE_SPDIFIN_EC:2708	case AFE_SPDIFIN_CKLOCK_CFG:2709	case AFE_SPDIFIN_BR_DBG1:2710	case AFE_SPDIFIN_CKFBDIV:2711	case AFE_SPDIFIN_INT_EXT:2712	case AFE_SPDIFIN_INT_EXT2:2713	case SPDIFIN_FREQ_STATUS:2714	case SPDIFIN_USERCODE1:2715	case SPDIFIN_USERCODE2:2716	case SPDIFIN_USERCODE3:2717	case SPDIFIN_USERCODE4:2718	case SPDIFIN_USERCODE5:2719	case SPDIFIN_USERCODE6:2720	case SPDIFIN_USERCODE7:2721	case SPDIFIN_USERCODE8:2722	case SPDIFIN_USERCODE9:2723	case SPDIFIN_USERCODE10:2724	case SPDIFIN_USERCODE11:2725	case SPDIFIN_USERCODE12:2726	case AFE_LINEIN_APLL_TUNER_MON:2727	case AFE_EARC_APLL_TUNER_MON:2728	case AFE_CM0_MON:2729	case AFE_CM1_MON:2730	case AFE_CM2_MON:2731	case AFE_MPHONE_MULTI_DET_MON0:2732	case AFE_MPHONE_MULTI_DET_MON1:2733	case AFE_MPHONE_MULTI_DET_MON2:2734	case AFE_MPHONE_MULTI2_DET_MON0:2735	case AFE_MPHONE_MULTI2_DET_MON1:2736	case AFE_MPHONE_MULTI2_DET_MON2:2737	case AFE_ADDA_MTKAIF_MON0:2738	case AFE_ADDA_MTKAIF_MON1:2739	case AFE_AUD_PAD_TOP:2740	case AFE_ADDA6_MTKAIF_MON0:2741	case AFE_ADDA6_MTKAIF_MON1:2742	case AFE_ADDA6_SRC_DEBUG_MON0:2743	case AFE_ADDA6_UL_SRC_MON0:2744	case AFE_ADDA6_UL_SRC_MON1:2745	case AFE_ASRC11_NEW_CON8:2746	case AFE_ASRC11_NEW_CON9:2747	case AFE_ASRC12_NEW_CON8:2748	case AFE_ASRC12_NEW_CON9:2749	case AFE_LRCK_CNT:2750	case AFE_DAC_MON0:2751	case AFE_DAC_CON0:2752	case AFE_DL2_CUR:2753	case AFE_DL3_CUR:2754	case AFE_DL6_CUR:2755	case AFE_DL7_CUR:2756	case AFE_DL8_CUR:2757	case AFE_DL10_CUR:2758	case AFE_DL11_CUR:2759	case AFE_UL1_CUR:2760	case AFE_UL2_CUR:2761	case AFE_UL3_CUR:2762	case AFE_UL4_CUR:2763	case AFE_UL5_CUR:2764	case AFE_UL6_CUR:2765	case AFE_UL8_CUR:2766	case AFE_UL9_CUR:2767	case AFE_UL10_CUR:2768	case AFE_DL8_CHK_SUM1:2769	case AFE_DL8_CHK_SUM2:2770	case AFE_DL8_CHK_SUM3:2771	case AFE_DL8_CHK_SUM4:2772	case AFE_DL8_CHK_SUM5:2773	case AFE_DL8_CHK_SUM6:2774	case AFE_DL10_CHK_SUM1:2775	case AFE_DL10_CHK_SUM2:2776	case AFE_DL10_CHK_SUM3:2777	case AFE_DL10_CHK_SUM4:2778	case AFE_DL10_CHK_SUM5:2779	case AFE_DL10_CHK_SUM6:2780	case AFE_DL11_CHK_SUM1:2781	case AFE_DL11_CHK_SUM2:2782	case AFE_DL11_CHK_SUM3:2783	case AFE_DL11_CHK_SUM4:2784	case AFE_DL11_CHK_SUM5:2785	case AFE_DL11_CHK_SUM6:2786	case AFE_UL1_CHK_SUM1:2787	case AFE_UL1_CHK_SUM2:2788	case AFE_UL2_CHK_SUM1:2789	case AFE_UL2_CHK_SUM2:2790	case AFE_UL3_CHK_SUM1:2791	case AFE_UL3_CHK_SUM2:2792	case AFE_UL4_CHK_SUM1:2793	case AFE_UL4_CHK_SUM2:2794	case AFE_UL5_CHK_SUM1:2795	case AFE_UL5_CHK_SUM2:2796	case AFE_UL6_CHK_SUM1:2797	case AFE_UL6_CHK_SUM2:2798	case AFE_UL8_CHK_SUM1:2799	case AFE_UL8_CHK_SUM2:2800	case AFE_DL2_CHK_SUM1:2801	case AFE_DL2_CHK_SUM2:2802	case AFE_DL3_CHK_SUM1:2803	case AFE_DL3_CHK_SUM2:2804	case AFE_DL6_CHK_SUM1:2805	case AFE_DL6_CHK_SUM2:2806	case AFE_DL7_CHK_SUM1:2807	case AFE_DL7_CHK_SUM2:2808	case AFE_UL9_CHK_SUM1:2809	case AFE_UL9_CHK_SUM2:2810	case AFE_BUS_MON1:2811	case UL1_MOD2AGT_CNT_LAT:2812	case UL2_MOD2AGT_CNT_LAT:2813	case UL3_MOD2AGT_CNT_LAT:2814	case UL4_MOD2AGT_CNT_LAT:2815	case UL5_MOD2AGT_CNT_LAT:2816	case UL6_MOD2AGT_CNT_LAT:2817	case UL8_MOD2AGT_CNT_LAT:2818	case UL9_MOD2AGT_CNT_LAT:2819	case UL10_MOD2AGT_CNT_LAT:2820	case AFE_MEMIF_BUF_FULL_MON:2821	case AFE_MEMIF_BUF_MON1:2822	case AFE_MEMIF_BUF_MON3:2823	case AFE_MEMIF_BUF_MON4:2824	case AFE_MEMIF_BUF_MON5:2825	case AFE_MEMIF_BUF_MON6:2826	case AFE_MEMIF_BUF_MON7:2827	case AFE_MEMIF_BUF_MON8:2828	case AFE_MEMIF_BUF_MON9:2829	case AFE_MEMIF_BUF_MON10:2830	case DL2_AGENT2MODULE_CNT:2831	case DL3_AGENT2MODULE_CNT:2832	case DL6_AGENT2MODULE_CNT:2833	case DL7_AGENT2MODULE_CNT:2834	case DL8_AGENT2MODULE_CNT:2835	case DL10_AGENT2MODULE_CNT:2836	case DL11_AGENT2MODULE_CNT:2837	case UL1_MODULE2AGENT_CNT:2838	case UL2_MODULE2AGENT_CNT:2839	case UL3_MODULE2AGENT_CNT:2840	case UL4_MODULE2AGENT_CNT:2841	case UL5_MODULE2AGENT_CNT:2842	case UL6_MODULE2AGENT_CNT:2843	case UL8_MODULE2AGENT_CNT:2844	case UL9_MODULE2AGENT_CNT:2845	case UL10_MODULE2AGENT_CNT:2846	case AFE_DMIC0_SRC_DEBUG_MON0:2847	case AFE_DMIC0_UL_SRC_MON0:2848	case AFE_DMIC0_UL_SRC_MON1:2849	case AFE_DMIC1_SRC_DEBUG_MON0:2850	case AFE_DMIC1_UL_SRC_MON0:2851	case AFE_DMIC1_UL_SRC_MON1:2852	case AFE_DMIC2_SRC_DEBUG_MON0:2853	case AFE_DMIC2_UL_SRC_MON0:2854	case AFE_DMIC2_UL_SRC_MON1:2855	case AFE_DMIC3_SRC_DEBUG_MON0:2856	case AFE_DMIC3_UL_SRC_MON0:2857	case AFE_DMIC3_UL_SRC_MON1:2858	case DMIC_GAIN1_CUR:2859	case DMIC_GAIN2_CUR:2860	case DMIC_GAIN3_CUR:2861	case DMIC_GAIN4_CUR:2862	case ETDM_IN1_MONITOR:2863	case ETDM_IN2_MONITOR:2864	case ETDM_OUT1_MONITOR:2865	case ETDM_OUT2_MONITOR:2866	case ETDM_OUT3_MONITOR:2867	case AFE_ADDA_SRC_DEBUG_MON0:2868	case AFE_ADDA_SRC_DEBUG_MON1:2869	case AFE_ADDA_DL_SDM_FIFO_MON:2870	case AFE_ADDA_DL_SRC_LCH_MON:2871	case AFE_ADDA_DL_SRC_RCH_MON:2872	case AFE_ADDA_DL_SDM_OUT_MON:2873	case AFE_GASRC0_NEW_CON8:2874	case AFE_GASRC0_NEW_CON9:2875	case AFE_GASRC0_NEW_CON12:2876	case AFE_GASRC1_NEW_CON8:2877	case AFE_GASRC1_NEW_CON9:2878	case AFE_GASRC1_NEW_CON12:2879	case AFE_GASRC2_NEW_CON8:2880	case AFE_GASRC2_NEW_CON9:2881	case AFE_GASRC2_NEW_CON12:2882	case AFE_GASRC3_NEW_CON8:2883	case AFE_GASRC3_NEW_CON9:2884	case AFE_GASRC3_NEW_CON12:2885	case AFE_GASRC4_NEW_CON8:2886	case AFE_GASRC4_NEW_CON9:2887	case AFE_GASRC4_NEW_CON12:2888	case AFE_GASRC5_NEW_CON8:2889	case AFE_GASRC5_NEW_CON9:2890	case AFE_GASRC5_NEW_CON12:2891	case AFE_GASRC6_NEW_CON8:2892	case AFE_GASRC6_NEW_CON9:2893	case AFE_GASRC6_NEW_CON12:2894	case AFE_GASRC7_NEW_CON8:2895	case AFE_GASRC7_NEW_CON9:2896	case AFE_GASRC7_NEW_CON12:2897	case AFE_GASRC8_NEW_CON8:2898	case AFE_GASRC8_NEW_CON9:2899	case AFE_GASRC8_NEW_CON12:2900	case AFE_GASRC9_NEW_CON8:2901	case AFE_GASRC9_NEW_CON9:2902	case AFE_GASRC9_NEW_CON12:2903	case AFE_GASRC10_NEW_CON8:2904	case AFE_GASRC10_NEW_CON9:2905	case AFE_GASRC10_NEW_CON12:2906	case AFE_GASRC11_NEW_CON8:2907	case AFE_GASRC11_NEW_CON9:2908	case AFE_GASRC11_NEW_CON12:2909		return true;2910	default:2911		return false;2912	};2913}2914 2915static const struct regmap_config mt8188_afe_regmap_config = {2916	.reg_bits = 32,2917	.reg_stride = 4,2918	.val_bits = 32,2919	.volatile_reg = mt8188_is_volatile_reg,2920	.max_register = AFE_MAX_REGISTER,2921	.num_reg_defaults_raw = ((AFE_MAX_REGISTER / 4) + 1),2922	.cache_type = REGCACHE_FLAT,2923};2924 2925#define AFE_IRQ_CLR_BITS (0x387)2926#define ASYS_IRQ_CLR_BITS (0xffff)2927 2928static irqreturn_t mt8188_afe_irq_handler(int irq_id, void *dev_id)2929{2930	struct mtk_base_afe *afe = dev_id;2931	unsigned int val = 0;2932	unsigned int asys_irq_clr_bits = 0;2933	unsigned int afe_irq_clr_bits = 0;2934	unsigned int irq_status_bits = 0;2935	unsigned int irq_clr_bits = 0;2936	unsigned int mcu_irq_mask = 0;2937	int i = 0;2938	int ret = 0;2939 2940	ret = regmap_read(afe->regmap, AFE_IRQ_STATUS, &val);2941	if (ret) {2942		dev_err(afe->dev, "%s irq status err\n", __func__);2943		afe_irq_clr_bits = AFE_IRQ_CLR_BITS;2944		asys_irq_clr_bits = ASYS_IRQ_CLR_BITS;2945		goto err_irq;2946	}2947 2948	ret = regmap_read(afe->regmap, AFE_IRQ_MASK, &mcu_irq_mask);2949	if (ret) {2950		dev_err(afe->dev, "%s read irq mask err\n", __func__);2951		afe_irq_clr_bits = AFE_IRQ_CLR_BITS;2952		asys_irq_clr_bits = ASYS_IRQ_CLR_BITS;2953		goto err_irq;2954	}2955 2956	/* only clr cpu irq */2957	val &= mcu_irq_mask;2958 2959	for (i = 0; i < MT8188_AFE_MEMIF_NUM; i++) {2960		struct mtk_base_afe_memif *memif = &afe->memif[i];2961		struct mtk_base_irq_data const *irq_data;2962 2963		if (memif->irq_usage < 0)2964			continue;2965 2966		irq_data = afe->irqs[memif->irq_usage].irq_data;2967 2968		irq_status_bits = BIT(irq_data->irq_status_shift);2969		irq_clr_bits = BIT(irq_data->irq_clr_shift);2970 2971		if (!(val & irq_status_bits))2972			continue;2973 2974		if (irq_data->irq_clr_reg == ASYS_IRQ_CLR)2975			asys_irq_clr_bits |= irq_clr_bits;2976		else2977			afe_irq_clr_bits |= irq_clr_bits;2978 2979		snd_pcm_period_elapsed(memif->substream);2980	}2981 2982err_irq:2983	/* clear irq */2984	if (asys_irq_clr_bits)2985		regmap_write(afe->regmap, ASYS_IRQ_CLR, asys_irq_clr_bits);2986	if (afe_irq_clr_bits)2987		regmap_write(afe->regmap, AFE_IRQ_MCU_CLR, afe_irq_clr_bits);2988 2989	return IRQ_HANDLED;2990}2991 2992static int mt8188_afe_runtime_suspend(struct device *dev)2993{2994	struct mtk_base_afe *afe = dev_get_drvdata(dev);2995	struct mt8188_afe_private *afe_priv = afe->platform_priv;2996 2997	if (!afe->regmap || afe_priv->pm_runtime_bypass_reg_ctl)2998		goto skip_regmap;2999 3000	mt8188_afe_disable_main_clock(afe);3001 3002	regcache_cache_only(afe->regmap, true);3003	regcache_mark_dirty(afe->regmap);3004 3005skip_regmap:3006	mt8188_afe_disable_reg_rw_clk(afe);3007 3008	return 0;3009}3010 3011static int mt8188_afe_runtime_resume(struct device *dev)3012{3013	struct mtk_base_afe *afe = dev_get_drvdata(dev);3014	struct mt8188_afe_private *afe_priv = afe->platform_priv;3015	struct arm_smccc_res res;3016 3017	arm_smccc_smc(MTK_SIP_AUDIO_CONTROL,3018		      MTK_AUDIO_SMC_OP_DOMAIN_SIDEBANDS,3019		      0, 0, 0, 0, 0, 0, &res);3020 3021	mt8188_afe_enable_reg_rw_clk(afe);3022 3023	if (!afe->regmap || afe_priv->pm_runtime_bypass_reg_ctl)3024		goto skip_regmap;3025 3026	regcache_cache_only(afe->regmap, false);3027	regcache_sync(afe->regmap);3028 3029	mt8188_afe_enable_main_clock(afe);3030skip_regmap:3031	return 0;3032}3033 3034static int init_memif_priv_data(struct mtk_base_afe *afe)3035{3036	struct mt8188_afe_private *afe_priv = afe->platform_priv;3037	struct mtk_dai_memif_priv *memif_priv;3038	int i;3039 3040	for (i = MT8188_AFE_MEMIF_START; i < MT8188_AFE_MEMIF_END; i++) {3041		memif_priv = devm_kzalloc(afe->dev,3042					  sizeof(struct mtk_dai_memif_priv),3043					  GFP_KERNEL);3044		if (!memif_priv)3045			return -ENOMEM;3046 3047		afe_priv->dai_priv[i] = memif_priv;3048	}3049 3050	return 0;3051}3052 3053static int mt8188_dai_memif_register(struct mtk_base_afe *afe)3054{3055	struct mtk_base_afe_dai *dai;3056 3057	dai = devm_kzalloc(afe->dev, sizeof(*dai), GFP_KERNEL);3058	if (!dai)3059		return -ENOMEM;3060 3061	list_add(&dai->list, &afe->sub_dais);3062 3063	dai->dai_drivers = mt8188_memif_dai_driver;3064	dai->num_dai_drivers = ARRAY_SIZE(mt8188_memif_dai_driver);3065 3066	dai->dapm_widgets = mt8188_memif_widgets;3067	dai->num_dapm_widgets = ARRAY_SIZE(mt8188_memif_widgets);3068	dai->dapm_routes = mt8188_memif_routes;3069	dai->num_dapm_routes = ARRAY_SIZE(mt8188_memif_routes);3070	dai->controls = mt8188_memif_controls;3071	dai->num_controls = ARRAY_SIZE(mt8188_memif_controls);3072 3073	return init_memif_priv_data(afe);3074}3075 3076typedef int (*dai_register_cb)(struct mtk_base_afe *);3077static const dai_register_cb dai_register_cbs[] = {3078	mt8188_dai_adda_register,3079	mt8188_dai_etdm_register,3080	mt8188_dai_pcm_register,3081	mt8188_dai_memif_register,3082};3083 3084static const struct reg_sequence mt8188_afe_reg_defaults[] = {3085	{ AFE_IRQ_MASK, 0x387ffff },3086	{ AFE_IRQ3_CON, BIT(30) },3087	{ AFE_IRQ9_CON, BIT(30) },3088	{ ETDM_IN1_CON4, 0x12000100 },3089	{ ETDM_IN2_CON4, 0x12000100 },3090};3091 3092static const struct reg_sequence mt8188_cg_patch[] = {3093	{ AUDIO_TOP_CON0, 0xfffffffb },3094	{ AUDIO_TOP_CON1, 0xfffffff8 },3095};3096 3097static int mt8188_afe_init_registers(struct mtk_base_afe *afe)3098{3099	return regmap_multi_reg_write(afe->regmap,3100				      mt8188_afe_reg_defaults,3101				      ARRAY_SIZE(mt8188_afe_reg_defaults));3102}3103 3104static int mt8188_afe_parse_of(struct mtk_base_afe *afe,3105			       struct device_node *np)3106{3107#if IS_ENABLED(CONFIG_SND_SOC_MT6359)3108	struct mt8188_afe_private *afe_priv = afe->platform_priv;3109 3110	afe_priv->topckgen = syscon_regmap_lookup_by_phandle(afe->dev->of_node,3111							     "mediatek,topckgen");3112	if (IS_ERR(afe_priv->topckgen))3113		return dev_err_probe(afe->dev,  PTR_ERR(afe_priv->topckgen),3114				     "%s() Cannot find topckgen controller\n",3115				     __func__);3116#endif3117	return 0;3118}3119 3120#define MT8188_DELAY_US 103121#define MT8188_TIMEOUT_US USEC_PER_SEC3122 3123static int bus_protect_enable(struct regmap *regmap)3124{3125	int ret;3126	u32 val;3127	u32 mask;3128 3129	val = 0;3130	mask = MT8188_TOP_AXI_PROT_EN_2_AUDIO_STEP1;3131	regmap_write(regmap, MT8188_TOP_AXI_PROT_EN_2_SET, mask);3132 3133	ret = regmap_read_poll_timeout(regmap, MT8188_TOP_AXI_PROT_EN_2_STA,3134				       val, (val & mask) == mask,3135				       MT8188_DELAY_US, MT8188_TIMEOUT_US);3136	if (ret)3137		return ret;3138 3139	val = 0;3140	mask = MT8188_TOP_AXI_PROT_EN_2_AUDIO_STEP2;3141	regmap_write(regmap, MT8188_TOP_AXI_PROT_EN_2_SET, mask);3142 3143	ret = regmap_read_poll_timeout(regmap, MT8188_TOP_AXI_PROT_EN_2_STA,3144				       val, (val & mask) == mask,3145				       MT8188_DELAY_US, MT8188_TIMEOUT_US);3146	return ret;3147}3148 3149static int bus_protect_disable(struct regmap *regmap)3150{3151	int ret;3152	u32 val;3153	u32 mask;3154 3155	val = 0;3156	mask = MT8188_TOP_AXI_PROT_EN_2_AUDIO_STEP2;3157	regmap_write(regmap, MT8188_TOP_AXI_PROT_EN_2_CLR, mask);3158 3159	ret = regmap_read_poll_timeout(regmap, MT8188_TOP_AXI_PROT_EN_2_STA,3160				       val, !(val & mask),3161				       MT8188_DELAY_US, MT8188_TIMEOUT_US);3162	if (ret)3163		return ret;3164 3165	val = 0;3166	mask = MT8188_TOP_AXI_PROT_EN_2_AUDIO_STEP1;3167	regmap_write(regmap, MT8188_TOP_AXI_PROT_EN_2_CLR, mask);3168 3169	ret = regmap_read_poll_timeout(regmap, MT8188_TOP_AXI_PROT_EN_2_STA,3170				       val, !(val & mask),3171				       MT8188_DELAY_US, MT8188_TIMEOUT_US);3172	return ret;3173}3174 3175static int mt8188_afe_pcm_dev_probe(struct platform_device *pdev)3176{3177	struct mtk_base_afe *afe;3178	struct mt8188_afe_private *afe_priv;3179	struct device *dev = &pdev->dev;3180	struct reset_control *rstc;3181	struct regmap *infra_ao;3182	int i, irq_id, ret;3183 3184	ret = of_reserved_mem_device_init(dev);3185	if (ret)3186		dev_dbg(dev, "failed to assign memory region: %d\n", ret);3187 3188	ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(33));3189	if (ret)3190		return ret;3191 3192	afe = devm_kzalloc(&pdev->dev, sizeof(*afe), GFP_KERNEL);3193	if (!afe)3194		return -ENOMEM;3195 3196	afe->platform_priv = devm_kzalloc(&pdev->dev, sizeof(*afe_priv),3197					  GFP_KERNEL);3198	if (!afe->platform_priv)3199		return -ENOMEM;3200 3201	afe_priv = afe->platform_priv;3202	afe->dev = &pdev->dev;3203 3204	afe->base_addr = devm_platform_ioremap_resource(pdev, 0);3205	if (IS_ERR(afe->base_addr))3206		return dev_err_probe(dev, PTR_ERR(afe->base_addr),3207				     "AFE base_addr not found\n");3208 3209	infra_ao = syscon_regmap_lookup_by_phandle(dev->of_node,3210						   "mediatek,infracfg");3211	if (IS_ERR(infra_ao))3212		return dev_err_probe(dev, PTR_ERR(infra_ao),3213				     "%s() Cannot find infra_ao controller\n",3214				     __func__);3215 3216	/* reset controller to reset audio regs before regmap cache */3217	rstc = devm_reset_control_get_exclusive(dev, "audiosys");3218	if (IS_ERR(rstc))3219		return dev_err_probe(dev, PTR_ERR(rstc),3220				     "could not get audiosys reset\n");3221 3222	ret = bus_protect_enable(infra_ao);3223	if (ret) {3224		dev_err(dev, "bus_protect_enable failed\n");3225		return ret;3226	}3227 3228	ret = reset_control_reset(rstc);3229	if (ret) {3230		dev_err(dev, "failed to trigger audio reset:%d\n", ret);3231		return ret;3232	}3233 3234	ret = bus_protect_disable(infra_ao);3235	if (ret) {3236		dev_err(dev, "bus_protect_disable failed\n");3237		return ret;3238	}3239 3240	/* initial audio related clock */3241	ret = mt8188_afe_init_clock(afe);3242	if (ret)3243		return dev_err_probe(dev, ret, "init clock error");3244 3245	spin_lock_init(&afe_priv->afe_ctrl_lock);3246 3247	mutex_init(&afe->irq_alloc_lock);3248 3249	/* irq initialize */3250	afe->irqs_size = MT8188_AFE_IRQ_NUM;3251	afe->irqs = devm_kcalloc(dev, afe->irqs_size, sizeof(*afe->irqs),3252				 GFP_KERNEL);3253	if (!afe->irqs)3254		return -ENOMEM;3255 3256	for (i = 0; i < afe->irqs_size; i++)3257		afe->irqs[i].irq_data = &irq_data[i];3258 3259	/* init memif */3260	afe->memif_size = MT8188_AFE_MEMIF_NUM;3261	afe->memif = devm_kcalloc(dev, afe->memif_size, sizeof(*afe->memif),3262				  GFP_KERNEL);3263	if (!afe->memif)3264		return -ENOMEM;3265 3266	for (i = 0; i < afe->memif_size; i++) {3267		afe->memif[i].data = &memif_data[i];3268		afe->memif[i].irq_usage = mt8188_afe_memif_const_irqs[i];3269		afe->memif[i].const_irq = 1;3270		afe->irqs[afe->memif[i].irq_usage].irq_occupyed = true;3271	}3272 3273	/* request irq */3274	irq_id = platform_get_irq(pdev, 0);3275	if (irq_id < 0)3276		return dev_err_probe(dev, irq_id, "no irq found");3277 3278	ret = devm_request_irq(dev, irq_id, mt8188_afe_irq_handler,3279			       IRQF_TRIGGER_NONE, "asys-isr", (void *)afe);3280	if (ret)3281		return dev_err_probe(dev, ret, "could not request_irq for asys-isr\n");3282 3283	/* init sub_dais */3284	INIT_LIST_HEAD(&afe->sub_dais);3285 3286	for (i = 0; i < ARRAY_SIZE(dai_register_cbs); i++) {3287		ret = dai_register_cbs[i](afe);3288		if (ret)3289			return dev_err_probe(dev, ret, "dai register i %d fail\n", i);3290	}3291 3292	/* init dai_driver and component_driver */3293	ret = mtk_afe_combine_sub_dai(afe);3294	if (ret)3295		return dev_err_probe(dev, ret, "mtk_afe_combine_sub_dai fail\n");3296 3297	afe->mtk_afe_hardware = &mt8188_afe_hardware;3298	afe->memif_fs = mt8188_memif_fs;3299	afe->irq_fs = mt8188_irq_fs;3300 3301	afe->runtime_resume = mt8188_afe_runtime_resume;3302	afe->runtime_suspend = mt8188_afe_runtime_suspend;3303 3304	platform_set_drvdata(pdev, afe);3305 3306	ret = mt8188_afe_parse_of(afe, pdev->dev.of_node);3307	if (ret)3308		return ret;3309 3310	ret = devm_pm_runtime_enable(dev);3311	if (ret)3312		return ret;3313 3314	/* enable clock for regcache get default value from hw */3315	afe_priv->pm_runtime_bypass_reg_ctl = true;3316	ret = pm_runtime_resume_and_get(dev);3317	if (ret)3318		return dev_err_probe(dev, ret, "failed to resume device\n");3319 3320	afe->regmap = devm_regmap_init_mmio(&pdev->dev, afe->base_addr,3321					    &mt8188_afe_regmap_config);3322	if (IS_ERR(afe->regmap)) {3323		ret = PTR_ERR(afe->regmap);3324		goto err_pm_put;3325	}3326 3327	ret = regmap_register_patch(afe->regmap, mt8188_cg_patch,3328				    ARRAY_SIZE(mt8188_cg_patch));3329	if (ret < 0) {3330		dev_info(dev, "Failed to apply cg patch\n");3331		goto err_pm_put;3332	}3333 3334	/* register component */3335	ret = devm_snd_soc_register_component(dev, &mtk_afe_pcm_platform,3336					      afe->dai_drivers, afe->num_dai_drivers);3337	if (ret) {3338		dev_warn(dev, "err_platform\n");3339		goto err_pm_put;3340	}3341 3342	mt8188_afe_init_registers(afe);3343 3344	pm_runtime_put_sync(&pdev->dev);3345	afe_priv->pm_runtime_bypass_reg_ctl = false;3346 3347	regcache_cache_only(afe->regmap, true);3348	regcache_mark_dirty(afe->regmap);3349 3350	return 0;3351err_pm_put:3352	pm_runtime_put_sync(dev);3353 3354	return ret;3355}3356 3357static const struct of_device_id mt8188_afe_pcm_dt_match[] = {3358	{ .compatible = "mediatek,mt8188-afe", },3359	{},3360};3361MODULE_DEVICE_TABLE(of, mt8188_afe_pcm_dt_match);3362 3363static const struct dev_pm_ops mt8188_afe_pm_ops = {3364	SET_RUNTIME_PM_OPS(mt8188_afe_runtime_suspend,3365			   mt8188_afe_runtime_resume, NULL)3366};3367 3368static struct platform_driver mt8188_afe_pcm_driver = {3369	.driver = {3370		   .name = "mt8188-audio",3371		   .of_match_table = mt8188_afe_pcm_dt_match,3372		   .pm = &mt8188_afe_pm_ops,3373	},3374	.probe = mt8188_afe_pcm_dev_probe,3375};3376 3377module_platform_driver(mt8188_afe_pcm_driver);3378 3379MODULE_DESCRIPTION("MediaTek SoC AFE platform driver for ALSA 8188");3380MODULE_AUTHOR("Chun-Chia.Chiu <chun-chia.chiu@mediatek.com>");3381MODULE_LICENSE("GPL");3382