2336 lines · c
1// SPDX-License-Identifier: GPL-2.02//3// Mediatek ALSA SoC AFE platform driver for 81924//5// Copyright (c) 2020 MediaTek Inc.6// Author: Shane Chien <shane.chien@mediatek.com>7//8 9#include <linux/delay.h>10#include <linux/dma-mapping.h>11#include <linux/module.h>12#include <linux/mfd/syscon.h>13#include <linux/of.h>14#include <linux/of_address.h>15#include <linux/pm_runtime.h>16#include <linux/reset.h>17#include <sound/soc.h>18 19#include "../common/mtk-afe-fe-dai.h"20#include "../common/mtk-afe-platform-driver.h"21 22#include "mt8192-afe-common.h"23#include "mt8192-afe-clk.h"24#include "mt8192-afe-gpio.h"25#include "mt8192-interconnection.h"26 27static const struct snd_pcm_hardware mt8192_afe_hardware = {28 .info = (SNDRV_PCM_INFO_MMAP |29 SNDRV_PCM_INFO_INTERLEAVED |30 SNDRV_PCM_INFO_MMAP_VALID),31 .formats = (SNDRV_PCM_FMTBIT_S16_LE |32 SNDRV_PCM_FMTBIT_S24_LE |33 SNDRV_PCM_FMTBIT_S32_LE),34 .period_bytes_min = 96,35 .period_bytes_max = 4 * 48 * 1024,36 .periods_min = 2,37 .periods_max = 256,38 .buffer_bytes_max = 4 * 48 * 1024,39 .fifo_size = 0,40};41 42static int mt8192_memif_fs(struct snd_pcm_substream *substream,43 unsigned int rate)44{45 struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream);46 struct snd_soc_component *component =47 snd_soc_rtdcom_lookup(rtd, AFE_PCM_NAME);48 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(component);49 int id = snd_soc_rtd_to_cpu(rtd, 0)->id;50 51 return mt8192_rate_transform(afe->dev, rate, id);52}53 54static int mt8192_get_dai_fs(struct mtk_base_afe *afe,55 int dai_id, unsigned int rate)56{57 return mt8192_rate_transform(afe->dev, rate, dai_id);58}59 60static int mt8192_irq_fs(struct snd_pcm_substream *substream, unsigned int rate)61{62 struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream);63 struct snd_soc_component *component =64 snd_soc_rtdcom_lookup(rtd, AFE_PCM_NAME);65 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(component);66 67 return mt8192_general_rate_transform(afe->dev, rate);68}69 70static int mt8192_get_memif_pbuf_size(struct snd_pcm_substream *substream)71{72 struct snd_pcm_runtime *runtime = substream->runtime;73 74 if ((runtime->period_size * 1000) / runtime->rate > 10)75 return MT8192_MEMIF_PBUF_SIZE_256_BYTES;76 else77 return MT8192_MEMIF_PBUF_SIZE_32_BYTES;78}79 80#define MTK_PCM_RATES (SNDRV_PCM_RATE_8000_48000 |\81 SNDRV_PCM_RATE_88200 |\82 SNDRV_PCM_RATE_96000 |\83 SNDRV_PCM_RATE_176400 |\84 SNDRV_PCM_RATE_192000)85 86#define MTK_PCM_DAI_RATES (SNDRV_PCM_RATE_8000 |\87 SNDRV_PCM_RATE_16000 |\88 SNDRV_PCM_RATE_32000 |\89 SNDRV_PCM_RATE_48000)90 91#define MTK_PCM_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\92 SNDRV_PCM_FMTBIT_S24_LE |\93 SNDRV_PCM_FMTBIT_S32_LE)94 95static struct snd_soc_dai_driver mt8192_memif_dai_driver[] = {96 /* FE DAIs: memory intefaces to CPU */97 {98 .name = "DL1",99 .id = MT8192_MEMIF_DL1,100 .playback = {101 .stream_name = "DL1",102 .channels_min = 1,103 .channels_max = 2,104 .rates = MTK_PCM_RATES,105 .formats = MTK_PCM_FORMATS,106 },107 .ops = &mtk_afe_fe_ops,108 },109 {110 .name = "DL12",111 .id = MT8192_MEMIF_DL12,112 .playback = {113 .stream_name = "DL12",114 .channels_min = 1,115 .channels_max = 2,116 .rates = MTK_PCM_RATES,117 .formats = MTK_PCM_FORMATS,118 },119 .ops = &mtk_afe_fe_ops,120 },121 {122 .name = "DL2",123 .id = MT8192_MEMIF_DL2,124 .playback = {125 .stream_name = "DL2",126 .channels_min = 1,127 .channels_max = 2,128 .rates = MTK_PCM_RATES,129 .formats = MTK_PCM_FORMATS,130 },131 .ops = &mtk_afe_fe_ops,132 },133 {134 .name = "DL3",135 .id = MT8192_MEMIF_DL3,136 .playback = {137 .stream_name = "DL3",138 .channels_min = 1,139 .channels_max = 2,140 .rates = MTK_PCM_RATES,141 .formats = MTK_PCM_FORMATS,142 },143 .ops = &mtk_afe_fe_ops,144 },145 {146 .name = "DL4",147 .id = MT8192_MEMIF_DL4,148 .playback = {149 .stream_name = "DL4",150 .channels_min = 1,151 .channels_max = 2,152 .rates = MTK_PCM_RATES,153 .formats = MTK_PCM_FORMATS,154 },155 .ops = &mtk_afe_fe_ops,156 },157 {158 .name = "DL5",159 .id = MT8192_MEMIF_DL5,160 .playback = {161 .stream_name = "DL5",162 .channels_min = 1,163 .channels_max = 2,164 .rates = MTK_PCM_RATES,165 .formats = MTK_PCM_FORMATS,166 },167 .ops = &mtk_afe_fe_ops,168 },169 {170 .name = "DL6",171 .id = MT8192_MEMIF_DL6,172 .playback = {173 .stream_name = "DL6",174 .channels_min = 1,175 .channels_max = 2,176 .rates = MTK_PCM_RATES,177 .formats = MTK_PCM_FORMATS,178 },179 .ops = &mtk_afe_fe_ops,180 },181 {182 .name = "DL7",183 .id = MT8192_MEMIF_DL7,184 .playback = {185 .stream_name = "DL7",186 .channels_min = 1,187 .channels_max = 2,188 .rates = MTK_PCM_RATES,189 .formats = MTK_PCM_FORMATS,190 },191 .ops = &mtk_afe_fe_ops,192 },193 {194 .name = "DL8",195 .id = MT8192_MEMIF_DL8,196 .playback = {197 .stream_name = "DL8",198 .channels_min = 1,199 .channels_max = 2,200 .rates = MTK_PCM_RATES,201 .formats = MTK_PCM_FORMATS,202 },203 .ops = &mtk_afe_fe_ops,204 },205 {206 .name = "DL9",207 .id = MT8192_MEMIF_DL9,208 .playback = {209 .stream_name = "DL9",210 .channels_min = 1,211 .channels_max = 2,212 .rates = MTK_PCM_RATES,213 .formats = MTK_PCM_FORMATS,214 },215 .ops = &mtk_afe_fe_ops,216 },217 {218 .name = "UL1",219 .id = MT8192_MEMIF_VUL12,220 .capture = {221 .stream_name = "UL1",222 .channels_min = 1,223 .channels_max = 4,224 .rates = MTK_PCM_RATES,225 .formats = MTK_PCM_FORMATS,226 },227 .ops = &mtk_afe_fe_ops,228 },229 {230 .name = "UL2",231 .id = MT8192_MEMIF_AWB,232 .capture = {233 .stream_name = "UL2",234 .channels_min = 1,235 .channels_max = 2,236 .rates = MTK_PCM_RATES,237 .formats = MTK_PCM_FORMATS,238 },239 .ops = &mtk_afe_fe_ops,240 },241 {242 .name = "UL3",243 .id = MT8192_MEMIF_VUL2,244 .capture = {245 .stream_name = "UL3",246 .channels_min = 1,247 .channels_max = 2,248 .rates = MTK_PCM_RATES,249 .formats = MTK_PCM_FORMATS,250 },251 .ops = &mtk_afe_fe_ops,252 },253 {254 .name = "UL4",255 .id = MT8192_MEMIF_AWB2,256 .capture = {257 .stream_name = "UL4",258 .channels_min = 1,259 .channels_max = 2,260 .rates = MTK_PCM_RATES,261 .formats = MTK_PCM_FORMATS,262 },263 .ops = &mtk_afe_fe_ops,264 },265 {266 .name = "UL5",267 .id = MT8192_MEMIF_VUL3,268 .capture = {269 .stream_name = "UL5",270 .channels_min = 1,271 .channels_max = 2,272 .rates = MTK_PCM_RATES,273 .formats = MTK_PCM_FORMATS,274 },275 .ops = &mtk_afe_fe_ops,276 },277 {278 .name = "UL6",279 .id = MT8192_MEMIF_VUL4,280 .capture = {281 .stream_name = "UL6",282 .channels_min = 1,283 .channels_max = 2,284 .rates = MTK_PCM_RATES,285 .formats = MTK_PCM_FORMATS,286 },287 .ops = &mtk_afe_fe_ops,288 },289 {290 .name = "UL7",291 .id = MT8192_MEMIF_VUL5,292 .capture = {293 .stream_name = "UL7",294 .channels_min = 1,295 .channels_max = 2,296 .rates = MTK_PCM_RATES,297 .formats = MTK_PCM_FORMATS,298 },299 .ops = &mtk_afe_fe_ops,300 },301 {302 .name = "UL8",303 .id = MT8192_MEMIF_VUL6,304 .capture = {305 .stream_name = "UL8",306 .channels_min = 1,307 .channels_max = 2,308 .rates = MTK_PCM_RATES,309 .formats = MTK_PCM_FORMATS,310 },311 .ops = &mtk_afe_fe_ops,312 },313 {314 .name = "UL_MONO_1",315 .id = MT8192_MEMIF_MOD_DAI,316 .capture = {317 .stream_name = "UL_MONO_1",318 .channels_min = 1,319 .channels_max = 2,320 .rates = MTK_PCM_DAI_RATES,321 .formats = MTK_PCM_FORMATS,322 },323 .ops = &mtk_afe_fe_ops,324 },325 {326 .name = "UL_MONO_2",327 .id = MT8192_MEMIF_DAI,328 .capture = {329 .stream_name = "UL_MONO_2",330 .channels_min = 1,331 .channels_max = 2,332 .rates = MTK_PCM_DAI_RATES,333 .formats = MTK_PCM_FORMATS,334 },335 .ops = &mtk_afe_fe_ops,336 },337 {338 .name = "UL_MONO_3",339 .id = MT8192_MEMIF_DAI2,340 .capture = {341 .stream_name = "UL_MONO_3",342 .channels_min = 1,343 .channels_max = 2,344 .rates = MTK_PCM_DAI_RATES,345 .formats = MTK_PCM_FORMATS,346 },347 .ops = &mtk_afe_fe_ops,348 },349 {350 .name = "HDMI",351 .id = MT8192_MEMIF_HDMI,352 .playback = {353 .stream_name = "HDMI",354 .channels_min = 2,355 .channels_max = 8,356 .rates = MTK_PCM_RATES,357 .formats = MTK_PCM_FORMATS,358 },359 .ops = &mtk_afe_fe_ops,360 },361};362 363static int ul_tinyconn_event(struct snd_soc_dapm_widget *w,364 struct snd_kcontrol *kcontrol,365 int event)366{367 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);368 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);369 unsigned int reg_shift;370 unsigned int reg_mask_shift;371 372 dev_dbg(afe->dev, "%s(), event 0x%x\n", __func__, event);373 374 if (strstr(w->name, "UL1")) {375 reg_shift = VUL1_USE_TINY_SFT;376 reg_mask_shift = VUL1_USE_TINY_MASK_SFT;377 } else if (strstr(w->name, "UL2")) {378 reg_shift = VUL2_USE_TINY_SFT;379 reg_mask_shift = VUL2_USE_TINY_MASK_SFT;380 } else if (strstr(w->name, "UL3")) {381 reg_shift = VUL12_USE_TINY_SFT;382 reg_mask_shift = VUL12_USE_TINY_MASK_SFT;383 } else if (strstr(w->name, "UL4")) {384 reg_shift = AWB2_USE_TINY_SFT;385 reg_mask_shift = AWB2_USE_TINY_MASK_SFT;386 } else {387 reg_shift = AWB2_USE_TINY_SFT;388 reg_mask_shift = AWB2_USE_TINY_MASK_SFT;389 dev_warn(afe->dev, "%s(), err widget name %s, default use UL4",390 __func__, w->name);391 }392 393 switch (event) {394 case SND_SOC_DAPM_PRE_PMU:395 regmap_update_bits(afe->regmap, AFE_MEMIF_CONN, reg_mask_shift,396 0x1 << reg_shift);397 break;398 case SND_SOC_DAPM_PRE_PMD:399 regmap_update_bits(afe->regmap, AFE_MEMIF_CONN, reg_mask_shift,400 0x0 << reg_shift);401 break;402 default:403 break;404 }405 406 return 0;407}408 409/* dma widget & routes*/410static const struct snd_kcontrol_new memif_ul1_ch1_mix[] = {411 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN21,412 I_ADDA_UL_CH1, 1, 0),413 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN21,414 I_ADDA_UL_CH2, 1, 0),415 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN21,416 I_ADDA_UL_CH3, 1, 0),417};418 419static const struct snd_kcontrol_new memif_ul1_ch2_mix[] = {420 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN22,421 I_ADDA_UL_CH1, 1, 0),422 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN22,423 I_ADDA_UL_CH2, 1, 0),424 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN22,425 I_ADDA_UL_CH3, 1, 0),426 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4", AFE_CONN22,427 I_ADDA_UL_CH4, 1, 0),428};429 430static const struct snd_kcontrol_new memif_ul1_ch3_mix[] = {431 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN9,432 I_ADDA_UL_CH1, 1, 0),433 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN9,434 I_ADDA_UL_CH2, 1, 0),435 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN9,436 I_ADDA_UL_CH3, 1, 0),437};438 439static const struct snd_kcontrol_new memif_ul1_ch4_mix[] = {440 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN10,441 I_ADDA_UL_CH1, 1, 0),442 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN10,443 I_ADDA_UL_CH2, 1, 0),444 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN10,445 I_ADDA_UL_CH3, 1, 0),446 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4", AFE_CONN10,447 I_ADDA_UL_CH4, 1, 0),448};449 450static const struct snd_kcontrol_new memif_ul2_ch1_mix[] = {451 SOC_DAPM_SINGLE_AUTODISABLE("I2S0_CH1", AFE_CONN5,452 I_I2S0_CH1, 1, 0),453 SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH1", AFE_CONN5,454 I_DL1_CH1, 1, 0),455 SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH1", AFE_CONN5,456 I_DL12_CH1, 1, 0),457 SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1", AFE_CONN5,458 I_DL2_CH1, 1, 0),459 SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH1", AFE_CONN5,460 I_DL3_CH1, 1, 0),461 SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH1", AFE_CONN5_1,462 I_DL4_CH1, 1, 0),463 SOC_DAPM_SINGLE_AUTODISABLE("DL5_CH1", AFE_CONN5_1,464 I_DL5_CH1, 1, 0),465 SOC_DAPM_SINGLE_AUTODISABLE("DL6_CH1", AFE_CONN5_1,466 I_DL6_CH1, 1, 0),467 SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH1", AFE_CONN5,468 I_PCM_1_CAP_CH1, 1, 0),469 SOC_DAPM_SINGLE_AUTODISABLE("PCM_2_CAP_CH1", AFE_CONN5,470 I_PCM_2_CAP_CH1, 1, 0),471 SOC_DAPM_SINGLE_AUTODISABLE("I2S2_CH1", AFE_CONN5,472 I_I2S2_CH1, 1, 0),473 SOC_DAPM_SINGLE_AUTODISABLE("I2S6_CH1", AFE_CONN5_1,474 I_I2S6_CH1, 1, 0),475 SOC_DAPM_SINGLE_AUTODISABLE("I2S8_CH1", AFE_CONN5_1,476 I_I2S8_CH1, 1, 0),477 SOC_DAPM_SINGLE_AUTODISABLE("CONNSYS_I2S_CH1", AFE_CONN5_1,478 I_CONNSYS_I2S_CH1, 1, 0),479 SOC_DAPM_SINGLE_AUTODISABLE("SRC_1_OUT_CH1", AFE_CONN5_1,480 I_SRC_1_OUT_CH1, 1, 0),481};482 483static const struct snd_kcontrol_new memif_ul2_ch2_mix[] = {484 SOC_DAPM_SINGLE_AUTODISABLE("I2S0_CH2", AFE_CONN6,485 I_I2S0_CH2, 1, 0),486 SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH2", AFE_CONN6,487 I_DL1_CH2, 1, 0),488 SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH2", AFE_CONN6,489 I_DL12_CH2, 1, 0),490 SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH2", AFE_CONN6,491 I_DL2_CH2, 1, 0),492 SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH2", AFE_CONN6,493 I_DL3_CH2, 1, 0),494 SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH2", AFE_CONN6_1,495 I_DL4_CH2, 1, 0),496 SOC_DAPM_SINGLE_AUTODISABLE("DL5_CH2", AFE_CONN6_1,497 I_DL5_CH2, 1, 0),498 SOC_DAPM_SINGLE_AUTODISABLE("DL6_CH2", AFE_CONN6_1,499 I_DL6_CH2, 1, 0),500 SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH1", AFE_CONN6,501 I_PCM_1_CAP_CH1, 1, 0),502 SOC_DAPM_SINGLE_AUTODISABLE("PCM_2_CAP_CH1", AFE_CONN6,503 I_PCM_2_CAP_CH1, 1, 0),504 SOC_DAPM_SINGLE_AUTODISABLE("I2S2_CH2", AFE_CONN6,505 I_I2S2_CH2, 1, 0),506 SOC_DAPM_SINGLE_AUTODISABLE("I2S6_CH2", AFE_CONN6_1,507 I_I2S6_CH2, 1, 0),508 SOC_DAPM_SINGLE_AUTODISABLE("I2S8_CH2", AFE_CONN6_1,509 I_I2S8_CH2, 1, 0),510 SOC_DAPM_SINGLE_AUTODISABLE("CONNSYS_I2S_CH2", AFE_CONN6_1,511 I_CONNSYS_I2S_CH2, 1, 0),512 SOC_DAPM_SINGLE_AUTODISABLE("SRC_1_OUT_CH2", AFE_CONN6_1,513 I_SRC_1_OUT_CH2, 1, 0),514};515 516static const struct snd_kcontrol_new memif_ul3_ch1_mix[] = {517 SOC_DAPM_SINGLE_AUTODISABLE("CONNSYS_I2S_CH1", AFE_CONN32_1,518 I_CONNSYS_I2S_CH1, 1, 0),519 SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH1", AFE_CONN32,520 I_DL1_CH1, 1, 0),521 SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1", AFE_CONN32,522 I_DL2_CH1, 1, 0),523};524 525static const struct snd_kcontrol_new memif_ul3_ch2_mix[] = {526 SOC_DAPM_SINGLE_AUTODISABLE("CONNSYS_I2S_CH2", AFE_CONN33_1,527 I_CONNSYS_I2S_CH2, 1, 0),528};529 530static const struct snd_kcontrol_new memif_ul4_ch1_mix[] = {531 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN38,532 I_ADDA_UL_CH1, 1, 0),533 SOC_DAPM_SINGLE_AUTODISABLE("I2S0_CH1", AFE_CONN38,534 I_I2S0_CH1, 1, 0),535};536 537static const struct snd_kcontrol_new memif_ul4_ch2_mix[] = {538 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN39,539 I_ADDA_UL_CH2, 1, 0),540 SOC_DAPM_SINGLE_AUTODISABLE("I2S0_CH2", AFE_CONN39,541 I_I2S0_CH2, 1, 0),542};543 544static const struct snd_kcontrol_new memif_ul5_ch1_mix[] = {545 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN44,546 I_ADDA_UL_CH1, 1, 0),547};548 549static const struct snd_kcontrol_new memif_ul5_ch2_mix[] = {550 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN45,551 I_ADDA_UL_CH2, 1, 0),552};553 554static const struct snd_kcontrol_new memif_ul6_ch1_mix[] = {555 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN46,556 I_ADDA_UL_CH1, 1, 0),557 SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH1", AFE_CONN46,558 I_DL1_CH1, 1, 0),559 SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH1", AFE_CONN46,560 I_DL12_CH1, 1, 0),561 SOC_DAPM_SINGLE_AUTODISABLE("DL6_CH1", AFE_CONN46_1,562 I_DL6_CH1, 1, 0),563 SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1", AFE_CONN46,564 I_DL2_CH1, 1, 0),565 SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH1", AFE_CONN46,566 I_DL3_CH1, 1, 0),567 SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH1", AFE_CONN46_1,568 I_DL4_CH1, 1, 0),569 SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH1", AFE_CONN46,570 I_PCM_1_CAP_CH1, 1, 0),571 SOC_DAPM_SINGLE_AUTODISABLE("PCM_2_CAP_CH1", AFE_CONN46,572 I_PCM_2_CAP_CH1, 1, 0),573};574 575static const struct snd_kcontrol_new memif_ul6_ch2_mix[] = {576 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN47,577 I_ADDA_UL_CH2, 1, 0),578 SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH2", AFE_CONN47,579 I_DL1_CH2, 1, 0),580 SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH2", AFE_CONN47,581 I_DL12_CH2, 1, 0),582 SOC_DAPM_SINGLE_AUTODISABLE("DL6_CH2", AFE_CONN47_1,583 I_DL6_CH2, 1, 0),584 SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH2", AFE_CONN47,585 I_DL2_CH2, 1, 0),586 SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH2", AFE_CONN47,587 I_DL3_CH2, 1, 0),588 SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH2", AFE_CONN47_1,589 I_DL4_CH2, 1, 0),590 SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH1", AFE_CONN47,591 I_PCM_1_CAP_CH1, 1, 0),592 SOC_DAPM_SINGLE_AUTODISABLE("PCM_2_CAP_CH1", AFE_CONN47,593 I_PCM_2_CAP_CH1, 1, 0),594};595 596static const struct snd_kcontrol_new memif_ul7_ch1_mix[] = {597 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN48,598 I_ADDA_UL_CH1, 1, 0),599};600 601static const struct snd_kcontrol_new memif_ul7_ch2_mix[] = {602 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN49,603 I_ADDA_UL_CH2, 1, 0),604};605 606static const struct snd_kcontrol_new memif_ul8_ch1_mix[] = {607 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN50,608 I_ADDA_UL_CH1, 1, 0),609};610 611static const struct snd_kcontrol_new memif_ul8_ch2_mix[] = {612 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN51,613 I_ADDA_UL_CH2, 1, 0),614};615 616static const struct snd_kcontrol_new memif_ul_mono_1_mix[] = {617 SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH1", AFE_CONN12,618 I_PCM_1_CAP_CH1, 1, 0),619 SOC_DAPM_SINGLE_AUTODISABLE("PCM_2_CAP_CH1", AFE_CONN12,620 I_PCM_2_CAP_CH1, 1, 0),621};622 623static const struct snd_kcontrol_new memif_ul_mono_2_mix[] = {624 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN11,625 I_ADDA_UL_CH1, 1, 0),626};627 628static const struct snd_kcontrol_new memif_ul_mono_3_mix[] = {629 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN35,630 I_ADDA_UL_CH1, 1, 0),631};632 633/* TINYCONN MUX */634enum {635 TINYCONN_CH1_MUX_I2S0 = 0x14,636 TINYCONN_CH2_MUX_I2S0 = 0x15,637 TINYCONN_CH1_MUX_I2S6 = 0x1a,638 TINYCONN_CH2_MUX_I2S6 = 0x1b,639 TINYCONN_CH1_MUX_I2S8 = 0x1c,640 TINYCONN_CH2_MUX_I2S8 = 0x1d,641 TINYCONN_MUX_NONE = 0x1f,642};643 644static const char * const tinyconn_mux_map[] = {645 "NONE",646 "I2S0_CH1",647 "I2S0_CH2",648 "I2S6_CH1",649 "I2S6_CH2",650 "I2S8_CH1",651 "I2S8_CH2",652};653 654static int tinyconn_mux_map_value[] = {655 TINYCONN_MUX_NONE,656 TINYCONN_CH1_MUX_I2S0,657 TINYCONN_CH2_MUX_I2S0,658 TINYCONN_CH1_MUX_I2S6,659 TINYCONN_CH2_MUX_I2S6,660 TINYCONN_CH1_MUX_I2S8,661 TINYCONN_CH2_MUX_I2S8,662};663 664static SOC_VALUE_ENUM_SINGLE_DECL(ul4_tinyconn_ch1_mux_map_enum,665 AFE_TINY_CONN0,666 O_2_CFG_SFT,667 O_2_CFG_MASK,668 tinyconn_mux_map,669 tinyconn_mux_map_value);670static SOC_VALUE_ENUM_SINGLE_DECL(ul4_tinyconn_ch2_mux_map_enum,671 AFE_TINY_CONN0,672 O_3_CFG_SFT,673 O_3_CFG_MASK,674 tinyconn_mux_map,675 tinyconn_mux_map_value);676 677static const struct snd_kcontrol_new ul4_tinyconn_ch1_mux_control =678 SOC_DAPM_ENUM("UL4_TINYCONN_CH1_MUX", ul4_tinyconn_ch1_mux_map_enum);679static const struct snd_kcontrol_new ul4_tinyconn_ch2_mux_control =680 SOC_DAPM_ENUM("UL4_TINYCONN_CH2_MUX", ul4_tinyconn_ch2_mux_map_enum);681 682static const struct snd_soc_dapm_widget mt8192_memif_widgets[] = {683 /* inter-connections */684 SND_SOC_DAPM_MIXER("UL1_CH1", SND_SOC_NOPM, 0, 0,685 memif_ul1_ch1_mix, ARRAY_SIZE(memif_ul1_ch1_mix)),686 SND_SOC_DAPM_MIXER("UL1_CH2", SND_SOC_NOPM, 0, 0,687 memif_ul1_ch2_mix, ARRAY_SIZE(memif_ul1_ch2_mix)),688 SND_SOC_DAPM_MIXER("UL1_CH3", SND_SOC_NOPM, 0, 0,689 memif_ul1_ch3_mix, ARRAY_SIZE(memif_ul1_ch3_mix)),690 SND_SOC_DAPM_MIXER("UL1_CH4", SND_SOC_NOPM, 0, 0,691 memif_ul1_ch4_mix, ARRAY_SIZE(memif_ul1_ch4_mix)),692 693 SND_SOC_DAPM_MIXER("UL2_CH1", SND_SOC_NOPM, 0, 0,694 memif_ul2_ch1_mix, ARRAY_SIZE(memif_ul2_ch1_mix)),695 SND_SOC_DAPM_MIXER("UL2_CH2", SND_SOC_NOPM, 0, 0,696 memif_ul2_ch2_mix, ARRAY_SIZE(memif_ul2_ch2_mix)),697 698 SND_SOC_DAPM_MIXER("UL3_CH1", SND_SOC_NOPM, 0, 0,699 memif_ul3_ch1_mix, ARRAY_SIZE(memif_ul3_ch1_mix)),700 SND_SOC_DAPM_MIXER("UL3_CH2", SND_SOC_NOPM, 0, 0,701 memif_ul3_ch2_mix, ARRAY_SIZE(memif_ul3_ch2_mix)),702 703 SND_SOC_DAPM_MIXER("UL4_CH1", SND_SOC_NOPM, 0, 0,704 memif_ul4_ch1_mix, ARRAY_SIZE(memif_ul4_ch1_mix)),705 SND_SOC_DAPM_MIXER("UL4_CH2", SND_SOC_NOPM, 0, 0,706 memif_ul4_ch2_mix, ARRAY_SIZE(memif_ul4_ch2_mix)),707 SND_SOC_DAPM_MUX_E("UL4_TINYCONN_CH1_MUX", SND_SOC_NOPM, 0, 0,708 &ul4_tinyconn_ch1_mux_control,709 ul_tinyconn_event,710 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD),711 SND_SOC_DAPM_MUX_E("UL4_TINYCONN_CH2_MUX", SND_SOC_NOPM, 0, 0,712 &ul4_tinyconn_ch2_mux_control,713 ul_tinyconn_event,714 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD),715 716 SND_SOC_DAPM_MIXER("UL5_CH1", SND_SOC_NOPM, 0, 0,717 memif_ul5_ch1_mix, ARRAY_SIZE(memif_ul5_ch1_mix)),718 SND_SOC_DAPM_MIXER("UL5_CH2", SND_SOC_NOPM, 0, 0,719 memif_ul5_ch2_mix, ARRAY_SIZE(memif_ul5_ch2_mix)),720 721 SND_SOC_DAPM_MIXER("UL6_CH1", SND_SOC_NOPM, 0, 0,722 memif_ul6_ch1_mix, ARRAY_SIZE(memif_ul6_ch1_mix)),723 SND_SOC_DAPM_MIXER("UL6_CH2", SND_SOC_NOPM, 0, 0,724 memif_ul6_ch2_mix, ARRAY_SIZE(memif_ul6_ch2_mix)),725 726 SND_SOC_DAPM_MIXER("UL7_CH1", SND_SOC_NOPM, 0, 0,727 memif_ul7_ch1_mix, ARRAY_SIZE(memif_ul7_ch1_mix)),728 SND_SOC_DAPM_MIXER("UL7_CH2", SND_SOC_NOPM, 0, 0,729 memif_ul7_ch2_mix, ARRAY_SIZE(memif_ul7_ch2_mix)),730 731 SND_SOC_DAPM_MIXER("UL8_CH1", SND_SOC_NOPM, 0, 0,732 memif_ul8_ch1_mix, ARRAY_SIZE(memif_ul8_ch1_mix)),733 SND_SOC_DAPM_MIXER("UL8_CH2", SND_SOC_NOPM, 0, 0,734 memif_ul8_ch2_mix, ARRAY_SIZE(memif_ul8_ch2_mix)),735 736 SND_SOC_DAPM_MIXER("UL_MONO_1_CH1", SND_SOC_NOPM, 0, 0,737 memif_ul_mono_1_mix,738 ARRAY_SIZE(memif_ul_mono_1_mix)),739 740 SND_SOC_DAPM_MIXER("UL_MONO_2_CH1", SND_SOC_NOPM, 0, 0,741 memif_ul_mono_2_mix,742 ARRAY_SIZE(memif_ul_mono_2_mix)),743 744 SND_SOC_DAPM_MIXER("UL_MONO_3_CH1", SND_SOC_NOPM, 0, 0,745 memif_ul_mono_3_mix,746 ARRAY_SIZE(memif_ul_mono_3_mix)),747 748 SND_SOC_DAPM_INPUT("UL1_VIRTUAL_INPUT"),749 SND_SOC_DAPM_INPUT("UL2_VIRTUAL_INPUT"),750 SND_SOC_DAPM_INPUT("UL6_VIRTUAL_INPUT"),751};752 753static const struct snd_soc_dapm_route mt8192_memif_routes[] = {754 {"UL1", NULL, "UL1_CH1"},755 {"UL1", NULL, "UL1_CH2"},756 {"UL1", NULL, "UL1_CH3"},757 {"UL1", NULL, "UL1_CH4"},758 {"UL1_CH1", "ADDA_UL_CH1", "ADDA_UL_Mux"},759 {"UL1_CH1", "ADDA_UL_CH2", "ADDA_UL_Mux"},760 {"UL1_CH1", "ADDA_UL_CH3", "ADDA_CH34_UL_Mux"},761 {"UL1_CH2", "ADDA_UL_CH1", "ADDA_UL_Mux"},762 {"UL1_CH2", "ADDA_UL_CH2", "ADDA_UL_Mux"},763 {"UL1_CH2", "ADDA_UL_CH3", "ADDA_CH34_UL_Mux"},764 {"UL1_CH2", "ADDA_UL_CH4", "ADDA_CH34_UL_Mux"},765 {"UL1_CH3", "ADDA_UL_CH1", "ADDA_UL_Mux"},766 {"UL1_CH3", "ADDA_UL_CH2", "ADDA_UL_Mux"},767 {"UL1_CH3", "ADDA_UL_CH3", "ADDA_CH34_UL_Mux"},768 {"UL1_CH4", "ADDA_UL_CH1", "ADDA_UL_Mux"},769 {"UL1_CH4", "ADDA_UL_CH2", "ADDA_UL_Mux"},770 {"UL1_CH4", "ADDA_UL_CH3", "ADDA_CH34_UL_Mux"},771 {"UL1_CH4", "ADDA_UL_CH4", "ADDA_CH34_UL_Mux"},772 773 {"UL2", NULL, "UL2_CH1"},774 {"UL2", NULL, "UL2_CH2"},775 {"UL2_CH1", "I2S0_CH1", "I2S0"},776 {"UL2_CH2", "I2S0_CH2", "I2S0"},777 {"UL2_CH1", "I2S2_CH1", "I2S2"},778 {"UL2_CH2", "I2S2_CH2", "I2S2"},779 {"UL2_CH1", "I2S6_CH1", "I2S6"},780 {"UL2_CH2", "I2S6_CH2", "I2S6"},781 {"UL2_CH1", "I2S8_CH1", "I2S8"},782 {"UL2_CH2", "I2S8_CH2", "I2S8"},783 784 {"UL2_CH1", "PCM_1_CAP_CH1", "PCM 1 Capture"},785 {"UL2_CH2", "PCM_1_CAP_CH1", "PCM 1 Capture"},786 {"UL2_CH1", "PCM_2_CAP_CH1", "PCM 2 Capture"},787 {"UL2_CH2", "PCM_2_CAP_CH1", "PCM 2 Capture"},788 789 {"UL_MONO_1", NULL, "UL_MONO_1_CH1"},790 {"UL_MONO_1_CH1", "PCM_1_CAP_CH1", "PCM 1 Capture"},791 {"UL_MONO_1_CH1", "PCM_2_CAP_CH1", "PCM 2 Capture"},792 793 {"UL_MONO_2", NULL, "UL_MONO_2_CH1"},794 {"UL_MONO_2_CH1", "ADDA_UL_CH1", "ADDA_UL_Mux"},795 796 {"UL_MONO_3", NULL, "UL_MONO_3_CH1"},797 {"UL_MONO_3_CH1", "ADDA_UL_CH1", "ADDA_UL_Mux"},798 799 {"UL2_CH1", "CONNSYS_I2S_CH1", "Connsys I2S"},800 {"UL2_CH2", "CONNSYS_I2S_CH2", "Connsys I2S"},801 802 {"UL3", NULL, "UL3_CH1"},803 {"UL3", NULL, "UL3_CH2"},804 {"UL3_CH1", "CONNSYS_I2S_CH1", "Connsys I2S"},805 {"UL3_CH2", "CONNSYS_I2S_CH2", "Connsys I2S"},806 807 {"UL4", NULL, "UL4_CH1"},808 {"UL4", NULL, "UL4_CH2"},809 {"UL4", NULL, "UL4_TINYCONN_CH1_MUX"},810 {"UL4", NULL, "UL4_TINYCONN_CH2_MUX"},811 {"UL4_CH1", "ADDA_UL_CH1", "ADDA_UL_Mux"},812 {"UL4_CH2", "ADDA_UL_CH2", "ADDA_UL_Mux"},813 {"UL4_CH1", "I2S0_CH1", "I2S0"},814 {"UL4_CH2", "I2S0_CH2", "I2S0"},815 {"UL4_TINYCONN_CH1_MUX", "I2S0_CH1", "I2S0"},816 {"UL4_TINYCONN_CH2_MUX", "I2S0_CH2", "I2S0"},817 818 {"UL5", NULL, "UL5_CH1"},819 {"UL5", NULL, "UL5_CH2"},820 {"UL5_CH1", "ADDA_UL_CH1", "ADDA_UL_Mux"},821 {"UL5_CH2", "ADDA_UL_CH2", "ADDA_UL_Mux"},822 823 {"UL6", NULL, "UL6_CH1"},824 {"UL6", NULL, "UL6_CH2"},825 826 {"UL6_CH1", "ADDA_UL_CH1", "ADDA_UL_Mux"},827 {"UL6_CH2", "ADDA_UL_CH2", "ADDA_UL_Mux"},828 {"UL6_CH1", "PCM_1_CAP_CH1", "PCM 1 Capture"},829 {"UL6_CH2", "PCM_1_CAP_CH1", "PCM 1 Capture"},830 {"UL6_CH1", "PCM_2_CAP_CH1", "PCM 2 Capture"},831 {"UL6_CH2", "PCM_2_CAP_CH1", "PCM 2 Capture"},832 833 {"UL7", NULL, "UL7_CH1"},834 {"UL7", NULL, "UL7_CH2"},835 {"UL7_CH1", "ADDA_UL_CH1", "ADDA_UL_Mux"},836 {"UL7_CH2", "ADDA_UL_CH2", "ADDA_UL_Mux"},837 838 {"UL8", NULL, "UL8_CH1"},839 {"UL8", NULL, "UL8_CH2"},840 {"UL8_CH1", "ADDA_UL_CH1", "ADDA_UL_Mux"},841 {"UL8_CH2", "ADDA_UL_CH2", "ADDA_UL_Mux"},842};843 844static const struct mtk_base_memif_data memif_data[MT8192_MEMIF_NUM] = {845 [MT8192_MEMIF_DL1] = {846 .name = "DL1",847 .id = MT8192_MEMIF_DL1,848 .reg_ofs_base = AFE_DL1_BASE,849 .reg_ofs_cur = AFE_DL1_CUR,850 .reg_ofs_end = AFE_DL1_END,851 .reg_ofs_base_msb = AFE_DL1_BASE_MSB,852 .reg_ofs_cur_msb = AFE_DL1_CUR_MSB,853 .reg_ofs_end_msb = AFE_DL1_END_MSB,854 .fs_reg = AFE_DL1_CON0,855 .fs_shift = DL1_MODE_SFT,856 .fs_maskbit = DL1_MODE_MASK,857 .mono_reg = AFE_DL1_CON0,858 .mono_shift = DL1_MONO_SFT,859 .enable_reg = AFE_DAC_CON0,860 .enable_shift = DL1_ON_SFT,861 .hd_reg = AFE_DL1_CON0,862 .hd_shift = DL1_HD_MODE_SFT,863 .hd_align_reg = AFE_DL1_CON0,864 .hd_align_mshift = DL1_HALIGN_SFT,865 .pbuf_reg = AFE_DL1_CON0,866 .pbuf_shift = DL1_PBUF_SIZE_SFT,867 .minlen_reg = AFE_DL1_CON0,868 .minlen_shift = DL1_MINLEN_SFT,869 },870 [MT8192_MEMIF_DL12] = {871 .name = "DL12",872 .id = MT8192_MEMIF_DL12,873 .reg_ofs_base = AFE_DL12_BASE,874 .reg_ofs_cur = AFE_DL12_CUR,875 .reg_ofs_end = AFE_DL12_END,876 .reg_ofs_base_msb = AFE_DL12_BASE_MSB,877 .reg_ofs_cur_msb = AFE_DL12_CUR_MSB,878 .reg_ofs_end_msb = AFE_DL12_END_MSB,879 .fs_reg = AFE_DL12_CON0,880 .fs_shift = DL12_MODE_SFT,881 .fs_maskbit = DL12_MODE_MASK,882 .mono_reg = AFE_DL12_CON0,883 .mono_shift = DL12_MONO_SFT,884 .enable_reg = AFE_DAC_CON0,885 .enable_shift = DL12_ON_SFT,886 .hd_reg = AFE_DL12_CON0,887 .hd_shift = DL12_HD_MODE_SFT,888 .hd_align_reg = AFE_DL12_CON0,889 .hd_align_mshift = DL12_HALIGN_SFT,890 .pbuf_reg = AFE_DL12_CON0,891 .pbuf_shift = DL12_PBUF_SIZE_SFT,892 .minlen_reg = AFE_DL12_CON0,893 .minlen_shift = DL12_MINLEN_SFT,894 },895 [MT8192_MEMIF_DL2] = {896 .name = "DL2",897 .id = MT8192_MEMIF_DL2,898 .reg_ofs_base = AFE_DL2_BASE,899 .reg_ofs_cur = AFE_DL2_CUR,900 .reg_ofs_end = AFE_DL2_END,901 .reg_ofs_base_msb = AFE_DL2_BASE_MSB,902 .reg_ofs_cur_msb = AFE_DL2_CUR_MSB,903 .reg_ofs_end_msb = AFE_DL2_END_MSB,904 .fs_reg = AFE_DL2_CON0,905 .fs_shift = DL2_MODE_SFT,906 .fs_maskbit = DL2_MODE_MASK,907 .mono_reg = AFE_DL2_CON0,908 .mono_shift = DL2_MONO_SFT,909 .enable_reg = AFE_DAC_CON0,910 .enable_shift = DL2_ON_SFT,911 .hd_reg = AFE_DL2_CON0,912 .hd_shift = DL2_HD_MODE_SFT,913 .hd_align_reg = AFE_DL2_CON0,914 .hd_align_mshift = DL2_HALIGN_SFT,915 .pbuf_reg = AFE_DL2_CON0,916 .pbuf_shift = DL2_PBUF_SIZE_SFT,917 .minlen_reg = AFE_DL2_CON0,918 .minlen_shift = DL2_MINLEN_SFT,919 },920 [MT8192_MEMIF_DL3] = {921 .name = "DL3",922 .id = MT8192_MEMIF_DL3,923 .reg_ofs_base = AFE_DL3_BASE,924 .reg_ofs_cur = AFE_DL3_CUR,925 .reg_ofs_end = AFE_DL3_END,926 .reg_ofs_base_msb = AFE_DL3_BASE_MSB,927 .reg_ofs_cur_msb = AFE_DL3_CUR_MSB,928 .reg_ofs_end_msb = AFE_DL3_END_MSB,929 .fs_reg = AFE_DL3_CON0,930 .fs_shift = DL3_MODE_SFT,931 .fs_maskbit = DL3_MODE_MASK,932 .mono_reg = AFE_DL3_CON0,933 .mono_shift = DL3_MONO_SFT,934 .enable_reg = AFE_DAC_CON0,935 .enable_shift = DL3_ON_SFT,936 .hd_reg = AFE_DL3_CON0,937 .hd_shift = DL3_HD_MODE_SFT,938 .hd_align_reg = AFE_DL3_CON0,939 .hd_align_mshift = DL3_HALIGN_SFT,940 .pbuf_reg = AFE_DL3_CON0,941 .pbuf_shift = DL3_PBUF_SIZE_SFT,942 .minlen_reg = AFE_DL3_CON0,943 .minlen_shift = DL3_MINLEN_SFT,944 },945 [MT8192_MEMIF_DL4] = {946 .name = "DL4",947 .id = MT8192_MEMIF_DL4,948 .reg_ofs_base = AFE_DL4_BASE,949 .reg_ofs_cur = AFE_DL4_CUR,950 .reg_ofs_end = AFE_DL4_END,951 .reg_ofs_base_msb = AFE_DL4_BASE_MSB,952 .reg_ofs_cur_msb = AFE_DL4_CUR_MSB,953 .reg_ofs_end_msb = AFE_DL4_END_MSB,954 .fs_reg = AFE_DL4_CON0,955 .fs_shift = DL4_MODE_SFT,956 .fs_maskbit = DL4_MODE_MASK,957 .mono_reg = AFE_DL4_CON0,958 .mono_shift = DL4_MONO_SFT,959 .enable_reg = AFE_DAC_CON0,960 .enable_shift = DL4_ON_SFT,961 .hd_reg = AFE_DL4_CON0,962 .hd_shift = DL4_HD_MODE_SFT,963 .hd_align_reg = AFE_DL4_CON0,964 .hd_align_mshift = DL4_HALIGN_SFT,965 .pbuf_reg = AFE_DL4_CON0,966 .pbuf_shift = DL4_PBUF_SIZE_SFT,967 .minlen_reg = AFE_DL4_CON0,968 .minlen_shift = DL4_MINLEN_SFT,969 },970 [MT8192_MEMIF_DL5] = {971 .name = "DL5",972 .id = MT8192_MEMIF_DL5,973 .reg_ofs_base = AFE_DL5_BASE,974 .reg_ofs_cur = AFE_DL5_CUR,975 .reg_ofs_end = AFE_DL5_END,976 .reg_ofs_base_msb = AFE_DL5_BASE_MSB,977 .reg_ofs_cur_msb = AFE_DL5_CUR_MSB,978 .reg_ofs_end_msb = AFE_DL5_END_MSB,979 .fs_reg = AFE_DL5_CON0,980 .fs_shift = DL5_MODE_SFT,981 .fs_maskbit = DL5_MODE_MASK,982 .mono_reg = AFE_DL5_CON0,983 .mono_shift = DL5_MONO_SFT,984 .enable_reg = AFE_DAC_CON0,985 .enable_shift = DL5_ON_SFT,986 .hd_reg = AFE_DL5_CON0,987 .hd_shift = DL5_HD_MODE_SFT,988 .hd_align_reg = AFE_DL5_CON0,989 .hd_align_mshift = DL5_HALIGN_SFT,990 .pbuf_reg = AFE_DL5_CON0,991 .pbuf_shift = DL5_PBUF_SIZE_SFT,992 .minlen_reg = AFE_DL5_CON0,993 .minlen_shift = DL5_MINLEN_SFT,994 },995 [MT8192_MEMIF_DL6] = {996 .name = "DL6",997 .id = MT8192_MEMIF_DL6,998 .reg_ofs_base = AFE_DL6_BASE,999 .reg_ofs_cur = AFE_DL6_CUR,1000 .reg_ofs_end = AFE_DL6_END,1001 .reg_ofs_base_msb = AFE_DL6_BASE_MSB,1002 .reg_ofs_cur_msb = AFE_DL6_CUR_MSB,1003 .reg_ofs_end_msb = AFE_DL6_END_MSB,1004 .fs_reg = AFE_DL6_CON0,1005 .fs_shift = DL6_MODE_SFT,1006 .fs_maskbit = DL6_MODE_MASK,1007 .mono_reg = AFE_DL6_CON0,1008 .mono_shift = DL6_MONO_SFT,1009 .enable_reg = AFE_DAC_CON0,1010 .enable_shift = DL6_ON_SFT,1011 .hd_reg = AFE_DL6_CON0,1012 .hd_shift = DL6_HD_MODE_SFT,1013 .hd_align_reg = AFE_DL6_CON0,1014 .hd_align_mshift = DL6_HALIGN_SFT,1015 .pbuf_reg = AFE_DL6_CON0,1016 .pbuf_shift = DL6_PBUF_SIZE_SFT,1017 .minlen_reg = AFE_DL6_CON0,1018 .minlen_shift = DL6_MINLEN_SFT,1019 },1020 [MT8192_MEMIF_DL7] = {1021 .name = "DL7",1022 .id = MT8192_MEMIF_DL7,1023 .reg_ofs_base = AFE_DL7_BASE,1024 .reg_ofs_cur = AFE_DL7_CUR,1025 .reg_ofs_end = AFE_DL7_END,1026 .reg_ofs_base_msb = AFE_DL7_BASE_MSB,1027 .reg_ofs_cur_msb = AFE_DL7_CUR_MSB,1028 .reg_ofs_end_msb = AFE_DL7_END_MSB,1029 .fs_reg = AFE_DL7_CON0,1030 .fs_shift = DL7_MODE_SFT,1031 .fs_maskbit = DL7_MODE_MASK,1032 .mono_reg = AFE_DL7_CON0,1033 .mono_shift = DL7_MONO_SFT,1034 .enable_reg = AFE_DAC_CON0,1035 .enable_shift = DL7_ON_SFT,1036 .hd_reg = AFE_DL7_CON0,1037 .hd_shift = DL7_HD_MODE_SFT,1038 .hd_align_reg = AFE_DL7_CON0,1039 .hd_align_mshift = DL7_HALIGN_SFT,1040 .pbuf_reg = AFE_DL7_CON0,1041 .pbuf_shift = DL7_PBUF_SIZE_SFT,1042 .minlen_reg = AFE_DL7_CON0,1043 .minlen_shift = DL7_MINLEN_SFT,1044 },1045 [MT8192_MEMIF_DL8] = {1046 .name = "DL8",1047 .id = MT8192_MEMIF_DL8,1048 .reg_ofs_base = AFE_DL8_BASE,1049 .reg_ofs_cur = AFE_DL8_CUR,1050 .reg_ofs_end = AFE_DL8_END,1051 .reg_ofs_base_msb = AFE_DL8_BASE_MSB,1052 .reg_ofs_cur_msb = AFE_DL8_CUR_MSB,1053 .reg_ofs_end_msb = AFE_DL8_END_MSB,1054 .fs_reg = AFE_DL8_CON0,1055 .fs_shift = DL8_MODE_SFT,1056 .fs_maskbit = DL8_MODE_MASK,1057 .mono_reg = AFE_DL8_CON0,1058 .mono_shift = DL8_MONO_SFT,1059 .enable_reg = AFE_DAC_CON0,1060 .enable_shift = DL8_ON_SFT,1061 .hd_reg = AFE_DL8_CON0,1062 .hd_shift = DL8_HD_MODE_SFT,1063 .hd_align_reg = AFE_DL8_CON0,1064 .hd_align_mshift = DL8_HALIGN_SFT,1065 .pbuf_reg = AFE_DL8_CON0,1066 .pbuf_shift = DL8_PBUF_SIZE_SFT,1067 .minlen_reg = AFE_DL8_CON0,1068 .minlen_shift = DL8_MINLEN_SFT,1069 },1070 [MT8192_MEMIF_DL9] = {1071 .name = "DL9",1072 .id = MT8192_MEMIF_DL9,1073 .reg_ofs_base = AFE_DL9_BASE,1074 .reg_ofs_cur = AFE_DL9_CUR,1075 .reg_ofs_end = AFE_DL9_END,1076 .reg_ofs_base_msb = AFE_DL9_BASE_MSB,1077 .reg_ofs_cur_msb = AFE_DL9_CUR_MSB,1078 .reg_ofs_end_msb = AFE_DL9_END_MSB,1079 .fs_reg = AFE_DL9_CON0,1080 .fs_shift = DL9_MODE_SFT,1081 .fs_maskbit = DL9_MODE_MASK,1082 .mono_reg = AFE_DL9_CON0,1083 .mono_shift = DL9_MONO_SFT,1084 .enable_reg = AFE_DAC_CON0,1085 .enable_shift = DL9_ON_SFT,1086 .hd_reg = AFE_DL9_CON0,1087 .hd_shift = DL9_HD_MODE_SFT,1088 .hd_align_reg = AFE_DL9_CON0,1089 .hd_align_mshift = DL9_HALIGN_SFT,1090 .pbuf_reg = AFE_DL9_CON0,1091 .pbuf_shift = DL9_PBUF_SIZE_SFT,1092 .minlen_reg = AFE_DL9_CON0,1093 .minlen_shift = DL9_MINLEN_SFT,1094 },1095 [MT8192_MEMIF_DAI] = {1096 .name = "DAI",1097 .id = MT8192_MEMIF_DAI,1098 .reg_ofs_base = AFE_DAI_BASE,1099 .reg_ofs_cur = AFE_DAI_CUR,1100 .reg_ofs_end = AFE_DAI_END,1101 .reg_ofs_base_msb = AFE_DAI_BASE_MSB,1102 .reg_ofs_cur_msb = AFE_DAI_CUR_MSB,1103 .reg_ofs_end_msb = AFE_DAI_END_MSB,1104 .fs_reg = AFE_DAI_CON0,1105 .fs_shift = DAI_MODE_SFT,1106 .fs_maskbit = DAI_MODE_MASK,1107 .mono_reg = AFE_DAI_CON0,1108 .mono_shift = DAI_DUPLICATE_WR_SFT,1109 .mono_invert = 1,1110 .enable_reg = AFE_DAC_CON0,1111 .enable_shift = DAI_ON_SFT,1112 .hd_reg = AFE_DAI_CON0,1113 .hd_shift = DAI_HD_MODE_SFT,1114 .hd_align_reg = AFE_DAI_CON0,1115 .hd_align_mshift = DAI_HALIGN_SFT,1116 },1117 [MT8192_MEMIF_MOD_DAI] = {1118 .name = "MOD_DAI",1119 .id = MT8192_MEMIF_MOD_DAI,1120 .reg_ofs_base = AFE_MOD_DAI_BASE,1121 .reg_ofs_cur = AFE_MOD_DAI_CUR,1122 .reg_ofs_end = AFE_MOD_DAI_END,1123 .reg_ofs_base_msb = AFE_MOD_DAI_BASE_MSB,1124 .reg_ofs_cur_msb = AFE_MOD_DAI_CUR_MSB,1125 .reg_ofs_end_msb = AFE_MOD_DAI_END_MSB,1126 .fs_reg = AFE_MOD_DAI_CON0,1127 .fs_shift = MOD_DAI_MODE_SFT,1128 .fs_maskbit = MOD_DAI_MODE_MASK,1129 .mono_reg = AFE_MOD_DAI_CON0,1130 .mono_shift = MOD_DAI_DUPLICATE_WR_SFT,1131 .mono_invert = 1,1132 .enable_reg = AFE_DAC_CON0,1133 .enable_shift = MOD_DAI_ON_SFT,1134 .hd_reg = AFE_MOD_DAI_CON0,1135 .hd_shift = MOD_DAI_HD_MODE_SFT,1136 .hd_align_reg = AFE_MOD_DAI_CON0,1137 .hd_align_mshift = MOD_DAI_HALIGN_SFT,1138 },1139 [MT8192_MEMIF_DAI2] = {1140 .name = "DAI2",1141 .id = MT8192_MEMIF_DAI2,1142 .reg_ofs_base = AFE_DAI2_BASE,1143 .reg_ofs_cur = AFE_DAI2_CUR,1144 .reg_ofs_end = AFE_DAI2_END,1145 .reg_ofs_base_msb = AFE_DAI2_BASE_MSB,1146 .reg_ofs_cur_msb = AFE_DAI2_CUR_MSB,1147 .reg_ofs_end_msb = AFE_DAI2_END_MSB,1148 .fs_reg = AFE_DAI2_CON0,1149 .fs_shift = DAI2_MODE_SFT,1150 .fs_maskbit = DAI2_MODE_MASK,1151 .mono_reg = AFE_DAI2_CON0,1152 .mono_shift = DAI2_DUPLICATE_WR_SFT,1153 .mono_invert = 1,1154 .enable_reg = AFE_DAC_CON0,1155 .enable_shift = DAI2_ON_SFT,1156 .hd_reg = AFE_DAI2_CON0,1157 .hd_shift = DAI2_HD_MODE_SFT,1158 .hd_align_reg = AFE_DAI2_CON0,1159 .hd_align_mshift = DAI2_HALIGN_SFT,1160 },1161 [MT8192_MEMIF_VUL12] = {1162 .name = "VUL12",1163 .id = MT8192_MEMIF_VUL12,1164 .reg_ofs_base = AFE_VUL12_BASE,1165 .reg_ofs_cur = AFE_VUL12_CUR,1166 .reg_ofs_end = AFE_VUL12_END,1167 .reg_ofs_base_msb = AFE_VUL12_BASE_MSB,1168 .reg_ofs_cur_msb = AFE_VUL12_CUR_MSB,1169 .reg_ofs_end_msb = AFE_VUL12_END_MSB,1170 .fs_reg = AFE_VUL12_CON0,1171 .fs_shift = VUL12_MODE_SFT,1172 .fs_maskbit = VUL12_MODE_MASK,1173 .mono_reg = AFE_VUL12_CON0,1174 .mono_shift = VUL12_MONO_SFT,1175 .quad_ch_reg = AFE_VUL12_CON0,1176 .quad_ch_shift = VUL12_4CH_EN_SFT,1177 .quad_ch_mask = VUL12_4CH_EN_MASK,1178 .enable_reg = AFE_DAC_CON0,1179 .enable_shift = VUL12_ON_SFT,1180 .hd_reg = AFE_VUL12_CON0,1181 .hd_shift = VUL12_HD_MODE_SFT,1182 .hd_align_reg = AFE_VUL12_CON0,1183 .hd_align_mshift = VUL12_HALIGN_SFT,1184 },1185 [MT8192_MEMIF_VUL2] = {1186 .name = "VUL2",1187 .id = MT8192_MEMIF_VUL2,1188 .reg_ofs_base = AFE_VUL2_BASE,1189 .reg_ofs_cur = AFE_VUL2_CUR,1190 .reg_ofs_end = AFE_VUL2_END,1191 .reg_ofs_base_msb = AFE_VUL2_BASE_MSB,1192 .reg_ofs_cur_msb = AFE_VUL2_CUR_MSB,1193 .reg_ofs_end_msb = AFE_VUL2_END_MSB,1194 .fs_reg = AFE_VUL2_CON0,1195 .fs_shift = VUL2_MODE_SFT,1196 .fs_maskbit = VUL2_MODE_MASK,1197 .mono_reg = AFE_VUL2_CON0,1198 .mono_shift = VUL2_MONO_SFT,1199 .enable_reg = AFE_DAC_CON0,1200 .enable_shift = VUL2_ON_SFT,1201 .hd_reg = AFE_VUL2_CON0,1202 .hd_shift = VUL2_HD_MODE_SFT,1203 .hd_align_reg = AFE_VUL2_CON0,1204 .hd_align_mshift = VUL2_HALIGN_SFT,1205 },1206 [MT8192_MEMIF_AWB] = {1207 .name = "AWB",1208 .id = MT8192_MEMIF_AWB,1209 .reg_ofs_base = AFE_AWB_BASE,1210 .reg_ofs_cur = AFE_AWB_CUR,1211 .reg_ofs_end = AFE_AWB_END,1212 .reg_ofs_base_msb = AFE_AWB_BASE_MSB,1213 .reg_ofs_cur_msb = AFE_AWB_CUR_MSB,1214 .reg_ofs_end_msb = AFE_AWB_END_MSB,1215 .fs_reg = AFE_AWB_CON0,1216 .fs_shift = AWB_MODE_SFT,1217 .fs_maskbit = AWB_MODE_MASK,1218 .mono_reg = AFE_AWB_CON0,1219 .mono_shift = AWB_MONO_SFT,1220 .enable_reg = AFE_DAC_CON0,1221 .enable_shift = AWB_ON_SFT,1222 .hd_reg = AFE_AWB_CON0,1223 .hd_shift = AWB_HD_MODE_SFT,1224 .hd_align_reg = AFE_AWB_CON0,1225 .hd_align_mshift = AWB_HALIGN_SFT,1226 },1227 [MT8192_MEMIF_AWB2] = {1228 .name = "AWB2",1229 .id = MT8192_MEMIF_AWB2,1230 .reg_ofs_base = AFE_AWB2_BASE,1231 .reg_ofs_cur = AFE_AWB2_CUR,1232 .reg_ofs_end = AFE_AWB2_END,1233 .reg_ofs_base_msb = AFE_AWB2_BASE_MSB,1234 .reg_ofs_cur_msb = AFE_AWB2_CUR_MSB,1235 .reg_ofs_end_msb = AFE_AWB2_END_MSB,1236 .fs_reg = AFE_AWB2_CON0,1237 .fs_shift = AWB2_MODE_SFT,1238 .fs_maskbit = AWB2_MODE_MASK,1239 .mono_reg = AFE_AWB2_CON0,1240 .mono_shift = AWB2_MONO_SFT,1241 .enable_reg = AFE_DAC_CON0,1242 .enable_shift = AWB2_ON_SFT,1243 .hd_reg = AFE_AWB2_CON0,1244 .hd_shift = AWB2_HD_MODE_SFT,1245 .hd_align_reg = AFE_AWB2_CON0,1246 .hd_align_mshift = AWB2_HALIGN_SFT,1247 },1248 [MT8192_MEMIF_VUL3] = {1249 .name = "VUL3",1250 .id = MT8192_MEMIF_VUL3,1251 .reg_ofs_base = AFE_VUL3_BASE,1252 .reg_ofs_cur = AFE_VUL3_CUR,1253 .reg_ofs_end = AFE_VUL3_END,1254 .reg_ofs_base_msb = AFE_VUL3_BASE_MSB,1255 .reg_ofs_cur_msb = AFE_VUL3_CUR_MSB,1256 .reg_ofs_end_msb = AFE_VUL3_END_MSB,1257 .fs_reg = AFE_VUL3_CON0,1258 .fs_shift = VUL3_MODE_SFT,1259 .fs_maskbit = VUL3_MODE_MASK,1260 .mono_reg = AFE_VUL3_CON0,1261 .mono_shift = VUL3_MONO_SFT,1262 .enable_reg = AFE_DAC_CON0,1263 .enable_shift = VUL3_ON_SFT,1264 .hd_reg = AFE_VUL3_CON0,1265 .hd_shift = VUL3_HD_MODE_SFT,1266 .hd_align_reg = AFE_VUL3_CON0,1267 .hd_align_mshift = VUL3_HALIGN_SFT,1268 },1269 [MT8192_MEMIF_VUL4] = {1270 .name = "VUL4",1271 .id = MT8192_MEMIF_VUL4,1272 .reg_ofs_base = AFE_VUL4_BASE,1273 .reg_ofs_cur = AFE_VUL4_CUR,1274 .reg_ofs_end = AFE_VUL4_END,1275 .reg_ofs_base_msb = AFE_VUL4_BASE_MSB,1276 .reg_ofs_cur_msb = AFE_VUL4_CUR_MSB,1277 .reg_ofs_end_msb = AFE_VUL4_END_MSB,1278 .fs_reg = AFE_VUL4_CON0,1279 .fs_shift = VUL4_MODE_SFT,1280 .fs_maskbit = VUL4_MODE_MASK,1281 .mono_reg = AFE_VUL4_CON0,1282 .mono_shift = VUL4_MONO_SFT,1283 .enable_reg = AFE_DAC_CON0,1284 .enable_shift = VUL4_ON_SFT,1285 .hd_reg = AFE_VUL4_CON0,1286 .hd_shift = VUL4_HD_MODE_SFT,1287 .hd_align_reg = AFE_VUL4_CON0,1288 .hd_align_mshift = VUL4_HALIGN_SFT,1289 },1290 [MT8192_MEMIF_VUL5] = {1291 .name = "VUL5",1292 .id = MT8192_MEMIF_VUL5,1293 .reg_ofs_base = AFE_VUL5_BASE,1294 .reg_ofs_cur = AFE_VUL5_CUR,1295 .reg_ofs_end = AFE_VUL5_END,1296 .reg_ofs_base_msb = AFE_VUL5_BASE_MSB,1297 .reg_ofs_cur_msb = AFE_VUL5_CUR_MSB,1298 .reg_ofs_end_msb = AFE_VUL5_END_MSB,1299 .fs_reg = AFE_VUL5_CON0,1300 .fs_shift = VUL5_MODE_SFT,1301 .fs_maskbit = VUL5_MODE_MASK,1302 .mono_reg = AFE_VUL5_CON0,1303 .mono_shift = VUL5_MONO_SFT,1304 .enable_reg = AFE_DAC_CON0,1305 .enable_shift = VUL5_ON_SFT,1306 .hd_reg = AFE_VUL5_CON0,1307 .hd_shift = VUL5_HD_MODE_SFT,1308 .hd_align_reg = AFE_VUL5_CON0,1309 .hd_align_mshift = VUL5_HALIGN_SFT,1310 },1311 [MT8192_MEMIF_VUL6] = {1312 .name = "VUL6",1313 .id = MT8192_MEMIF_VUL6,1314 .reg_ofs_base = AFE_VUL6_BASE,1315 .reg_ofs_cur = AFE_VUL6_CUR,1316 .reg_ofs_end = AFE_VUL6_END,1317 .reg_ofs_base_msb = AFE_VUL6_BASE_MSB,1318 .reg_ofs_cur_msb = AFE_VUL6_CUR_MSB,1319 .reg_ofs_end_msb = AFE_VUL6_END_MSB,1320 .fs_reg = AFE_VUL6_CON0,1321 .fs_shift = VUL6_MODE_SFT,1322 .fs_maskbit = VUL6_MODE_MASK,1323 .mono_reg = AFE_VUL6_CON0,1324 .mono_shift = VUL6_MONO_SFT,1325 .enable_reg = AFE_DAC_CON0,1326 .enable_shift = VUL6_ON_SFT,1327 .hd_reg = AFE_VUL6_CON0,1328 .hd_shift = VUL6_HD_MODE_SFT,1329 .hd_align_reg = AFE_VUL6_CON0,1330 .hd_align_mshift = VUL6_HALIGN_SFT,1331 },1332 [MT8192_MEMIF_HDMI] = {1333 .name = "HDMI",1334 .id = MT8192_MEMIF_HDMI,1335 .reg_ofs_base = AFE_HDMI_OUT_BASE,1336 .reg_ofs_cur = AFE_HDMI_OUT_CUR,1337 .reg_ofs_end = AFE_HDMI_OUT_END,1338 .reg_ofs_base_msb = AFE_HDMI_OUT_BASE_MSB,1339 .reg_ofs_cur_msb = AFE_HDMI_OUT_CUR_MSB,1340 .reg_ofs_end_msb = AFE_HDMI_OUT_END_MSB,1341 .fs_reg = -1,1342 .fs_shift = -1,1343 .fs_maskbit = -1,1344 .mono_reg = -1,1345 .mono_shift = -1,1346 .enable_reg = AFE_DAC_CON0,1347 .enable_shift = HDMI_OUT_ON_SFT,1348 .hd_reg = AFE_HDMI_OUT_CON0,1349 .hd_shift = HDMI_OUT_HD_MODE_SFT,1350 .hd_align_reg = AFE_HDMI_OUT_CON0,1351 .hd_align_mshift = HDMI_OUT_HALIGN_SFT,1352 .pbuf_reg = AFE_HDMI_OUT_CON0,1353 .minlen_reg = AFE_HDMI_OUT_CON0,1354 .minlen_shift = HDMI_OUT_MINLEN_SFT,1355 },1356};1357 1358static const struct mtk_base_irq_data irq_data[MT8192_IRQ_NUM] = {1359 [MT8192_IRQ_0] = {1360 .id = MT8192_IRQ_0,1361 .irq_cnt_reg = AFE_IRQ_MCU_CNT0,1362 .irq_cnt_shift = AFE_IRQ_CNT_SHIFT,1363 .irq_cnt_maskbit = AFE_IRQ_CNT_MASK,1364 .irq_fs_reg = AFE_IRQ_MCU_CON1,1365 .irq_fs_shift = IRQ0_MCU_MODE_SFT,1366 .irq_fs_maskbit = IRQ0_MCU_MODE_MASK,1367 .irq_en_reg = AFE_IRQ_MCU_CON0,1368 .irq_en_shift = IRQ0_MCU_ON_SFT,1369 .irq_clr_reg = AFE_IRQ_MCU_CLR,1370 .irq_clr_shift = IRQ0_MCU_CLR_SFT,1371 },1372 [MT8192_IRQ_1] = {1373 .id = MT8192_IRQ_1,1374 .irq_cnt_reg = AFE_IRQ_MCU_CNT1,1375 .irq_cnt_shift = AFE_IRQ_CNT_SHIFT,1376 .irq_cnt_maskbit = AFE_IRQ_CNT_MASK,1377 .irq_fs_reg = AFE_IRQ_MCU_CON1,1378 .irq_fs_shift = IRQ1_MCU_MODE_SFT,1379 .irq_fs_maskbit = IRQ1_MCU_MODE_MASK,1380 .irq_en_reg = AFE_IRQ_MCU_CON0,1381 .irq_en_shift = IRQ1_MCU_ON_SFT,1382 .irq_clr_reg = AFE_IRQ_MCU_CLR,1383 .irq_clr_shift = IRQ1_MCU_CLR_SFT,1384 },1385 [MT8192_IRQ_2] = {1386 .id = MT8192_IRQ_2,1387 .irq_cnt_reg = AFE_IRQ_MCU_CNT2,1388 .irq_cnt_shift = AFE_IRQ_CNT_SHIFT,1389 .irq_cnt_maskbit = AFE_IRQ_CNT_MASK,1390 .irq_fs_reg = AFE_IRQ_MCU_CON1,1391 .irq_fs_shift = IRQ2_MCU_MODE_SFT,1392 .irq_fs_maskbit = IRQ2_MCU_MODE_MASK,1393 .irq_en_reg = AFE_IRQ_MCU_CON0,1394 .irq_en_shift = IRQ2_MCU_ON_SFT,1395 .irq_clr_reg = AFE_IRQ_MCU_CLR,1396 .irq_clr_shift = IRQ2_MCU_CLR_SFT,1397 },1398 [MT8192_IRQ_3] = {1399 .id = MT8192_IRQ_3,1400 .irq_cnt_reg = AFE_IRQ_MCU_CNT3,1401 .irq_cnt_shift = AFE_IRQ_CNT_SHIFT,1402 .irq_cnt_maskbit = AFE_IRQ_CNT_MASK,1403 .irq_fs_reg = AFE_IRQ_MCU_CON1,1404 .irq_fs_shift = IRQ3_MCU_MODE_SFT,1405 .irq_fs_maskbit = IRQ3_MCU_MODE_MASK,1406 .irq_en_reg = AFE_IRQ_MCU_CON0,1407 .irq_en_shift = IRQ3_MCU_ON_SFT,1408 .irq_clr_reg = AFE_IRQ_MCU_CLR,1409 .irq_clr_shift = IRQ3_MCU_CLR_SFT,1410 },1411 [MT8192_IRQ_4] = {1412 .id = MT8192_IRQ_4,1413 .irq_cnt_reg = AFE_IRQ_MCU_CNT4,1414 .irq_cnt_shift = AFE_IRQ_CNT_SHIFT,1415 .irq_cnt_maskbit = AFE_IRQ_CNT_MASK,1416 .irq_fs_reg = AFE_IRQ_MCU_CON1,1417 .irq_fs_shift = IRQ4_MCU_MODE_SFT,1418 .irq_fs_maskbit = IRQ4_MCU_MODE_MASK,1419 .irq_en_reg = AFE_IRQ_MCU_CON0,1420 .irq_en_shift = IRQ4_MCU_ON_SFT,1421 .irq_clr_reg = AFE_IRQ_MCU_CLR,1422 .irq_clr_shift = IRQ4_MCU_CLR_SFT,1423 },1424 [MT8192_IRQ_5] = {1425 .id = MT8192_IRQ_5,1426 .irq_cnt_reg = AFE_IRQ_MCU_CNT5,1427 .irq_cnt_shift = AFE_IRQ_CNT_SHIFT,1428 .irq_cnt_maskbit = AFE_IRQ_CNT_MASK,1429 .irq_fs_reg = AFE_IRQ_MCU_CON1,1430 .irq_fs_shift = IRQ5_MCU_MODE_SFT,1431 .irq_fs_maskbit = IRQ5_MCU_MODE_MASK,1432 .irq_en_reg = AFE_IRQ_MCU_CON0,1433 .irq_en_shift = IRQ5_MCU_ON_SFT,1434 .irq_clr_reg = AFE_IRQ_MCU_CLR,1435 .irq_clr_shift = IRQ5_MCU_CLR_SFT,1436 },1437 [MT8192_IRQ_6] = {1438 .id = MT8192_IRQ_6,1439 .irq_cnt_reg = AFE_IRQ_MCU_CNT6,1440 .irq_cnt_shift = AFE_IRQ_CNT_SHIFT,1441 .irq_cnt_maskbit = AFE_IRQ_CNT_MASK,1442 .irq_fs_reg = AFE_IRQ_MCU_CON1,1443 .irq_fs_shift = IRQ6_MCU_MODE_SFT,1444 .irq_fs_maskbit = IRQ6_MCU_MODE_MASK,1445 .irq_en_reg = AFE_IRQ_MCU_CON0,1446 .irq_en_shift = IRQ6_MCU_ON_SFT,1447 .irq_clr_reg = AFE_IRQ_MCU_CLR,1448 .irq_clr_shift = IRQ6_MCU_CLR_SFT,1449 },1450 [MT8192_IRQ_7] = {1451 .id = MT8192_IRQ_7,1452 .irq_cnt_reg = AFE_IRQ_MCU_CNT7,1453 .irq_cnt_shift = AFE_IRQ_CNT_SHIFT,1454 .irq_cnt_maskbit = AFE_IRQ_CNT_MASK,1455 .irq_fs_reg = AFE_IRQ_MCU_CON1,1456 .irq_fs_shift = IRQ7_MCU_MODE_SFT,1457 .irq_fs_maskbit = IRQ7_MCU_MODE_MASK,1458 .irq_en_reg = AFE_IRQ_MCU_CON0,1459 .irq_en_shift = IRQ7_MCU_ON_SFT,1460 .irq_clr_reg = AFE_IRQ_MCU_CLR,1461 .irq_clr_shift = IRQ7_MCU_CLR_SFT,1462 },1463 [MT8192_IRQ_8] = {1464 .id = MT8192_IRQ_8,1465 .irq_cnt_reg = AFE_IRQ_MCU_CNT8,1466 .irq_cnt_shift = AFE_IRQ_CNT_SHIFT,1467 .irq_cnt_maskbit = AFE_IRQ_CNT_MASK,1468 .irq_fs_reg = AFE_IRQ_MCU_CON2,1469 .irq_fs_shift = IRQ8_MCU_MODE_SFT,1470 .irq_fs_maskbit = IRQ8_MCU_MODE_MASK,1471 .irq_en_reg = AFE_IRQ_MCU_CON0,1472 .irq_en_shift = IRQ8_MCU_ON_SFT,1473 .irq_clr_reg = AFE_IRQ_MCU_CLR,1474 .irq_clr_shift = IRQ8_MCU_CLR_SFT,1475 },1476 [MT8192_IRQ_9] = {1477 .id = MT8192_IRQ_9,1478 .irq_cnt_reg = AFE_IRQ_MCU_CNT9,1479 .irq_cnt_shift = AFE_IRQ_CNT_SHIFT,1480 .irq_cnt_maskbit = AFE_IRQ_CNT_MASK,1481 .irq_fs_reg = AFE_IRQ_MCU_CON2,1482 .irq_fs_shift = IRQ9_MCU_MODE_SFT,1483 .irq_fs_maskbit = IRQ9_MCU_MODE_MASK,1484 .irq_en_reg = AFE_IRQ_MCU_CON0,1485 .irq_en_shift = IRQ9_MCU_ON_SFT,1486 .irq_clr_reg = AFE_IRQ_MCU_CLR,1487 .irq_clr_shift = IRQ9_MCU_CLR_SFT,1488 },1489 [MT8192_IRQ_10] = {1490 .id = MT8192_IRQ_10,1491 .irq_cnt_reg = AFE_IRQ_MCU_CNT10,1492 .irq_cnt_shift = AFE_IRQ_CNT_SHIFT,1493 .irq_cnt_maskbit = AFE_IRQ_CNT_MASK,1494 .irq_fs_reg = AFE_IRQ_MCU_CON2,1495 .irq_fs_shift = IRQ10_MCU_MODE_SFT,1496 .irq_fs_maskbit = IRQ10_MCU_MODE_MASK,1497 .irq_en_reg = AFE_IRQ_MCU_CON0,1498 .irq_en_shift = IRQ10_MCU_ON_SFT,1499 .irq_clr_reg = AFE_IRQ_MCU_CLR,1500 .irq_clr_shift = IRQ10_MCU_CLR_SFT,1501 },1502 [MT8192_IRQ_11] = {1503 .id = MT8192_IRQ_11,1504 .irq_cnt_reg = AFE_IRQ_MCU_CNT11,1505 .irq_cnt_shift = AFE_IRQ_CNT_SHIFT,1506 .irq_cnt_maskbit = AFE_IRQ_CNT_MASK,1507 .irq_fs_reg = AFE_IRQ_MCU_CON2,1508 .irq_fs_shift = IRQ11_MCU_MODE_SFT,1509 .irq_fs_maskbit = IRQ11_MCU_MODE_MASK,1510 .irq_en_reg = AFE_IRQ_MCU_CON0,1511 .irq_en_shift = IRQ11_MCU_ON_SFT,1512 .irq_clr_reg = AFE_IRQ_MCU_CLR,1513 .irq_clr_shift = IRQ11_MCU_CLR_SFT,1514 },1515 [MT8192_IRQ_12] = {1516 .id = MT8192_IRQ_12,1517 .irq_cnt_reg = AFE_IRQ_MCU_CNT12,1518 .irq_cnt_shift = AFE_IRQ_CNT_SHIFT,1519 .irq_cnt_maskbit = AFE_IRQ_CNT_MASK,1520 .irq_fs_reg = AFE_IRQ_MCU_CON2,1521 .irq_fs_shift = IRQ12_MCU_MODE_SFT,1522 .irq_fs_maskbit = IRQ12_MCU_MODE_MASK,1523 .irq_en_reg = AFE_IRQ_MCU_CON0,1524 .irq_en_shift = IRQ12_MCU_ON_SFT,1525 .irq_clr_reg = AFE_IRQ_MCU_CLR,1526 .irq_clr_shift = IRQ12_MCU_CLR_SFT,1527 },1528 [MT8192_IRQ_13] = {1529 .id = MT8192_IRQ_13,1530 .irq_cnt_reg = AFE_IRQ_MCU_CNT13,1531 .irq_cnt_shift = AFE_IRQ_CNT_SHIFT,1532 .irq_cnt_maskbit = AFE_IRQ_CNT_MASK,1533 .irq_fs_reg = AFE_IRQ_MCU_CON2,1534 .irq_fs_shift = IRQ13_MCU_MODE_SFT,1535 .irq_fs_maskbit = IRQ13_MCU_MODE_MASK,1536 .irq_en_reg = AFE_IRQ_MCU_CON0,1537 .irq_en_shift = IRQ13_MCU_ON_SFT,1538 .irq_clr_reg = AFE_IRQ_MCU_CLR,1539 .irq_clr_shift = IRQ13_MCU_CLR_SFT,1540 },1541 [MT8192_IRQ_14] = {1542 .id = MT8192_IRQ_14,1543 .irq_cnt_reg = AFE_IRQ_MCU_CNT14,1544 .irq_cnt_shift = AFE_IRQ_CNT_SHIFT,1545 .irq_cnt_maskbit = AFE_IRQ_CNT_MASK,1546 .irq_fs_reg = AFE_IRQ_MCU_CON2,1547 .irq_fs_shift = IRQ14_MCU_MODE_SFT,1548 .irq_fs_maskbit = IRQ14_MCU_MODE_MASK,1549 .irq_en_reg = AFE_IRQ_MCU_CON0,1550 .irq_en_shift = IRQ14_MCU_ON_SFT,1551 .irq_clr_reg = AFE_IRQ_MCU_CLR,1552 .irq_clr_shift = IRQ14_MCU_CLR_SFT,1553 },1554 [MT8192_IRQ_15] = {1555 .id = MT8192_IRQ_15,1556 .irq_cnt_reg = AFE_IRQ_MCU_CNT15,1557 .irq_cnt_shift = AFE_IRQ_CNT_SHIFT,1558 .irq_cnt_maskbit = AFE_IRQ_CNT_MASK,1559 .irq_fs_reg = AFE_IRQ_MCU_CON2,1560 .irq_fs_shift = IRQ15_MCU_MODE_SFT,1561 .irq_fs_maskbit = IRQ15_MCU_MODE_MASK,1562 .irq_en_reg = AFE_IRQ_MCU_CON0,1563 .irq_en_shift = IRQ15_MCU_ON_SFT,1564 .irq_clr_reg = AFE_IRQ_MCU_CLR,1565 .irq_clr_shift = IRQ15_MCU_CLR_SFT,1566 },1567 [MT8192_IRQ_16] = {1568 .id = MT8192_IRQ_16,1569 .irq_cnt_reg = AFE_IRQ_MCU_CNT16,1570 .irq_cnt_shift = AFE_IRQ_CNT_SHIFT,1571 .irq_cnt_maskbit = AFE_IRQ_CNT_MASK,1572 .irq_fs_reg = AFE_IRQ_MCU_CON3,1573 .irq_fs_shift = IRQ16_MCU_MODE_SFT,1574 .irq_fs_maskbit = IRQ16_MCU_MODE_MASK,1575 .irq_en_reg = AFE_IRQ_MCU_CON0,1576 .irq_en_shift = IRQ16_MCU_ON_SFT,1577 .irq_clr_reg = AFE_IRQ_MCU_CLR,1578 .irq_clr_shift = IRQ16_MCU_CLR_SFT,1579 },1580 [MT8192_IRQ_17] = {1581 .id = MT8192_IRQ_17,1582 .irq_cnt_reg = AFE_IRQ_MCU_CNT17,1583 .irq_cnt_shift = AFE_IRQ_CNT_SHIFT,1584 .irq_cnt_maskbit = AFE_IRQ_CNT_MASK,1585 .irq_fs_reg = AFE_IRQ_MCU_CON3,1586 .irq_fs_shift = IRQ17_MCU_MODE_SFT,1587 .irq_fs_maskbit = IRQ17_MCU_MODE_MASK,1588 .irq_en_reg = AFE_IRQ_MCU_CON0,1589 .irq_en_shift = IRQ17_MCU_ON_SFT,1590 .irq_clr_reg = AFE_IRQ_MCU_CLR,1591 .irq_clr_shift = IRQ17_MCU_CLR_SFT,1592 },1593 [MT8192_IRQ_18] = {1594 .id = MT8192_IRQ_18,1595 .irq_cnt_reg = AFE_IRQ_MCU_CNT18,1596 .irq_cnt_shift = AFE_IRQ_CNT_SHIFT,1597 .irq_cnt_maskbit = AFE_IRQ_CNT_MASK,1598 .irq_fs_reg = AFE_IRQ_MCU_CON3,1599 .irq_fs_shift = IRQ18_MCU_MODE_SFT,1600 .irq_fs_maskbit = IRQ18_MCU_MODE_MASK,1601 .irq_en_reg = AFE_IRQ_MCU_CON0,1602 .irq_en_shift = IRQ18_MCU_ON_SFT,1603 .irq_clr_reg = AFE_IRQ_MCU_CLR,1604 .irq_clr_shift = IRQ18_MCU_CLR_SFT,1605 },1606 [MT8192_IRQ_19] = {1607 .id = MT8192_IRQ_19,1608 .irq_cnt_reg = AFE_IRQ_MCU_CNT19,1609 .irq_cnt_shift = AFE_IRQ_CNT_SHIFT,1610 .irq_cnt_maskbit = AFE_IRQ_CNT_MASK,1611 .irq_fs_reg = AFE_IRQ_MCU_CON3,1612 .irq_fs_shift = IRQ19_MCU_MODE_SFT,1613 .irq_fs_maskbit = IRQ19_MCU_MODE_MASK,1614 .irq_en_reg = AFE_IRQ_MCU_CON0,1615 .irq_en_shift = IRQ19_MCU_ON_SFT,1616 .irq_clr_reg = AFE_IRQ_MCU_CLR,1617 .irq_clr_shift = IRQ19_MCU_CLR_SFT,1618 },1619 [MT8192_IRQ_20] = {1620 .id = MT8192_IRQ_20,1621 .irq_cnt_reg = AFE_IRQ_MCU_CNT20,1622 .irq_cnt_shift = AFE_IRQ_CNT_SHIFT,1623 .irq_cnt_maskbit = AFE_IRQ_CNT_MASK,1624 .irq_fs_reg = AFE_IRQ_MCU_CON3,1625 .irq_fs_shift = IRQ20_MCU_MODE_SFT,1626 .irq_fs_maskbit = IRQ20_MCU_MODE_MASK,1627 .irq_en_reg = AFE_IRQ_MCU_CON0,1628 .irq_en_shift = IRQ20_MCU_ON_SFT,1629 .irq_clr_reg = AFE_IRQ_MCU_CLR,1630 .irq_clr_shift = IRQ20_MCU_CLR_SFT,1631 },1632 [MT8192_IRQ_21] = {1633 .id = MT8192_IRQ_21,1634 .irq_cnt_reg = AFE_IRQ_MCU_CNT21,1635 .irq_cnt_shift = AFE_IRQ_CNT_SHIFT,1636 .irq_cnt_maskbit = AFE_IRQ_CNT_MASK,1637 .irq_fs_reg = AFE_IRQ_MCU_CON3,1638 .irq_fs_shift = IRQ21_MCU_MODE_SFT,1639 .irq_fs_maskbit = IRQ21_MCU_MODE_MASK,1640 .irq_en_reg = AFE_IRQ_MCU_CON0,1641 .irq_en_shift = IRQ21_MCU_ON_SFT,1642 .irq_clr_reg = AFE_IRQ_MCU_CLR,1643 .irq_clr_shift = IRQ21_MCU_CLR_SFT,1644 },1645 [MT8192_IRQ_22] = {1646 .id = MT8192_IRQ_22,1647 .irq_cnt_reg = AFE_IRQ_MCU_CNT22,1648 .irq_cnt_shift = AFE_IRQ_CNT_SHIFT,1649 .irq_cnt_maskbit = AFE_IRQ_CNT_MASK,1650 .irq_fs_reg = AFE_IRQ_MCU_CON3,1651 .irq_fs_shift = IRQ22_MCU_MODE_SFT,1652 .irq_fs_maskbit = IRQ22_MCU_MODE_MASK,1653 .irq_en_reg = AFE_IRQ_MCU_CON0,1654 .irq_en_shift = IRQ22_MCU_ON_SFT,1655 .irq_clr_reg = AFE_IRQ_MCU_CLR,1656 .irq_clr_shift = IRQ22_MCU_CLR_SFT,1657 },1658 [MT8192_IRQ_23] = {1659 .id = MT8192_IRQ_23,1660 .irq_cnt_reg = AFE_IRQ_MCU_CNT23,1661 .irq_cnt_shift = AFE_IRQ_CNT_SHIFT,1662 .irq_cnt_maskbit = AFE_IRQ_CNT_MASK,1663 .irq_fs_reg = AFE_IRQ_MCU_CON3,1664 .irq_fs_shift = IRQ23_MCU_MODE_SFT,1665 .irq_fs_maskbit = IRQ23_MCU_MODE_MASK,1666 .irq_en_reg = AFE_IRQ_MCU_CON0,1667 .irq_en_shift = IRQ23_MCU_ON_SFT,1668 .irq_clr_reg = AFE_IRQ_MCU_CLR,1669 .irq_clr_shift = IRQ23_MCU_CLR_SFT,1670 },1671 [MT8192_IRQ_24] = {1672 .id = MT8192_IRQ_24,1673 .irq_cnt_reg = AFE_IRQ_MCU_CNT24,1674 .irq_cnt_shift = AFE_IRQ_CNT_SHIFT,1675 .irq_cnt_maskbit = AFE_IRQ_CNT_MASK,1676 .irq_fs_reg = AFE_IRQ_MCU_CON4,1677 .irq_fs_shift = IRQ24_MCU_MODE_SFT,1678 .irq_fs_maskbit = IRQ24_MCU_MODE_MASK,1679 .irq_en_reg = AFE_IRQ_MCU_CON0,1680 .irq_en_shift = IRQ24_MCU_ON_SFT,1681 .irq_clr_reg = AFE_IRQ_MCU_CLR,1682 .irq_clr_shift = IRQ24_MCU_CLR_SFT,1683 },1684 [MT8192_IRQ_25] = {1685 .id = MT8192_IRQ_25,1686 .irq_cnt_reg = AFE_IRQ_MCU_CNT25,1687 .irq_cnt_shift = AFE_IRQ_CNT_SHIFT,1688 .irq_cnt_maskbit = AFE_IRQ_CNT_MASK,1689 .irq_fs_reg = AFE_IRQ_MCU_CON4,1690 .irq_fs_shift = IRQ25_MCU_MODE_SFT,1691 .irq_fs_maskbit = IRQ25_MCU_MODE_MASK,1692 .irq_en_reg = AFE_IRQ_MCU_CON0,1693 .irq_en_shift = IRQ25_MCU_ON_SFT,1694 .irq_clr_reg = AFE_IRQ_MCU_CLR,1695 .irq_clr_shift = IRQ25_MCU_CLR_SFT,1696 },1697 [MT8192_IRQ_26] = {1698 .id = MT8192_IRQ_26,1699 .irq_cnt_reg = AFE_IRQ_MCU_CNT26,1700 .irq_cnt_shift = AFE_IRQ_CNT_SHIFT,1701 .irq_cnt_maskbit = AFE_IRQ_CNT_MASK,1702 .irq_fs_reg = AFE_IRQ_MCU_CON4,1703 .irq_fs_shift = IRQ26_MCU_MODE_SFT,1704 .irq_fs_maskbit = IRQ26_MCU_MODE_MASK,1705 .irq_en_reg = AFE_IRQ_MCU_CON0,1706 .irq_en_shift = IRQ26_MCU_ON_SFT,1707 .irq_clr_reg = AFE_IRQ_MCU_CLR,1708 .irq_clr_shift = IRQ26_MCU_CLR_SFT,1709 },1710 [MT8192_IRQ_31] = {1711 .id = MT8192_IRQ_31,1712 .irq_cnt_reg = AFE_IRQ_MCU_CNT31,1713 .irq_cnt_shift = AFE_IRQ_CNT_SHIFT,1714 .irq_cnt_maskbit = AFE_IRQ_CNT_MASK,1715 .irq_fs_reg = -1,1716 .irq_fs_shift = -1,1717 .irq_fs_maskbit = -1,1718 .irq_en_reg = AFE_IRQ_MCU_CON0,1719 .irq_en_shift = IRQ31_MCU_ON_SFT,1720 .irq_clr_reg = AFE_IRQ_MCU_CLR,1721 .irq_clr_shift = IRQ31_MCU_CLR_SFT,1722 },1723};1724 1725static const int memif_irq_usage[MT8192_MEMIF_NUM] = {1726 [MT8192_MEMIF_DL1] = MT8192_IRQ_0,1727 [MT8192_MEMIF_DL2] = MT8192_IRQ_1,1728 [MT8192_MEMIF_DL3] = MT8192_IRQ_2,1729 [MT8192_MEMIF_DL4] = MT8192_IRQ_3,1730 [MT8192_MEMIF_DL5] = MT8192_IRQ_4,1731 [MT8192_MEMIF_DL6] = MT8192_IRQ_5,1732 [MT8192_MEMIF_DL7] = MT8192_IRQ_6,1733 [MT8192_MEMIF_DL8] = MT8192_IRQ_7,1734 [MT8192_MEMIF_DL9] = MT8192_IRQ_8,1735 [MT8192_MEMIF_DL12] = MT8192_IRQ_9,1736 [MT8192_MEMIF_DAI] = MT8192_IRQ_10,1737 [MT8192_MEMIF_MOD_DAI] = MT8192_IRQ_11,1738 [MT8192_MEMIF_DAI2] = MT8192_IRQ_12,1739 [MT8192_MEMIF_VUL12] = MT8192_IRQ_13,1740 [MT8192_MEMIF_VUL2] = MT8192_IRQ_14,1741 [MT8192_MEMIF_AWB] = MT8192_IRQ_15,1742 [MT8192_MEMIF_AWB2] = MT8192_IRQ_16,1743 [MT8192_MEMIF_VUL3] = MT8192_IRQ_17,1744 [MT8192_MEMIF_VUL4] = MT8192_IRQ_18,1745 [MT8192_MEMIF_VUL5] = MT8192_IRQ_19,1746 [MT8192_MEMIF_VUL6] = MT8192_IRQ_20,1747 [MT8192_MEMIF_HDMI] = MT8192_IRQ_31,1748};1749 1750static bool mt8192_is_volatile_reg(struct device *dev, unsigned int reg)1751{1752 /* these auto-gen reg has read-only bit, so put it as volatile */1753 /* volatile reg cannot be cached, so cannot be set when power off */1754 switch (reg) {1755 case AUDIO_TOP_CON0: /* reg bit controlled by CCF */1756 case AUDIO_TOP_CON1: /* reg bit controlled by CCF */1757 case AUDIO_TOP_CON2:1758 case AUDIO_TOP_CON3:1759 case AFE_DL1_CUR_MSB:1760 case AFE_DL1_CUR:1761 case AFE_DL1_END:1762 case AFE_DL2_CUR_MSB:1763 case AFE_DL2_CUR:1764 case AFE_DL2_END:1765 case AFE_DL3_CUR_MSB:1766 case AFE_DL3_CUR:1767 case AFE_DL3_END:1768 case AFE_DL4_CUR_MSB:1769 case AFE_DL4_CUR:1770 case AFE_DL4_END:1771 case AFE_DL12_CUR_MSB:1772 case AFE_DL12_CUR:1773 case AFE_DL12_END:1774 case AFE_ADDA_SRC_DEBUG_MON0:1775 case AFE_ADDA_SRC_DEBUG_MON1:1776 case AFE_ADDA_UL_SRC_MON0:1777 case AFE_ADDA_UL_SRC_MON1:1778 case AFE_SECURE_CON0:1779 case AFE_SRAM_BOUND:1780 case AFE_SECURE_CON1:1781 case AFE_VUL_CUR_MSB:1782 case AFE_VUL_CUR:1783 case AFE_VUL_END:1784 case AFE_ADDA_3RD_DAC_DL_SDM_FIFO_MON:1785 case AFE_ADDA_3RD_DAC_DL_SRC_LCH_MON:1786 case AFE_ADDA_3RD_DAC_DL_SRC_RCH_MON:1787 case AFE_ADDA_3RD_DAC_DL_SDM_OUT_MON:1788 case AFE_SIDETONE_MON:1789 case AFE_SIDETONE_CON0:1790 case AFE_SIDETONE_COEFF:1791 case AFE_VUL2_CUR_MSB:1792 case AFE_VUL2_CUR:1793 case AFE_VUL2_END:1794 case AFE_VUL3_CUR_MSB:1795 case AFE_VUL3_CUR:1796 case AFE_VUL3_END:1797 case AFE_I2S_MON:1798 case AFE_DAC_MON:1799 case AFE_IRQ0_MCU_CNT_MON:1800 case AFE_IRQ6_MCU_CNT_MON:1801 case AFE_VUL4_CUR_MSB:1802 case AFE_VUL4_CUR:1803 case AFE_VUL4_END:1804 case AFE_VUL12_CUR_MSB:1805 case AFE_VUL12_CUR:1806 case AFE_VUL12_END:1807 case AFE_IRQ3_MCU_CNT_MON:1808 case AFE_IRQ4_MCU_CNT_MON:1809 case AFE_IRQ_MCU_STATUS:1810 case AFE_IRQ_MCU_CLR:1811 case AFE_IRQ_MCU_MON2:1812 case AFE_IRQ1_MCU_CNT_MON:1813 case AFE_IRQ2_MCU_CNT_MON:1814 case AFE_IRQ5_MCU_CNT_MON:1815 case AFE_IRQ7_MCU_CNT_MON:1816 case AFE_IRQ_MCU_MISS_CLR:1817 case AFE_GAIN1_CUR:1818 case AFE_GAIN2_CUR:1819 case AFE_SRAM_DELSEL_CON1:1820 case PCM_INTF_CON2:1821 case FPGA_CFG0:1822 case FPGA_CFG1:1823 case FPGA_CFG2:1824 case FPGA_CFG3:1825 case AUDIO_TOP_DBG_MON0:1826 case AUDIO_TOP_DBG_MON1:1827 case AFE_IRQ8_MCU_CNT_MON:1828 case AFE_IRQ11_MCU_CNT_MON:1829 case AFE_IRQ12_MCU_CNT_MON:1830 case AFE_IRQ9_MCU_CNT_MON:1831 case AFE_IRQ10_MCU_CNT_MON:1832 case AFE_IRQ13_MCU_CNT_MON:1833 case AFE_IRQ14_MCU_CNT_MON:1834 case AFE_IRQ15_MCU_CNT_MON:1835 case AFE_IRQ16_MCU_CNT_MON:1836 case AFE_IRQ17_MCU_CNT_MON:1837 case AFE_IRQ18_MCU_CNT_MON:1838 case AFE_IRQ19_MCU_CNT_MON:1839 case AFE_IRQ20_MCU_CNT_MON:1840 case AFE_IRQ21_MCU_CNT_MON:1841 case AFE_IRQ22_MCU_CNT_MON:1842 case AFE_IRQ23_MCU_CNT_MON:1843 case AFE_IRQ24_MCU_CNT_MON:1844 case AFE_IRQ25_MCU_CNT_MON:1845 case AFE_IRQ26_MCU_CNT_MON:1846 case AFE_IRQ31_MCU_CNT_MON:1847 case AFE_CBIP_MON0:1848 case AFE_CBIP_SLV_MUX_MON0:1849 case AFE_CBIP_SLV_DECODER_MON0:1850 case AFE_ADDA6_MTKAIF_MON0:1851 case AFE_ADDA6_MTKAIF_MON1:1852 case AFE_AWB_CUR_MSB:1853 case AFE_AWB_CUR:1854 case AFE_AWB_END:1855 case AFE_AWB2_CUR_MSB:1856 case AFE_AWB2_CUR:1857 case AFE_AWB2_END:1858 case AFE_DAI_CUR_MSB:1859 case AFE_DAI_CUR:1860 case AFE_DAI_END:1861 case AFE_DAI2_CUR_MSB:1862 case AFE_DAI2_CUR:1863 case AFE_DAI2_END:1864 case AFE_ADDA6_SRC_DEBUG_MON0:1865 case AFE_ADD6A_UL_SRC_MON0:1866 case AFE_ADDA6_UL_SRC_MON1:1867 case AFE_MOD_DAI_CUR_MSB:1868 case AFE_MOD_DAI_CUR:1869 case AFE_MOD_DAI_END:1870 case AFE_HDMI_OUT_CUR_MSB:1871 case AFE_HDMI_OUT_CUR:1872 case AFE_HDMI_OUT_END:1873 case AFE_AWB_RCH_MON:1874 case AFE_AWB_LCH_MON:1875 case AFE_VUL_RCH_MON:1876 case AFE_VUL_LCH_MON:1877 case AFE_VUL12_RCH_MON:1878 case AFE_VUL12_LCH_MON:1879 case AFE_VUL2_RCH_MON:1880 case AFE_VUL2_LCH_MON:1881 case AFE_DAI_DATA_MON:1882 case AFE_MOD_DAI_DATA_MON:1883 case AFE_DAI2_DATA_MON:1884 case AFE_AWB2_RCH_MON:1885 case AFE_AWB2_LCH_MON:1886 case AFE_VUL3_RCH_MON:1887 case AFE_VUL3_LCH_MON:1888 case AFE_VUL4_RCH_MON:1889 case AFE_VUL4_LCH_MON:1890 case AFE_VUL5_RCH_MON:1891 case AFE_VUL5_LCH_MON:1892 case AFE_VUL6_RCH_MON:1893 case AFE_VUL6_LCH_MON:1894 case AFE_DL1_RCH_MON:1895 case AFE_DL1_LCH_MON:1896 case AFE_DL2_RCH_MON:1897 case AFE_DL2_LCH_MON:1898 case AFE_DL12_RCH1_MON:1899 case AFE_DL12_LCH1_MON:1900 case AFE_DL12_RCH2_MON:1901 case AFE_DL12_LCH2_MON:1902 case AFE_DL3_RCH_MON:1903 case AFE_DL3_LCH_MON:1904 case AFE_DL4_RCH_MON:1905 case AFE_DL4_LCH_MON:1906 case AFE_DL5_RCH_MON:1907 case AFE_DL5_LCH_MON:1908 case AFE_DL6_RCH_MON:1909 case AFE_DL6_LCH_MON:1910 case AFE_DL7_RCH_MON:1911 case AFE_DL7_LCH_MON:1912 case AFE_DL8_RCH_MON:1913 case AFE_DL8_LCH_MON:1914 case AFE_VUL5_CUR_MSB:1915 case AFE_VUL5_CUR:1916 case AFE_VUL5_END:1917 case AFE_VUL6_CUR_MSB:1918 case AFE_VUL6_CUR:1919 case AFE_VUL6_END:1920 case AFE_ADDA_DL_SDM_FIFO_MON:1921 case AFE_ADDA_DL_SRC_LCH_MON:1922 case AFE_ADDA_DL_SRC_RCH_MON:1923 case AFE_ADDA_DL_SDM_OUT_MON:1924 case AFE_CONNSYS_I2S_MON:1925 case AFE_ASRC_2CH_CON0:1926 case AFE_ASRC_2CH_CON2:1927 case AFE_ASRC_2CH_CON3:1928 case AFE_ASRC_2CH_CON4:1929 case AFE_ASRC_2CH_CON5:1930 case AFE_ASRC_2CH_CON7:1931 case AFE_ASRC_2CH_CON8:1932 case AFE_ASRC_2CH_CON12:1933 case AFE_ASRC_2CH_CON13:1934 case AFE_DL9_CUR_MSB:1935 case AFE_DL9_CUR:1936 case AFE_DL9_END:1937 case AFE_ADDA_MTKAIF_MON0:1938 case AFE_ADDA_MTKAIF_MON1:1939 case AFE_DL_NLE_R_MON0:1940 case AFE_DL_NLE_R_MON1:1941 case AFE_DL_NLE_R_MON2:1942 case AFE_DL_NLE_L_MON0:1943 case AFE_DL_NLE_L_MON1:1944 case AFE_DL_NLE_L_MON2:1945 case AFE_GENERAL1_ASRC_2CH_CON0:1946 case AFE_GENERAL1_ASRC_2CH_CON2:1947 case AFE_GENERAL1_ASRC_2CH_CON3:1948 case AFE_GENERAL1_ASRC_2CH_CON4:1949 case AFE_GENERAL1_ASRC_2CH_CON5:1950 case AFE_GENERAL1_ASRC_2CH_CON7:1951 case AFE_GENERAL1_ASRC_2CH_CON8:1952 case AFE_GENERAL1_ASRC_2CH_CON12:1953 case AFE_GENERAL1_ASRC_2CH_CON13:1954 case AFE_GENERAL2_ASRC_2CH_CON0:1955 case AFE_GENERAL2_ASRC_2CH_CON2:1956 case AFE_GENERAL2_ASRC_2CH_CON3:1957 case AFE_GENERAL2_ASRC_2CH_CON4:1958 case AFE_GENERAL2_ASRC_2CH_CON5:1959 case AFE_GENERAL2_ASRC_2CH_CON7:1960 case AFE_GENERAL2_ASRC_2CH_CON8:1961 case AFE_GENERAL2_ASRC_2CH_CON12:1962 case AFE_GENERAL2_ASRC_2CH_CON13:1963 case AFE_DL9_RCH_MON:1964 case AFE_DL9_LCH_MON:1965 case AFE_DL5_CUR_MSB:1966 case AFE_DL5_CUR:1967 case AFE_DL5_END:1968 case AFE_DL6_CUR_MSB:1969 case AFE_DL6_CUR:1970 case AFE_DL6_END:1971 case AFE_DL7_CUR_MSB:1972 case AFE_DL7_CUR:1973 case AFE_DL7_END:1974 case AFE_DL8_CUR_MSB:1975 case AFE_DL8_CUR:1976 case AFE_DL8_END:1977 case AFE_PROT_SIDEBAND_MON:1978 case AFE_DOMAIN_SIDEBAND0_MON:1979 case AFE_DOMAIN_SIDEBAND1_MON:1980 case AFE_DOMAIN_SIDEBAND2_MON:1981 case AFE_DOMAIN_SIDEBAND3_MON:1982 case AFE_APLL1_TUNER_CFG: /* [20:31] is monitor */1983 case AFE_APLL2_TUNER_CFG: /* [20:31] is monitor */1984 case AFE_DAC_CON0:1985 case AFE_IRQ_MCU_CON0:1986 case AFE_IRQ_MCU_EN:1987 return true;1988 default:1989 return false;1990 };1991}1992 1993static const struct regmap_config mt8192_afe_regmap_config = {1994 .reg_bits = 32,1995 .reg_stride = 4,1996 .val_bits = 32,1997 .volatile_reg = mt8192_is_volatile_reg,1998 .max_register = AFE_MAX_REGISTER,1999 .num_reg_defaults_raw = AFE_MAX_REGISTER,2000 .cache_type = REGCACHE_FLAT,2001};2002 2003static irqreturn_t mt8192_afe_irq_handler(int irq_id, void *dev)2004{2005 struct mtk_base_afe *afe = dev;2006 struct mtk_base_afe_irq *irq;2007 unsigned int status;2008 unsigned int status_mcu;2009 unsigned int mcu_en;2010 int ret;2011 int i;2012 2013 /* get irq that is sent to MCU */2014 regmap_read(afe->regmap, AFE_IRQ_MCU_EN, &mcu_en);2015 2016 ret = regmap_read(afe->regmap, AFE_IRQ_MCU_STATUS, &status);2017 /* only care IRQ which is sent to MCU */2018 status_mcu = status & mcu_en & AFE_IRQ_STATUS_BITS;2019 2020 if (ret || status_mcu == 0) {2021 dev_err(afe->dev, "%s(), irq status err, ret %d, status 0x%x, mcu_en 0x%x\n",2022 __func__, ret, status, mcu_en);2023 2024 goto err_irq;2025 }2026 2027 for (i = 0; i < MT8192_MEMIF_NUM; i++) {2028 struct mtk_base_afe_memif *memif = &afe->memif[i];2029 2030 if (!memif->substream)2031 continue;2032 2033 if (memif->irq_usage < 0)2034 continue;2035 2036 irq = &afe->irqs[memif->irq_usage];2037 2038 if (status_mcu & (1 << irq->irq_data->irq_en_shift))2039 snd_pcm_period_elapsed(memif->substream);2040 }2041 2042err_irq:2043 /* clear irq */2044 regmap_write(afe->regmap,2045 AFE_IRQ_MCU_CLR,2046 status_mcu);2047 2048 return IRQ_HANDLED;2049}2050 2051static int mt8192_afe_runtime_suspend(struct device *dev)2052{2053 struct mtk_base_afe *afe = dev_get_drvdata(dev);2054 struct mt8192_afe_private *afe_priv = afe->platform_priv;2055 unsigned int value;2056 int ret;2057 2058 if (!afe->regmap || afe_priv->pm_runtime_bypass_reg_ctl)2059 goto skip_regmap;2060 2061 /* disable AFE */2062 regmap_update_bits(afe->regmap, AFE_DAC_CON0, AFE_ON_MASK_SFT, 0x0);2063 2064 ret = regmap_read_poll_timeout(afe->regmap,2065 AFE_DAC_MON,2066 value,2067 (value & AFE_ON_RETM_MASK_SFT) == 0,2068 20,2069 1 * 1000 * 1000);2070 if (ret)2071 dev_warn(afe->dev, "%s(), ret %d\n", __func__, ret);2072 2073 /* make sure all irq status are cleared */2074 regmap_write(afe->regmap, AFE_IRQ_MCU_CLR, 0xffffffff);2075 regmap_write(afe->regmap, AFE_IRQ_MCU_CLR, 0xffffffff);2076 2077 /* reset sgen */2078 regmap_write(afe->regmap, AFE_SINEGEN_CON0, 0x0);2079 regmap_update_bits(afe->regmap, AFE_SINEGEN_CON2,2080 INNER_LOOP_BACK_MODE_MASK_SFT,2081 0x3f << INNER_LOOP_BACK_MODE_SFT);2082 2083 /* cache only */2084 regcache_cache_only(afe->regmap, true);2085 regcache_mark_dirty(afe->regmap);2086 2087skip_regmap:2088 mt8192_afe_disable_clock(afe);2089 return 0;2090}2091 2092static int mt8192_afe_runtime_resume(struct device *dev)2093{2094 struct mtk_base_afe *afe = dev_get_drvdata(dev);2095 struct mt8192_afe_private *afe_priv = afe->platform_priv;2096 int ret;2097 2098 ret = mt8192_afe_enable_clock(afe);2099 if (ret)2100 return ret;2101 2102 if (!afe->regmap || afe_priv->pm_runtime_bypass_reg_ctl)2103 goto skip_regmap;2104 2105 regcache_cache_only(afe->regmap, false);2106 regcache_sync(afe->regmap);2107 2108 /* enable audio sys DCM for power saving */2109 regmap_update_bits(afe_priv->infracfg,2110 PERI_BUS_DCM_CTRL, 0x1 << 29, 0x1 << 29);2111 regmap_update_bits(afe->regmap, AUDIO_TOP_CON0, 0x1 << 29, 0x1 << 29);2112 2113 /* force cpu use 8_24 format when writing 32bit data */2114 regmap_update_bits(afe->regmap, AFE_MEMIF_CON0,2115 CPU_HD_ALIGN_MASK_SFT, 0 << CPU_HD_ALIGN_SFT);2116 2117 /* set all output port to 24bit */2118 regmap_write(afe->regmap, AFE_CONN_24BIT, 0xffffffff);2119 regmap_write(afe->regmap, AFE_CONN_24BIT_1, 0xffffffff);2120 2121 /* enable AFE */2122 regmap_update_bits(afe->regmap, AFE_DAC_CON0, AFE_ON_MASK_SFT, 0x1);2123 2124skip_regmap:2125 return 0;2126}2127 2128static int mt8192_dai_memif_register(struct mtk_base_afe *afe)2129{2130 struct mtk_base_afe_dai *dai;2131 2132 dai = devm_kzalloc(afe->dev, sizeof(*dai), GFP_KERNEL);2133 if (!dai)2134 return -ENOMEM;2135 2136 list_add(&dai->list, &afe->sub_dais);2137 2138 dai->dai_drivers = mt8192_memif_dai_driver;2139 dai->num_dai_drivers = ARRAY_SIZE(mt8192_memif_dai_driver);2140 2141 dai->dapm_widgets = mt8192_memif_widgets;2142 dai->num_dapm_widgets = ARRAY_SIZE(mt8192_memif_widgets);2143 dai->dapm_routes = mt8192_memif_routes;2144 dai->num_dapm_routes = ARRAY_SIZE(mt8192_memif_routes);2145 return 0;2146}2147 2148typedef int (*dai_register_cb)(struct mtk_base_afe *);2149static const dai_register_cb dai_register_cbs[] = {2150 mt8192_dai_adda_register,2151 mt8192_dai_i2s_register,2152 mt8192_dai_pcm_register,2153 mt8192_dai_tdm_register,2154 mt8192_dai_memif_register,2155};2156 2157static int mt8192_afe_pcm_dev_probe(struct platform_device *pdev)2158{2159 struct mtk_base_afe *afe;2160 struct mt8192_afe_private *afe_priv;2161 struct device *dev;2162 struct reset_control *rstc;2163 int i, ret, irq_id;2164 2165 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(34));2166 if (ret)2167 return ret;2168 2169 afe = devm_kzalloc(&pdev->dev, sizeof(*afe), GFP_KERNEL);2170 if (!afe)2171 return -ENOMEM;2172 platform_set_drvdata(pdev, afe);2173 2174 afe->platform_priv = devm_kzalloc(&pdev->dev, sizeof(*afe_priv),2175 GFP_KERNEL);2176 if (!afe->platform_priv)2177 return -ENOMEM;2178 afe_priv = afe->platform_priv;2179 2180 afe->dev = &pdev->dev;2181 dev = afe->dev;2182 2183 /* init audio related clock */2184 ret = mt8192_init_clock(afe);2185 if (ret) {2186 dev_err(dev, "init clock error\n");2187 return ret;2188 }2189 2190 /* reset controller to reset audio regs before regmap cache */2191 rstc = devm_reset_control_get_exclusive(dev, "audiosys");2192 if (IS_ERR(rstc))2193 return dev_err_probe(dev, PTR_ERR(rstc), "could not get audiosys reset\n");2194 2195 ret = reset_control_reset(rstc);2196 if (ret)2197 return dev_err_probe(dev, ret, "failed to trigger audio reset\n");2198 2199 ret = devm_pm_runtime_enable(&pdev->dev);2200 if (ret)2201 return ret;2202 2203 /* regmap init */2204 afe->regmap = syscon_node_to_regmap(dev->parent->of_node);2205 if (IS_ERR(afe->regmap))2206 return dev_err_probe(dev, PTR_ERR(afe->regmap),2207 "could not get regmap from parent");2208 2209 ret = regmap_attach_dev(dev, afe->regmap, &mt8192_afe_regmap_config);2210 if (ret)2211 return dev_err_probe(dev, ret, "regmap_attach_dev fail\n");2212 2213 /* enable clock for regcache get default value from hw */2214 afe_priv->pm_runtime_bypass_reg_ctl = true;2215 pm_runtime_get_sync(&pdev->dev);2216 2217 ret = regmap_reinit_cache(afe->regmap, &mt8192_afe_regmap_config);2218 if (ret)2219 return dev_err_probe(dev, ret, "regmap_reinit_cache fail\n");2220 2221 pm_runtime_put_sync(&pdev->dev);2222 afe_priv->pm_runtime_bypass_reg_ctl = false;2223 2224 regcache_cache_only(afe->regmap, true);2225 regcache_mark_dirty(afe->regmap);2226 2227 /* init memif */2228 afe->memif_size = MT8192_MEMIF_NUM;2229 afe->memif = devm_kcalloc(dev, afe->memif_size, sizeof(*afe->memif),2230 GFP_KERNEL);2231 if (!afe->memif)2232 return -ENOMEM;2233 2234 for (i = 0; i < afe->memif_size; i++) {2235 afe->memif[i].data = &memif_data[i];2236 afe->memif[i].irq_usage = memif_irq_usage[i];2237 afe->memif[i].const_irq = 1;2238 }2239 2240 mutex_init(&afe->irq_alloc_lock); /* needed when dynamic irq */2241 2242 /* init irq */2243 afe->irqs_size = MT8192_IRQ_NUM;2244 afe->irqs = devm_kcalloc(dev, afe->irqs_size, sizeof(*afe->irqs),2245 GFP_KERNEL);2246 if (!afe->irqs)2247 return -ENOMEM;2248 2249 for (i = 0; i < afe->irqs_size; i++)2250 afe->irqs[i].irq_data = &irq_data[i];2251 2252 /* request irq */2253 irq_id = platform_get_irq(pdev, 0);2254 if (irq_id < 0)2255 return irq_id;2256 2257 ret = devm_request_irq(dev, irq_id, mt8192_afe_irq_handler,2258 IRQF_TRIGGER_NONE, "asys-isr", (void *)afe);2259 if (ret)2260 return dev_err_probe(dev, ret, "could not request_irq for Afe_ISR_Handle\n");2261 2262 /* init sub_dais */2263 INIT_LIST_HEAD(&afe->sub_dais);2264 2265 for (i = 0; i < ARRAY_SIZE(dai_register_cbs); i++) {2266 ret = dai_register_cbs[i](afe);2267 if (ret)2268 return dev_err_probe(afe->dev, ret, "dai %d register fail", i);2269 }2270 2271 /* init dai_driver and component_driver */2272 ret = mtk_afe_combine_sub_dai(afe);2273 if (ret)2274 return dev_err_probe(afe->dev, ret, "mtk_afe_combine_sub_dai fail\n");2275 2276 /* others */2277 afe->mtk_afe_hardware = &mt8192_afe_hardware;2278 afe->memif_fs = mt8192_memif_fs;2279 afe->irq_fs = mt8192_irq_fs;2280 afe->get_dai_fs = mt8192_get_dai_fs;2281 afe->get_memif_pbuf_size = mt8192_get_memif_pbuf_size;2282 afe->memif_32bit_supported = 1;2283 2284 afe->runtime_resume = mt8192_afe_runtime_resume;2285 afe->runtime_suspend = mt8192_afe_runtime_suspend;2286 2287 /* register platform */2288 ret = devm_snd_soc_register_component(&pdev->dev,2289 &mtk_afe_pcm_platform,2290 afe->dai_drivers,2291 afe->num_dai_drivers);2292 if (ret)2293 return dev_err_probe(dev, ret, "Couldn't register AFE component\n");2294 2295 return 0;2296}2297 2298static void mt8192_afe_pcm_dev_remove(struct platform_device *pdev)2299{2300 struct mtk_base_afe *afe = platform_get_drvdata(pdev);2301 2302 pm_runtime_disable(&pdev->dev);2303 if (!pm_runtime_status_suspended(&pdev->dev))2304 mt8192_afe_runtime_suspend(&pdev->dev);2305 2306 /* disable afe clock */2307 mt8192_afe_disable_clock(afe);2308}2309 2310static const struct of_device_id mt8192_afe_pcm_dt_match[] = {2311 { .compatible = "mediatek,mt8192-audio", },2312 {},2313};2314MODULE_DEVICE_TABLE(of, mt8192_afe_pcm_dt_match);2315 2316static const struct dev_pm_ops mt8192_afe_pm_ops = {2317 SET_RUNTIME_PM_OPS(mt8192_afe_runtime_suspend,2318 mt8192_afe_runtime_resume, NULL)2319};2320 2321static struct platform_driver mt8192_afe_pcm_driver = {2322 .driver = {2323 .name = "mt8192-audio",2324 .of_match_table = mt8192_afe_pcm_dt_match,2325 .pm = &mt8192_afe_pm_ops,2326 },2327 .probe = mt8192_afe_pcm_dev_probe,2328 .remove = mt8192_afe_pcm_dev_remove,2329};2330 2331module_platform_driver(mt8192_afe_pcm_driver);2332 2333MODULE_DESCRIPTION("Mediatek ALSA SoC AFE platform driver for 8192");2334MODULE_AUTHOR("Shane Chien <shane.chien@mediatek.com>");2335MODULE_LICENSE("GPL v2");2336