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1/* SPDX-License-Identifier: GPL-2.0 */2/*3 * Mediatek MT8192 audio driver interconnection definition4 *5 * Copyright (c) 2020 MediaTek Inc.6 * Author: Shane Chien <shane.chien@mediatek.com>7 */8 9#ifndef _MT8192_INTERCONNECTION_H_10#define _MT8192_INTERCONNECTION_H_11 12/* in port define */13#define I_I2S0_CH1 014#define I_I2S0_CH2 115#define I_ADDA_UL_CH1 316#define I_ADDA_UL_CH2 417#define I_DL1_CH1 518#define I_DL1_CH2 619#define I_DL2_CH1 720#define I_DL2_CH2 821#define I_PCM_1_CAP_CH1 922#define I_GAIN1_OUT_CH1 1023#define I_GAIN1_OUT_CH2 1124#define I_GAIN2_OUT_CH1 1225#define I_GAIN2_OUT_CH2 1326#define I_PCM_2_CAP_CH1 1427#define I_ADDA_UL_CH3 1728#define I_ADDA_UL_CH4 1829#define I_DL12_CH1 1930#define I_DL12_CH2 2031#define I_PCM_2_CAP_CH2 2132#define I_PCM_1_CAP_CH2 2233#define I_DL3_CH1 2334#define I_DL3_CH2 2435#define I_I2S2_CH1 2536#define I_I2S2_CH2 2637#define I_I2S2_CH3 2738#define I_I2S2_CH4 2839 40/* in port define >= 32 */41#define I_32_OFFSET 3242#define I_CONNSYS_I2S_CH1 (34 - I_32_OFFSET)43#define I_CONNSYS_I2S_CH2 (35 - I_32_OFFSET)44#define I_SRC_1_OUT_CH1 (36 - I_32_OFFSET)45#define I_SRC_1_OUT_CH2 (37 - I_32_OFFSET)46#define I_SRC_2_OUT_CH1 (38 - I_32_OFFSET)47#define I_SRC_2_OUT_CH2 (39 - I_32_OFFSET)48#define I_DL4_CH1 (40 - I_32_OFFSET)49#define I_DL4_CH2 (41 - I_32_OFFSET)50#define I_DL5_CH1 (42 - I_32_OFFSET)51#define I_DL5_CH2 (43 - I_32_OFFSET)52#define I_DL6_CH1 (44 - I_32_OFFSET)53#define I_DL6_CH2 (45 - I_32_OFFSET)54#define I_DL7_CH1 (46 - I_32_OFFSET)55#define I_DL7_CH2 (47 - I_32_OFFSET)56#define I_DL8_CH1 (48 - I_32_OFFSET)57#define I_DL8_CH2 (49 - I_32_OFFSET)58#define I_DL9_CH1 (50 - I_32_OFFSET)59#define I_DL9_CH2 (51 - I_32_OFFSET)60#define I_I2S6_CH1 (52 - I_32_OFFSET)61#define I_I2S6_CH2 (53 - I_32_OFFSET)62#define I_I2S8_CH1 (54 - I_32_OFFSET)63#define I_I2S8_CH2 (55 - I_32_OFFSET)64 65#endif66