3134 lines · c
1/* SPDX-License-Identifier: GPL-2.0 */2/*3 * mt8192-reg.h -- Mediatek 8192 audio driver reg definition4 *5 * Copyright (c) 2020 MediaTek Inc.6 * Author: Shane Chien <shane.chien@mediatek.com>7 */8 9#ifndef _MT8192_REG_H_10#define _MT8192_REG_H_11 12/* reg bit enum */13enum {14 MT8192_MEMIF_PBUF_SIZE_32_BYTES,15 MT8192_MEMIF_PBUF_SIZE_64_BYTES,16 MT8192_MEMIF_PBUF_SIZE_128_BYTES,17 MT8192_MEMIF_PBUF_SIZE_256_BYTES,18 MT8192_MEMIF_PBUF_SIZE_NUM,19};20 21/*****************************************************************************22 * R E G I S T E R D E F I N I T I O N23 *****************************************************************************/24/* AUDIO_TOP_CON3 */25#define BCK_INVERSE_SFT 326#define BCK_INVERSE_MASK 0x127#define BCK_INVERSE_MASK_SFT (0x1 << 3)28 29/* AFE_DAC_CON0 */30#define VUL12_ON_SFT 3131#define VUL12_ON_MASK 0x132#define VUL12_ON_MASK_SFT (0x1 << 31)33#define MOD_DAI_ON_SFT 3034#define MOD_DAI_ON_MASK 0x135#define MOD_DAI_ON_MASK_SFT (0x1 << 30)36#define DAI_ON_SFT 2937#define DAI_ON_MASK 0x138#define DAI_ON_MASK_SFT (0x1 << 29)39#define DAI2_ON_SFT 2840#define DAI2_ON_MASK 0x141#define DAI2_ON_MASK_SFT (0x1 << 28)42#define VUL6_ON_SFT 2343#define VUL6_ON_MASK 0x144#define VUL6_ON_MASK_SFT (0x1 << 23)45#define VUL5_ON_SFT 2246#define VUL5_ON_MASK 0x147#define VUL5_ON_MASK_SFT (0x1 << 22)48#define VUL4_ON_SFT 2149#define VUL4_ON_MASK 0x150#define VUL4_ON_MASK_SFT (0x1 << 21)51#define VUL3_ON_SFT 2052#define VUL3_ON_MASK 0x153#define VUL3_ON_MASK_SFT (0x1 << 20)54#define VUL2_ON_SFT 1955#define VUL2_ON_MASK 0x156#define VUL2_ON_MASK_SFT (0x1 << 19)57#define VUL_ON_SFT 1858#define VUL_ON_MASK 0x159#define VUL_ON_MASK_SFT (0x1 << 18)60#define AWB2_ON_SFT 1761#define AWB2_ON_MASK 0x162#define AWB2_ON_MASK_SFT (0x1 << 17)63#define AWB_ON_SFT 1664#define AWB_ON_MASK 0x165#define AWB_ON_MASK_SFT (0x1 << 16)66#define DL12_ON_SFT 1567#define DL12_ON_MASK 0x168#define DL12_ON_MASK_SFT (0x1 << 15)69#define DL9_ON_SFT 1270#define DL9_ON_MASK 0x171#define DL9_ON_MASK_SFT (0x1 << 12)72#define DL8_ON_SFT 1173#define DL8_ON_MASK 0x174#define DL8_ON_MASK_SFT (0x1 << 11)75#define DL7_ON_SFT 1076#define DL7_ON_MASK 0x177#define DL7_ON_MASK_SFT (0x1 << 10)78#define DL6_ON_SFT 979#define DL6_ON_MASK 0x180#define DL6_ON_MASK_SFT (0x1 << 9)81#define DL5_ON_SFT 882#define DL5_ON_MASK 0x183#define DL5_ON_MASK_SFT (0x1 << 8)84#define DL4_ON_SFT 785#define DL4_ON_MASK 0x186#define DL4_ON_MASK_SFT (0x1 << 7)87#define DL3_ON_SFT 688#define DL3_ON_MASK 0x189#define DL3_ON_MASK_SFT (0x1 << 6)90#define DL2_ON_SFT 591#define DL2_ON_MASK 0x192#define DL2_ON_MASK_SFT (0x1 << 5)93#define DL1_ON_SFT 494#define DL1_ON_MASK 0x195#define DL1_ON_MASK_SFT (0x1 << 4)96#define HDMI_OUT_ON_SFT 197#define HDMI_OUT_ON_MASK 0x198#define HDMI_OUT_ON_MASK_SFT (0x1 << 1)99#define AFE_ON_SFT 0100#define AFE_ON_MASK 0x1101#define AFE_ON_MASK_SFT (0x1 << 0)102 103/* AFE_DAC_MON */104#define AFE_ON_RETM_SFT 0105#define AFE_ON_RETM_MASK 0x1106#define AFE_ON_RETM_MASK_SFT (0x1 << 0)107 108/* AFE_I2S_CON */109#define BCK_NEG_EG_LATCH_SFT 30110#define BCK_NEG_EG_LATCH_MASK 0x1111#define BCK_NEG_EG_LATCH_MASK_SFT (0x1 << 30)112#define BCK_INV_SFT 29113#define BCK_INV_MASK 0x1114#define BCK_INV_MASK_SFT (0x1 << 29)115#define I2SIN_PAD_SEL_SFT 28116#define I2SIN_PAD_SEL_MASK 0x1117#define I2SIN_PAD_SEL_MASK_SFT (0x1 << 28)118#define I2S_LOOPBACK_SFT 20119#define I2S_LOOPBACK_MASK 0x1120#define I2S_LOOPBACK_MASK_SFT (0x1 << 20)121#define I2S_ONOFF_NOT_RESET_CK_ENABLE_SFT 17122#define I2S_ONOFF_NOT_RESET_CK_ENABLE_MASK 0x1123#define I2S_ONOFF_NOT_RESET_CK_ENABLE_MASK_SFT (0x1 << 17)124#define I2S1_HD_EN_SFT 12125#define I2S1_HD_EN_MASK 0x1126#define I2S1_HD_EN_MASK_SFT (0x1 << 12)127#define I2S_OUT_MODE_SFT 8128#define I2S_OUT_MODE_MASK 0xf129#define I2S_OUT_MODE_MASK_SFT (0xf << 8)130#define INV_PAD_CTRL_SFT 7131#define INV_PAD_CTRL_MASK 0x1132#define INV_PAD_CTRL_MASK_SFT (0x1 << 7)133#define I2S_BYPSRC_SFT 6134#define I2S_BYPSRC_MASK 0x1135#define I2S_BYPSRC_MASK_SFT (0x1 << 6)136#define INV_LRCK_SFT 5137#define INV_LRCK_MASK 0x1138#define INV_LRCK_MASK_SFT (0x1 << 5)139#define I2S_FMT_SFT 3140#define I2S_FMT_MASK 0x1141#define I2S_FMT_MASK_SFT (0x1 << 3)142#define I2S_SRC_SFT 2143#define I2S_SRC_MASK 0x1144#define I2S_SRC_MASK_SFT (0x1 << 2)145#define I2S_WLEN_SFT 1146#define I2S_WLEN_MASK 0x1147#define I2S_WLEN_MASK_SFT (0x1 << 1)148#define I2S_EN_SFT 0149#define I2S_EN_MASK 0x1150#define I2S_EN_MASK_SFT (0x1 << 0)151 152/* AFE_I2S_CON1 */153#define I2S2_LR_SWAP_SFT 31154#define I2S2_LR_SWAP_MASK 0x1155#define I2S2_LR_SWAP_MASK_SFT (0x1 << 31)156#define I2S2_SEL_O19_O20_SFT 18157#define I2S2_SEL_O19_O20_MASK 0x1158#define I2S2_SEL_O19_O20_MASK_SFT (0x1 << 18)159#define I2S_ONOFF_NOT_RESET_CK_ENABLE_SFT 17160#define I2S_ONOFF_NOT_RESET_CK_ENABLE_MASK 0x1161#define I2S_ONOFF_NOT_RESET_CK_ENABLE_MASK_SFT (0x1 << 17)162#define I2S2_SEL_O03_O04_SFT 16163#define I2S2_SEL_O03_O04_MASK 0x1164#define I2S2_SEL_O03_O04_MASK_SFT (0x1 << 16)165#define I2S2_32BIT_EN_SFT 13166#define I2S2_32BIT_EN_MASK 0x1167#define I2S2_32BIT_EN_MASK_SFT (0x1 << 13)168#define I2S2_HD_EN_SFT 12169#define I2S2_HD_EN_MASK 0x1170#define I2S2_HD_EN_MASK_SFT (0x1 << 12)171#define I2S2_OUT_MODE_SFT 8172#define I2S2_OUT_MODE_MASK 0xf173#define I2S2_OUT_MODE_MASK_SFT (0xf << 8)174#define INV_LRCK_SFT 5175#define INV_LRCK_MASK 0x1176#define INV_LRCK_MASK_SFT (0x1 << 5)177#define I2S2_FMT_SFT 3178#define I2S2_FMT_MASK 0x1179#define I2S2_FMT_MASK_SFT (0x1 << 3)180#define I2S2_WLEN_SFT 1181#define I2S2_WLEN_MASK 0x1182#define I2S2_WLEN_MASK_SFT (0x1 << 1)183#define I2S2_EN_SFT 0184#define I2S2_EN_MASK 0x1185#define I2S2_EN_MASK_SFT (0x1 << 0)186 187/* AFE_I2S_CON2 */188#define I2S3_LR_SWAP_SFT 31189#define I2S3_LR_SWAP_MASK 0x1190#define I2S3_LR_SWAP_MASK_SFT (0x1 << 31)191#define I2S3_UPDATE_WORD_SFT 24192#define I2S3_UPDATE_WORD_MASK 0x1f193#define I2S3_UPDATE_WORD_MASK_SFT (0x1f << 24)194#define I2S3_BCK_INV_SFT 23195#define I2S3_BCK_INV_MASK 0x1196#define I2S3_BCK_INV_MASK_SFT (0x1 << 23)197#define I2S3_FPGA_BIT_TEST_SFT 22198#define I2S3_FPGA_BIT_TEST_MASK 0x1199#define I2S3_FPGA_BIT_TEST_MASK_SFT (0x1 << 22)200#define I2S3_FPGA_BIT_SFT 21201#define I2S3_FPGA_BIT_MASK 0x1202#define I2S3_FPGA_BIT_MASK_SFT (0x1 << 21)203#define I2S3_LOOPBACK_SFT 20204#define I2S3_LOOPBACK_MASK 0x1205#define I2S3_LOOPBACK_MASK_SFT (0x1 << 20)206#define I2S_ONOFF_NOT_RESET_CK_ENABLE_SFT 17207#define I2S_ONOFF_NOT_RESET_CK_ENABLE_MASK 0x1208#define I2S_ONOFF_NOT_RESET_CK_ENABLE_MASK_SFT (0x1 << 17)209#define I2S3_HD_EN_SFT 12210#define I2S3_HD_EN_MASK 0x1211#define I2S3_HD_EN_MASK_SFT (0x1 << 12)212#define I2S3_OUT_MODE_SFT 8213#define I2S3_OUT_MODE_MASK 0xf214#define I2S3_OUT_MODE_MASK_SFT (0xf << 8)215#define I2S3_FMT_SFT 3216#define I2S3_FMT_MASK 0x1217#define I2S3_FMT_MASK_SFT (0x1 << 3)218#define I2S3_WLEN_SFT 1219#define I2S3_WLEN_MASK 0x1220#define I2S3_WLEN_MASK_SFT (0x1 << 1)221#define I2S3_EN_SFT 0222#define I2S3_EN_MASK 0x1223#define I2S3_EN_MASK_SFT (0x1 << 0)224 225/* AFE_I2S_CON3 */226#define I2S4_LR_SWAP_SFT 31227#define I2S4_LR_SWAP_MASK 0x1228#define I2S4_LR_SWAP_MASK_SFT (0x1 << 31)229#define I2S_ONOFF_NOT_RESET_CK_ENABLE_SFT 17230#define I2S_ONOFF_NOT_RESET_CK_ENABLE_MASK 0x1231#define I2S_ONOFF_NOT_RESET_CK_ENABLE_MASK_SFT (0x1 << 17)232#define I2S4_32BIT_EN_SFT 13233#define I2S4_32BIT_EN_MASK 0x1234#define I2S4_32BIT_EN_MASK_SFT (0x1 << 13)235#define I2S4_HD_EN_SFT 12236#define I2S4_HD_EN_MASK 0x1237#define I2S4_HD_EN_MASK_SFT (0x1 << 12)238#define I2S4_OUT_MODE_SFT 8239#define I2S4_OUT_MODE_MASK 0xf240#define I2S4_OUT_MODE_MASK_SFT (0xf << 8)241#define INV_LRCK_SFT 5242#define INV_LRCK_MASK 0x1243#define INV_LRCK_MASK_SFT (0x1 << 5)244#define I2S4_FMT_SFT 3245#define I2S4_FMT_MASK 0x1246#define I2S4_FMT_MASK_SFT (0x1 << 3)247#define I2S4_WLEN_SFT 1248#define I2S4_WLEN_MASK 0x1249#define I2S4_WLEN_MASK_SFT (0x1 << 1)250#define I2S4_EN_SFT 0251#define I2S4_EN_MASK 0x1252#define I2S4_EN_MASK_SFT (0x1 << 0)253 254/* AFE_I2S_CON4 */255#define I2S5_LR_SWAP_SFT 31256#define I2S5_LR_SWAP_MASK 0x1257#define I2S5_LR_SWAP_MASK_SFT (0x1 << 31)258#define I2S_LOOPBACK_SFT 20259#define I2S_LOOPBACK_MASK 0x1260#define I2S_LOOPBACK_MASK_SFT (0x1 << 20)261#define I2S_ONOFF_NOT_RESET_CK_ENABLE_SFT 17262#define I2S_ONOFF_NOT_RESET_CK_ENABLE_MASK 0x1263#define I2S_ONOFF_NOT_RESET_CK_ENABLE_MASK_SFT (0x1 << 17)264#define I2S5_32BIT_EN_SFT 13265#define I2S5_32BIT_EN_MASK 0x1266#define I2S5_32BIT_EN_MASK_SFT (0x1 << 13)267#define I2S5_HD_EN_SFT 12268#define I2S5_HD_EN_MASK 0x1269#define I2S5_HD_EN_MASK_SFT (0x1 << 12)270#define I2S5_OUT_MODE_SFT 8271#define I2S5_OUT_MODE_MASK 0xf272#define I2S5_OUT_MODE_MASK_SFT (0xf << 8)273#define INV_LRCK_SFT 5274#define INV_LRCK_MASK 0x1275#define INV_LRCK_MASK_SFT (0x1 << 5)276#define I2S5_FMT_SFT 3277#define I2S5_FMT_MASK 0x1278#define I2S5_FMT_MASK_SFT (0x1 << 3)279#define I2S5_WLEN_SFT 1280#define I2S5_WLEN_MASK 0x1281#define I2S5_WLEN_MASK_SFT (0x1 << 1)282#define I2S5_EN_SFT 0283#define I2S5_EN_MASK 0x1284#define I2S5_EN_MASK_SFT (0x1 << 0)285 286/* AFE_CONNSYS_I2S_CON */287#define BCK_NEG_EG_LATCH_SFT 30288#define BCK_NEG_EG_LATCH_MASK 0x1289#define BCK_NEG_EG_LATCH_MASK_SFT (0x1 << 30)290#define BCK_INV_SFT 29291#define BCK_INV_MASK 0x1292#define BCK_INV_MASK_SFT (0x1 << 29)293#define I2SIN_PAD_SEL_SFT 28294#define I2SIN_PAD_SEL_MASK 0x1295#define I2SIN_PAD_SEL_MASK_SFT (0x1 << 28)296#define I2S_LOOPBACK_SFT 20297#define I2S_LOOPBACK_MASK 0x1298#define I2S_LOOPBACK_MASK_SFT (0x1 << 20)299#define I2S_ONOFF_NOT_RESET_CK_ENABLE_SFT 17300#define I2S_ONOFF_NOT_RESET_CK_ENABLE_MASK 0x1301#define I2S_ONOFF_NOT_RESET_CK_ENABLE_MASK_SFT (0x1 << 17)302#define I2S_MODE_SFT 8303#define I2S_MODE_MASK 0xf304#define I2S_MODE_MASK_SFT (0xf << 8)305#define INV_PAD_CTRL_SFT 7306#define INV_PAD_CTRL_MASK 0x1307#define INV_PAD_CTRL_MASK_SFT (0x1 << 7)308#define I2S_BYPSRC_SFT 6309#define I2S_BYPSRC_MASK 0x1310#define I2S_BYPSRC_MASK_SFT (0x1 << 6)311#define INV_LRCK_SFT 5312#define INV_LRCK_MASK 0x1313#define INV_LRCK_MASK_SFT (0x1 << 5)314#define I2S_FMT_SFT 3315#define I2S_FMT_MASK 0x1316#define I2S_FMT_MASK_SFT (0x1 << 3)317#define I2S_SRC_SFT 2318#define I2S_SRC_MASK 0x1319#define I2S_SRC_MASK_SFT (0x1 << 2)320#define I2S_WLEN_SFT 1321#define I2S_WLEN_MASK 0x1322#define I2S_WLEN_MASK_SFT (0x1 << 1)323#define I2S_EN_SFT 0324#define I2S_EN_MASK 0x1325#define I2S_EN_MASK_SFT (0x1 << 0)326 327/* AFE_I2S_CON6 */328#define BCK_NEG_EG_LATCH_SFT 30329#define BCK_NEG_EG_LATCH_MASK 0x1330#define BCK_NEG_EG_LATCH_MASK_SFT (0x1 << 30)331#define BCK_INV_SFT 29332#define BCK_INV_MASK 0x1333#define BCK_INV_MASK_SFT (0x1 << 29)334#define I2S6_LOOPBACK_SFT 20335#define I2S6_LOOPBACK_MASK 0x1336#define I2S6_LOOPBACK_MASK_SFT (0x1 << 20)337#define I2S6_ONOFF_NOT_RESET_CK_ENABLE_SFT 17338#define I2S6_ONOFF_NOT_RESET_CK_ENABLE_MASK 0x1339#define I2S6_ONOFF_NOT_RESET_CK_ENABLE_MASK_SFT (0x1 << 17)340#define I2S6_HD_EN_SFT 12341#define I2S6_HD_EN_MASK 0x1342#define I2S6_HD_EN_MASK_SFT (0x1 << 12)343#define I2S6_OUT_MODE_SFT 8344#define I2S6_OUT_MODE_MASK 0xf345#define I2S6_OUT_MODE_MASK_SFT (0xf << 8)346#define I2S6_BYPSRC_SFT 6347#define I2S6_BYPSRC_MASK 0x1348#define I2S6_BYPSRC_MASK_SFT (0x1 << 6)349#define INV_LRCK_SFT 5350#define INV_LRCK_MASK 0x1351#define INV_LRCK_MASK_SFT (0x1 << 5)352#define I2S6_FMT_SFT 3353#define I2S6_FMT_MASK 0x1354#define I2S6_FMT_MASK_SFT (0x1 << 3)355#define I2S6_SRC_SFT 2356#define I2S6_SRC_MASK 0x1357#define I2S6_SRC_MASK_SFT (0x1 << 2)358#define I2S6_WLEN_SFT 1359#define I2S6_WLEN_MASK 0x1360#define I2S6_WLEN_MASK_SFT (0x1 << 1)361#define I2S6_EN_SFT 0362#define I2S6_EN_MASK 0x1363#define I2S6_EN_MASK_SFT (0x1 << 0)364 365/* AFE_I2S_CON7 */366#define I2S7_LR_SWAP_SFT 31367#define I2S7_LR_SWAP_MASK 0x1368#define I2S7_LR_SWAP_MASK_SFT (0x1 << 31)369#define I2S_ONOFF_NOT_RESET_CK_ENABLE_SFT 17370#define I2S_ONOFF_NOT_RESET_CK_ENABLE_MASK 0x1371#define I2S_ONOFF_NOT_RESET_CK_ENABLE_MASK_SFT (0x1 << 17)372#define I2S7_32BIT_EN_SFT 13373#define I2S7_32BIT_EN_MASK 0x1374#define I2S7_32BIT_EN_MASK_SFT (0x1 << 13)375#define I2S7_HD_EN_SFT 12376#define I2S7_HD_EN_MASK 0x1377#define I2S7_HD_EN_MASK_SFT (0x1 << 12)378#define I2S7_OUT_MODE_SFT 8379#define I2S7_OUT_MODE_MASK 0xf380#define I2S7_OUT_MODE_MASK_SFT (0xf << 8)381#define INV_LRCK_SFT 5382#define INV_LRCK_MASK 0x1383#define INV_LRCK_MASK_SFT (0x1 << 5)384#define I2S7_FMT_SFT 3385#define I2S7_FMT_MASK 0x1386#define I2S7_FMT_MASK_SFT (0x1 << 3)387#define I2S7_WLEN_SFT 1388#define I2S7_WLEN_MASK 0x1389#define I2S7_WLEN_MASK_SFT (0x1 << 1)390#define I2S7_EN_SFT 0391#define I2S7_EN_MASK 0x1392#define I2S7_EN_MASK_SFT (0x1 << 0)393 394/* AFE_I2S_CON8 */395#define BCK_NEG_EG_LATCH_SFT 30396#define BCK_NEG_EG_LATCH_MASK 0x1397#define BCK_NEG_EG_LATCH_MASK_SFT (0x1 << 30)398#define BCK_INV_SFT 29399#define BCK_INV_MASK 0x1400#define BCK_INV_MASK_SFT (0x1 << 29)401#define I2S8_LOOPBACK_SFT 20402#define I2S8_LOOPBACK_MASK 0x1403#define I2S8_LOOPBACK_MASK_SFT (0x1 << 20)404#define I2S8_ONOFF_NOT_RESET_CK_ENABLE_SFT 17405#define I2S8_ONOFF_NOT_RESET_CK_ENABLE_MASK 0x1406#define I2S8_ONOFF_NOT_RESET_CK_ENABLE_MASK_SFT (0x1 << 17)407#define I2S8_HD_EN_SFT 12408#define I2S8_HD_EN_MASK 0x1409#define I2S8_HD_EN_MASK_SFT (0x1 << 12)410#define I2S8_OUT_MODE_SFT 8411#define I2S8_OUT_MODE_MASK 0xf412#define I2S8_OUT_MODE_MASK_SFT (0xf << 8)413#define I2S8_BYPSRC_SFT 6414#define I2S8_BYPSRC_MASK 0x1415#define I2S8_BYPSRC_MASK_SFT (0x1 << 6)416#define INV_LRCK_SFT 5417#define INV_LRCK_MASK 0x1418#define INV_LRCK_MASK_SFT (0x1 << 5)419#define I2S8_FMT_SFT 3420#define I2S8_FMT_MASK 0x1421#define I2S8_FMT_MASK_SFT (0x1 << 3)422#define I2S8_SRC_SFT 2423#define I2S8_SRC_MASK 0x1424#define I2S8_SRC_MASK_SFT (0x1 << 2)425#define I2S8_WLEN_SFT 1426#define I2S8_WLEN_MASK 0x1427#define I2S8_WLEN_MASK_SFT (0x1 << 1)428#define I2S8_EN_SFT 0429#define I2S8_EN_MASK 0x1430#define I2S8_EN_MASK_SFT (0x1 << 0)431 432/* AFE_I2S_CON9 */433#define I2S9_LR_SWAP_SFT 31434#define I2S9_LR_SWAP_MASK 0x1435#define I2S9_LR_SWAP_MASK_SFT (0x1 << 31)436#define I2S_ONOFF_NOT_RESET_CK_ENABLE_SFT 17437#define I2S_ONOFF_NOT_RESET_CK_ENABLE_MASK 0x1438#define I2S_ONOFF_NOT_RESET_CK_ENABLE_MASK_SFT (0x1 << 17)439#define I2S9_32BIT_EN_SFT 13440#define I2S9_32BIT_EN_MASK 0x1441#define I2S9_32BIT_EN_MASK_SFT (0x1 << 13)442#define I2S9_HD_EN_SFT 12443#define I2S9_HD_EN_MASK 0x1444#define I2S9_HD_EN_MASK_SFT (0x1 << 12)445#define I2S9_OUT_MODE_SFT 8446#define I2S9_OUT_MODE_MASK 0xf447#define I2S9_OUT_MODE_MASK_SFT (0xf << 8)448#define INV_LRCK_SFT 5449#define INV_LRCK_MASK 0x1450#define INV_LRCK_MASK_SFT (0x1 << 5)451#define I2S9_FMT_SFT 3452#define I2S9_FMT_MASK 0x1453#define I2S9_FMT_MASK_SFT (0x1 << 3)454#define I2S9_WLEN_SFT 1455#define I2S9_WLEN_MASK 0x1456#define I2S9_WLEN_MASK_SFT (0x1 << 1)457#define I2S9_EN_SFT 0458#define I2S9_EN_MASK 0x1459#define I2S9_EN_MASK_SFT (0x1 << 0)460 461/* AFE_ASRC_2CH_CON2 */462#define CHSET_O16BIT_SFT 19463#define CHSET_O16BIT_MASK 0x1464#define CHSET_O16BIT_MASK_SFT (0x1 << 19)465#define CHSET_CLR_IIR_HISTORY_SFT 17466#define CHSET_CLR_IIR_HISTORY_MASK 0x1467#define CHSET_CLR_IIR_HISTORY_MASK_SFT (0x1 << 17)468#define CHSET_IS_MONO_SFT 16469#define CHSET_IS_MONO_MASK 0x1470#define CHSET_IS_MONO_MASK_SFT (0x1 << 16)471#define CHSET_IIR_EN_SFT 11472#define CHSET_IIR_EN_MASK 0x1473#define CHSET_IIR_EN_MASK_SFT (0x1 << 11)474#define CHSET_IIR_STAGE_SFT 8475#define CHSET_IIR_STAGE_MASK 0x7476#define CHSET_IIR_STAGE_MASK_SFT (0x7 << 8)477#define CHSET_STR_CLR_SFT 5478#define CHSET_STR_CLR_MASK 0x1479#define CHSET_STR_CLR_MASK_SFT (0x1 << 5)480#define CHSET_ON_SFT 2481#define CHSET_ON_MASK 0x1482#define CHSET_ON_MASK_SFT (0x1 << 2)483#define COEFF_SRAM_CTRL_SFT 1484#define COEFF_SRAM_CTRL_MASK 0x1485#define COEFF_SRAM_CTRL_MASK_SFT (0x1 << 1)486#define ASM_ON_SFT 0487#define ASM_ON_MASK 0x1488#define ASM_ON_MASK_SFT (0x1 << 0)489 490/* AFE_GAIN1_CON0 */491#define GAIN1_SAMPLE_PER_STEP_SFT 8492#define GAIN1_SAMPLE_PER_STEP_MASK 0xff493#define GAIN1_SAMPLE_PER_STEP_MASK_SFT (0xff << 8)494#define GAIN1_MODE_SFT 4495#define GAIN1_MODE_MASK 0xf496#define GAIN1_MODE_MASK_SFT (0xf << 4)497#define GAIN1_ON_SFT 0498#define GAIN1_ON_MASK 0x1499#define GAIN1_ON_MASK_SFT (0x1 << 0)500 501/* AFE_GAIN1_CON1 */502#define GAIN1_TARGET_SFT 0503#define GAIN1_TARGET_MASK 0xfffffff504#define GAIN1_TARGET_MASK_SFT (0xfffffff << 0)505 506/* AFE_GAIN2_CON0 */507#define GAIN2_SAMPLE_PER_STEP_SFT 8508#define GAIN2_SAMPLE_PER_STEP_MASK 0xff509#define GAIN2_SAMPLE_PER_STEP_MASK_SFT (0xff << 8)510#define GAIN2_MODE_SFT 4511#define GAIN2_MODE_MASK 0xf512#define GAIN2_MODE_MASK_SFT (0xf << 4)513#define GAIN2_ON_SFT 0514#define GAIN2_ON_MASK 0x1515#define GAIN2_ON_MASK_SFT (0x1 << 0)516 517/* AFE_GAIN2_CON1 */518#define GAIN2_TARGET_SFT 0519#define GAIN2_TARGET_MASK 0xfffffff520#define GAIN2_TARGET_MASK_SFT (0xfffffff << 0)521 522/* AFE_GAIN1_CUR */523#define AFE_GAIN1_CUR_SFT 0524#define AFE_GAIN1_CUR_MASK 0xfffffff525#define AFE_GAIN1_CUR_MASK_SFT (0xfffffff << 0)526 527/* AFE_GAIN2_CUR */528#define AFE_GAIN2_CUR_SFT 0529#define AFE_GAIN2_CUR_MASK 0xfffffff530#define AFE_GAIN2_CUR_MASK_SFT (0xfffffff << 0)531 532/* PCM_INTF_CON1 */533#define PCM_FIX_VALUE_SEL_SFT 31534#define PCM_FIX_VALUE_SEL_MASK 0x1535#define PCM_FIX_VALUE_SEL_MASK_SFT (0x1 << 31)536#define PCM_BUFFER_LOOPBACK_SFT 30537#define PCM_BUFFER_LOOPBACK_MASK 0x1538#define PCM_BUFFER_LOOPBACK_MASK_SFT (0x1 << 30)539#define PCM_PARALLEL_LOOPBACK_SFT 29540#define PCM_PARALLEL_LOOPBACK_MASK 0x1541#define PCM_PARALLEL_LOOPBACK_MASK_SFT (0x1 << 29)542#define PCM_SERIAL_LOOPBACK_SFT 28543#define PCM_SERIAL_LOOPBACK_MASK 0x1544#define PCM_SERIAL_LOOPBACK_MASK_SFT (0x1 << 28)545#define PCM_DAI_PCM_LOOPBACK_SFT 27546#define PCM_DAI_PCM_LOOPBACK_MASK 0x1547#define PCM_DAI_PCM_LOOPBACK_MASK_SFT (0x1 << 27)548#define PCM_I2S_PCM_LOOPBACK_SFT 26549#define PCM_I2S_PCM_LOOPBACK_MASK 0x1550#define PCM_I2S_PCM_LOOPBACK_MASK_SFT (0x1 << 26)551#define PCM_SYNC_DELSEL_SFT 25552#define PCM_SYNC_DELSEL_MASK 0x1553#define PCM_SYNC_DELSEL_MASK_SFT (0x1 << 25)554#define PCM_TX_LR_SWAP_SFT 24555#define PCM_TX_LR_SWAP_MASK 0x1556#define PCM_TX_LR_SWAP_MASK_SFT (0x1 << 24)557#define PCM_SYNC_OUT_INV_SFT 23558#define PCM_SYNC_OUT_INV_MASK 0x1559#define PCM_SYNC_OUT_INV_MASK_SFT (0x1 << 23)560#define PCM_BCLK_OUT_INV_SFT 22561#define PCM_BCLK_OUT_INV_MASK 0x1562#define PCM_BCLK_OUT_INV_MASK_SFT (0x1 << 22)563#define PCM_SYNC_IN_INV_SFT 21564#define PCM_SYNC_IN_INV_MASK 0x1565#define PCM_SYNC_IN_INV_MASK_SFT (0x1 << 21)566#define PCM_BCLK_IN_INV_SFT 20567#define PCM_BCLK_IN_INV_MASK 0x1568#define PCM_BCLK_IN_INV_MASK_SFT (0x1 << 20)569#define PCM_TX_LCH_RPT_SFT 19570#define PCM_TX_LCH_RPT_MASK 0x1571#define PCM_TX_LCH_RPT_MASK_SFT (0x1 << 19)572#define PCM_VBT_16K_MODE_SFT 18573#define PCM_VBT_16K_MODE_MASK 0x1574#define PCM_VBT_16K_MODE_MASK_SFT (0x1 << 18)575#define PCM_EXT_MODEM_SFT 17576#define PCM_EXT_MODEM_MASK 0x1577#define PCM_EXT_MODEM_MASK_SFT (0x1 << 17)578#define PCM_24BIT_SFT 16579#define PCM_24BIT_MASK 0x1580#define PCM_24BIT_MASK_SFT (0x1 << 16)581#define PCM_WLEN_SFT 14582#define PCM_WLEN_MASK 0x3583#define PCM_WLEN_MASK_SFT (0x3 << 14)584#define PCM_SYNC_LENGTH_SFT 9585#define PCM_SYNC_LENGTH_MASK 0x1f586#define PCM_SYNC_LENGTH_MASK_SFT (0x1f << 9)587#define PCM_SYNC_TYPE_SFT 8588#define PCM_SYNC_TYPE_MASK 0x1589#define PCM_SYNC_TYPE_MASK_SFT (0x1 << 8)590#define PCM_BT_MODE_SFT 7591#define PCM_BT_MODE_MASK 0x1592#define PCM_BT_MODE_MASK_SFT (0x1 << 7)593#define PCM_BYP_ASRC_SFT 6594#define PCM_BYP_ASRC_MASK 0x1595#define PCM_BYP_ASRC_MASK_SFT (0x1 << 6)596#define PCM_SLAVE_SFT 5597#define PCM_SLAVE_MASK 0x1598#define PCM_SLAVE_MASK_SFT (0x1 << 5)599#define PCM_MODE_SFT 3600#define PCM_MODE_MASK 0x3601#define PCM_MODE_MASK_SFT (0x3 << 3)602#define PCM_FMT_SFT 1603#define PCM_FMT_MASK 0x3604#define PCM_FMT_MASK_SFT (0x3 << 1)605#define PCM_EN_SFT 0606#define PCM_EN_MASK 0x1607#define PCM_EN_MASK_SFT (0x1 << 0)608 609/* PCM_INTF_CON2 */610#define PCM1_TX_FIFO_OV_SFT 31611#define PCM1_TX_FIFO_OV_MASK 0x1612#define PCM1_TX_FIFO_OV_MASK_SFT (0x1 << 31)613#define PCM1_RX_FIFO_OV_SFT 30614#define PCM1_RX_FIFO_OV_MASK 0x1615#define PCM1_RX_FIFO_OV_MASK_SFT (0x1 << 30)616#define PCM2_TX_FIFO_OV_SFT 29617#define PCM2_TX_FIFO_OV_MASK 0x1618#define PCM2_TX_FIFO_OV_MASK_SFT (0x1 << 29)619#define PCM2_RX_FIFO_OV_SFT 28620#define PCM2_RX_FIFO_OV_MASK 0x1621#define PCM2_RX_FIFO_OV_MASK_SFT (0x1 << 28)622#define PCM1_SYNC_GLITCH_SFT 27623#define PCM1_SYNC_GLITCH_MASK 0x1624#define PCM1_SYNC_GLITCH_MASK_SFT (0x1 << 27)625#define PCM2_SYNC_GLITCH_SFT 26626#define PCM2_SYNC_GLITCH_MASK 0x1627#define PCM2_SYNC_GLITCH_MASK_SFT (0x1 << 26)628#define TX3_RCH_DBG_MODE_SFT 17629#define TX3_RCH_DBG_MODE_MASK 0x1630#define TX3_RCH_DBG_MODE_MASK_SFT (0x1 << 17)631#define PCM1_PCM2_LOOPBACK_SFT 16632#define PCM1_PCM2_LOOPBACK_MASK 0x1633#define PCM1_PCM2_LOOPBACK_MASK_SFT (0x1 << 16)634#define DAI_PCM_LOOPBACK_CH_SFT 14635#define DAI_PCM_LOOPBACK_CH_MASK 0x3636#define DAI_PCM_LOOPBACK_CH_MASK_SFT (0x3 << 14)637#define I2S_PCM_LOOPBACK_CH_SFT 12638#define I2S_PCM_LOOPBACK_CH_MASK 0x3639#define I2S_PCM_LOOPBACK_CH_MASK_SFT (0x3 << 12)640#define TX_FIX_VALUE_SFT 0641#define TX_FIX_VALUE_MASK 0xff642#define TX_FIX_VALUE_MASK_SFT (0xff << 0)643 644/* PCM2_INTF_CON */645#define PCM2_TX_FIX_VALUE_SFT 24646#define PCM2_TX_FIX_VALUE_MASK 0xff647#define PCM2_TX_FIX_VALUE_MASK_SFT (0xff << 24)648#define PCM2_FIX_VALUE_SEL_SFT 23649#define PCM2_FIX_VALUE_SEL_MASK 0x1650#define PCM2_FIX_VALUE_SEL_MASK_SFT (0x1 << 23)651#define PCM2_BUFFER_LOOPBACK_SFT 22652#define PCM2_BUFFER_LOOPBACK_MASK 0x1653#define PCM2_BUFFER_LOOPBACK_MASK_SFT (0x1 << 22)654#define PCM2_PARALLEL_LOOPBACK_SFT 21655#define PCM2_PARALLEL_LOOPBACK_MASK 0x1656#define PCM2_PARALLEL_LOOPBACK_MASK_SFT (0x1 << 21)657#define PCM2_SERIAL_LOOPBACK_SFT 20658#define PCM2_SERIAL_LOOPBACK_MASK 0x1659#define PCM2_SERIAL_LOOPBACK_MASK_SFT (0x1 << 20)660#define PCM2_DAI_PCM_LOOPBACK_SFT 19661#define PCM2_DAI_PCM_LOOPBACK_MASK 0x1662#define PCM2_DAI_PCM_LOOPBACK_MASK_SFT (0x1 << 19)663#define PCM2_I2S_PCM_LOOPBACK_SFT 18664#define PCM2_I2S_PCM_LOOPBACK_MASK 0x1665#define PCM2_I2S_PCM_LOOPBACK_MASK_SFT (0x1 << 18)666#define PCM2_SYNC_DELSEL_SFT 17667#define PCM2_SYNC_DELSEL_MASK 0x1668#define PCM2_SYNC_DELSEL_MASK_SFT (0x1 << 17)669#define PCM2_TX_LR_SWAP_SFT 16670#define PCM2_TX_LR_SWAP_MASK 0x1671#define PCM2_TX_LR_SWAP_MASK_SFT (0x1 << 16)672#define PCM2_SYNC_IN_INV_SFT 15673#define PCM2_SYNC_IN_INV_MASK 0x1674#define PCM2_SYNC_IN_INV_MASK_SFT (0x1 << 15)675#define PCM2_BCLK_IN_INV_SFT 14676#define PCM2_BCLK_IN_INV_MASK 0x1677#define PCM2_BCLK_IN_INV_MASK_SFT (0x1 << 14)678#define PCM2_TX_LCH_RPT_SFT 13679#define PCM2_TX_LCH_RPT_MASK 0x1680#define PCM2_TX_LCH_RPT_MASK_SFT (0x1 << 13)681#define PCM2_VBT_16K_MODE_SFT 12682#define PCM2_VBT_16K_MODE_MASK 0x1683#define PCM2_VBT_16K_MODE_MASK_SFT (0x1 << 12)684#define PCM2_LOOPBACK_CH_SEL_SFT 10685#define PCM2_LOOPBACK_CH_SEL_MASK 0x3686#define PCM2_LOOPBACK_CH_SEL_MASK_SFT (0x3 << 10)687#define PCM2_TX2_BT_MODE_SFT 8688#define PCM2_TX2_BT_MODE_MASK 0x1689#define PCM2_TX2_BT_MODE_MASK_SFT (0x1 << 8)690#define PCM2_BT_MODE_SFT 7691#define PCM2_BT_MODE_MASK 0x1692#define PCM2_BT_MODE_MASK_SFT (0x1 << 7)693#define PCM2_AFIFO_SFT 6694#define PCM2_AFIFO_MASK 0x1695#define PCM2_AFIFO_MASK_SFT (0x1 << 6)696#define PCM2_WLEN_SFT 5697#define PCM2_WLEN_MASK 0x1698#define PCM2_WLEN_MASK_SFT (0x1 << 5)699#define PCM2_MODE_SFT 3700#define PCM2_MODE_MASK 0x3701#define PCM2_MODE_MASK_SFT (0x3 << 3)702#define PCM2_FMT_SFT 1703#define PCM2_FMT_MASK 0x3704#define PCM2_FMT_MASK_SFT (0x3 << 1)705#define PCM2_EN_SFT 0706#define PCM2_EN_MASK 0x1707#define PCM2_EN_MASK_SFT (0x1 << 0)708 709/* AFE_ADDA_MTKAIF_CFG0 */710#define MTKAIF_RXIF_CLKINV_ADC_SFT 31711#define MTKAIF_RXIF_CLKINV_ADC_MASK 0x1712#define MTKAIF_RXIF_CLKINV_ADC_MASK_SFT (0x1 << 31)713#define MTKAIF_RXIF_BYPASS_SRC_SFT 17714#define MTKAIF_RXIF_BYPASS_SRC_MASK 0x1715#define MTKAIF_RXIF_BYPASS_SRC_MASK_SFT (0x1 << 17)716#define MTKAIF_RXIF_PROTOCOL2_SFT 16717#define MTKAIF_RXIF_PROTOCOL2_MASK 0x1718#define MTKAIF_RXIF_PROTOCOL2_MASK_SFT (0x1 << 16)719#define MTKAIF_TXIF_BYPASS_SRC_SFT 5720#define MTKAIF_TXIF_BYPASS_SRC_MASK 0x1721#define MTKAIF_TXIF_BYPASS_SRC_MASK_SFT (0x1 << 5)722#define MTKAIF_TXIF_PROTOCOL2_SFT 4723#define MTKAIF_TXIF_PROTOCOL2_MASK 0x1724#define MTKAIF_TXIF_PROTOCOL2_MASK_SFT (0x1 << 4)725#define MTKAIF_TXIF_8TO5_SFT 2726#define MTKAIF_TXIF_8TO5_MASK 0x1727#define MTKAIF_TXIF_8TO5_MASK_SFT (0x1 << 2)728#define MTKAIF_RXIF_8TO5_SFT 1729#define MTKAIF_RXIF_8TO5_MASK 0x1730#define MTKAIF_RXIF_8TO5_MASK_SFT (0x1 << 1)731#define MTKAIF_IF_LOOPBACK1_SFT 0732#define MTKAIF_IF_LOOPBACK1_MASK 0x1733#define MTKAIF_IF_LOOPBACK1_MASK_SFT (0x1 << 0)734 735/* AFE_ADDA_MTKAIF_RX_CFG2 */736#define MTKAIF_RXIF_DETECT_ON_PROTOCOL2_SFT 16737#define MTKAIF_RXIF_DETECT_ON_PROTOCOL2_MASK 0x1738#define MTKAIF_RXIF_DETECT_ON_PROTOCOL2_MASK_SFT (0x1 << 16)739#define MTKAIF_RXIF_DELAY_CYCLE_SFT 12740#define MTKAIF_RXIF_DELAY_CYCLE_MASK 0xf741#define MTKAIF_RXIF_DELAY_CYCLE_MASK_SFT (0xf << 12)742#define MTKAIF_RXIF_DELAY_DATA_SFT 8743#define MTKAIF_RXIF_DELAY_DATA_MASK 0x1744#define MTKAIF_RXIF_DELAY_DATA_MASK_SFT (0x1 << 8)745#define MTKAIF_RXIF_FIFO_RSP_PROTOCOL2_SFT 4746#define MTKAIF_RXIF_FIFO_RSP_PROTOCOL2_MASK 0x7747#define MTKAIF_RXIF_FIFO_RSP_PROTOCOL2_MASK_SFT (0x7 << 4)748 749/* AFE_ADDA_DL_SRC2_CON0 */750#define DL_2_INPUT_MODE_CTL_SFT 28751#define DL_2_INPUT_MODE_CTL_MASK 0xf752#define DL_2_INPUT_MODE_CTL_MASK_SFT (0xf << 28)753#define DL_2_CH1_SATURATION_EN_CTL_SFT 27754#define DL_2_CH1_SATURATION_EN_CTL_MASK 0x1755#define DL_2_CH1_SATURATION_EN_CTL_MASK_SFT (0x1 << 27)756#define DL_2_CH2_SATURATION_EN_CTL_SFT 26757#define DL_2_CH2_SATURATION_EN_CTL_MASK 0x1758#define DL_2_CH2_SATURATION_EN_CTL_MASK_SFT (0x1 << 26)759#define DL_2_OUTPUT_SEL_CTL_SFT 24760#define DL_2_OUTPUT_SEL_CTL_MASK 0x3761#define DL_2_OUTPUT_SEL_CTL_MASK_SFT (0x3 << 24)762#define DL_2_FADEIN_0START_EN_SFT 16763#define DL_2_FADEIN_0START_EN_MASK 0x3764#define DL_2_FADEIN_0START_EN_MASK_SFT (0x3 << 16)765#define DL_DISABLE_HW_CG_CTL_SFT 15766#define DL_DISABLE_HW_CG_CTL_MASK 0x1767#define DL_DISABLE_HW_CG_CTL_MASK_SFT (0x1 << 15)768#define C_DATA_EN_SEL_CTL_PRE_SFT 14769#define C_DATA_EN_SEL_CTL_PRE_MASK 0x1770#define C_DATA_EN_SEL_CTL_PRE_MASK_SFT (0x1 << 14)771#define DL_2_SIDE_TONE_ON_CTL_PRE_SFT 13772#define DL_2_SIDE_TONE_ON_CTL_PRE_MASK 0x1773#define DL_2_SIDE_TONE_ON_CTL_PRE_MASK_SFT (0x1 << 13)774#define DL_2_MUTE_CH1_OFF_CTL_PRE_SFT 12775#define DL_2_MUTE_CH1_OFF_CTL_PRE_MASK 0x1776#define DL_2_MUTE_CH1_OFF_CTL_PRE_MASK_SFT (0x1 << 12)777#define DL_2_MUTE_CH2_OFF_CTL_PRE_SFT 11778#define DL_2_MUTE_CH2_OFF_CTL_PRE_MASK 0x1779#define DL_2_MUTE_CH2_OFF_CTL_PRE_MASK_SFT (0x1 << 11)780#define DL2_ARAMPSP_CTL_PRE_SFT 9781#define DL2_ARAMPSP_CTL_PRE_MASK 0x3782#define DL2_ARAMPSP_CTL_PRE_MASK_SFT (0x3 << 9)783#define DL_2_IIRMODE_CTL_PRE_SFT 6784#define DL_2_IIRMODE_CTL_PRE_MASK 0x7785#define DL_2_IIRMODE_CTL_PRE_MASK_SFT (0x7 << 6)786#define DL_2_VOICE_MODE_CTL_PRE_SFT 5787#define DL_2_VOICE_MODE_CTL_PRE_MASK 0x1788#define DL_2_VOICE_MODE_CTL_PRE_MASK_SFT (0x1 << 5)789#define D2_2_MUTE_CH1_ON_CTL_PRE_SFT 4790#define D2_2_MUTE_CH1_ON_CTL_PRE_MASK 0x1791#define D2_2_MUTE_CH1_ON_CTL_PRE_MASK_SFT (0x1 << 4)792#define D2_2_MUTE_CH2_ON_CTL_PRE_SFT 3793#define D2_2_MUTE_CH2_ON_CTL_PRE_MASK 0x1794#define D2_2_MUTE_CH2_ON_CTL_PRE_MASK_SFT (0x1 << 3)795#define DL_2_IIR_ON_CTL_PRE_SFT 2796#define DL_2_IIR_ON_CTL_PRE_MASK 0x1797#define DL_2_IIR_ON_CTL_PRE_MASK_SFT (0x1 << 2)798#define DL_2_GAIN_ON_CTL_PRE_SFT 1799#define DL_2_GAIN_ON_CTL_PRE_MASK 0x1800#define DL_2_GAIN_ON_CTL_PRE_MASK_SFT (0x1 << 1)801#define DL_2_SRC_ON_TMP_CTL_PRE_SFT 0802#define DL_2_SRC_ON_TMP_CTL_PRE_MASK 0x1803#define DL_2_SRC_ON_TMP_CTL_PRE_MASK_SFT (0x1 << 0)804 805/* AFE_ADDA_DL_SRC2_CON1 */806#define DL_2_GAIN_CTL_PRE_SFT 16807#define DL_2_GAIN_CTL_PRE_MASK 0xffff808#define DL_2_GAIN_CTL_PRE_MASK_SFT (0xffff << 16)809#define DL_2_GAIN_MODE_CTL_SFT 0810#define DL_2_GAIN_MODE_CTL_MASK 0x1811#define DL_2_GAIN_MODE_CTL_MASK_SFT (0x1 << 0)812 813/* AFE_ADDA_UL_SRC_CON0 */814#define ULCF_CFG_EN_CTL_SFT 31815#define ULCF_CFG_EN_CTL_MASK 0x1816#define ULCF_CFG_EN_CTL_MASK_SFT (0x1 << 31)817#define UL_DMIC_PHASE_SEL_CH1_SFT 27818#define UL_DMIC_PHASE_SEL_CH1_MASK 0x7819#define UL_DMIC_PHASE_SEL_CH1_MASK_SFT (0x7 << 27)820#define UL_DMIC_PHASE_SEL_CH2_SFT 24821#define UL_DMIC_PHASE_SEL_CH2_MASK 0x7822#define UL_DMIC_PHASE_SEL_CH2_MASK_SFT (0x7 << 24)823#define UL_MODE_3P25M_CH2_CTL_SFT 22824#define UL_MODE_3P25M_CH2_CTL_MASK 0x1825#define UL_MODE_3P25M_CH2_CTL_MASK_SFT (0x1 << 22)826#define UL_MODE_3P25M_CH1_CTL_SFT 21827#define UL_MODE_3P25M_CH1_CTL_MASK 0x1828#define UL_MODE_3P25M_CH1_CTL_MASK_SFT (0x1 << 21)829#define UL_VOICE_MODE_CH1_CH2_CTL_SFT 17830#define UL_VOICE_MODE_CH1_CH2_CTL_MASK 0x7831#define UL_VOICE_MODE_CH1_CH2_CTL_MASK_SFT (0x7 << 17)832#define UL_AP_DMIC_ON_SFT 16833#define UL_AP_DMIC_ON_MASK 0x1834#define UL_AP_DMIC_ON_MASK_SFT (0x1 << 16)835#define DMIC_LOW_POWER_MODE_CTL_SFT 14836#define DMIC_LOW_POWER_MODE_CTL_MASK 0x3837#define DMIC_LOW_POWER_MODE_CTL_MASK_SFT (0x3 << 14)838#define UL_DISABLE_HW_CG_CTL_SFT 12839#define UL_DISABLE_HW_CG_CTL_MASK 0x1840#define UL_DISABLE_HW_CG_CTL_MASK_SFT (0x1 << 12)841#define UL_IIR_ON_TMP_CTL_SFT 10842#define UL_IIR_ON_TMP_CTL_MASK 0x1843#define UL_IIR_ON_TMP_CTL_MASK_SFT (0x1 << 10)844#define UL_IIRMODE_CTL_SFT 7845#define UL_IIRMODE_CTL_MASK 0x7846#define UL_IIRMODE_CTL_MASK_SFT (0x7 << 7)847#define DIGMIC_4P33M_SEL_SFT 6848#define DIGMIC_4P33M_SEL_MASK 0x1849#define DIGMIC_4P33M_SEL_MASK_SFT (0x1 << 6)850#define DIGMIC_3P25M_1P625M_SEL_CTL_SFT 5851#define DIGMIC_3P25M_1P625M_SEL_CTL_MASK 0x1852#define DIGMIC_3P25M_1P625M_SEL_CTL_MASK_SFT (0x1 << 5)853#define UL_LOOP_BACK_MODE_CTL_SFT 2854#define UL_LOOP_BACK_MODE_CTL_MASK 0x1855#define UL_LOOP_BACK_MODE_CTL_MASK_SFT (0x1 << 2)856#define UL_SDM_3_LEVEL_CTL_SFT 1857#define UL_SDM_3_LEVEL_CTL_MASK 0x1858#define UL_SDM_3_LEVEL_CTL_MASK_SFT (0x1 << 1)859#define UL_SRC_ON_TMP_CTL_SFT 0860#define UL_SRC_ON_TMP_CTL_MASK 0x1861#define UL_SRC_ON_TMP_CTL_MASK_SFT (0x1 << 0)862 863/* AFE_ADDA_UL_SRC_CON1 */864#define C_DAC_EN_CTL_SFT 27865#define C_DAC_EN_CTL_MASK 0x1866#define C_DAC_EN_CTL_MASK_SFT (0x1 << 27)867#define C_MUTE_SW_CTL_SFT 26868#define C_MUTE_SW_CTL_MASK 0x1869#define C_MUTE_SW_CTL_MASK_SFT (0x1 << 26)870#define ASDM_SRC_SEL_CTL_SFT 25871#define ASDM_SRC_SEL_CTL_MASK 0x1872#define ASDM_SRC_SEL_CTL_MASK_SFT (0x1 << 25)873#define C_AMP_DIV_CH2_CTL_SFT 21874#define C_AMP_DIV_CH2_CTL_MASK 0x7875#define C_AMP_DIV_CH2_CTL_MASK_SFT (0x7 << 21)876#define C_FREQ_DIV_CH2_CTL_SFT 16877#define C_FREQ_DIV_CH2_CTL_MASK 0x1f878#define C_FREQ_DIV_CH2_CTL_MASK_SFT (0x1f << 16)879#define C_SINE_MODE_CH2_CTL_SFT 12880#define C_SINE_MODE_CH2_CTL_MASK 0xf881#define C_SINE_MODE_CH2_CTL_MASK_SFT (0xf << 12)882#define C_AMP_DIV_CH1_CTL_SFT 9883#define C_AMP_DIV_CH1_CTL_MASK 0x7884#define C_AMP_DIV_CH1_CTL_MASK_SFT (0x7 << 9)885#define C_FREQ_DIV_CH1_CTL_SFT 4886#define C_FREQ_DIV_CH1_CTL_MASK 0x1f887#define C_FREQ_DIV_CH1_CTL_MASK_SFT (0x1f << 4)888#define C_SINE_MODE_CH1_CTL_SFT 0889#define C_SINE_MODE_CH1_CTL_MASK 0xf890#define C_SINE_MODE_CH1_CTL_MASK_SFT (0xf << 0)891 892/* AFE_ADDA_TOP_CON0 */893#define C_LOOP_BACK_MODE_CTL_SFT 12894#define C_LOOP_BACK_MODE_CTL_MASK 0xf895#define C_LOOP_BACK_MODE_CTL_MASK_SFT (0xf << 12)896#define ADDA_UL_GAIN_MODE_SFT 8897#define ADDA_UL_GAIN_MODE_MASK 0x3898#define ADDA_UL_GAIN_MODE_MASK_SFT (0x3 << 8)899#define C_EXT_ADC_CTL_SFT 0900#define C_EXT_ADC_CTL_MASK 0x1901#define C_EXT_ADC_CTL_MASK_SFT (0x1 << 0)902 903/* AFE_ADDA_UL_DL_CON0 */904#define AFE_ADDA_UL_LR_SWAP_SFT 31905#define AFE_ADDA_UL_LR_SWAP_MASK 0x1906#define AFE_ADDA_UL_LR_SWAP_MASK_SFT (0x1 << 31)907#define AFE_ADDA_CKDIV_RST_SFT 30908#define AFE_ADDA_CKDIV_RST_MASK 0x1909#define AFE_ADDA_CKDIV_RST_MASK_SFT (0x1 << 30)910#define AFE_ADDA_FIFO_AUTO_RST_SFT 29911#define AFE_ADDA_FIFO_AUTO_RST_MASK 0x1912#define AFE_ADDA_FIFO_AUTO_RST_MASK_SFT (0x1 << 29)913#define AFE_ADDA_UL_FIFO_DIGMIC_TESTIN_SFT 21914#define AFE_ADDA_UL_FIFO_DIGMIC_TESTIN_MASK 0x3915#define AFE_ADDA_UL_FIFO_DIGMIC_TESTIN_MASK_SFT (0x3 << 21)916#define AFE_ADDA_UL_FIFO_DIGMIC_WDATA_TESTEN_SFT 20917#define AFE_ADDA_UL_FIFO_DIGMIC_WDATA_TESTEN_MASK 0x1918#define AFE_ADDA_UL_FIFO_DIGMIC_WDATA_TESTEN_MASK_SFT (0x1 << 20)919#define AFE_ADDA6_UL_LR_SWAP_SFT 15920#define AFE_ADDA6_UL_LR_SWAP_MASK 0x1921#define AFE_ADDA6_UL_LR_SWAP_MASK_SFT (0x1 << 15)922#define AFE_ADDA6_CKDIV_RST_SFT 14923#define AFE_ADDA6_CKDIV_RST_MASK 0x1924#define AFE_ADDA6_CKDIV_RST_MASK_SFT (0x1 << 14)925#define AFE_ADDA6_FIFO_AUTO_RST_SFT 13926#define AFE_ADDA6_FIFO_AUTO_RST_MASK 0x1927#define AFE_ADDA6_FIFO_AUTO_RST_MASK_SFT (0x1 << 13)928#define AFE_ADDA6_UL_FIFO_DIGMIC_TESTIN_SFT 5929#define AFE_ADDA6_UL_FIFO_DIGMIC_TESTIN_MASK 0x3930#define AFE_ADDA6_UL_FIFO_DIGMIC_TESTIN_MASK_SFT (0x3 << 5)931#define AFE_ADDA6_UL_FIFO_DIGMIC_WDATA_TESTEN_SFT 4932#define AFE_ADDA6_UL_FIFO_DIGMIC_WDATA_TESTEN_MASK 0x1933#define AFE_ADDA6_UL_FIFO_DIGMIC_WDATA_TESTEN_MASK_SFT (0x1 << 4)934#define ADDA_AFE_ON_SFT 0935#define ADDA_AFE_ON_MASK 0x1936#define ADDA_AFE_ON_MASK_SFT (0x1 << 0)937 938/* AFE_SIDETONE_CON0 */939#define R_RDY_SFT 30940#define R_RDY_MASK 0x1941#define R_RDY_MASK_SFT (0x1 << 30)942#define W_RDY_SFT 29943#define W_RDY_MASK 0x1944#define W_RDY_MASK_SFT (0x1 << 29)945#define R_W_EN_SFT 25946#define R_W_EN_MASK 0x1947#define R_W_EN_MASK_SFT (0x1 << 25)948#define R_W_SEL_SFT 24949#define R_W_SEL_MASK 0x1950#define R_W_SEL_MASK_SFT (0x1 << 24)951#define SEL_CH2_SFT 23952#define SEL_CH2_MASK 0x1953#define SEL_CH2_MASK_SFT (0x1 << 23)954#define SIDE_TONE_COEFFICIENT_ADDR_SFT 16955#define SIDE_TONE_COEFFICIENT_ADDR_MASK 0x1f956#define SIDE_TONE_COEFFICIENT_ADDR_MASK_SFT (0x1f << 16)957#define SIDE_TONE_COEFFICIENT_SFT 0958#define SIDE_TONE_COEFFICIENT_MASK 0xffff959#define SIDE_TONE_COEFFICIENT_MASK_SFT (0xffff << 0)960 961/* AFE_SIDETONE_COEFF */962#define SIDE_TONE_COEFF_SFT 0963#define SIDE_TONE_COEFF_MASK 0xffff964#define SIDE_TONE_COEFF_MASK_SFT (0xffff << 0)965 966/* AFE_SIDETONE_CON1 */967#define STF_BYPASS_MODE_SFT 31968#define STF_BYPASS_MODE_MASK 0x1969#define STF_BYPASS_MODE_MASK_SFT (0x1 << 31)970#define STF_BYPASS_MODE_O28_O29_SFT 30971#define STF_BYPASS_MODE_O28_O29_MASK 0x1972#define STF_BYPASS_MODE_O28_O29_MASK_SFT (0x1 << 30)973#define STF_BYPASS_MODE_I2S4_SFT 29974#define STF_BYPASS_MODE_I2S4_MASK 0x1975#define STF_BYPASS_MODE_I2S4_MASK_SFT (0x1 << 29)976#define STF_BYPASS_MODE_I2S5_SFT 28977#define STF_BYPASS_MODE_I2S5_MASK 0x1978#define STF_BYPASS_MODE_I2S5_MASK_SFT (0x1 << 28)979#define STF_BYPASS_MODE_DL3_SFT 27980#define STF_BYPASS_MODE_DL3_MASK 0x1981#define STF_BYPASS_MODE_DL3_MASK_SFT (0x1 << 27)982#define STF_BYPASS_MODE_I2S7_SFT 26983#define STF_BYPASS_MODE_I2S7_MASK 0x1984#define STF_BYPASS_MODE_I2S7_MASK_SFT (0x1 << 26)985#define STF_BYPASS_MODE_I2S9_SFT 25986#define STF_BYPASS_MODE_I2S9_MASK 0x1987#define STF_BYPASS_MODE_I2S9_MASK_SFT (0x1 << 25)988#define STF_O19O20_OUT_EN_SEL_SFT 13989#define STF_O19O20_OUT_EN_SEL_MASK 0x1990#define STF_O19O20_OUT_EN_SEL_MASK_SFT (0x1 << 13)991#define STF_SOURCE_FROM_O19O20_SFT 12992#define STF_SOURCE_FROM_O19O20_MASK 0x1993#define STF_SOURCE_FROM_O19O20_MASK_SFT (0x1 << 12)994#define SIDE_TONE_ON_SFT 8995#define SIDE_TONE_ON_MASK 0x1996#define SIDE_TONE_ON_MASK_SFT (0x1 << 8)997#define SIDE_TONE_HALF_TAP_NUM_SFT 0998#define SIDE_TONE_HALF_TAP_NUM_MASK 0x3f999#define SIDE_TONE_HALF_TAP_NUM_MASK_SFT (0x3f << 0)1000 1001/* AFE_SIDETONE_GAIN */1002#define POSITIVE_GAIN_SFT 161003#define POSITIVE_GAIN_MASK 0x71004#define POSITIVE_GAIN_MASK_SFT (0x7 << 16)1005#define SIDE_TONE_GAIN_SFT 01006#define SIDE_TONE_GAIN_MASK 0xffff1007#define SIDE_TONE_GAIN_MASK_SFT (0xffff << 0)1008 1009/* AFE_ADDA_DL_SDM_DCCOMP_CON */1010#define USE_3RD_SDM_SFT 281011#define USE_3RD_SDM_MASK 0x11012#define USE_3RD_SDM_MASK_SFT (0x1 << 28)1013#define DL_FIFO_START_POINT_SFT 241014#define DL_FIFO_START_POINT_MASK 0x71015#define DL_FIFO_START_POINT_MASK_SFT (0x7 << 24)1016#define DL_FIFO_SWAP_SFT 201017#define DL_FIFO_SWAP_MASK 0x11018#define DL_FIFO_SWAP_MASK_SFT (0x1 << 20)1019#define C_AUDSDM1ORDSELECT_CTL_SFT 191020#define C_AUDSDM1ORDSELECT_CTL_MASK 0x11021#define C_AUDSDM1ORDSELECT_CTL_MASK_SFT (0x1 << 19)1022#define C_SDM7BITSEL_CTL_SFT 181023#define C_SDM7BITSEL_CTL_MASK 0x11024#define C_SDM7BITSEL_CTL_MASK_SFT (0x1 << 18)1025#define GAIN_AT_SDM_RST_PRE_CTL_SFT 151026#define GAIN_AT_SDM_RST_PRE_CTL_MASK 0x11027#define GAIN_AT_SDM_RST_PRE_CTL_MASK_SFT (0x1 << 15)1028#define DL_DCM_AUTO_IDLE_EN_SFT 141029#define DL_DCM_AUTO_IDLE_EN_MASK 0x11030#define DL_DCM_AUTO_IDLE_EN_MASK_SFT (0x1 << 14)1031#define AFE_DL_SRC_DCM_EN_SFT 131032#define AFE_DL_SRC_DCM_EN_MASK 0x11033#define AFE_DL_SRC_DCM_EN_MASK_SFT (0x1 << 13)1034#define AFE_DL_POST_SRC_DCM_EN_SFT 121035#define AFE_DL_POST_SRC_DCM_EN_MASK 0x11036#define AFE_DL_POST_SRC_DCM_EN_MASK_SFT (0x1 << 12)1037#define AUD_SDM_MONO_SFT 91038#define AUD_SDM_MONO_MASK 0x11039#define AUD_SDM_MONO_MASK_SFT (0x1 << 9)1040#define AUD_DC_COMP_EN_SFT 81041#define AUD_DC_COMP_EN_MASK 0x11042#define AUD_DC_COMP_EN_MASK_SFT (0x1 << 8)1043#define ATTGAIN_CTL_SFT 01044#define ATTGAIN_CTL_MASK 0x3f1045#define ATTGAIN_CTL_MASK_SFT (0x3f << 0)1046 1047/* AFE_SINEGEN_CON0 */1048#define DAC_EN_SFT 261049#define DAC_EN_MASK 0x11050#define DAC_EN_MASK_SFT (0x1 << 26)1051#define MUTE_SW_CH2_SFT 251052#define MUTE_SW_CH2_MASK 0x11053#define MUTE_SW_CH2_MASK_SFT (0x1 << 25)1054#define MUTE_SW_CH1_SFT 241055#define MUTE_SW_CH1_MASK 0x11056#define MUTE_SW_CH1_MASK_SFT (0x1 << 24)1057#define SINE_MODE_CH2_SFT 201058#define SINE_MODE_CH2_MASK 0xf1059#define SINE_MODE_CH2_MASK_SFT (0xf << 20)1060#define AMP_DIV_CH2_SFT 171061#define AMP_DIV_CH2_MASK 0x71062#define AMP_DIV_CH2_MASK_SFT (0x7 << 17)1063#define FREQ_DIV_CH2_SFT 121064#define FREQ_DIV_CH2_MASK 0x1f1065#define FREQ_DIV_CH2_MASK_SFT (0x1f << 12)1066#define SINE_MODE_CH1_SFT 81067#define SINE_MODE_CH1_MASK 0xf1068#define SINE_MODE_CH1_MASK_SFT (0xf << 8)1069#define AMP_DIV_CH1_SFT 51070#define AMP_DIV_CH1_MASK 0x71071#define AMP_DIV_CH1_MASK_SFT (0x7 << 5)1072#define FREQ_DIV_CH1_SFT 01073#define FREQ_DIV_CH1_MASK 0x1f1074#define FREQ_DIV_CH1_MASK_SFT (0x1f << 0)1075 1076/* AFE_SINEGEN_CON2 */1077#define INNER_LOOP_BACK_MODE_SFT 01078#define INNER_LOOP_BACK_MODE_MASK 0x3f1079#define INNER_LOOP_BACK_MODE_MASK_SFT (0x3f << 0)1080 1081/* AFE_HD_ENGEN_ENABLE */1082#define AFE_24M_ON_SFT 11083#define AFE_24M_ON_MASK 0x11084#define AFE_24M_ON_MASK_SFT (0x1 << 1)1085#define AFE_22M_ON_SFT 01086#define AFE_22M_ON_MASK 0x11087#define AFE_22M_ON_MASK_SFT (0x1 << 0)1088 1089/* AFE_ADDA_DL_NLE_FIFO_MON */1090#define DL_NLE_FIFO_WBIN_SFT 81091#define DL_NLE_FIFO_WBIN_MASK 0xf1092#define DL_NLE_FIFO_WBIN_MASK_SFT (0xf << 8)1093#define DL_NLE_FIFO_RBIN_SFT 41094#define DL_NLE_FIFO_RBIN_MASK 0xf1095#define DL_NLE_FIFO_RBIN_MASK_SFT (0xf << 4)1096#define DL_NLE_FIFO_RDACTIVE_SFT 31097#define DL_NLE_FIFO_RDACTIVE_MASK 0x11098#define DL_NLE_FIFO_RDACTIVE_MASK_SFT (0x1 << 3)1099#define DL_NLE_FIFO_STARTRD_SFT 21100#define DL_NLE_FIFO_STARTRD_MASK 0x11101#define DL_NLE_FIFO_STARTRD_MASK_SFT (0x1 << 2)1102#define DL_NLE_FIFO_RD_EMPTY_SFT 11103#define DL_NLE_FIFO_RD_EMPTY_MASK 0x11104#define DL_NLE_FIFO_RD_EMPTY_MASK_SFT (0x1 << 1)1105#define DL_NLE_FIFO_WR_FULL_SFT 01106#define DL_NLE_FIFO_WR_FULL_MASK 0x11107#define DL_NLE_FIFO_WR_FULL_MASK_SFT (0x1 << 0)1108 1109/* AFE_DL1_CON0 */1110#define DL1_MODE_SFT 241111#define DL1_MODE_MASK 0xf1112#define DL1_MODE_MASK_SFT (0xf << 24)1113#define DL1_MINLEN_SFT 201114#define DL1_MINLEN_MASK 0xf1115#define DL1_MINLEN_MASK_SFT (0xf << 20)1116#define DL1_MAXLEN_SFT 161117#define DL1_MAXLEN_MASK 0xf1118#define DL1_MAXLEN_MASK_SFT (0xf << 16)1119#define DL1_SW_CLEAR_BUF_EMPTY_SFT 151120#define DL1_SW_CLEAR_BUF_EMPTY_MASK 0x11121#define DL1_SW_CLEAR_BUF_EMPTY_MASK_SFT (0x1 << 15)1122#define DL1_PBUF_SIZE_SFT 121123#define DL1_PBUF_SIZE_MASK 0x31124#define DL1_PBUF_SIZE_MASK_SFT (0x3 << 12)1125#define DL1_MONO_SFT 81126#define DL1_MONO_MASK 0x11127#define DL1_MONO_MASK_SFT (0x1 << 8)1128#define DL1_NORMAL_MODE_SFT 51129#define DL1_NORMAL_MODE_MASK 0x11130#define DL1_NORMAL_MODE_MASK_SFT (0x1 << 5)1131#define DL1_HALIGN_SFT 41132#define DL1_HALIGN_MASK 0x11133#define DL1_HALIGN_MASK_SFT (0x1 << 4)1134#define DL1_HD_MODE_SFT 01135#define DL1_HD_MODE_MASK 0x31136#define DL1_HD_MODE_MASK_SFT (0x3 << 0)1137 1138/* AFE_DL2_CON0 */1139#define DL2_MODE_SFT 241140#define DL2_MODE_MASK 0xf1141#define DL2_MODE_MASK_SFT (0xf << 24)1142#define DL2_MINLEN_SFT 201143#define DL2_MINLEN_MASK 0xf1144#define DL2_MINLEN_MASK_SFT (0xf << 20)1145#define DL2_MAXLEN_SFT 161146#define DL2_MAXLEN_MASK 0xf1147#define DL2_MAXLEN_MASK_SFT (0xf << 16)1148#define DL2_SW_CLEAR_BUF_EMPTY_SFT 151149#define DL2_SW_CLEAR_BUF_EMPTY_MASK 0x11150#define DL2_SW_CLEAR_BUF_EMPTY_MASK_SFT (0x1 << 15)1151#define DL2_PBUF_SIZE_SFT 121152#define DL2_PBUF_SIZE_MASK 0x31153#define DL2_PBUF_SIZE_MASK_SFT (0x3 << 12)1154#define DL2_MONO_SFT 81155#define DL2_MONO_MASK 0x11156#define DL2_MONO_MASK_SFT (0x1 << 8)1157#define DL2_NORMAL_MODE_SFT 51158#define DL2_NORMAL_MODE_MASK 0x11159#define DL2_NORMAL_MODE_MASK_SFT (0x1 << 5)1160#define DL2_HALIGN_SFT 41161#define DL2_HALIGN_MASK 0x11162#define DL2_HALIGN_MASK_SFT (0x1 << 4)1163#define DL2_HD_MODE_SFT 01164#define DL2_HD_MODE_MASK 0x31165#define DL2_HD_MODE_MASK_SFT (0x3 << 0)1166 1167/* AFE_DL3_CON0 */1168#define DL3_MODE_SFT 241169#define DL3_MODE_MASK 0xf1170#define DL3_MODE_MASK_SFT (0xf << 24)1171#define DL3_MINLEN_SFT 201172#define DL3_MINLEN_MASK 0xf1173#define DL3_MINLEN_MASK_SFT (0xf << 20)1174#define DL3_MAXLEN_SFT 161175#define DL3_MAXLEN_MASK 0xf1176#define DL3_MAXLEN_MASK_SFT (0xf << 16)1177#define DL3_SW_CLEAR_BUF_EMPTY_SFT 151178#define DL3_SW_CLEAR_BUF_EMPTY_MASK 0x11179#define DL3_SW_CLEAR_BUF_EMPTY_MASK_SFT (0x1 << 15)1180#define DL3_PBUF_SIZE_SFT 121181#define DL3_PBUF_SIZE_MASK 0x31182#define DL3_PBUF_SIZE_MASK_SFT (0x3 << 12)1183#define DL3_MONO_SFT 81184#define DL3_MONO_MASK 0x11185#define DL3_MONO_MASK_SFT (0x1 << 8)1186#define DL3_NORMAL_MODE_SFT 51187#define DL3_NORMAL_MODE_MASK 0x11188#define DL3_NORMAL_MODE_MASK_SFT (0x1 << 5)1189#define DL3_HALIGN_SFT 41190#define DL3_HALIGN_MASK 0x11191#define DL3_HALIGN_MASK_SFT (0x1 << 4)1192#define DL3_HD_MODE_SFT 01193#define DL3_HD_MODE_MASK 0x31194#define DL3_HD_MODE_MASK_SFT (0x3 << 0)1195 1196/* AFE_DL4_CON0 */1197#define DL4_MODE_SFT 241198#define DL4_MODE_MASK 0xf1199#define DL4_MODE_MASK_SFT (0xf << 24)1200#define DL4_MINLEN_SFT 201201#define DL4_MINLEN_MASK 0xf1202#define DL4_MINLEN_MASK_SFT (0xf << 20)1203#define DL4_MAXLEN_SFT 161204#define DL4_MAXLEN_MASK 0xf1205#define DL4_MAXLEN_MASK_SFT (0xf << 16)1206#define DL4_SW_CLEAR_BUF_EMPTY_SFT 151207#define DL4_SW_CLEAR_BUF_EMPTY_MASK 0x11208#define DL4_SW_CLEAR_BUF_EMPTY_MASK_SFT (0x1 << 15)1209#define DL4_PBUF_SIZE_SFT 121210#define DL4_PBUF_SIZE_MASK 0x31211#define DL4_PBUF_SIZE_MASK_SFT (0x3 << 12)1212#define DL4_MONO_SFT 81213#define DL4_MONO_MASK 0x11214#define DL4_MONO_MASK_SFT (0x1 << 8)1215#define DL4_NORMAL_MODE_SFT 51216#define DL4_NORMAL_MODE_MASK 0x11217#define DL4_NORMAL_MODE_MASK_SFT (0x1 << 5)1218#define DL4_HALIGN_SFT 41219#define DL4_HALIGN_MASK 0x11220#define DL4_HALIGN_MASK_SFT (0x1 << 4)1221#define DL4_HD_MODE_SFT 01222#define DL4_HD_MODE_MASK 0x31223#define DL4_HD_MODE_MASK_SFT (0x3 << 0)1224 1225/* AFE_DL5_CON0 */1226#define DL5_MODE_SFT 241227#define DL5_MODE_MASK 0xf1228#define DL5_MODE_MASK_SFT (0xf << 24)1229#define DL5_MINLEN_SFT 201230#define DL5_MINLEN_MASK 0xf1231#define DL5_MINLEN_MASK_SFT (0xf << 20)1232#define DL5_MAXLEN_SFT 161233#define DL5_MAXLEN_MASK 0xf1234#define DL5_MAXLEN_MASK_SFT (0xf << 16)1235#define DL5_SW_CLEAR_BUF_EMPTY_SFT 151236#define DL5_SW_CLEAR_BUF_EMPTY_MASK 0x11237#define DL5_SW_CLEAR_BUF_EMPTY_MASK_SFT (0x1 << 15)1238#define DL5_PBUF_SIZE_SFT 121239#define DL5_PBUF_SIZE_MASK 0x31240#define DL5_PBUF_SIZE_MASK_SFT (0x3 << 12)1241#define DL5_MONO_SFT 81242#define DL5_MONO_MASK 0x11243#define DL5_MONO_MASK_SFT (0x1 << 8)1244#define DL5_NORMAL_MODE_SFT 51245#define DL5_NORMAL_MODE_MASK 0x11246#define DL5_NORMAL_MODE_MASK_SFT (0x1 << 5)1247#define DL5_HALIGN_SFT 41248#define DL5_HALIGN_MASK 0x11249#define DL5_HALIGN_MASK_SFT (0x1 << 4)1250#define DL5_HD_MODE_SFT 01251#define DL5_HD_MODE_MASK 0x31252#define DL5_HD_MODE_MASK_SFT (0x3 << 0)1253 1254/* AFE_DL6_CON0 */1255#define DL6_MODE_SFT 241256#define DL6_MODE_MASK 0xf1257#define DL6_MODE_MASK_SFT (0xf << 24)1258#define DL6_MINLEN_SFT 201259#define DL6_MINLEN_MASK 0xf1260#define DL6_MINLEN_MASK_SFT (0xf << 20)1261#define DL6_MAXLEN_SFT 161262#define DL6_MAXLEN_MASK 0xf1263#define DL6_MAXLEN_MASK_SFT (0xf << 16)1264#define DL6_SW_CLEAR_BUF_EMPTY_SFT 151265#define DL6_SW_CLEAR_BUF_EMPTY_MASK 0x11266#define DL6_SW_CLEAR_BUF_EMPTY_MASK_SFT (0x1 << 15)1267#define DL6_PBUF_SIZE_SFT 121268#define DL6_PBUF_SIZE_MASK 0x31269#define DL6_PBUF_SIZE_MASK_SFT (0x3 << 12)1270#define DL6_MONO_SFT 81271#define DL6_MONO_MASK 0x11272#define DL6_MONO_MASK_SFT (0x1 << 8)1273#define DL6_NORMAL_MODE_SFT 51274#define DL6_NORMAL_MODE_MASK 0x11275#define DL6_NORMAL_MODE_MASK_SFT (0x1 << 5)1276#define DL6_HALIGN_SFT 41277#define DL6_HALIGN_MASK 0x11278#define DL6_HALIGN_MASK_SFT (0x1 << 4)1279#define DL6_HD_MODE_SFT 01280#define DL6_HD_MODE_MASK 0x31281#define DL6_HD_MODE_MASK_SFT (0x3 << 0)1282 1283/* AFE_DL7_CON0 */1284#define DL7_MODE_SFT 241285#define DL7_MODE_MASK 0xf1286#define DL7_MODE_MASK_SFT (0xf << 24)1287#define DL7_MINLEN_SFT 201288#define DL7_MINLEN_MASK 0xf1289#define DL7_MINLEN_MASK_SFT (0xf << 20)1290#define DL7_MAXLEN_SFT 161291#define DL7_MAXLEN_MASK 0xf1292#define DL7_MAXLEN_MASK_SFT (0xf << 16)1293#define DL7_SW_CLEAR_BUF_EMPTY_SFT 151294#define DL7_SW_CLEAR_BUF_EMPTY_MASK 0x11295#define DL7_SW_CLEAR_BUF_EMPTY_MASK_SFT (0x1 << 15)1296#define DL7_PBUF_SIZE_SFT 121297#define DL7_PBUF_SIZE_MASK 0x31298#define DL7_PBUF_SIZE_MASK_SFT (0x3 << 12)1299#define DL7_MONO_SFT 81300#define DL7_MONO_MASK 0x11301#define DL7_MONO_MASK_SFT (0x1 << 8)1302#define DL7_NORMAL_MODE_SFT 51303#define DL7_NORMAL_MODE_MASK 0x11304#define DL7_NORMAL_MODE_MASK_SFT (0x1 << 5)1305#define DL7_HALIGN_SFT 41306#define DL7_HALIGN_MASK 0x11307#define DL7_HALIGN_MASK_SFT (0x1 << 4)1308#define DL7_HD_MODE_SFT 01309#define DL7_HD_MODE_MASK 0x31310#define DL7_HD_MODE_MASK_SFT (0x3 << 0)1311 1312/* AFE_DL8_CON0 */1313#define DL8_MODE_SFT 241314#define DL8_MODE_MASK 0xf1315#define DL8_MODE_MASK_SFT (0xf << 24)1316#define DL8_MINLEN_SFT 201317#define DL8_MINLEN_MASK 0xf1318#define DL8_MINLEN_MASK_SFT (0xf << 20)1319#define DL8_MAXLEN_SFT 161320#define DL8_MAXLEN_MASK 0xf1321#define DL8_MAXLEN_MASK_SFT (0xf << 16)1322#define DL8_SW_CLEAR_BUF_EMPTY_SFT 151323#define DL8_SW_CLEAR_BUF_EMPTY_MASK 0x11324#define DL8_SW_CLEAR_BUF_EMPTY_MASK_SFT (0x1 << 15)1325#define DL8_PBUF_SIZE_SFT 121326#define DL8_PBUF_SIZE_MASK 0x31327#define DL8_PBUF_SIZE_MASK_SFT (0x3 << 12)1328#define DL8_MONO_SFT 81329#define DL8_MONO_MASK 0x11330#define DL8_MONO_MASK_SFT (0x1 << 8)1331#define DL8_NORMAL_MODE_SFT 51332#define DL8_NORMAL_MODE_MASK 0x11333#define DL8_NORMAL_MODE_MASK_SFT (0x1 << 5)1334#define DL8_HALIGN_SFT 41335#define DL8_HALIGN_MASK 0x11336#define DL8_HALIGN_MASK_SFT (0x1 << 4)1337#define DL8_HD_MODE_SFT 01338#define DL8_HD_MODE_MASK 0x31339#define DL8_HD_MODE_MASK_SFT (0x3 << 0)1340 1341/* AFE_DL9_CON0 */1342#define DL9_MODE_SFT 241343#define DL9_MODE_MASK 0xf1344#define DL9_MODE_MASK_SFT (0xf << 24)1345#define DL9_MINLEN_SFT 201346#define DL9_MINLEN_MASK 0xf1347#define DL9_MINLEN_MASK_SFT (0xf << 20)1348#define DL9_MAXLEN_SFT 161349#define DL9_MAXLEN_MASK 0xf1350#define DL9_MAXLEN_MASK_SFT (0xf << 16)1351#define DL9_SW_CLEAR_BUF_EMPTY_SFT 151352#define DL9_SW_CLEAR_BUF_EMPTY_MASK 0x11353#define DL9_SW_CLEAR_BUF_EMPTY_MASK_SFT (0x1 << 15)1354#define DL9_PBUF_SIZE_SFT 121355#define DL9_PBUF_SIZE_MASK 0x31356#define DL9_PBUF_SIZE_MASK_SFT (0x3 << 12)1357#define DL9_MONO_SFT 81358#define DL9_MONO_MASK 0x11359#define DL9_MONO_MASK_SFT (0x1 << 8)1360#define DL9_NORMAL_MODE_SFT 51361#define DL9_NORMAL_MODE_MASK 0x11362#define DL9_NORMAL_MODE_MASK_SFT (0x1 << 5)1363#define DL9_HALIGN_SFT 41364#define DL9_HALIGN_MASK 0x11365#define DL9_HALIGN_MASK_SFT (0x1 << 4)1366#define DL9_HD_MODE_SFT 01367#define DL9_HD_MODE_MASK 0x31368#define DL9_HD_MODE_MASK_SFT (0x3 << 0)1369 1370/* AFE_DL12_CON0 */1371#define DL12_MODE_SFT 241372#define DL12_MODE_MASK 0xf1373#define DL12_MODE_MASK_SFT (0xf << 24)1374#define DL12_MINLEN_SFT 201375#define DL12_MINLEN_MASK 0xf1376#define DL12_MINLEN_MASK_SFT (0xf << 20)1377#define DL12_MAXLEN_SFT 161378#define DL12_MAXLEN_MASK 0xf1379#define DL12_MAXLEN_MASK_SFT (0xf << 16)1380#define DL12_SW_CLEAR_BUF_EMPTY_SFT 151381#define DL12_SW_CLEAR_BUF_EMPTY_MASK 0x11382#define DL12_SW_CLEAR_BUF_EMPTY_MASK_SFT (0x1 << 15)1383#define DL12_PBUF_SIZE_SFT 121384#define DL12_PBUF_SIZE_MASK 0x31385#define DL12_PBUF_SIZE_MASK_SFT (0x3 << 12)1386#define DL12_4CH_EN_SFT 111387#define DL12_4CH_EN_MASK 0x11388#define DL12_4CH_EN_MASK_SFT (0x1 << 11)1389#define DL12_MONO_SFT 81390#define DL12_MONO_MASK 0x11391#define DL12_MONO_MASK_SFT (0x1 << 8)1392#define DL12_NORMAL_MODE_SFT 51393#define DL12_NORMAL_MODE_MASK 0x11394#define DL12_NORMAL_MODE_MASK_SFT (0x1 << 5)1395#define DL12_HALIGN_SFT 41396#define DL12_HALIGN_MASK 0x11397#define DL12_HALIGN_MASK_SFT (0x1 << 4)1398#define DL12_HD_MODE_SFT 01399#define DL12_HD_MODE_MASK 0x31400#define DL12_HD_MODE_MASK_SFT (0x3 << 0)1401 1402/* AFE_AWB_CON0 */1403#define AWB_MODE_SFT 241404#define AWB_MODE_MASK 0xf1405#define AWB_MODE_MASK_SFT (0xf << 24)1406#define AWB_SW_CLEAR_BUF_FULL_SFT 151407#define AWB_SW_CLEAR_BUF_FULL_MASK 0x11408#define AWB_SW_CLEAR_BUF_FULL_MASK_SFT (0x1 << 15)1409#define AWB_R_MONO_SFT 91410#define AWB_R_MONO_MASK 0x11411#define AWB_R_MONO_MASK_SFT (0x1 << 9)1412#define AWB_MONO_SFT 81413#define AWB_MONO_MASK 0x11414#define AWB_MONO_MASK_SFT (0x1 << 8)1415#define AWB_WR_SIGN_SFT 61416#define AWB_WR_SIGN_MASK 0x11417#define AWB_WR_SIGN_MASK_SFT (0x1 << 6)1418#define AWB_NORMAL_MODE_SFT 51419#define AWB_NORMAL_MODE_MASK 0x11420#define AWB_NORMAL_MODE_MASK_SFT (0x1 << 5)1421#define AWB_HALIGN_SFT 41422#define AWB_HALIGN_MASK 0x11423#define AWB_HALIGN_MASK_SFT (0x1 << 4)1424#define AWB_HD_MODE_SFT 01425#define AWB_HD_MODE_MASK 0x31426#define AWB_HD_MODE_MASK_SFT (0x3 << 0)1427 1428/* AFE_AWB2_CON0 */1429#define AWB2_MODE_SFT 241430#define AWB2_MODE_MASK 0xf1431#define AWB2_MODE_MASK_SFT (0xf << 24)1432#define AWB2_SW_CLEAR_BUF_FULL_SFT 151433#define AWB2_SW_CLEAR_BUF_FULL_MASK 0x11434#define AWB2_SW_CLEAR_BUF_FULL_MASK_SFT (0x1 << 15)1435#define AWB2_R_MONO_SFT 91436#define AWB2_R_MONO_MASK 0x11437#define AWB2_R_MONO_MASK_SFT (0x1 << 9)1438#define AWB2_MONO_SFT 81439#define AWB2_MONO_MASK 0x11440#define AWB2_MONO_MASK_SFT (0x1 << 8)1441#define AWB2_WR_SIGN_SFT 61442#define AWB2_WR_SIGN_MASK 0x11443#define AWB2_WR_SIGN_MASK_SFT (0x1 << 6)1444#define AWB2_NORMAL_MODE_SFT 51445#define AWB2_NORMAL_MODE_MASK 0x11446#define AWB2_NORMAL_MODE_MASK_SFT (0x1 << 5)1447#define AWB2_HALIGN_SFT 41448#define AWB2_HALIGN_MASK 0x11449#define AWB2_HALIGN_MASK_SFT (0x1 << 4)1450#define AWB2_HD_MODE_SFT 01451#define AWB2_HD_MODE_MASK 0x31452#define AWB2_HD_MODE_MASK_SFT (0x3 << 0)1453 1454/* AFE_VUL_CON0 */1455#define VUL_MODE_SFT 241456#define VUL_MODE_MASK 0xf1457#define VUL_MODE_MASK_SFT (0xf << 24)1458#define VUL_SW_CLEAR_BUF_FULL_SFT 151459#define VUL_SW_CLEAR_BUF_FULL_MASK 0x11460#define VUL_SW_CLEAR_BUF_FULL_MASK_SFT (0x1 << 15)1461#define VUL_R_MONO_SFT 91462#define VUL_R_MONO_MASK 0x11463#define VUL_R_MONO_MASK_SFT (0x1 << 9)1464#define VUL_MONO_SFT 81465#define VUL_MONO_MASK 0x11466#define VUL_MONO_MASK_SFT (0x1 << 8)1467#define VUL_WR_SIGN_SFT 61468#define VUL_WR_SIGN_MASK 0x11469#define VUL_WR_SIGN_MASK_SFT (0x1 << 6)1470#define VUL_NORMAL_MODE_SFT 51471#define VUL_NORMAL_MODE_MASK 0x11472#define VUL_NORMAL_MODE_MASK_SFT (0x1 << 5)1473#define VUL_HALIGN_SFT 41474#define VUL_HALIGN_MASK 0x11475#define VUL_HALIGN_MASK_SFT (0x1 << 4)1476#define VUL_HD_MODE_SFT 01477#define VUL_HD_MODE_MASK 0x31478#define VUL_HD_MODE_MASK_SFT (0x3 << 0)1479 1480/* AFE_VUL12_CON0 */1481#define VUL12_MODE_SFT 241482#define VUL12_MODE_MASK 0xf1483#define VUL12_MODE_MASK_SFT (0xf << 24)1484#define VUL12_SW_CLEAR_BUF_FULL_SFT 151485#define VUL12_SW_CLEAR_BUF_FULL_MASK 0x11486#define VUL12_SW_CLEAR_BUF_FULL_MASK_SFT (0x1 << 15)1487#define VUL12_4CH_EN_SFT 111488#define VUL12_4CH_EN_MASK 0x11489#define VUL12_4CH_EN_MASK_SFT (0x1 << 11)1490#define VUL12_R_MONO_SFT 91491#define VUL12_R_MONO_MASK 0x11492#define VUL12_R_MONO_MASK_SFT (0x1 << 9)1493#define VUL12_MONO_SFT 81494#define VUL12_MONO_MASK 0x11495#define VUL12_MONO_MASK_SFT (0x1 << 8)1496#define VUL12_WR_SIGN_SFT 61497#define VUL12_WR_SIGN_MASK 0x11498#define VUL12_WR_SIGN_MASK_SFT (0x1 << 6)1499#define VUL12_NORMAL_MODE_SFT 51500#define VUL12_NORMAL_MODE_MASK 0x11501#define VUL12_NORMAL_MODE_MASK_SFT (0x1 << 5)1502#define VUL12_HALIGN_SFT 41503#define VUL12_HALIGN_MASK 0x11504#define VUL12_HALIGN_MASK_SFT (0x1 << 4)1505#define VUL12_HD_MODE_SFT 01506#define VUL12_HD_MODE_MASK 0x31507#define VUL12_HD_MODE_MASK_SFT (0x3 << 0)1508 1509/* AFE_VUL2_CON0 */1510#define VUL2_MODE_SFT 241511#define VUL2_MODE_MASK 0xf1512#define VUL2_MODE_MASK_SFT (0xf << 24)1513#define VUL2_SW_CLEAR_BUF_FULL_SFT 151514#define VUL2_SW_CLEAR_BUF_FULL_MASK 0x11515#define VUL2_SW_CLEAR_BUF_FULL_MASK_SFT (0x1 << 15)1516#define VUL2_R_MONO_SFT 91517#define VUL2_R_MONO_MASK 0x11518#define VUL2_R_MONO_MASK_SFT (0x1 << 9)1519#define VUL2_MONO_SFT 81520#define VUL2_MONO_MASK 0x11521#define VUL2_MONO_MASK_SFT (0x1 << 8)1522#define VUL2_WR_SIGN_SFT 61523#define VUL2_WR_SIGN_MASK 0x11524#define VUL2_WR_SIGN_MASK_SFT (0x1 << 6)1525#define VUL2_NORMAL_MODE_SFT 51526#define VUL2_NORMAL_MODE_MASK 0x11527#define VUL2_NORMAL_MODE_MASK_SFT (0x1 << 5)1528#define VUL2_HALIGN_SFT 41529#define VUL2_HALIGN_MASK 0x11530#define VUL2_HALIGN_MASK_SFT (0x1 << 4)1531#define VUL2_HD_MODE_SFT 01532#define VUL2_HD_MODE_MASK 0x31533#define VUL2_HD_MODE_MASK_SFT (0x3 << 0)1534 1535/* AFE_VUL3_CON0 */1536#define VUL3_MODE_SFT 241537#define VUL3_MODE_MASK 0xf1538#define VUL3_MODE_MASK_SFT (0xf << 24)1539#define VUL3_SW_CLEAR_BUF_FULL_SFT 151540#define VUL3_SW_CLEAR_BUF_FULL_MASK 0x11541#define VUL3_SW_CLEAR_BUF_FULL_MASK_SFT (0x1 << 15)1542#define VUL3_R_MONO_SFT 91543#define VUL3_R_MONO_MASK 0x11544#define VUL3_R_MONO_MASK_SFT (0x1 << 9)1545#define VUL3_MONO_SFT 81546#define VUL3_MONO_MASK 0x11547#define VUL3_MONO_MASK_SFT (0x1 << 8)1548#define VUL3_WR_SIGN_SFT 61549#define VUL3_WR_SIGN_MASK 0x11550#define VUL3_WR_SIGN_MASK_SFT (0x1 << 6)1551#define VUL3_NORMAL_MODE_SFT 51552#define VUL3_NORMAL_MODE_MASK 0x11553#define VUL3_NORMAL_MODE_MASK_SFT (0x1 << 5)1554#define VUL3_HALIGN_SFT 41555#define VUL3_HALIGN_MASK 0x11556#define VUL3_HALIGN_MASK_SFT (0x1 << 4)1557#define VUL3_HD_MODE_SFT 01558#define VUL3_HD_MODE_MASK 0x31559#define VUL3_HD_MODE_MASK_SFT (0x3 << 0)1560 1561/* AFE_VUL4_CON0 */1562#define VUL4_MODE_SFT 241563#define VUL4_MODE_MASK 0xf1564#define VUL4_MODE_MASK_SFT (0xf << 24)1565#define VUL4_SW_CLEAR_BUF_FULL_SFT 151566#define VUL4_SW_CLEAR_BUF_FULL_MASK 0x11567#define VUL4_SW_CLEAR_BUF_FULL_MASK_SFT (0x1 << 15)1568#define VUL4_R_MONO_SFT 91569#define VUL4_R_MONO_MASK 0x11570#define VUL4_R_MONO_MASK_SFT (0x1 << 9)1571#define VUL4_MONO_SFT 81572#define VUL4_MONO_MASK 0x11573#define VUL4_MONO_MASK_SFT (0x1 << 8)1574#define VUL4_WR_SIGN_SFT 61575#define VUL4_WR_SIGN_MASK 0x11576#define VUL4_WR_SIGN_MASK_SFT (0x1 << 6)1577#define VUL4_NORMAL_MODE_SFT 51578#define VUL4_NORMAL_MODE_MASK 0x11579#define VUL4_NORMAL_MODE_MASK_SFT (0x1 << 5)1580#define VUL4_HALIGN_SFT 41581#define VUL4_HALIGN_MASK 0x11582#define VUL4_HALIGN_MASK_SFT (0x1 << 4)1583#define VUL4_HD_MODE_SFT 01584#define VUL4_HD_MODE_MASK 0x31585#define VUL4_HD_MODE_MASK_SFT (0x3 << 0)1586 1587/* AFE_VUL5_CON0 */1588#define VUL5_MODE_SFT 241589#define VUL5_MODE_MASK 0xf1590#define VUL5_MODE_MASK_SFT (0xf << 24)1591#define VUL5_SW_CLEAR_BUF_FULL_SFT 151592#define VUL5_SW_CLEAR_BUF_FULL_MASK 0x11593#define VUL5_SW_CLEAR_BUF_FULL_MASK_SFT (0x1 << 15)1594#define VUL5_R_MONO_SFT 91595#define VUL5_R_MONO_MASK 0x11596#define VUL5_R_MONO_MASK_SFT (0x1 << 9)1597#define VUL5_MONO_SFT 81598#define VUL5_MONO_MASK 0x11599#define VUL5_MONO_MASK_SFT (0x1 << 8)1600#define VUL5_WR_SIGN_SFT 61601#define VUL5_WR_SIGN_MASK 0x11602#define VUL5_WR_SIGN_MASK_SFT (0x1 << 6)1603#define VUL5_NORMAL_MODE_SFT 51604#define VUL5_NORMAL_MODE_MASK 0x11605#define VUL5_NORMAL_MODE_MASK_SFT (0x1 << 5)1606#define VUL5_HALIGN_SFT 41607#define VUL5_HALIGN_MASK 0x11608#define VUL5_HALIGN_MASK_SFT (0x1 << 4)1609#define VUL5_HD_MODE_SFT 01610#define VUL5_HD_MODE_MASK 0x31611#define VUL5_HD_MODE_MASK_SFT (0x3 << 0)1612 1613/* AFE_VUL6_CON0 */1614#define VUL6_MODE_SFT 241615#define VUL6_MODE_MASK 0xf1616#define VUL6_MODE_MASK_SFT (0xf << 24)1617#define VUL6_SW_CLEAR_BUF_FULL_SFT 151618#define VUL6_SW_CLEAR_BUF_FULL_MASK 0x11619#define VUL6_SW_CLEAR_BUF_FULL_MASK_SFT (0x1 << 15)1620#define VUL6_R_MONO_SFT 91621#define VUL6_R_MONO_MASK 0x11622#define VUL6_R_MONO_MASK_SFT (0x1 << 9)1623#define VUL6_MONO_SFT 81624#define VUL6_MONO_MASK 0x11625#define VUL6_MONO_MASK_SFT (0x1 << 8)1626#define VUL6_WR_SIGN_SFT 61627#define VUL6_WR_SIGN_MASK 0x11628#define VUL6_WR_SIGN_MASK_SFT (0x1 << 6)1629#define VUL6_NORMAL_MODE_SFT 51630#define VUL6_NORMAL_MODE_MASK 0x11631#define VUL6_NORMAL_MODE_MASK_SFT (0x1 << 5)1632#define VUL6_HALIGN_SFT 41633#define VUL6_HALIGN_MASK 0x11634#define VUL6_HALIGN_MASK_SFT (0x1 << 4)1635#define VUL6_HD_MODE_SFT 01636#define VUL6_HD_MODE_MASK 0x31637#define VUL6_HD_MODE_MASK_SFT (0x3 << 0)1638 1639/* AFE_DAI_CON0 */1640#define DAI_MODE_SFT 241641#define DAI_MODE_MASK 0x31642#define DAI_MODE_MASK_SFT (0x3 << 24)1643#define DAI_SW_CLEAR_BUF_FULL_SFT 151644#define DAI_SW_CLEAR_BUF_FULL_MASK 0x11645#define DAI_SW_CLEAR_BUF_FULL_MASK_SFT (0x1 << 15)1646#define DAI_DUPLICATE_WR_SFT 101647#define DAI_DUPLICATE_WR_MASK 0x11648#define DAI_DUPLICATE_WR_MASK_SFT (0x1 << 10)1649#define DAI_MONO_SFT 81650#define DAI_MONO_MASK 0x11651#define DAI_MONO_MASK_SFT (0x1 << 8)1652#define DAI_WR_SIGN_SFT 61653#define DAI_WR_SIGN_MASK 0x11654#define DAI_WR_SIGN_MASK_SFT (0x1 << 6)1655#define DAI_NORMAL_MODE_SFT 51656#define DAI_NORMAL_MODE_MASK 0x11657#define DAI_NORMAL_MODE_MASK_SFT (0x1 << 5)1658#define DAI_HALIGN_SFT 41659#define DAI_HALIGN_MASK 0x11660#define DAI_HALIGN_MASK_SFT (0x1 << 4)1661#define DAI_HD_MODE_SFT 01662#define DAI_HD_MODE_MASK 0x31663#define DAI_HD_MODE_MASK_SFT (0x3 << 0)1664 1665/* AFE_MOD_DAI_CON0 */1666#define MOD_DAI_MODE_SFT 241667#define MOD_DAI_MODE_MASK 0x31668#define MOD_DAI_MODE_MASK_SFT (0x3 << 24)1669#define MOD_DAI_SW_CLEAR_BUF_FULL_SFT 151670#define MOD_DAI_SW_CLEAR_BUF_FULL_MASK 0x11671#define MOD_DAI_SW_CLEAR_BUF_FULL_MASK_SFT (0x1 << 15)1672#define MOD_DAI_DUPLICATE_WR_SFT 101673#define MOD_DAI_DUPLICATE_WR_MASK 0x11674#define MOD_DAI_DUPLICATE_WR_MASK_SFT (0x1 << 10)1675#define MOD_DAI_MONO_SFT 81676#define MOD_DAI_MONO_MASK 0x11677#define MOD_DAI_MONO_MASK_SFT (0x1 << 8)1678#define MOD_DAI_WR_SIGN_SFT 61679#define MOD_DAI_WR_SIGN_MASK 0x11680#define MOD_DAI_WR_SIGN_MASK_SFT (0x1 << 6)1681#define MOD_DAI_NORMAL_MODE_SFT 51682#define MOD_DAI_NORMAL_MODE_MASK 0x11683#define MOD_DAI_NORMAL_MODE_MASK_SFT (0x1 << 5)1684#define MOD_DAI_HALIGN_SFT 41685#define MOD_DAI_HALIGN_MASK 0x11686#define MOD_DAI_HALIGN_MASK_SFT (0x1 << 4)1687#define MOD_DAI_HD_MODE_SFT 01688#define MOD_DAI_HD_MODE_MASK 0x31689#define MOD_DAI_HD_MODE_MASK_SFT (0x3 << 0)1690 1691/* AFE_DAI2_CON0 */1692#define DAI2_MODE_SFT 241693#define DAI2_MODE_MASK 0xf1694#define DAI2_MODE_MASK_SFT (0xf << 24)1695#define DAI2_SW_CLEAR_BUF_FULL_SFT 151696#define DAI2_SW_CLEAR_BUF_FULL_MASK 0x11697#define DAI2_SW_CLEAR_BUF_FULL_MASK_SFT (0x1 << 15)1698#define DAI2_DUPLICATE_WR_SFT 101699#define DAI2_DUPLICATE_WR_MASK 0x11700#define DAI2_DUPLICATE_WR_MASK_SFT (0x1 << 10)1701#define DAI2_MONO_SFT 81702#define DAI2_MONO_MASK 0x11703#define DAI2_MONO_MASK_SFT (0x1 << 8)1704#define DAI2_WR_SIGN_SFT 61705#define DAI2_WR_SIGN_MASK 0x11706#define DAI2_WR_SIGN_MASK_SFT (0x1 << 6)1707#define DAI2_NORMAL_MODE_SFT 51708#define DAI2_NORMAL_MODE_MASK 0x11709#define DAI2_NORMAL_MODE_MASK_SFT (0x1 << 5)1710#define DAI2_HALIGN_SFT 41711#define DAI2_HALIGN_MASK 0x11712#define DAI2_HALIGN_MASK_SFT (0x1 << 4)1713#define DAI2_HD_MODE_SFT 01714#define DAI2_HD_MODE_MASK 0x31715#define DAI2_HD_MODE_MASK_SFT (0x3 << 0)1716 1717/* AFE_MEMIF_CON0 */1718#define CPU_COMPACT_MODE_SFT 21719#define CPU_COMPACT_MODE_MASK 0x11720#define CPU_COMPACT_MODE_MASK_SFT (0x1 << 2)1721#define CPU_HD_ALIGN_SFT 11722#define CPU_HD_ALIGN_MASK 0x11723#define CPU_HD_ALIGN_MASK_SFT (0x1 << 1)1724#define SYSRAM_SIGN_SFT 01725#define SYSRAM_SIGN_MASK 0x11726#define SYSRAM_SIGN_MASK_SFT (0x1 << 0)1727 1728/* AFE_HDMI_OUT_CON0 */1729#define HDMI_CH_NUM_SFT 241730#define HDMI_CH_NUM_MASK 0xf1731#define HDMI_CH_NUM_MASK_SFT (0xf << 24)1732#define HDMI_OUT_MINLEN_SFT 201733#define HDMI_OUT_MINLEN_MASK 0xf1734#define HDMI_OUT_MINLEN_MASK_SFT (0xf << 20)1735#define HDMI_OUT_MAXLEN_SFT 161736#define HDMI_OUT_MAXLEN_MASK 0xf1737#define HDMI_OUT_MAXLEN_MASK_SFT (0xf << 16)1738#define HDMI_OUT_SW_CLEAR_BUF_EMPTY_SFT 151739#define HDMI_OUT_SW_CLEAR_BUF_EMPTY_MASK 0x11740#define HDMI_OUT_SW_CLEAR_BUF_EMPTY_MASK_SFT (0x1 << 15)1741#define HDMI_OUT_PBUF_SIZE_SFT 121742#define HDMI_OUT_PBUF_SIZE_MASK 0x31743#define HDMI_OUT_PBUF_SIZE_MASK_SFT (0x3 << 12)1744#define HDMI_OUT_NORMAL_MODE_SFT 51745#define HDMI_OUT_NORMAL_MODE_MASK 0x11746#define HDMI_OUT_NORMAL_MODE_MASK_SFT (0x1 << 5)1747#define HDMI_OUT_HALIGN_SFT 41748#define HDMI_OUT_HALIGN_MASK 0x11749#define HDMI_OUT_HALIGN_MASK_SFT (0x1 << 4)1750#define HDMI_OUT_HD_MODE_SFT 01751#define HDMI_OUT_HD_MODE_MASK 0x31752#define HDMI_OUT_HD_MODE_MASK_SFT (0x3 << 0)1753 1754/* AFE_IRQ_MCU_CON0 */1755#define IRQ31_MCU_ON_SFT 311756#define IRQ31_MCU_ON_MASK 0x11757#define IRQ31_MCU_ON_MASK_SFT (0x1 << 31)1758#define IRQ26_MCU_ON_SFT 261759#define IRQ26_MCU_ON_MASK 0x11760#define IRQ26_MCU_ON_MASK_SFT (0x1 << 26)1761#define IRQ25_MCU_ON_SFT 251762#define IRQ25_MCU_ON_MASK 0x11763#define IRQ25_MCU_ON_MASK_SFT (0x1 << 25)1764#define IRQ24_MCU_ON_SFT 241765#define IRQ24_MCU_ON_MASK 0x11766#define IRQ24_MCU_ON_MASK_SFT (0x1 << 24)1767#define IRQ23_MCU_ON_SFT 231768#define IRQ23_MCU_ON_MASK 0x11769#define IRQ23_MCU_ON_MASK_SFT (0x1 << 23)1770#define IRQ22_MCU_ON_SFT 221771#define IRQ22_MCU_ON_MASK 0x11772#define IRQ22_MCU_ON_MASK_SFT (0x1 << 22)1773#define IRQ21_MCU_ON_SFT 211774#define IRQ21_MCU_ON_MASK 0x11775#define IRQ21_MCU_ON_MASK_SFT (0x1 << 21)1776#define IRQ20_MCU_ON_SFT 201777#define IRQ20_MCU_ON_MASK 0x11778#define IRQ20_MCU_ON_MASK_SFT (0x1 << 20)1779#define IRQ19_MCU_ON_SFT 191780#define IRQ19_MCU_ON_MASK 0x11781#define IRQ19_MCU_ON_MASK_SFT (0x1 << 19)1782#define IRQ18_MCU_ON_SFT 181783#define IRQ18_MCU_ON_MASK 0x11784#define IRQ18_MCU_ON_MASK_SFT (0x1 << 18)1785#define IRQ17_MCU_ON_SFT 171786#define IRQ17_MCU_ON_MASK 0x11787#define IRQ17_MCU_ON_MASK_SFT (0x1 << 17)1788#define IRQ16_MCU_ON_SFT 161789#define IRQ16_MCU_ON_MASK 0x11790#define IRQ16_MCU_ON_MASK_SFT (0x1 << 16)1791#define IRQ15_MCU_ON_SFT 151792#define IRQ15_MCU_ON_MASK 0x11793#define IRQ15_MCU_ON_MASK_SFT (0x1 << 15)1794#define IRQ14_MCU_ON_SFT 141795#define IRQ14_MCU_ON_MASK 0x11796#define IRQ14_MCU_ON_MASK_SFT (0x1 << 14)1797#define IRQ13_MCU_ON_SFT 131798#define IRQ13_MCU_ON_MASK 0x11799#define IRQ13_MCU_ON_MASK_SFT (0x1 << 13)1800#define IRQ12_MCU_ON_SFT 121801#define IRQ12_MCU_ON_MASK 0x11802#define IRQ12_MCU_ON_MASK_SFT (0x1 << 12)1803#define IRQ11_MCU_ON_SFT 111804#define IRQ11_MCU_ON_MASK 0x11805#define IRQ11_MCU_ON_MASK_SFT (0x1 << 11)1806#define IRQ10_MCU_ON_SFT 101807#define IRQ10_MCU_ON_MASK 0x11808#define IRQ10_MCU_ON_MASK_SFT (0x1 << 10)1809#define IRQ9_MCU_ON_SFT 91810#define IRQ9_MCU_ON_MASK 0x11811#define IRQ9_MCU_ON_MASK_SFT (0x1 << 9)1812#define IRQ8_MCU_ON_SFT 81813#define IRQ8_MCU_ON_MASK 0x11814#define IRQ8_MCU_ON_MASK_SFT (0x1 << 8)1815#define IRQ7_MCU_ON_SFT 71816#define IRQ7_MCU_ON_MASK 0x11817#define IRQ7_MCU_ON_MASK_SFT (0x1 << 7)1818#define IRQ6_MCU_ON_SFT 61819#define IRQ6_MCU_ON_MASK 0x11820#define IRQ6_MCU_ON_MASK_SFT (0x1 << 6)1821#define IRQ5_MCU_ON_SFT 51822#define IRQ5_MCU_ON_MASK 0x11823#define IRQ5_MCU_ON_MASK_SFT (0x1 << 5)1824#define IRQ4_MCU_ON_SFT 41825#define IRQ4_MCU_ON_MASK 0x11826#define IRQ4_MCU_ON_MASK_SFT (0x1 << 4)1827#define IRQ3_MCU_ON_SFT 31828#define IRQ3_MCU_ON_MASK 0x11829#define IRQ3_MCU_ON_MASK_SFT (0x1 << 3)1830#define IRQ2_MCU_ON_SFT 21831#define IRQ2_MCU_ON_MASK 0x11832#define IRQ2_MCU_ON_MASK_SFT (0x1 << 2)1833#define IRQ1_MCU_ON_SFT 11834#define IRQ1_MCU_ON_MASK 0x11835#define IRQ1_MCU_ON_MASK_SFT (0x1 << 1)1836#define IRQ0_MCU_ON_SFT 01837#define IRQ0_MCU_ON_MASK 0x11838#define IRQ0_MCU_ON_MASK_SFT (0x1 << 0)1839 1840/* AFE_IRQ_MCU_CON1 */1841#define IRQ7_MCU_MODE_SFT 281842#define IRQ7_MCU_MODE_MASK 0xf1843#define IRQ7_MCU_MODE_MASK_SFT (0xf << 28)1844#define IRQ6_MCU_MODE_SFT 241845#define IRQ6_MCU_MODE_MASK 0xf1846#define IRQ6_MCU_MODE_MASK_SFT (0xf << 24)1847#define IRQ5_MCU_MODE_SFT 201848#define IRQ5_MCU_MODE_MASK 0xf1849#define IRQ5_MCU_MODE_MASK_SFT (0xf << 20)1850#define IRQ4_MCU_MODE_SFT 161851#define IRQ4_MCU_MODE_MASK 0xf1852#define IRQ4_MCU_MODE_MASK_SFT (0xf << 16)1853#define IRQ3_MCU_MODE_SFT 121854#define IRQ3_MCU_MODE_MASK 0xf1855#define IRQ3_MCU_MODE_MASK_SFT (0xf << 12)1856#define IRQ2_MCU_MODE_SFT 81857#define IRQ2_MCU_MODE_MASK 0xf1858#define IRQ2_MCU_MODE_MASK_SFT (0xf << 8)1859#define IRQ1_MCU_MODE_SFT 41860#define IRQ1_MCU_MODE_MASK 0xf1861#define IRQ1_MCU_MODE_MASK_SFT (0xf << 4)1862#define IRQ0_MCU_MODE_SFT 01863#define IRQ0_MCU_MODE_MASK 0xf1864#define IRQ0_MCU_MODE_MASK_SFT (0xf << 0)1865 1866/* AFE_IRQ_MCU_CON2 */1867#define IRQ15_MCU_MODE_SFT 281868#define IRQ15_MCU_MODE_MASK 0xf1869#define IRQ15_MCU_MODE_MASK_SFT (0xf << 28)1870#define IRQ14_MCU_MODE_SFT 241871#define IRQ14_MCU_MODE_MASK 0xf1872#define IRQ14_MCU_MODE_MASK_SFT (0xf << 24)1873#define IRQ13_MCU_MODE_SFT 201874#define IRQ13_MCU_MODE_MASK 0xf1875#define IRQ13_MCU_MODE_MASK_SFT (0xf << 20)1876#define IRQ12_MCU_MODE_SFT 161877#define IRQ12_MCU_MODE_MASK 0xf1878#define IRQ12_MCU_MODE_MASK_SFT (0xf << 16)1879#define IRQ11_MCU_MODE_SFT 121880#define IRQ11_MCU_MODE_MASK 0xf1881#define IRQ11_MCU_MODE_MASK_SFT (0xf << 12)1882#define IRQ10_MCU_MODE_SFT 81883#define IRQ10_MCU_MODE_MASK 0xf1884#define IRQ10_MCU_MODE_MASK_SFT (0xf << 8)1885#define IRQ9_MCU_MODE_SFT 41886#define IRQ9_MCU_MODE_MASK 0xf1887#define IRQ9_MCU_MODE_MASK_SFT (0xf << 4)1888#define IRQ8_MCU_MODE_SFT 01889#define IRQ8_MCU_MODE_MASK 0xf1890#define IRQ8_MCU_MODE_MASK_SFT (0xf << 0)1891 1892/* AFE_IRQ_MCU_CON3 */1893#define IRQ23_MCU_MODE_SFT 281894#define IRQ23_MCU_MODE_MASK 0xf1895#define IRQ23_MCU_MODE_MASK_SFT (0xf << 28)1896#define IRQ22_MCU_MODE_SFT 241897#define IRQ22_MCU_MODE_MASK 0xf1898#define IRQ22_MCU_MODE_MASK_SFT (0xf << 24)1899#define IRQ21_MCU_MODE_SFT 201900#define IRQ21_MCU_MODE_MASK 0xf1901#define IRQ21_MCU_MODE_MASK_SFT (0xf << 20)1902#define IRQ20_MCU_MODE_SFT 161903#define IRQ20_MCU_MODE_MASK 0xf1904#define IRQ20_MCU_MODE_MASK_SFT (0xf << 16)1905#define IRQ19_MCU_MODE_SFT 121906#define IRQ19_MCU_MODE_MASK 0xf1907#define IRQ19_MCU_MODE_MASK_SFT (0xf << 12)1908#define IRQ18_MCU_MODE_SFT 81909#define IRQ18_MCU_MODE_MASK 0xf1910#define IRQ18_MCU_MODE_MASK_SFT (0xf << 8)1911#define IRQ17_MCU_MODE_SFT 41912#define IRQ17_MCU_MODE_MASK 0xf1913#define IRQ17_MCU_MODE_MASK_SFT (0xf << 4)1914#define IRQ16_MCU_MODE_SFT 01915#define IRQ16_MCU_MODE_MASK 0xf1916#define IRQ16_MCU_MODE_MASK_SFT (0xf << 0)1917 1918/* AFE_IRQ_MCU_CON4 */1919#define IRQ26_MCU_MODE_SFT 81920#define IRQ26_MCU_MODE_MASK 0xf1921#define IRQ26_MCU_MODE_MASK_SFT (0xf << 8)1922#define IRQ25_MCU_MODE_SFT 41923#define IRQ25_MCU_MODE_MASK 0xf1924#define IRQ25_MCU_MODE_MASK_SFT (0xf << 4)1925#define IRQ24_MCU_MODE_SFT 01926#define IRQ24_MCU_MODE_MASK 0xf1927#define IRQ24_MCU_MODE_MASK_SFT (0xf << 0)1928 1929/* AFE_IRQ_MCU_CLR */1930#define IRQ31_MCU_CLR_SFT 311931#define IRQ31_MCU_CLR_MASK 0x11932#define IRQ31_MCU_CLR_MASK_SFT (0x1 << 31)1933#define IRQ26_MCU_CLR_SFT 261934#define IRQ26_MCU_CLR_MASK 0x11935#define IRQ26_MCU_CLR_MASK_SFT (0x1 << 26)1936#define IRQ25_MCU_CLR_SFT 251937#define IRQ25_MCU_CLR_MASK 0x11938#define IRQ25_MCU_CLR_MASK_SFT (0x1 << 25)1939#define IRQ24_MCU_CLR_SFT 241940#define IRQ24_MCU_CLR_MASK 0x11941#define IRQ24_MCU_CLR_MASK_SFT (0x1 << 24)1942#define IRQ23_MCU_CLR_SFT 231943#define IRQ23_MCU_CLR_MASK 0x11944#define IRQ23_MCU_CLR_MASK_SFT (0x1 << 23)1945#define IRQ22_MCU_CLR_SFT 221946#define IRQ22_MCU_CLR_MASK 0x11947#define IRQ22_MCU_CLR_MASK_SFT (0x1 << 22)1948#define IRQ21_MCU_CLR_SFT 211949#define IRQ21_MCU_CLR_MASK 0x11950#define IRQ21_MCU_CLR_MASK_SFT (0x1 << 21)1951#define IRQ20_MCU_CLR_SFT 201952#define IRQ20_MCU_CLR_MASK 0x11953#define IRQ20_MCU_CLR_MASK_SFT (0x1 << 20)1954#define IRQ19_MCU_CLR_SFT 191955#define IRQ19_MCU_CLR_MASK 0x11956#define IRQ19_MCU_CLR_MASK_SFT (0x1 << 19)1957#define IRQ18_MCU_CLR_SFT 181958#define IRQ18_MCU_CLR_MASK 0x11959#define IRQ18_MCU_CLR_MASK_SFT (0x1 << 18)1960#define IRQ17_MCU_CLR_SFT 171961#define IRQ17_MCU_CLR_MASK 0x11962#define IRQ17_MCU_CLR_MASK_SFT (0x1 << 17)1963#define IRQ16_MCU_CLR_SFT 161964#define IRQ16_MCU_CLR_MASK 0x11965#define IRQ16_MCU_CLR_MASK_SFT (0x1 << 16)1966#define IRQ15_MCU_CLR_SFT 151967#define IRQ15_MCU_CLR_MASK 0x11968#define IRQ15_MCU_CLR_MASK_SFT (0x1 << 15)1969#define IRQ14_MCU_CLR_SFT 141970#define IRQ14_MCU_CLR_MASK 0x11971#define IRQ14_MCU_CLR_MASK_SFT (0x1 << 14)1972#define IRQ13_MCU_CLR_SFT 131973#define IRQ13_MCU_CLR_MASK 0x11974#define IRQ13_MCU_CLR_MASK_SFT (0x1 << 13)1975#define IRQ12_MCU_CLR_SFT 121976#define IRQ12_MCU_CLR_MASK 0x11977#define IRQ12_MCU_CLR_MASK_SFT (0x1 << 12)1978#define IRQ11_MCU_CLR_SFT 111979#define IRQ11_MCU_CLR_MASK 0x11980#define IRQ11_MCU_CLR_MASK_SFT (0x1 << 11)1981#define IRQ10_MCU_CLR_SFT 101982#define IRQ10_MCU_CLR_MASK 0x11983#define IRQ10_MCU_CLR_MASK_SFT (0x1 << 10)1984#define IRQ9_MCU_CLR_SFT 91985#define IRQ9_MCU_CLR_MASK 0x11986#define IRQ9_MCU_CLR_MASK_SFT (0x1 << 9)1987#define IRQ8_MCU_CLR_SFT 81988#define IRQ8_MCU_CLR_MASK 0x11989#define IRQ8_MCU_CLR_MASK_SFT (0x1 << 8)1990#define IRQ7_MCU_CLR_SFT 71991#define IRQ7_MCU_CLR_MASK 0x11992#define IRQ7_MCU_CLR_MASK_SFT (0x1 << 7)1993#define IRQ6_MCU_CLR_SFT 61994#define IRQ6_MCU_CLR_MASK 0x11995#define IRQ6_MCU_CLR_MASK_SFT (0x1 << 6)1996#define IRQ5_MCU_CLR_SFT 51997#define IRQ5_MCU_CLR_MASK 0x11998#define IRQ5_MCU_CLR_MASK_SFT (0x1 << 5)1999#define IRQ4_MCU_CLR_SFT 42000#define IRQ4_MCU_CLR_MASK 0x12001#define IRQ4_MCU_CLR_MASK_SFT (0x1 << 4)2002#define IRQ3_MCU_CLR_SFT 32003#define IRQ3_MCU_CLR_MASK 0x12004#define IRQ3_MCU_CLR_MASK_SFT (0x1 << 3)2005#define IRQ2_MCU_CLR_SFT 22006#define IRQ2_MCU_CLR_MASK 0x12007#define IRQ2_MCU_CLR_MASK_SFT (0x1 << 2)2008#define IRQ1_MCU_CLR_SFT 12009#define IRQ1_MCU_CLR_MASK 0x12010#define IRQ1_MCU_CLR_MASK_SFT (0x1 << 1)2011#define IRQ0_MCU_CLR_SFT 02012#define IRQ0_MCU_CLR_MASK 0x12013#define IRQ0_MCU_CLR_MASK_SFT (0x1 << 0)2014 2015/* AFE_IRQ_MCU_EN */2016#define IRQ31_MCU_EN_SFT 312017#define IRQ30_MCU_EN_SFT 302018#define IRQ29_MCU_EN_SFT 292019#define IRQ28_MCU_EN_SFT 282020#define IRQ27_MCU_EN_SFT 272021#define IRQ26_MCU_EN_SFT 262022#define IRQ25_MCU_EN_SFT 252023#define IRQ24_MCU_EN_SFT 242024#define IRQ23_MCU_EN_SFT 232025#define IRQ22_MCU_EN_SFT 222026#define IRQ21_MCU_EN_SFT 212027#define IRQ20_MCU_EN_SFT 202028#define IRQ19_MCU_EN_SFT 192029#define IRQ18_MCU_EN_SFT 182030#define IRQ17_MCU_EN_SFT 172031#define IRQ16_MCU_EN_SFT 162032#define IRQ15_MCU_EN_SFT 152033#define IRQ14_MCU_EN_SFT 142034#define IRQ13_MCU_EN_SFT 132035#define IRQ12_MCU_EN_SFT 122036#define IRQ11_MCU_EN_SFT 112037#define IRQ10_MCU_EN_SFT 102038#define IRQ9_MCU_EN_SFT 92039#define IRQ8_MCU_EN_SFT 82040#define IRQ7_MCU_EN_SFT 72041#define IRQ6_MCU_EN_SFT 62042#define IRQ5_MCU_EN_SFT 52043#define IRQ4_MCU_EN_SFT 42044#define IRQ3_MCU_EN_SFT 32045#define IRQ2_MCU_EN_SFT 22046#define IRQ1_MCU_EN_SFT 12047#define IRQ0_MCU_EN_SFT 02048 2049/* AFE_IRQ_MCU_SCP_EN */2050#define IRQ31_MCU_SCP_EN_SFT 312051#define IRQ30_MCU_SCP_EN_SFT 302052#define IRQ29_MCU_SCP_EN_SFT 292053#define IRQ28_MCU_SCP_EN_SFT 282054#define IRQ27_MCU_SCP_EN_SFT 272055#define IRQ26_MCU_SCP_EN_SFT 262056#define IRQ25_MCU_SCP_EN_SFT 252057#define IRQ24_MCU_SCP_EN_SFT 242058#define IRQ23_MCU_SCP_EN_SFT 232059#define IRQ22_MCU_SCP_EN_SFT 222060#define IRQ21_MCU_SCP_EN_SFT 212061#define IRQ20_MCU_SCP_EN_SFT 202062#define IRQ19_MCU_SCP_EN_SFT 192063#define IRQ18_MCU_SCP_EN_SFT 182064#define IRQ17_MCU_SCP_EN_SFT 172065#define IRQ16_MCU_SCP_EN_SFT 162066#define IRQ15_MCU_SCP_EN_SFT 152067#define IRQ14_MCU_SCP_EN_SFT 142068#define IRQ13_MCU_SCP_EN_SFT 132069#define IRQ12_MCU_SCP_EN_SFT 122070#define IRQ11_MCU_SCP_EN_SFT 112071#define IRQ10_MCU_SCP_EN_SFT 102072#define IRQ9_MCU_SCP_EN_SFT 92073#define IRQ8_MCU_SCP_EN_SFT 82074#define IRQ7_MCU_SCP_EN_SFT 72075#define IRQ6_MCU_SCP_EN_SFT 62076#define IRQ5_MCU_SCP_EN_SFT 52077#define IRQ4_MCU_SCP_EN_SFT 42078#define IRQ3_MCU_SCP_EN_SFT 32079#define IRQ2_MCU_SCP_EN_SFT 22080#define IRQ1_MCU_SCP_EN_SFT 12081#define IRQ0_MCU_SCP_EN_SFT 02082 2083/* AFE_TDM_CON1 */2084#define TDM_EN_SFT 02085#define TDM_EN_MASK 0x12086#define TDM_EN_MASK_SFT (0x1 << 0)2087#define LRCK_INVERSE_SFT 22088#define LRCK_INVERSE_MASK 0x12089#define LRCK_INVERSE_MASK_SFT (0x1 << 2)2090#define DELAY_DATA_SFT 32091#define DELAY_DATA_MASK 0x12092#define DELAY_DATA_MASK_SFT (0x1 << 3)2093#define LEFT_ALIGN_SFT 42094#define LEFT_ALIGN_MASK 0x12095#define LEFT_ALIGN_MASK_SFT (0x1 << 4)2096#define WLEN_SFT 82097#define WLEN_MASK 0x32098#define WLEN_MASK_SFT (0x3 << 8)2099#define CHANNEL_NUM_SFT 102100#define CHANNEL_NUM_MASK 0x32101#define CHANNEL_NUM_MASK_SFT (0x3 << 10)2102#define CHANNEL_BCK_CYCLES_SFT 122103#define CHANNEL_BCK_CYCLES_MASK 0x32104#define CHANNEL_BCK_CYCLES_MASK_SFT (0x3 << 12)2105#define DAC_BIT_NUM_SFT 162106#define DAC_BIT_NUM_MASK 0x1f2107#define DAC_BIT_NUM_MASK_SFT (0x1f << 16)2108#define LRCK_TDM_WIDTH_SFT 242109#define LRCK_TDM_WIDTH_MASK 0xff2110#define LRCK_TDM_WIDTH_MASK_SFT (0xff << 24)2111 2112/* AFE_TDM_CON2 */2113#define ST_CH_PAIR_SOUT0_SFT 02114#define ST_CH_PAIR_SOUT0_MASK 0x72115#define ST_CH_PAIR_SOUT0_MASK_SFT (0x7 << 0)2116#define ST_CH_PAIR_SOUT1_SFT 42117#define ST_CH_PAIR_SOUT1_MASK 0x72118#define ST_CH_PAIR_SOUT1_MASK_SFT (0x7 << 4)2119#define ST_CH_PAIR_SOUT2_SFT 82120#define ST_CH_PAIR_SOUT2_MASK 0x72121#define ST_CH_PAIR_SOUT2_MASK_SFT (0x7 << 8)2122#define ST_CH_PAIR_SOUT3_SFT 122123#define ST_CH_PAIR_SOUT3_MASK 0x72124#define ST_CH_PAIR_SOUT3_MASK_SFT (0x7 << 12)2125#define TDM_FIX_VALUE_SEL_SFT 162126#define TDM_FIX_VALUE_SEL_MASK 0x12127#define TDM_FIX_VALUE_SEL_MASK_SFT (0x1 << 16)2128#define TDM_I2S_LOOPBACK_SFT 202129#define TDM_I2S_LOOPBACK_MASK 0x12130#define TDM_I2S_LOOPBACK_MASK_SFT (0x1 << 20)2131#define TDM_I2S_LOOPBACK_CH_SFT 212132#define TDM_I2S_LOOPBACK_CH_MASK 0x32133#define TDM_I2S_LOOPBACK_CH_MASK_SFT (0x3 << 21)2134#define TDM_FIX_VALUE_SFT 242135#define TDM_FIX_VALUE_MASK 0xff2136#define TDM_FIX_VALUE_MASK_SFT (0xff << 24)2137 2138/* AFE_HDMI_CONN0 */2139#define HDMI_O_7_SFT 212140#define HDMI_O_7_MASK 0x72141#define HDMI_O_7_MASK_SFT (0x7 << 21)2142#define HDMI_O_6_SFT 182143#define HDMI_O_6_MASK 0x72144#define HDMI_O_6_MASK_SFT (0x7 << 18)2145#define HDMI_O_5_SFT 152146#define HDMI_O_5_MASK 0x72147#define HDMI_O_5_MASK_SFT (0x7 << 15)2148#define HDMI_O_4_SFT 122149#define HDMI_O_4_MASK 0x72150#define HDMI_O_4_MASK_SFT (0x7 << 12)2151#define HDMI_O_3_SFT 92152#define HDMI_O_3_MASK 0x72153#define HDMI_O_3_MASK_SFT (0x7 << 9)2154#define HDMI_O_2_SFT 62155#define HDMI_O_2_MASK 0x72156#define HDMI_O_2_MASK_SFT (0x7 << 6)2157#define HDMI_O_1_SFT 32158#define HDMI_O_1_MASK 0x72159#define HDMI_O_1_MASK_SFT (0x7 << 3)2160#define HDMI_O_0_SFT 02161#define HDMI_O_0_MASK 0x72162#define HDMI_O_0_MASK_SFT (0x7 << 0)2163 2164/* AFE_AUD_PAD_TOP */2165#define AUD_PAD_TOP_MON_SFT 152166#define AUD_PAD_TOP_MON_MASK 0x1ffff2167#define AUD_PAD_TOP_MON_MASK_SFT (0x1ffff << 15)2168#define AUD_PAD_TOP_FIFO_RSP_SFT 42169#define AUD_PAD_TOP_FIFO_RSP_MASK 0xf2170#define AUD_PAD_TOP_FIFO_RSP_MASK_SFT (0xf << 4)2171#define RG_RX_PROTOCOL2_SFT 32172#define RG_RX_PROTOCOL2_MASK 0x12173#define RG_RX_PROTOCOL2_MASK_SFT (0x1 << 3)2174#define RESERVDED_01_SFT 12175#define RESERVDED_01_MASK 0x32176#define RESERVDED_01_MASK_SFT (0x3 << 1)2177#define RG_RX_FIFO_ON_SFT 02178#define RG_RX_FIFO_ON_MASK 0x12179#define RG_RX_FIFO_ON_MASK_SFT (0x1 << 0)2180 2181/* AFE_ADDA_MTKAIF_SYNCWORD_CFG */2182#define RG_ADDA6_MTKAIF_RX_SYNC_WORD2_DISABLE_SFT 232183#define RG_ADDA6_MTKAIF_RX_SYNC_WORD2_DISABLE_MASK 0x12184#define RG_ADDA6_MTKAIF_RX_SYNC_WORD2_DISABLE_MASK_SFT (0x1 << 23)2185 2186/* AFE_ADDA_MTKAIF_RX_CFG0 */2187#define MTKAIF_RXIF_VOICE_MODE_SFT 202188#define MTKAIF_RXIF_VOICE_MODE_MASK 0xf2189#define MTKAIF_RXIF_VOICE_MODE_MASK_SFT (0xf << 20)2190#define MTKAIF_RXIF_DETECT_ON_SFT 162191#define MTKAIF_RXIF_DETECT_ON_MASK 0x12192#define MTKAIF_RXIF_DETECT_ON_MASK_SFT (0x1 << 16)2193#define MTKAIF_RXIF_DATA_BIT_SFT 82194#define MTKAIF_RXIF_DATA_BIT_MASK 0x72195#define MTKAIF_RXIF_DATA_BIT_MASK_SFT (0x7 << 8)2196#define MTKAIF_RXIF_FIFO_RSP_SFT 42197#define MTKAIF_RXIF_FIFO_RSP_MASK 0x72198#define MTKAIF_RXIF_FIFO_RSP_MASK_SFT (0x7 << 4)2199#define MTKAIF_RXIF_DATA_MODE_SFT 02200#define MTKAIF_RXIF_DATA_MODE_MASK 0x12201#define MTKAIF_RXIF_DATA_MODE_MASK_SFT (0x1 << 0)2202 2203/* GENERAL_ASRC_MODE */2204#define GENERAL2_ASRCOUT_MODE_SFT 122205#define GENERAL2_ASRCOUT_MODE_MASK 0xf2206#define GENERAL2_ASRCOUT_MODE_MASK_SFT (0xf << 12)2207#define GENERAL2_ASRCIN_MODE_SFT 82208#define GENERAL2_ASRCIN_MODE_MASK 0xf2209#define GENERAL2_ASRCIN_MODE_MASK_SFT (0xf << 8)2210#define GENERAL1_ASRCOUT_MODE_SFT 42211#define GENERAL1_ASRCOUT_MODE_MASK 0xf2212#define GENERAL1_ASRCOUT_MODE_MASK_SFT (0xf << 4)2213#define GENERAL1_ASRCIN_MODE_SFT 02214#define GENERAL1_ASRCIN_MODE_MASK 0xf2215#define GENERAL1_ASRCIN_MODE_MASK_SFT (0xf << 0)2216 2217/* GENERAL_ASRC_EN_ON */2218#define GENERAL2_ASRC_EN_ON_SFT 12219#define GENERAL2_ASRC_EN_ON_MASK 0x12220#define GENERAL2_ASRC_EN_ON_MASK_SFT (0x1 << 1)2221#define GENERAL1_ASRC_EN_ON_SFT 02222#define GENERAL1_ASRC_EN_ON_MASK 0x12223#define GENERAL1_ASRC_EN_ON_MASK_SFT (0x1 << 0)2224 2225/* AFE_GENERAL1_ASRC_2CH_CON0 */2226#define G_SRC_CHSET_STR_CLR_SFT 42227#define G_SRC_CHSET_STR_CLR_MASK 0x12228#define G_SRC_CHSET_STR_CLR_MASK_SFT (0x1 << 4)2229#define G_SRC_CHSET_ON_SFT 22230#define G_SRC_CHSET_ON_MASK 0x12231#define G_SRC_CHSET_ON_MASK_SFT (0x1 << 2)2232#define G_SRC_COEFF_SRAM_CTRL_SFT 12233#define G_SRC_COEFF_SRAM_CTRL_MASK 0x12234#define G_SRC_COEFF_SRAM_CTRL_MASK_SFT (0x1 << 1)2235#define G_SRC_ASM_ON_SFT 02236#define G_SRC_ASM_ON_MASK 0x12237#define G_SRC_ASM_ON_MASK_SFT (0x1 << 0)2238 2239/* AFE_GENERAL1_ASRC_2CH_CON3 */2240#define G_SRC_ASM_FREQ_4_SFT 02241#define G_SRC_ASM_FREQ_4_MASK 0xffffff2242#define G_SRC_ASM_FREQ_4_MASK_SFT (0xffffff << 0)2243 2244/* AFE_GENERAL1_ASRC_2CH_CON4 */2245#define G_SRC_ASM_FREQ_5_SFT 02246#define G_SRC_ASM_FREQ_5_MASK 0xffffff2247#define G_SRC_ASM_FREQ_5_MASK_SFT (0xffffff << 0)2248 2249/* AFE_GENERAL1_ASRC_2CH_CON13 */2250#define G_SRC_COEFF_SRAM_ADR_SFT 02251#define G_SRC_COEFF_SRAM_ADR_MASK 0x3f2252#define G_SRC_COEFF_SRAM_ADR_MASK_SFT (0x3f << 0)2253 2254/* AFE_GENERAL1_ASRC_2CH_CON2 */2255#define G_SRC_CHSET_O16BIT_SFT 192256#define G_SRC_CHSET_O16BIT_MASK 0x12257#define G_SRC_CHSET_O16BIT_MASK_SFT (0x1 << 19)2258#define G_SRC_CHSET_CLR_IIR_HISTORY_SFT 172259#define G_SRC_CHSET_CLR_IIR_HISTORY_MASK 0x12260#define G_SRC_CHSET_CLR_IIR_HISTORY_MASK_SFT (0x1 << 17)2261#define G_SRC_CHSET_IS_MONO_SFT 162262#define G_SRC_CHSET_IS_MONO_MASK 0x12263#define G_SRC_CHSET_IS_MONO_MASK_SFT (0x1 << 16)2264#define G_SRC_CHSET_IIR_EN_SFT 112265#define G_SRC_CHSET_IIR_EN_MASK 0x12266#define G_SRC_CHSET_IIR_EN_MASK_SFT (0x1 << 11)2267#define G_SRC_CHSET_IIR_STAGE_SFT 82268#define G_SRC_CHSET_IIR_STAGE_MASK 0x72269#define G_SRC_CHSET_IIR_STAGE_MASK_SFT (0x7 << 8)2270#define G_SRC_CHSET_STR_CLR_RU_SFT 52271#define G_SRC_CHSET_STR_CLR_RU_MASK 0x12272#define G_SRC_CHSET_STR_CLR_RU_MASK_SFT (0x1 << 5)2273#define G_SRC_CHSET_ON_SFT 22274#define G_SRC_CHSET_ON_MASK 0x12275#define G_SRC_CHSET_ON_MASK_SFT (0x1 << 2)2276#define G_SRC_COEFF_SRAM_CTRL_SFT 12277#define G_SRC_COEFF_SRAM_CTRL_MASK 0x12278#define G_SRC_COEFF_SRAM_CTRL_MASK_SFT (0x1 << 1)2279#define G_SRC_ASM_ON_SFT 02280#define G_SRC_ASM_ON_MASK 0x12281#define G_SRC_ASM_ON_MASK_SFT (0x1 << 0)2282 2283/* AFE_ADDA_DL_SDM_AUTO_RESET_CON */2284#define ADDA_SDM_AUTO_RESET_ONOFF_SFT 312285#define ADDA_SDM_AUTO_RESET_ONOFF_MASK 0x12286#define ADDA_SDM_AUTO_RESET_ONOFF_MASK_SFT (0x1 << 31)2287 2288/* AFE_ADDA_3RD_DAC_DL_SDM_AUTO_RESET_CON */2289#define ADDA_3RD_DAC_SDM_AUTO_RESET_ONOFF_SFT 312290#define ADDA_3RD_DAC_SDM_AUTO_RESET_ONOFF_MASK 0x12291#define ADDA_3RD_DAC_SDM_AUTO_RESET_ONOFF_MASK_SFT (0x1 << 31)2292 2293/* AFE_TINY_CONN0 */2294#define O_3_CFG_SFT 242295#define O_3_CFG_MASK 0x1f2296#define O_3_CFG_MASK_SFT (0x1f << 24)2297#define O_2_CFG_SFT 162298#define O_2_CFG_MASK 0x1f2299#define O_2_CFG_MASK_SFT (0x1f << 16)2300#define O_1_CFG_SFT 82301#define O_1_CFG_MASK 0x1f2302#define O_1_CFG_MASK_SFT (0x1f << 8)2303#define O_0_CFG_SFT 02304#define O_0_CFG_MASK 0x1f2305#define O_0_CFG_MASK_SFT (0x1f << 0)2306 2307/* AFE_TINY_CONN5 */2308#define O_23_CFG_SFT 242309#define O_23_CFG_MASK 0x1f2310#define O_23_CFG_MASK_SFT (0x1f << 24)2311#define O_22_CFG_SFT 162312#define O_22_CFG_MASK 0x1f2313#define O_22_CFG_MASK_SFT (0x1f << 16)2314#define O_21_CFG_SFT 82315#define O_21_CFG_MASK 0x1f2316#define O_21_CFG_MASK_SFT (0x1f << 8)2317#define O_20_CFG_SFT 02318#define O_20_CFG_MASK 0x1f2319#define O_20_CFG_MASK_SFT (0x1f << 0)2320 2321/* AFE_MEMIF_CONN */2322#define VUL6_USE_TINY_SFT 82323#define VUL6_USE_TINY_MASK 12324#define VUL6_USE_TINY_MASK_SFT (0x1 << 8)2325#define VUL5_USE_TINY_SFT 72326#define VUL5_USE_TINY_MASK 12327#define VUL5_USE_TINY_MASK_SFT (0x1 << 7)2328#define VUL4_USE_TINY_SFT 62329#define VUL4_USE_TINY_MASK 12330#define VUL4_USE_TINY_MASK_SFT (0x1 << 6)2331#define VUL3_USE_TINY_SFT 52332#define VUL3_USE_TINY_MASK 12333#define VUL3_USE_TINY_MASK_SFT (0x1 << 5)2334#define AWB2_USE_TINY_SFT 42335#define AWB2_USE_TINY_MASK 12336#define AWB2_USE_TINY_MASK_SFT (0x1 << 4)2337#define AWB_USE_TINY_SFT 32338#define AWB_USE_TINY_MASK 12339#define AWB_USE_TINY_MASK_SFT (0x1 << 3)2340#define VUL12_USE_TINY_SFT 22341#define VUL12_USE_TINY_MASK 12342#define VUL12_USE_TINY_MASK_SFT (0x1 << 2)2343#define VUL2_USE_TINY_SFT 12344#define VUL2_USE_TINY_MASK 12345#define VUL2_USE_TINY_MASK_SFT (0x1 << 1)2346#define VUL1_USE_TINY_SFT 02347#define VUL1_USE_TINY_MASK 12348#define VUL1_USE_TINY_MASK_SFT (0x1 << 0)2349 2350/* AFE_ASRC_2CH_CON0 */2351#define CON0_CHSET_STR_CLR_SFT 42352#define CON0_CHSET_STR_CLR_MASK 12353#define CON0_CHSET_STR_CLR_MASK_SFT (0x1 << 4)2354#define CON0_ASM_ON_SFT 02355#define CON0_ASM_ON_MASK 12356#define CON0_ASM_ON_MASK_SFT (0x1 << 0)2357 2358/* AFE_ASRC_2CH_CON5 */2359#define CALI_EN_SFT 02360#define CALI_EN_MASK 12361#define CALI_EN_MASK_SFT (0x1 << 0)2362 2363#define AUDIO_TOP_CON0 0x00002364#define AUDIO_TOP_CON1 0x00042365#define AUDIO_TOP_CON2 0x00082366#define AUDIO_TOP_CON3 0x000c2367#define AFE_DAC_CON0 0x00102368#define AFE_I2S_CON 0x00182369#define AFE_CONN0 0x00202370#define AFE_CONN1 0x00242371#define AFE_CONN2 0x00282372#define AFE_CONN3 0x002c2373#define AFE_CONN4 0x00302374#define AFE_I2S_CON1 0x00342375#define AFE_I2S_CON2 0x00382376#define AFE_I2S_CON3 0x00402377#define AFE_CONN5 0x00442378#define AFE_CONN_24BIT 0x00482379#define AFE_DL1_CON0 0x004c2380#define AFE_DL1_BASE_MSB 0x00502381#define AFE_DL1_BASE 0x00542382#define AFE_DL1_CUR_MSB 0x00582383#define AFE_DL1_CUR 0x005c2384#define AFE_DL1_END_MSB 0x00602385#define AFE_DL1_END 0x00642386#define AFE_DL2_CON0 0x00682387#define AFE_DL2_BASE_MSB 0x006c2388#define AFE_DL2_BASE 0x00702389#define AFE_DL2_CUR_MSB 0x00742390#define AFE_DL2_CUR 0x00782391#define AFE_DL2_END_MSB 0x007c2392#define AFE_DL2_END 0x00802393#define AFE_DL3_CON0 0x00842394#define AFE_DL3_BASE_MSB 0x00882395#define AFE_DL3_BASE 0x008c2396#define AFE_DL3_CUR_MSB 0x00902397#define AFE_DL3_CUR 0x00942398#define AFE_DL3_END_MSB 0x00982399#define AFE_DL3_END 0x009c2400#define AFE_CONN6 0x00bc2401#define AFE_DL4_CON0 0x00cc2402#define AFE_DL4_BASE_MSB 0x00d02403#define AFE_DL4_BASE 0x00d42404#define AFE_DL4_CUR_MSB 0x00d82405#define AFE_DL4_CUR 0x00dc2406#define AFE_DL4_END_MSB 0x00e02407#define AFE_DL4_END 0x00e42408#define AFE_DL12_CON0 0x00e82409#define AFE_DL12_BASE_MSB 0x00ec2410#define AFE_DL12_BASE 0x00f02411#define AFE_DL12_CUR_MSB 0x00f42412#define AFE_DL12_CUR 0x00f82413#define AFE_DL12_END_MSB 0x00fc2414#define AFE_DL12_END 0x01002415#define AFE_ADDA_DL_SRC2_CON0 0x01082416#define AFE_ADDA_DL_SRC2_CON1 0x010c2417#define AFE_ADDA_UL_SRC_CON0 0x01142418#define AFE_ADDA_UL_SRC_CON1 0x01182419#define AFE_ADDA_TOP_CON0 0x01202420#define AFE_ADDA_UL_DL_CON0 0x01242421#define AFE_ADDA_SRC_DEBUG 0x012c2422#define AFE_ADDA_SRC_DEBUG_MON0 0x01302423#define AFE_ADDA_SRC_DEBUG_MON1 0x01342424#define AFE_ADDA_UL_SRC_MON0 0x01482425#define AFE_ADDA_UL_SRC_MON1 0x014c2426#define AFE_SECURE_CON0 0x01502427#define AFE_SRAM_BOUND 0x01542428#define AFE_SECURE_CON1 0x01582429#define AFE_SECURE_CONN0 0x015c2430#define AFE_VUL_CON0 0x01702431#define AFE_VUL_BASE_MSB 0x01742432#define AFE_VUL_BASE 0x01782433#define AFE_VUL_CUR_MSB 0x017c2434#define AFE_VUL_CUR 0x01802435#define AFE_VUL_END_MSB 0x01842436#define AFE_VUL_END 0x01882437#define AFE_ADDA_3RD_DAC_DL_SDM_AUTO_RESET_CON 0x018c2438#define AFE_ADDA_3RD_DAC_DL_SRC2_CON0 0x01902439#define AFE_ADDA_3RD_DAC_DL_SRC2_CON1 0x01942440#define AFE_ADDA_3RD_DAC_PREDIS_CON0 0x01a02441#define AFE_ADDA_3RD_DAC_PREDIS_CON1 0x01a42442#define AFE_ADDA_3RD_DAC_PREDIS_CON2 0x01a82443#define AFE_ADDA_3RD_DAC_PREDIS_CON3 0x01ac2444#define AFE_ADDA_3RD_DAC_DL_SDM_DCCOMP_CON 0x01b02445#define AFE_ADDA_3RD_DAC_DL_SDM_TEST 0x01b42446#define AFE_ADDA_3RD_DAC_DL_DC_COMP_CFG0 0x01b82447#define AFE_ADDA_3RD_DAC_DL_DC_COMP_CFG1 0x01bc2448#define AFE_ADDA_3RD_DAC_DL_SDM_FIFO_MON 0x01c02449#define AFE_ADDA_3RD_DAC_DL_SRC_LCH_MON 0x01c42450#define AFE_ADDA_3RD_DAC_DL_SRC_RCH_MON 0x01c82451#define AFE_ADDA_3RD_DAC_DL_SDM_OUT_MON 0x01cc2452#define AFE_SIDETONE_DEBUG 0x01d02453#define AFE_SIDETONE_MON 0x01d42454#define AFE_ADDA_3RD_DAC_DL_SDM_DITHER_CON 0x01d82455#define AFE_SINEGEN_CON2 0x01dc2456#define AFE_SIDETONE_CON0 0x01e02457#define AFE_SIDETONE_COEFF 0x01e42458#define AFE_SIDETONE_CON1 0x01e82459#define AFE_SIDETONE_GAIN 0x01ec2460#define AFE_SINEGEN_CON0 0x01f02461#define AFE_I2S_MON2 0x01f82462#define AFE_SINEGEN_CON_TDM 0x01fc2463#define AFE_TOP_CON0 0x02002464#define AFE_VUL2_CON0 0x020c2465#define AFE_VUL2_BASE_MSB 0x02102466#define AFE_VUL2_BASE 0x02142467#define AFE_VUL2_CUR_MSB 0x02182468#define AFE_VUL2_CUR 0x021c2469#define AFE_VUL2_END_MSB 0x02202470#define AFE_VUL2_END 0x02242471#define AFE_VUL3_CON0 0x02282472#define AFE_VUL3_BASE_MSB 0x022c2473#define AFE_VUL3_BASE 0x02302474#define AFE_VUL3_CUR_MSB 0x02342475#define AFE_VUL3_CUR 0x02382476#define AFE_VUL3_END_MSB 0x023c2477#define AFE_VUL3_END 0x02402478#define AFE_BUSY 0x02442479#define AFE_BUS_CFG 0x02502480#define AFE_ADDA_PREDIS_CON0 0x02602481#define AFE_ADDA_PREDIS_CON1 0x02642482#define AFE_I2S_MON 0x027c2483#define AFE_ADDA_IIR_COEF_02_01 0x02902484#define AFE_ADDA_IIR_COEF_04_03 0x02942485#define AFE_ADDA_IIR_COEF_06_05 0x02982486#define AFE_ADDA_IIR_COEF_08_07 0x029c2487#define AFE_ADDA_IIR_COEF_10_09 0x02a02488#define AFE_IRQ_MCU_CON1 0x02e42489#define AFE_IRQ_MCU_CON2 0x02e82490#define AFE_DAC_MON 0x02ec2491#define AFE_IRQ_MCU_CON3 0x02f02492#define AFE_IRQ_MCU_CON4 0x02f42493#define AFE_IRQ_MCU_CNT0 0x03002494#define AFE_IRQ_MCU_CNT6 0x03042495#define AFE_IRQ_MCU_CNT8 0x03082496#define AFE_IRQ_MCU_DSP2_EN 0x030c2497#define AFE_IRQ0_MCU_CNT_MON 0x03102498#define AFE_IRQ6_MCU_CNT_MON 0x03142499#define AFE_VUL4_CON0 0x03582500#define AFE_VUL4_BASE_MSB 0x035c2501#define AFE_VUL4_BASE 0x03602502#define AFE_VUL4_CUR_MSB 0x03642503#define AFE_VUL4_CUR 0x03682504#define AFE_VUL4_END_MSB 0x036c2505#define AFE_VUL4_END 0x03702506#define AFE_VUL12_CON0 0x03742507#define AFE_VUL12_BASE_MSB 0x03782508#define AFE_VUL12_BASE 0x037c2509#define AFE_VUL12_CUR_MSB 0x03802510#define AFE_VUL12_CUR 0x03842511#define AFE_VUL12_END_MSB 0x03882512#define AFE_VUL12_END 0x038c2513#define AFE_HDMI_CONN0 0x03902514#define AFE_IRQ3_MCU_CNT_MON 0x03982515#define AFE_IRQ4_MCU_CNT_MON 0x039c2516#define AFE_IRQ_MCU_CON0 0x03a02517#define AFE_IRQ_MCU_STATUS 0x03a42518#define AFE_IRQ_MCU_CLR 0x03a82519#define AFE_IRQ_MCU_CNT1 0x03ac2520#define AFE_IRQ_MCU_CNT2 0x03b02521#define AFE_IRQ_MCU_EN 0x03b42522#define AFE_IRQ_MCU_MON2 0x03b82523#define AFE_IRQ_MCU_CNT5 0x03bc2524#define AFE_IRQ1_MCU_CNT_MON 0x03c02525#define AFE_IRQ2_MCU_CNT_MON 0x03c42526#define AFE_IRQ5_MCU_CNT_MON 0x03cc2527#define AFE_IRQ_MCU_DSP_EN 0x03d02528#define AFE_IRQ_MCU_SCP_EN 0x03d42529#define AFE_IRQ_MCU_CNT7 0x03dc2530#define AFE_IRQ7_MCU_CNT_MON 0x03e02531#define AFE_IRQ_MCU_CNT3 0x03e42532#define AFE_IRQ_MCU_CNT4 0x03e82533#define AFE_IRQ_MCU_CNT11 0x03ec2534#define AFE_APLL1_TUNER_CFG 0x03f02535#define AFE_APLL2_TUNER_CFG 0x03f42536#define AFE_IRQ_MCU_MISS_CLR 0x03f82537#define AFE_CONN33 0x04082538#define AFE_IRQ_MCU_CNT12 0x040c2539#define AFE_GAIN1_CON0 0x04102540#define AFE_GAIN1_CON1 0x04142541#define AFE_GAIN1_CON2 0x04182542#define AFE_GAIN1_CON3 0x041c2543#define AFE_CONN7 0x04202544#define AFE_GAIN1_CUR 0x04242545#define AFE_GAIN2_CON0 0x04282546#define AFE_GAIN2_CON1 0x042c2547#define AFE_GAIN2_CON2 0x04302548#define AFE_GAIN2_CON3 0x04342549#define AFE_CONN8 0x04382550#define AFE_GAIN2_CUR 0x043c2551#define AFE_CONN9 0x04402552#define AFE_CONN10 0x04442553#define AFE_CONN11 0x04482554#define AFE_CONN12 0x044c2555#define AFE_CONN13 0x04502556#define AFE_CONN14 0x04542557#define AFE_CONN15 0x04582558#define AFE_CONN16 0x045c2559#define AFE_CONN17 0x04602560#define AFE_CONN18 0x04642561#define AFE_CONN19 0x04682562#define AFE_CONN20 0x046c2563#define AFE_CONN21 0x04702564#define AFE_CONN22 0x04742565#define AFE_CONN23 0x04782566#define AFE_CONN24 0x047c2567#define AFE_CONN_RS 0x04942568#define AFE_CONN_DI 0x04982569#define AFE_CONN25 0x04b02570#define AFE_CONN26 0x04b42571#define AFE_CONN27 0x04b82572#define AFE_CONN28 0x04bc2573#define AFE_CONN29 0x04c02574#define AFE_CONN30 0x04c42575#define AFE_CONN31 0x04c82576#define AFE_CONN32 0x04cc2577#define AFE_SRAM_DELSEL_CON1 0x04f42578#define AFE_CONN56 0x05002579#define AFE_CONN57 0x05042580#define AFE_CONN56_1 0x05102581#define AFE_CONN57_1 0x05142582#define AFE_TINY_CONN2 0x05202583#define AFE_TINY_CONN3 0x05242584#define AFE_TINY_CONN4 0x05282585#define AFE_TINY_CONN5 0x052c2586#define PCM_INTF_CON1 0x05302587#define PCM_INTF_CON2 0x05382588#define PCM2_INTF_CON 0x053c2589#define AFE_TDM_CON1 0x05482590#define AFE_TDM_CON2 0x054c2591#define AFE_I2S_CON6 0x05642592#define AFE_I2S_CON7 0x05682593#define AFE_I2S_CON8 0x056c2594#define AFE_I2S_CON9 0x05702595#define AFE_CONN34 0x05802596#define FPGA_CFG0 0x05b02597#define FPGA_CFG1 0x05b42598#define FPGA_CFG2 0x05c02599#define FPGA_CFG3 0x05c42600#define AUDIO_TOP_DBG_CON 0x05c82601#define AUDIO_TOP_DBG_MON0 0x05cc2602#define AUDIO_TOP_DBG_MON1 0x05d02603#define AFE_IRQ8_MCU_CNT_MON 0x05e42604#define AFE_IRQ11_MCU_CNT_MON 0x05e82605#define AFE_IRQ12_MCU_CNT_MON 0x05ec2606#define AFE_IRQ_MCU_CNT9 0x06002607#define AFE_IRQ_MCU_CNT10 0x06042608#define AFE_IRQ_MCU_CNT13 0x06082609#define AFE_IRQ_MCU_CNT14 0x060c2610#define AFE_IRQ_MCU_CNT15 0x06102611#define AFE_IRQ_MCU_CNT16 0x06142612#define AFE_IRQ_MCU_CNT17 0x06182613#define AFE_IRQ_MCU_CNT18 0x061c2614#define AFE_IRQ_MCU_CNT19 0x06202615#define AFE_IRQ_MCU_CNT20 0x06242616#define AFE_IRQ_MCU_CNT21 0x06282617#define AFE_IRQ_MCU_CNT22 0x062c2618#define AFE_IRQ_MCU_CNT23 0x06302619#define AFE_IRQ_MCU_CNT24 0x06342620#define AFE_IRQ_MCU_CNT25 0x06382621#define AFE_IRQ_MCU_CNT26 0x063c2622#define AFE_IRQ_MCU_CNT31 0x06402623#define AFE_TINY_CONN6 0x06502624#define AFE_TINY_CONN7 0x06542625#define AFE_IRQ9_MCU_CNT_MON 0x06602626#define AFE_IRQ10_MCU_CNT_MON 0x06642627#define AFE_IRQ13_MCU_CNT_MON 0x06682628#define AFE_IRQ14_MCU_CNT_MON 0x066c2629#define AFE_IRQ15_MCU_CNT_MON 0x06702630#define AFE_IRQ16_MCU_CNT_MON 0x06742631#define AFE_IRQ17_MCU_CNT_MON 0x06782632#define AFE_IRQ18_MCU_CNT_MON 0x067c2633#define AFE_IRQ19_MCU_CNT_MON 0x06802634#define AFE_IRQ20_MCU_CNT_MON 0x06842635#define AFE_IRQ21_MCU_CNT_MON 0x06882636#define AFE_IRQ22_MCU_CNT_MON 0x068c2637#define AFE_IRQ23_MCU_CNT_MON 0x06902638#define AFE_IRQ24_MCU_CNT_MON 0x06942639#define AFE_IRQ25_MCU_CNT_MON 0x06982640#define AFE_IRQ26_MCU_CNT_MON 0x069c2641#define AFE_IRQ31_MCU_CNT_MON 0x06a02642#define AFE_GENERAL_REG0 0x08002643#define AFE_GENERAL_REG1 0x08042644#define AFE_GENERAL_REG2 0x08082645#define AFE_GENERAL_REG3 0x080c2646#define AFE_GENERAL_REG4 0x08102647#define AFE_GENERAL_REG5 0x08142648#define AFE_GENERAL_REG6 0x08182649#define AFE_GENERAL_REG7 0x081c2650#define AFE_GENERAL_REG8 0x08202651#define AFE_GENERAL_REG9 0x08242652#define AFE_GENERAL_REG10 0x08282653#define AFE_GENERAL_REG11 0x082c2654#define AFE_GENERAL_REG12 0x08302655#define AFE_GENERAL_REG13 0x08342656#define AFE_GENERAL_REG14 0x08382657#define AFE_GENERAL_REG15 0x083c2658#define AFE_CBIP_CFG0 0x08402659#define AFE_CBIP_MON0 0x08442660#define AFE_CBIP_SLV_MUX_MON0 0x08482661#define AFE_CBIP_SLV_DECODER_MON0 0x084c2662#define AFE_ADDA6_MTKAIF_MON0 0x08542663#define AFE_ADDA6_MTKAIF_MON1 0x08582664#define AFE_AWB_CON0 0x085c2665#define AFE_AWB_BASE_MSB 0x08602666#define AFE_AWB_BASE 0x08642667#define AFE_AWB_CUR_MSB 0x08682668#define AFE_AWB_CUR 0x086c2669#define AFE_AWB_END_MSB 0x08702670#define AFE_AWB_END 0x08742671#define AFE_AWB2_CON0 0x08782672#define AFE_AWB2_BASE_MSB 0x087c2673#define AFE_AWB2_BASE 0x08802674#define AFE_AWB2_CUR_MSB 0x08842675#define AFE_AWB2_CUR 0x08882676#define AFE_AWB2_END_MSB 0x088c2677#define AFE_AWB2_END 0x08902678#define AFE_DAI_CON0 0x08942679#define AFE_DAI_BASE_MSB 0x08982680#define AFE_DAI_BASE 0x089c2681#define AFE_DAI_CUR_MSB 0x08a02682#define AFE_DAI_CUR 0x08a42683#define AFE_DAI_END_MSB 0x08a82684#define AFE_DAI_END 0x08ac2685#define AFE_DAI2_CON0 0x08b02686#define AFE_DAI2_BASE_MSB 0x08b42687#define AFE_DAI2_BASE 0x08b82688#define AFE_DAI2_CUR_MSB 0x08bc2689#define AFE_DAI2_CUR 0x08c02690#define AFE_DAI2_END_MSB 0x08c42691#define AFE_DAI2_END 0x08c82692#define AFE_MEMIF_CON0 0x08cc2693#define AFE_CONN0_1 0x09002694#define AFE_CONN1_1 0x09042695#define AFE_CONN2_1 0x09082696#define AFE_CONN3_1 0x090c2697#define AFE_CONN4_1 0x09102698#define AFE_CONN5_1 0x09142699#define AFE_CONN6_1 0x09182700#define AFE_CONN7_1 0x091c2701#define AFE_CONN8_1 0x09202702#define AFE_CONN9_1 0x09242703#define AFE_CONN10_1 0x09282704#define AFE_CONN11_1 0x092c2705#define AFE_CONN12_1 0x09302706#define AFE_CONN13_1 0x09342707#define AFE_CONN14_1 0x09382708#define AFE_CONN15_1 0x093c2709#define AFE_CONN16_1 0x09402710#define AFE_CONN17_1 0x09442711#define AFE_CONN18_1 0x09482712#define AFE_CONN19_1 0x094c2713#define AFE_CONN20_1 0x09502714#define AFE_CONN21_1 0x09542715#define AFE_CONN22_1 0x09582716#define AFE_CONN23_1 0x095c2717#define AFE_CONN24_1 0x09602718#define AFE_CONN25_1 0x09642719#define AFE_CONN26_1 0x09682720#define AFE_CONN27_1 0x096c2721#define AFE_CONN28_1 0x09702722#define AFE_CONN29_1 0x09742723#define AFE_CONN30_1 0x09782724#define AFE_CONN31_1 0x097c2725#define AFE_CONN32_1 0x09802726#define AFE_CONN33_1 0x09842727#define AFE_CONN34_1 0x09882728#define AFE_CONN_RS_1 0x098c2729#define AFE_CONN_DI_1 0x09902730#define AFE_CONN_24BIT_1 0x09942731#define AFE_CONN_REG 0x09982732#define AFE_CONN35 0x09a02733#define AFE_CONN36 0x09a42734#define AFE_CONN37 0x09a82735#define AFE_CONN38 0x09ac2736#define AFE_CONN35_1 0x09b02737#define AFE_CONN36_1 0x09b42738#define AFE_CONN37_1 0x09b82739#define AFE_CONN38_1 0x09bc2740#define AFE_CONN39 0x09c02741#define AFE_CONN40 0x09c42742#define AFE_CONN41 0x09c82743#define AFE_CONN42 0x09cc2744#define AFE_SGEN_CON_SGEN32 0x09d02745#define AFE_CONN39_1 0x09e02746#define AFE_CONN40_1 0x09e42747#define AFE_CONN41_1 0x09e82748#define AFE_CONN42_1 0x09ec2749#define AFE_I2S_CON4 0x09f82750#define AFE_ADDA6_TOP_CON0 0x0a802751#define AFE_ADDA6_UL_SRC_CON0 0x0a842752#define AFE_ADDA6_UL_SRC_CON1 0x0a882753#define AFE_ADDA6_SRC_DEBUG 0x0a8c2754#define AFE_ADDA6_SRC_DEBUG_MON0 0x0a902755#define AFE_ADDA6_ULCF_CFG_02_01 0x0aa02756#define AFE_ADDA6_ULCF_CFG_04_03 0x0aa42757#define AFE_ADDA6_ULCF_CFG_06_05 0x0aa82758#define AFE_ADDA6_ULCF_CFG_08_07 0x0aac2759#define AFE_ADDA6_ULCF_CFG_10_09 0x0ab02760#define AFE_ADDA6_ULCF_CFG_12_11 0x0ab42761#define AFE_ADDA6_ULCF_CFG_14_13 0x0ab82762#define AFE_ADDA6_ULCF_CFG_16_15 0x0abc2763#define AFE_ADDA6_ULCF_CFG_18_17 0x0ac02764#define AFE_ADDA6_ULCF_CFG_20_19 0x0ac42765#define AFE_ADDA6_ULCF_CFG_22_21 0x0ac82766#define AFE_ADDA6_ULCF_CFG_24_23 0x0acc2767#define AFE_ADDA6_ULCF_CFG_26_25 0x0ad02768#define AFE_ADDA6_ULCF_CFG_28_27 0x0ad42769#define AFE_ADDA6_ULCF_CFG_30_29 0x0ad82770#define AFE_ADD6A_UL_SRC_MON0 0x0ae42771#define AFE_ADDA6_UL_SRC_MON1 0x0ae82772#define AFE_TINY_CONN0 0x0af02773#define AFE_TINY_CONN1 0x0af42774#define AFE_CONN43 0x0af82775#define AFE_CONN43_1 0x0afc2776#define AFE_MOD_DAI_CON0 0x0b002777#define AFE_MOD_DAI_BASE_MSB 0x0b042778#define AFE_MOD_DAI_BASE 0x0b082779#define AFE_MOD_DAI_CUR_MSB 0x0b0c2780#define AFE_MOD_DAI_CUR 0x0b102781#define AFE_MOD_DAI_END_MSB 0x0b142782#define AFE_MOD_DAI_END 0x0b182783#define AFE_HDMI_OUT_CON0 0x0b1c2784#define AFE_HDMI_OUT_BASE_MSB 0x0b202785#define AFE_HDMI_OUT_BASE 0x0b242786#define AFE_HDMI_OUT_CUR_MSB 0x0b282787#define AFE_HDMI_OUT_CUR 0x0b2c2788#define AFE_HDMI_OUT_END_MSB 0x0b302789#define AFE_HDMI_OUT_END 0x0b342790#define AFE_AWB_RCH_MON 0x0b702791#define AFE_AWB_LCH_MON 0x0b742792#define AFE_VUL_RCH_MON 0x0b782793#define AFE_VUL_LCH_MON 0x0b7c2794#define AFE_VUL12_RCH_MON 0x0b802795#define AFE_VUL12_LCH_MON 0x0b842796#define AFE_VUL2_RCH_MON 0x0b882797#define AFE_VUL2_LCH_MON 0x0b8c2798#define AFE_DAI_DATA_MON 0x0b902799#define AFE_MOD_DAI_DATA_MON 0x0b942800#define AFE_DAI2_DATA_MON 0x0b982801#define AFE_AWB2_RCH_MON 0x0b9c2802#define AFE_AWB2_LCH_MON 0x0ba02803#define AFE_VUL3_RCH_MON 0x0ba42804#define AFE_VUL3_LCH_MON 0x0ba82805#define AFE_VUL4_RCH_MON 0x0bac2806#define AFE_VUL4_LCH_MON 0x0bb02807#define AFE_VUL5_RCH_MON 0x0bb42808#define AFE_VUL5_LCH_MON 0x0bb82809#define AFE_VUL6_RCH_MON 0x0bbc2810#define AFE_VUL6_LCH_MON 0x0bc02811#define AFE_DL1_RCH_MON 0x0bc42812#define AFE_DL1_LCH_MON 0x0bc82813#define AFE_DL2_RCH_MON 0x0bcc2814#define AFE_DL2_LCH_MON 0x0bd02815#define AFE_DL12_RCH1_MON 0x0bd42816#define AFE_DL12_LCH1_MON 0x0bd82817#define AFE_DL12_RCH2_MON 0x0bdc2818#define AFE_DL12_LCH2_MON 0x0be02819#define AFE_DL3_RCH_MON 0x0be42820#define AFE_DL3_LCH_MON 0x0be82821#define AFE_DL4_RCH_MON 0x0bec2822#define AFE_DL4_LCH_MON 0x0bf02823#define AFE_DL5_RCH_MON 0x0bf42824#define AFE_DL5_LCH_MON 0x0bf82825#define AFE_DL6_RCH_MON 0x0bfc2826#define AFE_DL6_LCH_MON 0x0c002827#define AFE_DL7_RCH_MON 0x0c042828#define AFE_DL7_LCH_MON 0x0c082829#define AFE_DL8_RCH_MON 0x0c0c2830#define AFE_DL8_LCH_MON 0x0c102831#define AFE_VUL5_CON0 0x0c142832#define AFE_VUL5_BASE_MSB 0x0c182833#define AFE_VUL5_BASE 0x0c1c2834#define AFE_VUL5_CUR_MSB 0x0c202835#define AFE_VUL5_CUR 0x0c242836#define AFE_VUL5_END_MSB 0x0c282837#define AFE_VUL5_END 0x0c2c2838#define AFE_VUL6_CON0 0x0c302839#define AFE_VUL6_BASE_MSB 0x0c342840#define AFE_VUL6_BASE 0x0c382841#define AFE_VUL6_CUR_MSB 0x0c3c2842#define AFE_VUL6_CUR 0x0c402843#define AFE_VUL6_END_MSB 0x0c442844#define AFE_VUL6_END 0x0c482845#define AFE_ADDA_DL_SDM_DCCOMP_CON 0x0c502846#define AFE_ADDA_DL_SDM_TEST 0x0c542847#define AFE_ADDA_DL_DC_COMP_CFG0 0x0c582848#define AFE_ADDA_DL_DC_COMP_CFG1 0x0c5c2849#define AFE_ADDA_DL_SDM_FIFO_MON 0x0c602850#define AFE_ADDA_DL_SRC_LCH_MON 0x0c642851#define AFE_ADDA_DL_SRC_RCH_MON 0x0c682852#define AFE_ADDA_DL_SDM_OUT_MON 0x0c6c2853#define AFE_ADDA_DL_SDM_DITHER_CON 0x0c702854#define AFE_ADDA_DL_SDM_AUTO_RESET_CON 0x0c742855#define AFE_CONNSYS_I2S_CON 0x0c782856#define AFE_CONNSYS_I2S_MON 0x0c7c2857#define AFE_ASRC_2CH_CON0 0x0c802858#define AFE_ASRC_2CH_CON1 0x0c842859#define AFE_ASRC_2CH_CON2 0x0c882860#define AFE_ASRC_2CH_CON3 0x0c8c2861#define AFE_ASRC_2CH_CON4 0x0c902862#define AFE_ASRC_2CH_CON5 0x0c942863#define AFE_ASRC_2CH_CON6 0x0c982864#define AFE_ASRC_2CH_CON7 0x0c9c2865#define AFE_ASRC_2CH_CON8 0x0ca02866#define AFE_ASRC_2CH_CON9 0x0ca42867#define AFE_ASRC_2CH_CON10 0x0ca82868#define AFE_ASRC_2CH_CON12 0x0cb02869#define AFE_ASRC_2CH_CON13 0x0cb42870#define AFE_ADDA6_IIR_COEF_02_01 0x0ce02871#define AFE_ADDA6_IIR_COEF_04_03 0x0ce42872#define AFE_ADDA6_IIR_COEF_06_05 0x0ce82873#define AFE_ADDA6_IIR_COEF_08_07 0x0cec2874#define AFE_ADDA6_IIR_COEF_10_09 0x0cf02875#define AFE_SE_PROT_SIDEBAND 0x0d382876#define AFE_SE_DOMAIN_SIDEBAND0 0x0d3c2877#define AFE_ADDA_PREDIS_CON2 0x0d402878#define AFE_ADDA_PREDIS_CON3 0x0d442879#define AFE_MEMIF_CONN 0x0d502880#define AFE_SE_DOMAIN_SIDEBAND1 0x0d542881#define AFE_SE_DOMAIN_SIDEBAND2 0x0d582882#define AFE_SE_DOMAIN_SIDEBAND3 0x0d5c2883#define AFE_CONN44 0x0d702884#define AFE_CONN45 0x0d742885#define AFE_CONN46 0x0d782886#define AFE_CONN47 0x0d7c2887#define AFE_CONN44_1 0x0d802888#define AFE_CONN45_1 0x0d842889#define AFE_CONN46_1 0x0d882890#define AFE_CONN47_1 0x0d8c2891#define AFE_DL9_CUR_MSB 0x0dc02892#define AFE_DL9_CUR 0x0dc42893#define AFE_DL9_END_MSB 0x0dc82894#define AFE_DL9_END 0x0dcc2895#define AFE_HD_ENGEN_ENABLE 0x0dd02896#define AFE_ADDA_DL_NLE_FIFO_MON 0x0dfc2897#define AFE_ADDA_MTKAIF_CFG0 0x0e002898#define AFE_ADDA_MTKAIF_SYNCWORD_CFG 0x0e142899#define AFE_ADDA_MTKAIF_RX_CFG0 0x0e202900#define AFE_ADDA_MTKAIF_RX_CFG1 0x0e242901#define AFE_ADDA_MTKAIF_RX_CFG2 0x0e282902#define AFE_ADDA_MTKAIF_MON0 0x0e342903#define AFE_ADDA_MTKAIF_MON1 0x0e382904#define AFE_AUD_PAD_TOP 0x0e402905#define AFE_DL_NLE_R_CFG0 0x0e442906#define AFE_DL_NLE_R_CFG1 0x0e482907#define AFE_DL_NLE_L_CFG0 0x0e4c2908#define AFE_DL_NLE_L_CFG1 0x0e502909#define AFE_DL_NLE_R_MON0 0x0e542910#define AFE_DL_NLE_R_MON1 0x0e582911#define AFE_DL_NLE_R_MON2 0x0e5c2912#define AFE_DL_NLE_L_MON0 0x0e602913#define AFE_DL_NLE_L_MON1 0x0e642914#define AFE_DL_NLE_L_MON2 0x0e682915#define AFE_DL_NLE_GAIN_CFG0 0x0e6c2916#define AFE_ADDA6_MTKAIF_CFG0 0x0e702917#define AFE_ADDA6_MTKAIF_RX_CFG0 0x0e742918#define AFE_ADDA6_MTKAIF_RX_CFG1 0x0e782919#define AFE_ADDA6_MTKAIF_RX_CFG2 0x0e7c2920#define AFE_GENERAL1_ASRC_2CH_CON0 0x0e802921#define AFE_GENERAL1_ASRC_2CH_CON1 0x0e842922#define AFE_GENERAL1_ASRC_2CH_CON2 0x0e882923#define AFE_GENERAL1_ASRC_2CH_CON3 0x0e8c2924#define AFE_GENERAL1_ASRC_2CH_CON4 0x0e902925#define AFE_GENERAL1_ASRC_2CH_CON5 0x0e942926#define AFE_GENERAL1_ASRC_2CH_CON6 0x0e982927#define AFE_GENERAL1_ASRC_2CH_CON7 0x0e9c2928#define AFE_GENERAL1_ASRC_2CH_CON8 0x0ea02929#define AFE_GENERAL1_ASRC_2CH_CON9 0x0ea42930#define AFE_GENERAL1_ASRC_2CH_CON10 0x0ea82931#define AFE_GENERAL1_ASRC_2CH_CON12 0x0eb02932#define AFE_GENERAL1_ASRC_2CH_CON13 0x0eb42933#define GENERAL_ASRC_MODE 0x0eb82934#define GENERAL_ASRC_EN_ON 0x0ebc2935#define AFE_CONN48 0x0ec02936#define AFE_CONN49 0x0ec42937#define AFE_CONN50 0x0ec82938#define AFE_CONN51 0x0ecc2939#define AFE_CONN52 0x0ed02940#define AFE_CONN53 0x0ed42941#define AFE_CONN54 0x0ed82942#define AFE_CONN55 0x0edc2943#define AFE_CONN48_1 0x0ee02944#define AFE_CONN49_1 0x0ee42945#define AFE_CONN50_1 0x0ee82946#define AFE_CONN51_1 0x0eec2947#define AFE_CONN52_1 0x0ef02948#define AFE_CONN53_1 0x0ef42949#define AFE_CONN54_1 0x0ef82950#define AFE_CONN55_1 0x0efc2951#define AFE_GENERAL2_ASRC_2CH_CON0 0x0f002952#define AFE_GENERAL2_ASRC_2CH_CON1 0x0f042953#define AFE_GENERAL2_ASRC_2CH_CON2 0x0f082954#define AFE_GENERAL2_ASRC_2CH_CON3 0x0f0c2955#define AFE_GENERAL2_ASRC_2CH_CON4 0x0f102956#define AFE_GENERAL2_ASRC_2CH_CON5 0x0f142957#define AFE_GENERAL2_ASRC_2CH_CON6 0x0f182958#define AFE_GENERAL2_ASRC_2CH_CON7 0x0f1c2959#define AFE_GENERAL2_ASRC_2CH_CON8 0x0f202960#define AFE_GENERAL2_ASRC_2CH_CON9 0x0f242961#define AFE_GENERAL2_ASRC_2CH_CON10 0x0f282962#define AFE_GENERAL2_ASRC_2CH_CON12 0x0f302963#define AFE_GENERAL2_ASRC_2CH_CON13 0x0f342964#define AFE_DL9_RCH_MON 0x0f382965#define AFE_DL9_LCH_MON 0x0f3c2966#define AFE_DL5_CON0 0x0f4c2967#define AFE_DL5_BASE_MSB 0x0f502968#define AFE_DL5_BASE 0x0f542969#define AFE_DL5_CUR_MSB 0x0f582970#define AFE_DL5_CUR 0x0f5c2971#define AFE_DL5_END_MSB 0x0f602972#define AFE_DL5_END 0x0f642973#define AFE_DL6_CON0 0x0f682974#define AFE_DL6_BASE_MSB 0x0f6c2975#define AFE_DL6_BASE 0x0f702976#define AFE_DL6_CUR_MSB 0x0f742977#define AFE_DL6_CUR 0x0f782978#define AFE_DL6_END_MSB 0x0f7c2979#define AFE_DL6_END 0x0f802980#define AFE_DL7_CON0 0x0f842981#define AFE_DL7_BASE_MSB 0x0f882982#define AFE_DL7_BASE 0x0f8c2983#define AFE_DL7_CUR_MSB 0x0f902984#define AFE_DL7_CUR 0x0f942985#define AFE_DL7_END_MSB 0x0f982986#define AFE_DL7_END 0x0f9c2987#define AFE_DL8_CON0 0x0fa02988#define AFE_DL8_BASE_MSB 0x0fa42989#define AFE_DL8_BASE 0x0fa82990#define AFE_DL8_CUR_MSB 0x0fac2991#define AFE_DL8_CUR 0x0fb02992#define AFE_DL8_END_MSB 0x0fb42993#define AFE_DL8_END 0x0fb82994#define AFE_DL9_CON0 0x0fbc2995#define AFE_DL9_BASE_MSB 0x0fc02996#define AFE_DL9_BASE 0x0fc42997#define AFE_SE_SECURE_CON 0x10042998#define AFE_PROT_SIDEBAND_MON 0x10082999#define AFE_DOMAIN_SIDEBAND0_MON 0x100c3000#define AFE_DOMAIN_SIDEBAND1_MON 0x10103001#define AFE_DOMAIN_SIDEBAND2_MON 0x10143002#define AFE_DOMAIN_SIDEBAND3_MON 0x10183003#define AFE_SECURE_MASK_CONN0 0x10203004#define AFE_SECURE_MASK_CONN1 0x10243005#define AFE_SECURE_MASK_CONN2 0x10283006#define AFE_SECURE_MASK_CONN3 0x102c3007#define AFE_SECURE_MASK_CONN4 0x10303008#define AFE_SECURE_MASK_CONN5 0x10343009#define AFE_SECURE_MASK_CONN6 0x10383010#define AFE_SECURE_MASK_CONN7 0x103c3011#define AFE_SECURE_MASK_CONN8 0x10403012#define AFE_SECURE_MASK_CONN9 0x10443013#define AFE_SECURE_MASK_CONN10 0x10483014#define AFE_SECURE_MASK_CONN11 0x104c3015#define AFE_SECURE_MASK_CONN12 0x10503016#define AFE_SECURE_MASK_CONN13 0x10543017#define AFE_SECURE_MASK_CONN14 0x10583018#define AFE_SECURE_MASK_CONN15 0x105c3019#define AFE_SECURE_MASK_CONN16 0x10603020#define AFE_SECURE_MASK_CONN17 0x10643021#define AFE_SECURE_MASK_CONN18 0x10683022#define AFE_SECURE_MASK_CONN19 0x106c3023#define AFE_SECURE_MASK_CONN20 0x10703024#define AFE_SECURE_MASK_CONN21 0x10743025#define AFE_SECURE_MASK_CONN22 0x10783026#define AFE_SECURE_MASK_CONN23 0x107c3027#define AFE_SECURE_MASK_CONN24 0x10803028#define AFE_SECURE_MASK_CONN25 0x10843029#define AFE_SECURE_MASK_CONN26 0x10883030#define AFE_SECURE_MASK_CONN27 0x108c3031#define AFE_SECURE_MASK_CONN28 0x10903032#define AFE_SECURE_MASK_CONN29 0x10943033#define AFE_SECURE_MASK_CONN30 0x10983034#define AFE_SECURE_MASK_CONN31 0x109c3035#define AFE_SECURE_MASK_CONN32 0x10a03036#define AFE_SECURE_MASK_CONN33 0x10a43037#define AFE_SECURE_MASK_CONN34 0x10a83038#define AFE_SECURE_MASK_CONN35 0x10ac3039#define AFE_SECURE_MASK_CONN36 0x10b03040#define AFE_SECURE_MASK_CONN37 0x10b43041#define AFE_SECURE_MASK_CONN38 0x10b83042#define AFE_SECURE_MASK_CONN39 0x10bc3043#define AFE_SECURE_MASK_CONN40 0x10c03044#define AFE_SECURE_MASK_CONN41 0x10c43045#define AFE_SECURE_MASK_CONN42 0x10c83046#define AFE_SECURE_MASK_CONN43 0x10cc3047#define AFE_SECURE_MASK_CONN44 0x10d03048#define AFE_SECURE_MASK_CONN45 0x10d43049#define AFE_SECURE_MASK_CONN46 0x10d83050#define AFE_SECURE_MASK_CONN47 0x10dc3051#define AFE_SECURE_MASK_CONN48 0x10e03052#define AFE_SECURE_MASK_CONN49 0x10e43053#define AFE_SECURE_MASK_CONN50 0x10e83054#define AFE_SECURE_MASK_CONN51 0x10ec3055#define AFE_SECURE_MASK_CONN52 0x10f03056#define AFE_SECURE_MASK_CONN53 0x10f43057#define AFE_SECURE_MASK_CONN54 0x10f83058#define AFE_SECURE_MASK_CONN55 0x10fc3059#define AFE_SECURE_MASK_CONN56 0x11003060#define AFE_SECURE_MASK_CONN57 0x11043061#define AFE_SECURE_MASK_CONN0_1 0x11083062#define AFE_SECURE_MASK_CONN1_1 0x110c3063#define AFE_SECURE_MASK_CONN2_1 0x11103064#define AFE_SECURE_MASK_CONN3_1 0x11143065#define AFE_SECURE_MASK_CONN4_1 0x11183066#define AFE_SECURE_MASK_CONN5_1 0x111c3067#define AFE_SECURE_MASK_CONN6_1 0x11203068#define AFE_SECURE_MASK_CONN7_1 0x11243069#define AFE_SECURE_MASK_CONN8_1 0x11283070#define AFE_SECURE_MASK_CONN9_1 0x112c3071#define AFE_SECURE_MASK_CONN10_1 0x11303072#define AFE_SECURE_MASK_CONN11_1 0x11343073#define AFE_SECURE_MASK_CONN12_1 0x11383074#define AFE_SECURE_MASK_CONN13_1 0x113c3075#define AFE_SECURE_MASK_CONN14_1 0x11403076#define AFE_SECURE_MASK_CONN15_1 0x11443077#define AFE_SECURE_MASK_CONN16_1 0x11483078#define AFE_SECURE_MASK_CONN17_1 0x114c3079#define AFE_SECURE_MASK_CONN18_1 0x11503080#define AFE_SECURE_MASK_CONN19_1 0x11543081#define AFE_SECURE_MASK_CONN20_1 0x11583082#define AFE_SECURE_MASK_CONN21_1 0x115c3083#define AFE_SECURE_MASK_CONN22_1 0x11603084#define AFE_SECURE_MASK_CONN23_1 0x11643085#define AFE_SECURE_MASK_CONN24_1 0x11683086#define AFE_SECURE_MASK_CONN25_1 0x116c3087#define AFE_SECURE_MASK_CONN26_1 0x11703088#define AFE_SECURE_MASK_CONN27_1 0x11743089#define AFE_SECURE_MASK_CONN28_1 0x11783090#define AFE_SECURE_MASK_CONN29_1 0x117c3091#define AFE_SECURE_MASK_CONN30_1 0x11803092#define AFE_SECURE_MASK_CONN31_1 0x11843093#define AFE_SECURE_MASK_CONN32_1 0x11883094#define AFE_SECURE_MASK_CONN33_1 0x118c3095#define AFE_SECURE_MASK_CONN34_1 0x11903096#define AFE_SECURE_MASK_CONN35_1 0x11943097#define AFE_SECURE_MASK_CONN36_1 0x11983098#define AFE_SECURE_MASK_CONN37_1 0x119c3099#define AFE_SECURE_MASK_CONN38_1 0x11a03100#define AFE_SECURE_MASK_CONN39_1 0x11a43101#define AFE_SECURE_MASK_CONN40_1 0x11a83102#define AFE_SECURE_MASK_CONN41_1 0x11ac3103#define AFE_SECURE_MASK_CONN42_1 0x11b03104#define AFE_SECURE_MASK_CONN43_1 0x11b43105#define AFE_SECURE_MASK_CONN44_1 0x11b83106#define AFE_SECURE_MASK_CONN45_1 0x11bc3107#define AFE_SECURE_MASK_CONN46_1 0x11c03108#define AFE_SECURE_MASK_CONN47_1 0x11c43109#define AFE_SECURE_MASK_CONN48_1 0x11c83110#define AFE_SECURE_MASK_CONN49_1 0x11cc3111#define AFE_SECURE_MASK_CONN50_1 0x11d03112#define AFE_SECURE_MASK_CONN51_1 0x11d43113#define AFE_SECURE_MASK_CONN52_1 0x11d83114#define AFE_SECURE_MASK_CONN53_1 0x11dc3115#define AFE_SECURE_MASK_CONN54_1 0x11e03116#define AFE_SECURE_MASK_CONN55_1 0x11e43117#define AFE_SECURE_MASK_CONN56_1 0x11e83118#define AFE_SECURE_MASK_TINY_CONN0 0x12003119#define AFE_SECURE_MASK_TINY_CONN1 0x12043120#define AFE_SECURE_MASK_TINY_CONN2 0x12083121#define AFE_SECURE_MASK_TINY_CONN3 0x120c3122#define AFE_SECURE_MASK_TINY_CONN4 0x12103123#define AFE_SECURE_MASK_TINY_CONN5 0x12143124#define AFE_SECURE_MASK_TINY_CONN6 0x12183125#define AFE_SECURE_MASK_TINY_CONN7 0x121c3126 3127#define AFE_MAX_REGISTER AFE_SECURE_MASK_TINY_CONN73128 3129#define AFE_IRQ_STATUS_BITS 0x87FFFFFF3130#define AFE_IRQ_CNT_SHIFT 03131#define AFE_IRQ_CNT_MASK 0x3ffff3132 3133#endif3134