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1// SPDX-License-Identifier: GPL-2.02/*3 * Mediatek ALSA SoC AFE platform driver for 81954 *5 * Copyright (c) 2021 MediaTek Inc.6 * Author: Bicycle Tsai <bicycle.tsai@mediatek.com>7 * Trevor Wu <trevor.wu@mediatek.com>8 */9 10#include <linux/delay.h>11#include <linux/dma-mapping.h>12#include <linux/module.h>13#include <linux/mfd/syscon.h>14#include <linux/of.h>15#include <linux/of_address.h>16#include <linux/of_platform.h>17#include <linux/of_reserved_mem.h>18#include <linux/pm_runtime.h>19#include <linux/reset.h>20#include "mt8195-afe-common.h"21#include "mt8195-afe-clk.h"22#include "mt8195-reg.h"23#include "../common/mtk-afe-platform-driver.h"24#include "../common/mtk-afe-fe-dai.h"25 26#define MT8195_MEMIF_BUFFER_BYTES_ALIGN (0x40)27#define MT8195_MEMIF_DL7_MAX_PERIOD_SIZE (0x3fff)28 29struct mtk_dai_memif_priv {30 unsigned int asys_timing_sel;31};32 33static const struct snd_pcm_hardware mt8195_afe_hardware = {34 .info = SNDRV_PCM_INFO_MMAP |35 SNDRV_PCM_INFO_INTERLEAVED |36 SNDRV_PCM_INFO_MMAP_VALID,37 .formats = SNDRV_PCM_FMTBIT_S16_LE |38 SNDRV_PCM_FMTBIT_S24_LE |39 SNDRV_PCM_FMTBIT_S32_LE,40 .period_bytes_min = 64,41 .period_bytes_max = 256 * 1024,42 .periods_min = 2,43 .periods_max = 256,44 .buffer_bytes_max = 256 * 2 * 1024,45};46 47struct mt8195_afe_rate {48 unsigned int rate;49 unsigned int reg_value;50};51 52static const struct mt8195_afe_rate mt8195_afe_rates[] = {53 { .rate = 8000, .reg_value = 0, },54 { .rate = 12000, .reg_value = 1, },55 { .rate = 16000, .reg_value = 2, },56 { .rate = 24000, .reg_value = 3, },57 { .rate = 32000, .reg_value = 4, },58 { .rate = 48000, .reg_value = 5, },59 { .rate = 96000, .reg_value = 6, },60 { .rate = 192000, .reg_value = 7, },61 { .rate = 384000, .reg_value = 8, },62 { .rate = 7350, .reg_value = 16, },63 { .rate = 11025, .reg_value = 17, },64 { .rate = 14700, .reg_value = 18, },65 { .rate = 22050, .reg_value = 19, },66 { .rate = 29400, .reg_value = 20, },67 { .rate = 44100, .reg_value = 21, },68 { .rate = 88200, .reg_value = 22, },69 { .rate = 176400, .reg_value = 23, },70 { .rate = 352800, .reg_value = 24, },71};72 73int mt8195_afe_fs_timing(unsigned int rate)74{75 int i;76 77 for (i = 0; i < ARRAY_SIZE(mt8195_afe_rates); i++)78 if (mt8195_afe_rates[i].rate == rate)79 return mt8195_afe_rates[i].reg_value;80 81 return -EINVAL;82}83 84static int mt8195_memif_fs(struct snd_pcm_substream *substream,85 unsigned int rate)86{87 struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream);88 struct snd_soc_component *component =89 snd_soc_rtdcom_lookup(rtd, AFE_PCM_NAME);90 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(component);91 int id = snd_soc_rtd_to_cpu(rtd, 0)->id;92 struct mtk_base_afe_memif *memif = &afe->memif[id];93 int fs = mt8195_afe_fs_timing(rate);94 95 switch (memif->data->id) {96 case MT8195_AFE_MEMIF_DL10:97 fs = MT8195_ETDM_OUT3_1X_EN;98 break;99 case MT8195_AFE_MEMIF_UL8:100 fs = MT8195_ETDM_IN1_NX_EN;101 break;102 case MT8195_AFE_MEMIF_UL3:103 fs = MT8195_ETDM_IN2_NX_EN;104 break;105 default:106 break;107 }108 109 return fs;110}111 112static int mt8195_irq_fs(struct snd_pcm_substream *substream,113 unsigned int rate)114{115 int fs = mt8195_memif_fs(substream, rate);116 117 switch (fs) {118 case MT8195_ETDM_IN1_NX_EN:119 fs = MT8195_ETDM_IN1_1X_EN;120 break;121 case MT8195_ETDM_IN2_NX_EN:122 fs = MT8195_ETDM_IN2_1X_EN;123 break;124 default:125 break;126 }127 128 return fs;129}130 131enum {132 MT8195_AFE_CM0,133 MT8195_AFE_CM1,134 MT8195_AFE_CM2,135 MT8195_AFE_CM_NUM,136};137 138struct mt8195_afe_channel_merge {139 int id;140 int reg;141 unsigned int sel_shift;142 unsigned int sel_maskbit;143 unsigned int sel_default;144 unsigned int ch_num_shift;145 unsigned int ch_num_maskbit;146 unsigned int en_shift;147 unsigned int en_maskbit;148 unsigned int update_cnt_shift;149 unsigned int update_cnt_maskbit;150 unsigned int update_cnt_default;151};152 153static const struct mt8195_afe_channel_merge154 mt8195_afe_cm[MT8195_AFE_CM_NUM] = {155 [MT8195_AFE_CM0] = {156 .id = MT8195_AFE_CM0,157 .reg = AFE_CM0_CON,158 .sel_shift = 30,159 .sel_maskbit = 0x1,160 .sel_default = 1,161 .ch_num_shift = 2,162 .ch_num_maskbit = 0x3f,163 .en_shift = 0,164 .en_maskbit = 0x1,165 .update_cnt_shift = 16,166 .update_cnt_maskbit = 0x1fff,167 .update_cnt_default = 0x3,168 },169 [MT8195_AFE_CM1] = {170 .id = MT8195_AFE_CM1,171 .reg = AFE_CM1_CON,172 .sel_shift = 30,173 .sel_maskbit = 0x1,174 .sel_default = 1,175 .ch_num_shift = 2,176 .ch_num_maskbit = 0x1f,177 .en_shift = 0,178 .en_maskbit = 0x1,179 .update_cnt_shift = 16,180 .update_cnt_maskbit = 0x1fff,181 .update_cnt_default = 0x3,182 },183 [MT8195_AFE_CM2] = {184 .id = MT8195_AFE_CM2,185 .reg = AFE_CM2_CON,186 .sel_shift = 30,187 .sel_maskbit = 0x1,188 .sel_default = 1,189 .ch_num_shift = 2,190 .ch_num_maskbit = 0x1f,191 .en_shift = 0,192 .en_maskbit = 0x1,193 .update_cnt_shift = 16,194 .update_cnt_maskbit = 0x1fff,195 .update_cnt_default = 0x3,196 },197};198 199static int mt8195_afe_memif_is_ul(int id)200{201 if (id >= MT8195_AFE_MEMIF_UL_START && id < MT8195_AFE_MEMIF_END)202 return 1;203 else204 return 0;205}206 207static const struct mt8195_afe_channel_merge*208mt8195_afe_found_cm(struct snd_soc_dai *dai)209{210 struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);211 int id = -EINVAL;212 213 if (mt8195_afe_memif_is_ul(dai->id) == 0)214 return NULL;215 216 switch (dai->id) {217 case MT8195_AFE_MEMIF_UL9:218 id = MT8195_AFE_CM0;219 break;220 case MT8195_AFE_MEMIF_UL2:221 id = MT8195_AFE_CM1;222 break;223 case MT8195_AFE_MEMIF_UL10:224 id = MT8195_AFE_CM2;225 break;226 default:227 break;228 }229 230 if (id < 0) {231 dev_dbg(afe->dev, "%s, memif %d cannot find CM!\n",232 __func__, dai->id);233 return NULL;234 }235 236 return &mt8195_afe_cm[id];237}238 239static int mt8195_afe_config_cm(struct mtk_base_afe *afe,240 const struct mt8195_afe_channel_merge *cm,241 unsigned int channels)242{243 if (!cm)244 return -EINVAL;245 246 regmap_update_bits(afe->regmap,247 cm->reg,248 cm->sel_maskbit << cm->sel_shift,249 cm->sel_default << cm->sel_shift);250 251 regmap_update_bits(afe->regmap,252 cm->reg,253 cm->ch_num_maskbit << cm->ch_num_shift,254 (channels - 1) << cm->ch_num_shift);255 256 regmap_update_bits(afe->regmap,257 cm->reg,258 cm->update_cnt_maskbit << cm->update_cnt_shift,259 cm->update_cnt_default << cm->update_cnt_shift);260 261 return 0;262}263 264static int mt8195_afe_enable_cm(struct mtk_base_afe *afe,265 const struct mt8195_afe_channel_merge *cm,266 bool enable)267{268 if (!cm)269 return -EINVAL;270 271 regmap_update_bits(afe->regmap,272 cm->reg,273 cm->en_maskbit << cm->en_shift,274 enable << cm->en_shift);275 276 return 0;277}278 279static int280mt8195_afe_paired_memif_clk_prepare(struct snd_pcm_substream *substream,281 struct snd_soc_dai *dai,282 int enable)283{284 struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream);285 struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);286 struct mt8195_afe_private *afe_priv = afe->platform_priv;287 int id = snd_soc_rtd_to_cpu(rtd, 0)->id;288 int clk_id;289 290 if (id != MT8195_AFE_MEMIF_DL8 && id != MT8195_AFE_MEMIF_DL10)291 return 0;292 293 if (enable) {294 clk_id = MT8195_CLK_AUD_MEMIF_DL10;295 mt8195_afe_prepare_clk(afe, afe_priv->clk[clk_id]);296 clk_id = MT8195_CLK_AUD_MEMIF_DL8;297 mt8195_afe_prepare_clk(afe, afe_priv->clk[clk_id]);298 } else {299 clk_id = MT8195_CLK_AUD_MEMIF_DL8;300 mt8195_afe_unprepare_clk(afe, afe_priv->clk[clk_id]);301 clk_id = MT8195_CLK_AUD_MEMIF_DL10;302 mt8195_afe_unprepare_clk(afe, afe_priv->clk[clk_id]);303 }304 305 return 0;306}307 308static int309mt8195_afe_paired_memif_clk_enable(struct snd_pcm_substream *substream,310 struct snd_soc_dai *dai,311 int enable)312{313 struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream);314 struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);315 struct mt8195_afe_private *afe_priv = afe->platform_priv;316 int id = snd_soc_rtd_to_cpu(rtd, 0)->id;317 int clk_id;318 319 if (id != MT8195_AFE_MEMIF_DL8 && id != MT8195_AFE_MEMIF_DL10)320 return 0;321 322 if (enable) {323 /* DL8_DL10_MEM */324 clk_id = MT8195_CLK_AUD_MEMIF_DL10;325 mt8195_afe_enable_clk_atomic(afe, afe_priv->clk[clk_id]);326 udelay(1);327 /* DL8_DL10_AGENT */328 clk_id = MT8195_CLK_AUD_MEMIF_DL8;329 mt8195_afe_enable_clk_atomic(afe, afe_priv->clk[clk_id]);330 } else {331 /* DL8_DL10_AGENT */332 clk_id = MT8195_CLK_AUD_MEMIF_DL8;333 mt8195_afe_disable_clk_atomic(afe, afe_priv->clk[clk_id]);334 /* DL8_DL10_MEM */335 clk_id = MT8195_CLK_AUD_MEMIF_DL10;336 mt8195_afe_disable_clk_atomic(afe, afe_priv->clk[clk_id]);337 }338 339 return 0;340}341 342static int mt8195_afe_fe_startup(struct snd_pcm_substream *substream,343 struct snd_soc_dai *dai)344{345 struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream);346 struct snd_pcm_runtime *runtime = substream->runtime;347 struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);348 int id = snd_soc_rtd_to_cpu(rtd, 0)->id;349 int ret = 0;350 351 mt8195_afe_paired_memif_clk_prepare(substream, dai, 1);352 353 ret = mtk_afe_fe_startup(substream, dai);354 355 snd_pcm_hw_constraint_step(runtime, 0,356 SNDRV_PCM_HW_PARAM_BUFFER_BYTES,357 MT8195_MEMIF_BUFFER_BYTES_ALIGN);358 359 if (id != MT8195_AFE_MEMIF_DL7)360 goto out;361 362 ret = snd_pcm_hw_constraint_minmax(runtime,363 SNDRV_PCM_HW_PARAM_PERIOD_SIZE,364 1,365 MT8195_MEMIF_DL7_MAX_PERIOD_SIZE);366 if (ret < 0)367 dev_dbg(afe->dev, "hw_constraint_minmax failed\n");368out:369 return ret;370}371 372static void mt8195_afe_fe_shutdown(struct snd_pcm_substream *substream,373 struct snd_soc_dai *dai)374{375 mtk_afe_fe_shutdown(substream, dai);376 mt8195_afe_paired_memif_clk_prepare(substream, dai, 0);377}378 379static int mt8195_afe_fe_hw_params(struct snd_pcm_substream *substream,380 struct snd_pcm_hw_params *params,381 struct snd_soc_dai *dai)382{383 struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream);384 struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);385 int id = snd_soc_rtd_to_cpu(rtd, 0)->id;386 struct mtk_base_afe_memif *memif = &afe->memif[id];387 const struct mtk_base_memif_data *data = memif->data;388 const struct mt8195_afe_channel_merge *cm = mt8195_afe_found_cm(dai);389 unsigned int ch_num = params_channels(params);390 391 mt8195_afe_config_cm(afe, cm, params_channels(params));392 393 if (data->ch_num_reg >= 0) {394 regmap_update_bits(afe->regmap, data->ch_num_reg,395 data->ch_num_maskbit << data->ch_num_shift,396 ch_num << data->ch_num_shift);397 }398 399 return mtk_afe_fe_hw_params(substream, params, dai);400}401 402static int mt8195_afe_fe_hw_free(struct snd_pcm_substream *substream,403 struct snd_soc_dai *dai)404{405 return mtk_afe_fe_hw_free(substream, dai);406}407 408static int mt8195_afe_fe_prepare(struct snd_pcm_substream *substream,409 struct snd_soc_dai *dai)410{411 return mtk_afe_fe_prepare(substream, dai);412}413 414static int mt8195_afe_fe_trigger(struct snd_pcm_substream *substream, int cmd,415 struct snd_soc_dai *dai)416{417 int ret = 0;418 struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);419 const struct mt8195_afe_channel_merge *cm = mt8195_afe_found_cm(dai);420 421 switch (cmd) {422 case SNDRV_PCM_TRIGGER_START:423 case SNDRV_PCM_TRIGGER_RESUME:424 mt8195_afe_enable_cm(afe, cm, true);425 break;426 case SNDRV_PCM_TRIGGER_STOP:427 case SNDRV_PCM_TRIGGER_SUSPEND:428 mt8195_afe_enable_cm(afe, cm, false);429 break;430 default:431 break;432 }433 434 ret = mtk_afe_fe_trigger(substream, cmd, dai);435 436 switch (cmd) {437 case SNDRV_PCM_TRIGGER_START:438 case SNDRV_PCM_TRIGGER_RESUME:439 mt8195_afe_paired_memif_clk_enable(substream, dai, 1);440 break;441 case SNDRV_PCM_TRIGGER_STOP:442 case SNDRV_PCM_TRIGGER_SUSPEND:443 mt8195_afe_paired_memif_clk_enable(substream, dai, 0);444 break;445 default:446 break;447 }448 449 return ret;450}451 452static int mt8195_afe_fe_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)453{454 return 0;455}456 457static const struct snd_soc_dai_ops mt8195_afe_fe_dai_ops = {458 .startup = mt8195_afe_fe_startup,459 .shutdown = mt8195_afe_fe_shutdown,460 .hw_params = mt8195_afe_fe_hw_params,461 .hw_free = mt8195_afe_fe_hw_free,462 .prepare = mt8195_afe_fe_prepare,463 .trigger = mt8195_afe_fe_trigger,464 .set_fmt = mt8195_afe_fe_set_fmt,465};466 467#define MTK_PCM_RATES (SNDRV_PCM_RATE_8000_48000 |\468 SNDRV_PCM_RATE_88200 |\469 SNDRV_PCM_RATE_96000 |\470 SNDRV_PCM_RATE_176400 |\471 SNDRV_PCM_RATE_192000 |\472 SNDRV_PCM_RATE_352800 |\473 SNDRV_PCM_RATE_384000)474 475#define MTK_PCM_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\476 SNDRV_PCM_FMTBIT_S24_LE |\477 SNDRV_PCM_FMTBIT_S32_LE)478 479static struct snd_soc_dai_driver mt8195_memif_dai_driver[] = {480 /* FE DAIs: memory intefaces to CPU */481 {482 .name = "DL2",483 .id = MT8195_AFE_MEMIF_DL2,484 .playback = {485 .stream_name = "DL2",486 .channels_min = 1,487 .channels_max = 2,488 .rates = MTK_PCM_RATES,489 .formats = MTK_PCM_FORMATS,490 },491 .ops = &mt8195_afe_fe_dai_ops,492 },493 {494 .name = "DL3",495 .id = MT8195_AFE_MEMIF_DL3,496 .playback = {497 .stream_name = "DL3",498 .channels_min = 1,499 .channels_max = 2,500 .rates = MTK_PCM_RATES,501 .formats = MTK_PCM_FORMATS,502 },503 .ops = &mt8195_afe_fe_dai_ops,504 },505 {506 .name = "DL6",507 .id = MT8195_AFE_MEMIF_DL6,508 .playback = {509 .stream_name = "DL6",510 .channels_min = 1,511 .channels_max = 2,512 .rates = MTK_PCM_RATES,513 .formats = MTK_PCM_FORMATS,514 },515 .ops = &mt8195_afe_fe_dai_ops,516 },517 {518 .name = "DL7",519 .id = MT8195_AFE_MEMIF_DL7,520 .playback = {521 .stream_name = "DL7",522 .channels_min = 1,523 .channels_max = 2,524 .rates = MTK_PCM_RATES,525 .formats = MTK_PCM_FORMATS,526 },527 .ops = &mt8195_afe_fe_dai_ops,528 },529 {530 .name = "DL8",531 .id = MT8195_AFE_MEMIF_DL8,532 .playback = {533 .stream_name = "DL8",534 .channels_min = 1,535 .channels_max = 24,536 .rates = MTK_PCM_RATES,537 .formats = MTK_PCM_FORMATS,538 },539 .ops = &mt8195_afe_fe_dai_ops,540 },541 {542 .name = "DL10",543 .id = MT8195_AFE_MEMIF_DL10,544 .playback = {545 .stream_name = "DL10",546 .channels_min = 1,547 .channels_max = 8,548 .rates = MTK_PCM_RATES,549 .formats = MTK_PCM_FORMATS,550 },551 .ops = &mt8195_afe_fe_dai_ops,552 },553 {554 .name = "DL11",555 .id = MT8195_AFE_MEMIF_DL11,556 .playback = {557 .stream_name = "DL11",558 .channels_min = 1,559 .channels_max = 48,560 .rates = MTK_PCM_RATES,561 .formats = MTK_PCM_FORMATS,562 },563 .ops = &mt8195_afe_fe_dai_ops,564 },565 {566 .name = "UL1",567 .id = MT8195_AFE_MEMIF_UL1,568 .capture = {569 .stream_name = "UL1",570 .channels_min = 1,571 .channels_max = 8,572 .rates = MTK_PCM_RATES,573 .formats = MTK_PCM_FORMATS,574 },575 .ops = &mt8195_afe_fe_dai_ops,576 },577 {578 .name = "UL2",579 .id = MT8195_AFE_MEMIF_UL2,580 .capture = {581 .stream_name = "UL2",582 .channels_min = 1,583 .channels_max = 8,584 .rates = MTK_PCM_RATES,585 .formats = MTK_PCM_FORMATS,586 },587 .ops = &mt8195_afe_fe_dai_ops,588 },589 {590 .name = "UL3",591 .id = MT8195_AFE_MEMIF_UL3,592 .capture = {593 .stream_name = "UL3",594 .channels_min = 1,595 .channels_max = 16,596 .rates = MTK_PCM_RATES,597 .formats = MTK_PCM_FORMATS,598 },599 .ops = &mt8195_afe_fe_dai_ops,600 },601 {602 .name = "UL4",603 .id = MT8195_AFE_MEMIF_UL4,604 .capture = {605 .stream_name = "UL4",606 .channels_min = 1,607 .channels_max = 2,608 .rates = MTK_PCM_RATES,609 .formats = MTK_PCM_FORMATS,610 },611 .ops = &mt8195_afe_fe_dai_ops,612 },613 {614 .name = "UL5",615 .id = MT8195_AFE_MEMIF_UL5,616 .capture = {617 .stream_name = "UL5",618 .channels_min = 1,619 .channels_max = 2,620 .rates = MTK_PCM_RATES,621 .formats = MTK_PCM_FORMATS,622 },623 .ops = &mt8195_afe_fe_dai_ops,624 },625 {626 .name = "UL6",627 .id = MT8195_AFE_MEMIF_UL6,628 .capture = {629 .stream_name = "UL6",630 .channels_min = 1,631 .channels_max = 8,632 .rates = MTK_PCM_RATES,633 .formats = MTK_PCM_FORMATS,634 },635 .ops = &mt8195_afe_fe_dai_ops,636 },637 {638 .name = "UL8",639 .id = MT8195_AFE_MEMIF_UL8,640 .capture = {641 .stream_name = "UL8",642 .channels_min = 1,643 .channels_max = 24,644 .rates = MTK_PCM_RATES,645 .formats = MTK_PCM_FORMATS,646 },647 .ops = &mt8195_afe_fe_dai_ops,648 },649 {650 .name = "UL9",651 .id = MT8195_AFE_MEMIF_UL9,652 .capture = {653 .stream_name = "UL9",654 .channels_min = 1,655 .channels_max = 32,656 .rates = MTK_PCM_RATES,657 .formats = MTK_PCM_FORMATS,658 },659 .ops = &mt8195_afe_fe_dai_ops,660 },661 {662 .name = "UL10",663 .id = MT8195_AFE_MEMIF_UL10,664 .capture = {665 .stream_name = "UL10",666 .channels_min = 1,667 .channels_max = 4,668 .rates = MTK_PCM_RATES,669 .formats = MTK_PCM_FORMATS,670 },671 .ops = &mt8195_afe_fe_dai_ops,672 },673};674 675static const struct snd_kcontrol_new o002_mix[] = {676 SOC_DAPM_SINGLE_AUTODISABLE("I000 Switch", AFE_CONN2, 0, 1, 0),677 SOC_DAPM_SINGLE_AUTODISABLE("I012 Switch", AFE_CONN2, 12, 1, 0),678 SOC_DAPM_SINGLE_AUTODISABLE("I020 Switch", AFE_CONN2, 20, 1, 0),679 SOC_DAPM_SINGLE_AUTODISABLE("I022 Switch", AFE_CONN2, 22, 1, 0),680 SOC_DAPM_SINGLE_AUTODISABLE("I070 Switch", AFE_CONN2_2, 6, 1, 0),681 SOC_DAPM_SINGLE_AUTODISABLE("I072 Switch", AFE_CONN2_2, 8, 1, 0),682 SOC_DAPM_SINGLE_AUTODISABLE("I168 Switch", AFE_CONN2_5, 8, 1, 0),683};684 685static const struct snd_kcontrol_new o003_mix[] = {686 SOC_DAPM_SINGLE_AUTODISABLE("I001 Switch", AFE_CONN3, 1, 1, 0),687 SOC_DAPM_SINGLE_AUTODISABLE("I013 Switch", AFE_CONN3, 13, 1, 0),688 SOC_DAPM_SINGLE_AUTODISABLE("I021 Switch", AFE_CONN3, 21, 1, 0),689 SOC_DAPM_SINGLE_AUTODISABLE("I023 Switch", AFE_CONN3, 23, 1, 0),690 SOC_DAPM_SINGLE_AUTODISABLE("I071 Switch", AFE_CONN3_2, 7, 1, 0),691 SOC_DAPM_SINGLE_AUTODISABLE("I073 Switch", AFE_CONN3_2, 9, 1, 0),692 SOC_DAPM_SINGLE_AUTODISABLE("I169 Switch", AFE_CONN3_5, 9, 1, 0),693};694 695static const struct snd_kcontrol_new o004_mix[] = {696 SOC_DAPM_SINGLE_AUTODISABLE("I000 Switch", AFE_CONN4, 0, 1, 0),697 SOC_DAPM_SINGLE_AUTODISABLE("I014 Switch", AFE_CONN4, 14, 1, 0),698 SOC_DAPM_SINGLE_AUTODISABLE("I024 Switch", AFE_CONN4, 24, 1, 0),699 SOC_DAPM_SINGLE_AUTODISABLE("I074 Switch", AFE_CONN4_2, 10, 1, 0),700 SOC_DAPM_SINGLE_AUTODISABLE("I170 Switch", AFE_CONN4_5, 10, 1, 0),701};702 703static const struct snd_kcontrol_new o005_mix[] = {704 SOC_DAPM_SINGLE_AUTODISABLE("I001 Switch", AFE_CONN5, 1, 1, 0),705 SOC_DAPM_SINGLE_AUTODISABLE("I015 Switch", AFE_CONN5, 15, 1, 0),706 SOC_DAPM_SINGLE_AUTODISABLE("I025 Switch", AFE_CONN5, 25, 1, 0),707 SOC_DAPM_SINGLE_AUTODISABLE("I075 Switch", AFE_CONN5_2, 11, 1, 0),708 SOC_DAPM_SINGLE_AUTODISABLE("I171 Switch", AFE_CONN5_5, 11, 1, 0),709};710 711static const struct snd_kcontrol_new o006_mix[] = {712 SOC_DAPM_SINGLE_AUTODISABLE("I000 Switch", AFE_CONN6, 0, 1, 0),713 SOC_DAPM_SINGLE_AUTODISABLE("I016 Switch", AFE_CONN6, 16, 1, 0),714 SOC_DAPM_SINGLE_AUTODISABLE("I026 Switch", AFE_CONN6, 26, 1, 0),715 SOC_DAPM_SINGLE_AUTODISABLE("I076 Switch", AFE_CONN6_2, 12, 1, 0),716};717 718static const struct snd_kcontrol_new o007_mix[] = {719 SOC_DAPM_SINGLE_AUTODISABLE("I001 Switch", AFE_CONN7, 1, 1, 0),720 SOC_DAPM_SINGLE_AUTODISABLE("I017 Switch", AFE_CONN7, 17, 1, 0),721 SOC_DAPM_SINGLE_AUTODISABLE("I027 Switch", AFE_CONN7, 27, 1, 0),722 SOC_DAPM_SINGLE_AUTODISABLE("I077 Switch", AFE_CONN7_2, 13, 1, 0),723};724 725static const struct snd_kcontrol_new o008_mix[] = {726 SOC_DAPM_SINGLE_AUTODISABLE("I018 Switch", AFE_CONN8, 18, 1, 0),727 SOC_DAPM_SINGLE_AUTODISABLE("I028 Switch", AFE_CONN8, 28, 1, 0),728 SOC_DAPM_SINGLE_AUTODISABLE("I078 Switch", AFE_CONN8_2, 14, 1, 0),729};730 731static const struct snd_kcontrol_new o009_mix[] = {732 SOC_DAPM_SINGLE_AUTODISABLE("I019 Switch", AFE_CONN9, 19, 1, 0),733 SOC_DAPM_SINGLE_AUTODISABLE("I029 Switch", AFE_CONN9, 29, 1, 0),734 SOC_DAPM_SINGLE_AUTODISABLE("I079 Switch", AFE_CONN9_2, 15, 1, 0),735};736 737static const struct snd_kcontrol_new o010_mix[] = {738 SOC_DAPM_SINGLE_AUTODISABLE("I022 Switch", AFE_CONN10, 22, 1, 0),739 SOC_DAPM_SINGLE_AUTODISABLE("I030 Switch", AFE_CONN10, 30, 1, 0),740 SOC_DAPM_SINGLE_AUTODISABLE("I046 Switch", AFE_CONN10_1, 14, 1, 0),741 SOC_DAPM_SINGLE_AUTODISABLE("I072 Switch", AFE_CONN10_2, 8, 1, 0),742};743 744static const struct snd_kcontrol_new o011_mix[] = {745 SOC_DAPM_SINGLE_AUTODISABLE("I023 Switch", AFE_CONN11, 23, 1, 0),746 SOC_DAPM_SINGLE_AUTODISABLE("I031 Switch", AFE_CONN11, 31, 1, 0),747 SOC_DAPM_SINGLE_AUTODISABLE("I047 Switch", AFE_CONN11_1, 15, 1, 0),748 SOC_DAPM_SINGLE_AUTODISABLE("I073 Switch", AFE_CONN11_2, 9, 1, 0),749};750 751static const struct snd_kcontrol_new o012_mix[] = {752 SOC_DAPM_SINGLE_AUTODISABLE("I024 Switch", AFE_CONN12, 24, 1, 0),753 SOC_DAPM_SINGLE_AUTODISABLE("I032 Switch", AFE_CONN12_1, 0, 1, 0),754 SOC_DAPM_SINGLE_AUTODISABLE("I048 Switch", AFE_CONN12_1, 16, 1, 0),755 SOC_DAPM_SINGLE_AUTODISABLE("I074 Switch", AFE_CONN12_2, 10, 1, 0),756};757 758static const struct snd_kcontrol_new o013_mix[] = {759 SOC_DAPM_SINGLE_AUTODISABLE("I025 Switch", AFE_CONN13, 25, 1, 0),760 SOC_DAPM_SINGLE_AUTODISABLE("I033 Switch", AFE_CONN13_1, 1, 1, 0),761 SOC_DAPM_SINGLE_AUTODISABLE("I049 Switch", AFE_CONN13_1, 17, 1, 0),762 SOC_DAPM_SINGLE_AUTODISABLE("I075 Switch", AFE_CONN13_2, 11, 1, 0),763};764 765static const struct snd_kcontrol_new o014_mix[] = {766 SOC_DAPM_SINGLE_AUTODISABLE("I026 Switch", AFE_CONN14, 26, 1, 0),767 SOC_DAPM_SINGLE_AUTODISABLE("I034 Switch", AFE_CONN14_1, 2, 1, 0),768 SOC_DAPM_SINGLE_AUTODISABLE("I050 Switch", AFE_CONN14_1, 18, 1, 0),769 SOC_DAPM_SINGLE_AUTODISABLE("I076 Switch", AFE_CONN14_2, 12, 1, 0),770};771 772static const struct snd_kcontrol_new o015_mix[] = {773 SOC_DAPM_SINGLE_AUTODISABLE("I027 Switch", AFE_CONN15, 27, 1, 0),774 SOC_DAPM_SINGLE_AUTODISABLE("I035 Switch", AFE_CONN15_1, 3, 1, 0),775 SOC_DAPM_SINGLE_AUTODISABLE("I051 Switch", AFE_CONN15_1, 19, 1, 0),776 SOC_DAPM_SINGLE_AUTODISABLE("I077 Switch", AFE_CONN15_2, 13, 1, 0),777};778 779static const struct snd_kcontrol_new o016_mix[] = {780 SOC_DAPM_SINGLE_AUTODISABLE("I028 Switch", AFE_CONN16, 28, 1, 0),781 SOC_DAPM_SINGLE_AUTODISABLE("I036 Switch", AFE_CONN16_1, 4, 1, 0),782 SOC_DAPM_SINGLE_AUTODISABLE("I052 Switch", AFE_CONN16_1, 20, 1, 0),783 SOC_DAPM_SINGLE_AUTODISABLE("I078 Switch", AFE_CONN16_2, 14, 1, 0),784};785 786static const struct snd_kcontrol_new o017_mix[] = {787 SOC_DAPM_SINGLE_AUTODISABLE("I029 Switch", AFE_CONN17, 29, 1, 0),788 SOC_DAPM_SINGLE_AUTODISABLE("I037 Switch", AFE_CONN17_1, 5, 1, 0),789 SOC_DAPM_SINGLE_AUTODISABLE("I053 Switch", AFE_CONN17_1, 21, 1, 0),790 SOC_DAPM_SINGLE_AUTODISABLE("I079 Switch", AFE_CONN17_2, 15, 1, 0),791};792 793static const struct snd_kcontrol_new o018_mix[] = {794 SOC_DAPM_SINGLE_AUTODISABLE("I038 Switch", AFE_CONN18_1, 6, 1, 0),795 SOC_DAPM_SINGLE_AUTODISABLE("I080 Switch", AFE_CONN18_2, 16, 1, 0),796};797 798static const struct snd_kcontrol_new o019_mix[] = {799 SOC_DAPM_SINGLE_AUTODISABLE("I039 Switch", AFE_CONN19_1, 7, 1, 0),800 SOC_DAPM_SINGLE_AUTODISABLE("I081 Switch", AFE_CONN19_2, 17, 1, 0),801};802 803static const struct snd_kcontrol_new o020_mix[] = {804 SOC_DAPM_SINGLE_AUTODISABLE("I040 Switch", AFE_CONN20_1, 8, 1, 0),805 SOC_DAPM_SINGLE_AUTODISABLE("I082 Switch", AFE_CONN20_2, 18, 1, 0),806};807 808static const struct snd_kcontrol_new o021_mix[] = {809 SOC_DAPM_SINGLE_AUTODISABLE("I041 Switch", AFE_CONN21_1, 9, 1, 0),810 SOC_DAPM_SINGLE_AUTODISABLE("I083 Switch", AFE_CONN21_2, 19, 1, 0),811};812 813static const struct snd_kcontrol_new o022_mix[] = {814 SOC_DAPM_SINGLE_AUTODISABLE("I042 Switch", AFE_CONN22_1, 10, 1, 0),815 SOC_DAPM_SINGLE_AUTODISABLE("I084 Switch", AFE_CONN22_2, 20, 1, 0),816};817 818static const struct snd_kcontrol_new o023_mix[] = {819 SOC_DAPM_SINGLE_AUTODISABLE("I043 Switch", AFE_CONN23_1, 11, 1, 0),820 SOC_DAPM_SINGLE_AUTODISABLE("I085 Switch", AFE_CONN23_2, 21, 1, 0),821};822 823static const struct snd_kcontrol_new o024_mix[] = {824 SOC_DAPM_SINGLE_AUTODISABLE("I044 Switch", AFE_CONN24_1, 12, 1, 0),825 SOC_DAPM_SINGLE_AUTODISABLE("I086 Switch", AFE_CONN24_2, 22, 1, 0),826};827 828static const struct snd_kcontrol_new o025_mix[] = {829 SOC_DAPM_SINGLE_AUTODISABLE("I045 Switch", AFE_CONN25_1, 13, 1, 0),830 SOC_DAPM_SINGLE_AUTODISABLE("I087 Switch", AFE_CONN25_2, 23, 1, 0),831};832 833static const struct snd_kcontrol_new o026_mix[] = {834 SOC_DAPM_SINGLE_AUTODISABLE("I046 Switch", AFE_CONN26_1, 14, 1, 0),835 SOC_DAPM_SINGLE_AUTODISABLE("I088 Switch", AFE_CONN26_2, 24, 1, 0),836};837 838static const struct snd_kcontrol_new o027_mix[] = {839 SOC_DAPM_SINGLE_AUTODISABLE("I047 Switch", AFE_CONN27_1, 15, 1, 0),840 SOC_DAPM_SINGLE_AUTODISABLE("I089 Switch", AFE_CONN27_2, 25, 1, 0),841};842 843static const struct snd_kcontrol_new o028_mix[] = {844 SOC_DAPM_SINGLE_AUTODISABLE("I048 Switch", AFE_CONN28_1, 16, 1, 0),845 SOC_DAPM_SINGLE_AUTODISABLE("I090 Switch", AFE_CONN28_2, 26, 1, 0),846};847 848static const struct snd_kcontrol_new o029_mix[] = {849 SOC_DAPM_SINGLE_AUTODISABLE("I049 Switch", AFE_CONN29_1, 17, 1, 0),850 SOC_DAPM_SINGLE_AUTODISABLE("I091 Switch", AFE_CONN29_2, 27, 1, 0),851};852 853static const struct snd_kcontrol_new o030_mix[] = {854 SOC_DAPM_SINGLE_AUTODISABLE("I050 Switch", AFE_CONN30_1, 18, 1, 0),855 SOC_DAPM_SINGLE_AUTODISABLE("I092 Switch", AFE_CONN30_2, 28, 1, 0),856};857 858static const struct snd_kcontrol_new o031_mix[] = {859 SOC_DAPM_SINGLE_AUTODISABLE("I051 Switch", AFE_CONN31_1, 19, 1, 0),860 SOC_DAPM_SINGLE_AUTODISABLE("I093 Switch", AFE_CONN31_2, 29, 1, 0),861};862 863static const struct snd_kcontrol_new o032_mix[] = {864 SOC_DAPM_SINGLE_AUTODISABLE("I052 Switch", AFE_CONN32_1, 20, 1, 0),865 SOC_DAPM_SINGLE_AUTODISABLE("I094 Switch", AFE_CONN32_2, 30, 1, 0),866};867 868static const struct snd_kcontrol_new o033_mix[] = {869 SOC_DAPM_SINGLE_AUTODISABLE("I053 Switch", AFE_CONN33_1, 21, 1, 0),870 SOC_DAPM_SINGLE_AUTODISABLE("I095 Switch", AFE_CONN33_2, 31, 1, 0),871};872 873static const struct snd_kcontrol_new o034_mix[] = {874 SOC_DAPM_SINGLE_AUTODISABLE("I000 Switch", AFE_CONN34, 0, 1, 0),875 SOC_DAPM_SINGLE_AUTODISABLE("I002 Switch", AFE_CONN34, 2, 1, 0),876 SOC_DAPM_SINGLE_AUTODISABLE("I012 Switch", AFE_CONN34, 12, 1, 0),877 SOC_DAPM_SINGLE_AUTODISABLE("I020 Switch", AFE_CONN34, 20, 1, 0),878 SOC_DAPM_SINGLE_AUTODISABLE("I070 Switch", AFE_CONN34_2, 6, 1, 0),879 SOC_DAPM_SINGLE_AUTODISABLE("I072 Switch", AFE_CONN34_2, 8, 1, 0),880 SOC_DAPM_SINGLE_AUTODISABLE("I168 Switch", AFE_CONN34_5, 8, 1, 0),881 SOC_DAPM_SINGLE_AUTODISABLE("I170 Switch", AFE_CONN34_5, 10, 1, 0),882};883 884static const struct snd_kcontrol_new o035_mix[] = {885 SOC_DAPM_SINGLE_AUTODISABLE("I001 Switch", AFE_CONN35, 1, 1, 0),886 SOC_DAPM_SINGLE_AUTODISABLE("I003 Switch", AFE_CONN35, 3, 1, 0),887 SOC_DAPM_SINGLE_AUTODISABLE("I013 Switch", AFE_CONN35, 13, 1, 0),888 SOC_DAPM_SINGLE_AUTODISABLE("I021 Switch", AFE_CONN35, 21, 1, 0),889 SOC_DAPM_SINGLE_AUTODISABLE("I071 Switch", AFE_CONN35_2, 7, 1, 0),890 SOC_DAPM_SINGLE_AUTODISABLE("I073 Switch", AFE_CONN35_2, 9, 1, 0),891 SOC_DAPM_SINGLE_AUTODISABLE("I137 Switch", AFE_CONN35_4, 9, 1, 0),892 SOC_DAPM_SINGLE_AUTODISABLE("I139 Switch", AFE_CONN35_4, 11, 1, 0),893 SOC_DAPM_SINGLE_AUTODISABLE("I168 Switch", AFE_CONN35_5, 8, 1, 0),894 SOC_DAPM_SINGLE_AUTODISABLE("I169 Switch", AFE_CONN35_5, 9, 1, 0),895 SOC_DAPM_SINGLE_AUTODISABLE("I170 Switch", AFE_CONN35_5, 10, 1, 0),896 SOC_DAPM_SINGLE_AUTODISABLE("I171 Switch", AFE_CONN35_5, 11, 1, 0),897};898 899static const struct snd_kcontrol_new o036_mix[] = {900 SOC_DAPM_SINGLE_AUTODISABLE("I000 Switch", AFE_CONN36, 0, 1, 0),901 SOC_DAPM_SINGLE_AUTODISABLE("I012 Switch", AFE_CONN36, 12, 1, 0),902 SOC_DAPM_SINGLE_AUTODISABLE("I020 Switch", AFE_CONN36, 20, 1, 0),903 SOC_DAPM_SINGLE_AUTODISABLE("I070 Switch", AFE_CONN36_2, 6, 1, 0),904 SOC_DAPM_SINGLE_AUTODISABLE("I168 Switch", AFE_CONN36_5, 8, 1, 0),905};906 907static const struct snd_kcontrol_new o037_mix[] = {908 SOC_DAPM_SINGLE_AUTODISABLE("I001 Switch", AFE_CONN37, 1, 1, 0),909 SOC_DAPM_SINGLE_AUTODISABLE("I013 Switch", AFE_CONN37, 13, 1, 0),910 SOC_DAPM_SINGLE_AUTODISABLE("I021 Switch", AFE_CONN37, 21, 1, 0),911 SOC_DAPM_SINGLE_AUTODISABLE("I071 Switch", AFE_CONN37_2, 7, 1, 0),912 SOC_DAPM_SINGLE_AUTODISABLE("I169 Switch", AFE_CONN37_5, 9, 1, 0),913};914 915static const struct snd_kcontrol_new o038_mix[] = {916 SOC_DAPM_SINGLE_AUTODISABLE("I022 Switch", AFE_CONN38, 22, 1, 0),917};918 919static const struct snd_kcontrol_new o039_mix[] = {920 SOC_DAPM_SINGLE_AUTODISABLE("I023 Switch", AFE_CONN39, 23, 1, 0),921};922 923static const struct snd_kcontrol_new o040_mix[] = {924 SOC_DAPM_SINGLE_AUTODISABLE("I002 Switch", AFE_CONN40, 2, 1, 0),925 SOC_DAPM_SINGLE_AUTODISABLE("I012 Switch", AFE_CONN40, 12, 1, 0),926 SOC_DAPM_SINGLE_AUTODISABLE("I022 Switch", AFE_CONN40, 22, 1, 0),927 SOC_DAPM_SINGLE_AUTODISABLE("I168 Switch", AFE_CONN40_5, 8, 1, 0),928};929 930static const struct snd_kcontrol_new o041_mix[] = {931 SOC_DAPM_SINGLE_AUTODISABLE("I003 Switch", AFE_CONN41, 3, 1, 0),932 SOC_DAPM_SINGLE_AUTODISABLE("I013 Switch", AFE_CONN41, 13, 1, 0),933 SOC_DAPM_SINGLE_AUTODISABLE("I023 Switch", AFE_CONN41, 23, 1, 0),934 SOC_DAPM_SINGLE_AUTODISABLE("I169 Switch", AFE_CONN41_5, 9, 1, 0),935};936 937static const struct snd_kcontrol_new o042_mix[] = {938 SOC_DAPM_SINGLE_AUTODISABLE("I014 Switch", AFE_CONN42, 14, 1, 0),939 SOC_DAPM_SINGLE_AUTODISABLE("I024 Switch", AFE_CONN42, 24, 1, 0),940 SOC_DAPM_SINGLE_AUTODISABLE("I170 Switch", AFE_CONN42_5, 10, 1, 0),941};942 943static const struct snd_kcontrol_new o043_mix[] = {944 SOC_DAPM_SINGLE_AUTODISABLE("I015 Switch", AFE_CONN43, 15, 1, 0),945 SOC_DAPM_SINGLE_AUTODISABLE("I025 Switch", AFE_CONN43, 25, 1, 0),946 SOC_DAPM_SINGLE_AUTODISABLE("I171 Switch", AFE_CONN43_5, 11, 1, 0),947};948 949static const struct snd_kcontrol_new o044_mix[] = {950 SOC_DAPM_SINGLE_AUTODISABLE("I016 Switch", AFE_CONN44, 16, 1, 0),951 SOC_DAPM_SINGLE_AUTODISABLE("I026 Switch", AFE_CONN44, 26, 1, 0),952};953 954static const struct snd_kcontrol_new o045_mix[] = {955 SOC_DAPM_SINGLE_AUTODISABLE("I017 Switch", AFE_CONN45, 17, 1, 0),956 SOC_DAPM_SINGLE_AUTODISABLE("I027 Switch", AFE_CONN45, 27, 1, 0),957};958 959static const struct snd_kcontrol_new o046_mix[] = {960 SOC_DAPM_SINGLE_AUTODISABLE("I018 Switch", AFE_CONN46, 18, 1, 0),961 SOC_DAPM_SINGLE_AUTODISABLE("I028 Switch", AFE_CONN46, 28, 1, 0),962};963 964static const struct snd_kcontrol_new o047_mix[] = {965 SOC_DAPM_SINGLE_AUTODISABLE("I019 Switch", AFE_CONN47, 19, 1, 0),966 SOC_DAPM_SINGLE_AUTODISABLE("I029 Switch", AFE_CONN47, 29, 1, 0),967};968 969static const struct snd_kcontrol_new o182_mix[] = {970 SOC_DAPM_SINGLE_AUTODISABLE("I024 Switch", AFE_CONN182, 24, 1, 0),971};972 973static const struct snd_kcontrol_new o183_mix[] = {974 SOC_DAPM_SINGLE_AUTODISABLE("I025 Switch", AFE_CONN183, 25, 1, 0),975};976 977static const char * const dl8_dl11_data_sel_mux_text[] = {978 "dl8", "dl11",979};980 981static SOC_ENUM_SINGLE_DECL(dl8_dl11_data_sel_mux_enum,982 AFE_DAC_CON2, 0, dl8_dl11_data_sel_mux_text);983 984static const struct snd_kcontrol_new dl8_dl11_data_sel_mux =985 SOC_DAPM_ENUM("DL8_DL11 Sink", dl8_dl11_data_sel_mux_enum);986 987static const struct snd_soc_dapm_widget mt8195_memif_widgets[] = {988 /* DL6 */989 SND_SOC_DAPM_MIXER("I000", SND_SOC_NOPM, 0, 0, NULL, 0),990 SND_SOC_DAPM_MIXER("I001", SND_SOC_NOPM, 0, 0, NULL, 0),991 992 /* DL3 */993 SND_SOC_DAPM_MIXER("I020", SND_SOC_NOPM, 0, 0, NULL, 0),994 SND_SOC_DAPM_MIXER("I021", SND_SOC_NOPM, 0, 0, NULL, 0),995 996 /* DL11 */997 SND_SOC_DAPM_MIXER("I022", SND_SOC_NOPM, 0, 0, NULL, 0),998 SND_SOC_DAPM_MIXER("I023", SND_SOC_NOPM, 0, 0, NULL, 0),999 SND_SOC_DAPM_MIXER("I024", SND_SOC_NOPM, 0, 0, NULL, 0),1000 SND_SOC_DAPM_MIXER("I025", SND_SOC_NOPM, 0, 0, NULL, 0),1001 SND_SOC_DAPM_MIXER("I026", SND_SOC_NOPM, 0, 0, NULL, 0),1002 SND_SOC_DAPM_MIXER("I027", SND_SOC_NOPM, 0, 0, NULL, 0),1003 SND_SOC_DAPM_MIXER("I028", SND_SOC_NOPM, 0, 0, NULL, 0),1004 SND_SOC_DAPM_MIXER("I029", SND_SOC_NOPM, 0, 0, NULL, 0),1005 SND_SOC_DAPM_MIXER("I030", SND_SOC_NOPM, 0, 0, NULL, 0),1006 SND_SOC_DAPM_MIXER("I031", SND_SOC_NOPM, 0, 0, NULL, 0),1007 SND_SOC_DAPM_MIXER("I032", SND_SOC_NOPM, 0, 0, NULL, 0),1008 SND_SOC_DAPM_MIXER("I033", SND_SOC_NOPM, 0, 0, NULL, 0),1009 SND_SOC_DAPM_MIXER("I034", SND_SOC_NOPM, 0, 0, NULL, 0),1010 SND_SOC_DAPM_MIXER("I035", SND_SOC_NOPM, 0, 0, NULL, 0),1011 SND_SOC_DAPM_MIXER("I036", SND_SOC_NOPM, 0, 0, NULL, 0),1012 SND_SOC_DAPM_MIXER("I037", SND_SOC_NOPM, 0, 0, NULL, 0),1013 SND_SOC_DAPM_MIXER("I038", SND_SOC_NOPM, 0, 0, NULL, 0),1014 SND_SOC_DAPM_MIXER("I039", SND_SOC_NOPM, 0, 0, NULL, 0),1015 SND_SOC_DAPM_MIXER("I040", SND_SOC_NOPM, 0, 0, NULL, 0),1016 SND_SOC_DAPM_MIXER("I041", SND_SOC_NOPM, 0, 0, NULL, 0),1017 SND_SOC_DAPM_MIXER("I042", SND_SOC_NOPM, 0, 0, NULL, 0),1018 SND_SOC_DAPM_MIXER("I043", SND_SOC_NOPM, 0, 0, NULL, 0),1019 SND_SOC_DAPM_MIXER("I044", SND_SOC_NOPM, 0, 0, NULL, 0),1020 SND_SOC_DAPM_MIXER("I045", SND_SOC_NOPM, 0, 0, NULL, 0),1021 1022 /* DL11/DL8 */1023 SND_SOC_DAPM_MIXER("I046", SND_SOC_NOPM, 0, 0, NULL, 0),1024 SND_SOC_DAPM_MIXER("I047", SND_SOC_NOPM, 0, 0, NULL, 0),1025 SND_SOC_DAPM_MIXER("I048", SND_SOC_NOPM, 0, 0, NULL, 0),1026 SND_SOC_DAPM_MIXER("I049", SND_SOC_NOPM, 0, 0, NULL, 0),1027 SND_SOC_DAPM_MIXER("I050", SND_SOC_NOPM, 0, 0, NULL, 0),1028 SND_SOC_DAPM_MIXER("I051", SND_SOC_NOPM, 0, 0, NULL, 0),1029 SND_SOC_DAPM_MIXER("I052", SND_SOC_NOPM, 0, 0, NULL, 0),1030 SND_SOC_DAPM_MIXER("I053", SND_SOC_NOPM, 0, 0, NULL, 0),1031 SND_SOC_DAPM_MIXER("I054", SND_SOC_NOPM, 0, 0, NULL, 0),1032 SND_SOC_DAPM_MIXER("I055", SND_SOC_NOPM, 0, 0, NULL, 0),1033 SND_SOC_DAPM_MIXER("I056", SND_SOC_NOPM, 0, 0, NULL, 0),1034 SND_SOC_DAPM_MIXER("I057", SND_SOC_NOPM, 0, 0, NULL, 0),1035 SND_SOC_DAPM_MIXER("I058", SND_SOC_NOPM, 0, 0, NULL, 0),1036 SND_SOC_DAPM_MIXER("I059", SND_SOC_NOPM, 0, 0, NULL, 0),1037 SND_SOC_DAPM_MIXER("I060", SND_SOC_NOPM, 0, 0, NULL, 0),1038 SND_SOC_DAPM_MIXER("I061", SND_SOC_NOPM, 0, 0, NULL, 0),1039 SND_SOC_DAPM_MIXER("I062", SND_SOC_NOPM, 0, 0, NULL, 0),1040 SND_SOC_DAPM_MIXER("I063", SND_SOC_NOPM, 0, 0, NULL, 0),1041 SND_SOC_DAPM_MIXER("I064", SND_SOC_NOPM, 0, 0, NULL, 0),1042 SND_SOC_DAPM_MIXER("I065", SND_SOC_NOPM, 0, 0, NULL, 0),1043 SND_SOC_DAPM_MIXER("I066", SND_SOC_NOPM, 0, 0, NULL, 0),1044 SND_SOC_DAPM_MIXER("I067", SND_SOC_NOPM, 0, 0, NULL, 0),1045 SND_SOC_DAPM_MIXER("I068", SND_SOC_NOPM, 0, 0, NULL, 0),1046 SND_SOC_DAPM_MIXER("I069", SND_SOC_NOPM, 0, 0, NULL, 0),1047 1048 /* DL2 */1049 SND_SOC_DAPM_MIXER("I070", SND_SOC_NOPM, 0, 0, NULL, 0),1050 SND_SOC_DAPM_MIXER("I071", SND_SOC_NOPM, 0, 0, NULL, 0),1051 1052 SND_SOC_DAPM_MUX("DL8_DL11 Mux",1053 SND_SOC_NOPM, 0, 0, &dl8_dl11_data_sel_mux),1054 1055 /* UL9 */1056 SND_SOC_DAPM_MIXER("O002", SND_SOC_NOPM, 0, 0,1057 o002_mix, ARRAY_SIZE(o002_mix)),1058 SND_SOC_DAPM_MIXER("O003", SND_SOC_NOPM, 0, 0,1059 o003_mix, ARRAY_SIZE(o003_mix)),1060 SND_SOC_DAPM_MIXER("O004", SND_SOC_NOPM, 0, 0,1061 o004_mix, ARRAY_SIZE(o004_mix)),1062 SND_SOC_DAPM_MIXER("O005", SND_SOC_NOPM, 0, 0,1063 o005_mix, ARRAY_SIZE(o005_mix)),1064 SND_SOC_DAPM_MIXER("O006", SND_SOC_NOPM, 0, 0,1065 o006_mix, ARRAY_SIZE(o006_mix)),1066 SND_SOC_DAPM_MIXER("O007", SND_SOC_NOPM, 0, 0,1067 o007_mix, ARRAY_SIZE(o007_mix)),1068 SND_SOC_DAPM_MIXER("O008", SND_SOC_NOPM, 0, 0,1069 o008_mix, ARRAY_SIZE(o008_mix)),1070 SND_SOC_DAPM_MIXER("O009", SND_SOC_NOPM, 0, 0,1071 o009_mix, ARRAY_SIZE(o009_mix)),1072 SND_SOC_DAPM_MIXER("O010", SND_SOC_NOPM, 0, 0,1073 o010_mix, ARRAY_SIZE(o010_mix)),1074 SND_SOC_DAPM_MIXER("O011", SND_SOC_NOPM, 0, 0,1075 o011_mix, ARRAY_SIZE(o011_mix)),1076 SND_SOC_DAPM_MIXER("O012", SND_SOC_NOPM, 0, 0,1077 o012_mix, ARRAY_SIZE(o012_mix)),1078 SND_SOC_DAPM_MIXER("O013", SND_SOC_NOPM, 0, 0,1079 o013_mix, ARRAY_SIZE(o013_mix)),1080 SND_SOC_DAPM_MIXER("O014", SND_SOC_NOPM, 0, 0,1081 o014_mix, ARRAY_SIZE(o014_mix)),1082 SND_SOC_DAPM_MIXER("O015", SND_SOC_NOPM, 0, 0,1083 o015_mix, ARRAY_SIZE(o015_mix)),1084 SND_SOC_DAPM_MIXER("O016", SND_SOC_NOPM, 0, 0,1085 o016_mix, ARRAY_SIZE(o016_mix)),1086 SND_SOC_DAPM_MIXER("O017", SND_SOC_NOPM, 0, 0,1087 o017_mix, ARRAY_SIZE(o017_mix)),1088 SND_SOC_DAPM_MIXER("O018", SND_SOC_NOPM, 0, 0,1089 o018_mix, ARRAY_SIZE(o018_mix)),1090 SND_SOC_DAPM_MIXER("O019", SND_SOC_NOPM, 0, 0,1091 o019_mix, ARRAY_SIZE(o019_mix)),1092 SND_SOC_DAPM_MIXER("O020", SND_SOC_NOPM, 0, 0,1093 o020_mix, ARRAY_SIZE(o020_mix)),1094 SND_SOC_DAPM_MIXER("O021", SND_SOC_NOPM, 0, 0,1095 o021_mix, ARRAY_SIZE(o021_mix)),1096 SND_SOC_DAPM_MIXER("O022", SND_SOC_NOPM, 0, 0,1097 o022_mix, ARRAY_SIZE(o022_mix)),1098 SND_SOC_DAPM_MIXER("O023", SND_SOC_NOPM, 0, 0,1099 o023_mix, ARRAY_SIZE(o023_mix)),1100 SND_SOC_DAPM_MIXER("O024", SND_SOC_NOPM, 0, 0,1101 o024_mix, ARRAY_SIZE(o024_mix)),1102 SND_SOC_DAPM_MIXER("O025", SND_SOC_NOPM, 0, 0,1103 o025_mix, ARRAY_SIZE(o025_mix)),1104 SND_SOC_DAPM_MIXER("O026", SND_SOC_NOPM, 0, 0,1105 o026_mix, ARRAY_SIZE(o026_mix)),1106 SND_SOC_DAPM_MIXER("O027", SND_SOC_NOPM, 0, 0,1107 o027_mix, ARRAY_SIZE(o027_mix)),1108 SND_SOC_DAPM_MIXER("O028", SND_SOC_NOPM, 0, 0,1109 o028_mix, ARRAY_SIZE(o028_mix)),1110 SND_SOC_DAPM_MIXER("O029", SND_SOC_NOPM, 0, 0,1111 o029_mix, ARRAY_SIZE(o029_mix)),1112 SND_SOC_DAPM_MIXER("O030", SND_SOC_NOPM, 0, 0,1113 o030_mix, ARRAY_SIZE(o030_mix)),1114 SND_SOC_DAPM_MIXER("O031", SND_SOC_NOPM, 0, 0,1115 o031_mix, ARRAY_SIZE(o031_mix)),1116 SND_SOC_DAPM_MIXER("O032", SND_SOC_NOPM, 0, 0,1117 o032_mix, ARRAY_SIZE(o032_mix)),1118 SND_SOC_DAPM_MIXER("O033", SND_SOC_NOPM, 0, 0,1119 o033_mix, ARRAY_SIZE(o033_mix)),1120 1121 /* UL4 */1122 SND_SOC_DAPM_MIXER("O034", SND_SOC_NOPM, 0, 0,1123 o034_mix, ARRAY_SIZE(o034_mix)),1124 SND_SOC_DAPM_MIXER("O035", SND_SOC_NOPM, 0, 0,1125 o035_mix, ARRAY_SIZE(o035_mix)),1126 1127 /* UL5 */1128 SND_SOC_DAPM_MIXER("O036", SND_SOC_NOPM, 0, 0,1129 o036_mix, ARRAY_SIZE(o036_mix)),1130 SND_SOC_DAPM_MIXER("O037", SND_SOC_NOPM, 0, 0,1131 o037_mix, ARRAY_SIZE(o037_mix)),1132 1133 /* UL10 */1134 SND_SOC_DAPM_MIXER("O038", SND_SOC_NOPM, 0, 0,1135 o038_mix, ARRAY_SIZE(o038_mix)),1136 SND_SOC_DAPM_MIXER("O039", SND_SOC_NOPM, 0, 0,1137 o039_mix, ARRAY_SIZE(o039_mix)),1138 SND_SOC_DAPM_MIXER("O182", SND_SOC_NOPM, 0, 0,1139 o182_mix, ARRAY_SIZE(o182_mix)),1140 SND_SOC_DAPM_MIXER("O183", SND_SOC_NOPM, 0, 0,1141 o183_mix, ARRAY_SIZE(o183_mix)),1142 1143 /* UL2 */1144 SND_SOC_DAPM_MIXER("O040", SND_SOC_NOPM, 0, 0,1145 o040_mix, ARRAY_SIZE(o040_mix)),1146 SND_SOC_DAPM_MIXER("O041", SND_SOC_NOPM, 0, 0,1147 o041_mix, ARRAY_SIZE(o041_mix)),1148 SND_SOC_DAPM_MIXER("O042", SND_SOC_NOPM, 0, 0,1149 o042_mix, ARRAY_SIZE(o042_mix)),1150 SND_SOC_DAPM_MIXER("O043", SND_SOC_NOPM, 0, 0,1151 o043_mix, ARRAY_SIZE(o043_mix)),1152 SND_SOC_DAPM_MIXER("O044", SND_SOC_NOPM, 0, 0,1153 o044_mix, ARRAY_SIZE(o044_mix)),1154 SND_SOC_DAPM_MIXER("O045", SND_SOC_NOPM, 0, 0,1155 o045_mix, ARRAY_SIZE(o045_mix)),1156 SND_SOC_DAPM_MIXER("O046", SND_SOC_NOPM, 0, 0,1157 o046_mix, ARRAY_SIZE(o046_mix)),1158 SND_SOC_DAPM_MIXER("O047", SND_SOC_NOPM, 0, 0,1159 o047_mix, ARRAY_SIZE(o047_mix)),1160};1161 1162static const struct snd_soc_dapm_route mt8195_memif_routes[] = {1163 {"I000", NULL, "DL6"},1164 {"I001", NULL, "DL6"},1165 1166 {"I020", NULL, "DL3"},1167 {"I021", NULL, "DL3"},1168 1169 {"I022", NULL, "DL11"},1170 {"I023", NULL, "DL11"},1171 {"I024", NULL, "DL11"},1172 {"I025", NULL, "DL11"},1173 {"I026", NULL, "DL11"},1174 {"I027", NULL, "DL11"},1175 {"I028", NULL, "DL11"},1176 {"I029", NULL, "DL11"},1177 {"I030", NULL, "DL11"},1178 {"I031", NULL, "DL11"},1179 {"I032", NULL, "DL11"},1180 {"I033", NULL, "DL11"},1181 {"I034", NULL, "DL11"},1182 {"I035", NULL, "DL11"},1183 {"I036", NULL, "DL11"},1184 {"I037", NULL, "DL11"},1185 {"I038", NULL, "DL11"},1186 {"I039", NULL, "DL11"},1187 {"I040", NULL, "DL11"},1188 {"I041", NULL, "DL11"},1189 {"I042", NULL, "DL11"},1190 {"I043", NULL, "DL11"},1191 {"I044", NULL, "DL11"},1192 {"I045", NULL, "DL11"},1193 1194 {"DL8_DL11 Mux", "dl8", "DL8"},1195 {"DL8_DL11 Mux", "dl11", "DL11"},1196 1197 {"I046", NULL, "DL8_DL11 Mux"},1198 {"I047", NULL, "DL8_DL11 Mux"},1199 {"I048", NULL, "DL8_DL11 Mux"},1200 {"I049", NULL, "DL8_DL11 Mux"},1201 {"I050", NULL, "DL8_DL11 Mux"},1202 {"I051", NULL, "DL8_DL11 Mux"},1203 {"I052", NULL, "DL8_DL11 Mux"},1204 {"I053", NULL, "DL8_DL11 Mux"},1205 {"I054", NULL, "DL8_DL11 Mux"},1206 {"I055", NULL, "DL8_DL11 Mux"},1207 {"I056", NULL, "DL8_DL11 Mux"},1208 {"I057", NULL, "DL8_DL11 Mux"},1209 {"I058", NULL, "DL8_DL11 Mux"},1210 {"I059", NULL, "DL8_DL11 Mux"},1211 {"I060", NULL, "DL8_DL11 Mux"},1212 {"I061", NULL, "DL8_DL11 Mux"},1213 {"I062", NULL, "DL8_DL11 Mux"},1214 {"I063", NULL, "DL8_DL11 Mux"},1215 {"I064", NULL, "DL8_DL11 Mux"},1216 {"I065", NULL, "DL8_DL11 Mux"},1217 {"I066", NULL, "DL8_DL11 Mux"},1218 {"I067", NULL, "DL8_DL11 Mux"},1219 {"I068", NULL, "DL8_DL11 Mux"},1220 {"I069", NULL, "DL8_DL11 Mux"},1221 1222 {"I070", NULL, "DL2"},1223 {"I071", NULL, "DL2"},1224 1225 {"UL9", NULL, "O002"},1226 {"UL9", NULL, "O003"},1227 {"UL9", NULL, "O004"},1228 {"UL9", NULL, "O005"},1229 {"UL9", NULL, "O006"},1230 {"UL9", NULL, "O007"},1231 {"UL9", NULL, "O008"},1232 {"UL9", NULL, "O009"},1233 {"UL9", NULL, "O010"},1234 {"UL9", NULL, "O011"},1235 {"UL9", NULL, "O012"},1236 {"UL9", NULL, "O013"},1237 {"UL9", NULL, "O014"},1238 {"UL9", NULL, "O015"},1239 {"UL9", NULL, "O016"},1240 {"UL9", NULL, "O017"},1241 {"UL9", NULL, "O018"},1242 {"UL9", NULL, "O019"},1243 {"UL9", NULL, "O020"},1244 {"UL9", NULL, "O021"},1245 {"UL9", NULL, "O022"},1246 {"UL9", NULL, "O023"},1247 {"UL9", NULL, "O024"},1248 {"UL9", NULL, "O025"},1249 {"UL9", NULL, "O026"},1250 {"UL9", NULL, "O027"},1251 {"UL9", NULL, "O028"},1252 {"UL9", NULL, "O029"},1253 {"UL9", NULL, "O030"},1254 {"UL9", NULL, "O031"},1255 {"UL9", NULL, "O032"},1256 {"UL9", NULL, "O033"},1257 1258 {"UL4", NULL, "O034"},1259 {"UL4", NULL, "O035"},1260 1261 {"UL5", NULL, "O036"},1262 {"UL5", NULL, "O037"},1263 1264 {"UL10", NULL, "O038"},1265 {"UL10", NULL, "O039"},1266 {"UL10", NULL, "O182"},1267 {"UL10", NULL, "O183"},1268 1269 {"UL2", NULL, "O040"},1270 {"UL2", NULL, "O041"},1271 {"UL2", NULL, "O042"},1272 {"UL2", NULL, "O043"},1273 {"UL2", NULL, "O044"},1274 {"UL2", NULL, "O045"},1275 {"UL2", NULL, "O046"},1276 {"UL2", NULL, "O047"},1277 1278 {"O004", "I000 Switch", "I000"},1279 {"O005", "I001 Switch", "I001"},1280 1281 {"O006", "I000 Switch", "I000"},1282 {"O007", "I001 Switch", "I001"},1283 1284 {"O010", "I022 Switch", "I022"},1285 {"O011", "I023 Switch", "I023"},1286 {"O012", "I024 Switch", "I024"},1287 {"O013", "I025 Switch", "I025"},1288 {"O014", "I026 Switch", "I026"},1289 {"O015", "I027 Switch", "I027"},1290 {"O016", "I028 Switch", "I028"},1291 {"O017", "I029 Switch", "I029"},1292 1293 {"O010", "I046 Switch", "I046"},1294 {"O011", "I047 Switch", "I047"},1295 {"O012", "I048 Switch", "I048"},1296 {"O013", "I049 Switch", "I049"},1297 {"O014", "I050 Switch", "I050"},1298 {"O015", "I051 Switch", "I051"},1299 {"O016", "I052 Switch", "I052"},1300 {"O017", "I053 Switch", "I053"},1301 {"O002", "I022 Switch", "I022"},1302 {"O003", "I023 Switch", "I023"},1303 {"O004", "I024 Switch", "I024"},1304 {"O005", "I025 Switch", "I025"},1305 {"O006", "I026 Switch", "I026"},1306 {"O007", "I027 Switch", "I027"},1307 {"O008", "I028 Switch", "I028"},1308 {"O009", "I029 Switch", "I029"},1309 {"O010", "I030 Switch", "I030"},1310 {"O011", "I031 Switch", "I031"},1311 {"O012", "I032 Switch", "I032"},1312 {"O013", "I033 Switch", "I033"},1313 {"O014", "I034 Switch", "I034"},1314 {"O015", "I035 Switch", "I035"},1315 {"O016", "I036 Switch", "I036"},1316 {"O017", "I037 Switch", "I037"},1317 {"O018", "I038 Switch", "I038"},1318 {"O019", "I039 Switch", "I039"},1319 {"O020", "I040 Switch", "I040"},1320 {"O021", "I041 Switch", "I041"},1321 {"O022", "I042 Switch", "I042"},1322 {"O023", "I043 Switch", "I043"},1323 {"O024", "I044 Switch", "I044"},1324 {"O025", "I045 Switch", "I045"},1325 {"O026", "I046 Switch", "I046"},1326 {"O027", "I047 Switch", "I047"},1327 {"O028", "I048 Switch", "I048"},1328 {"O029", "I049 Switch", "I049"},1329 {"O030", "I050 Switch", "I050"},1330 {"O031", "I051 Switch", "I051"},1331 {"O032", "I052 Switch", "I052"},1332 {"O033", "I053 Switch", "I053"},1333 1334 {"O002", "I000 Switch", "I000"},1335 {"O003", "I001 Switch", "I001"},1336 {"O002", "I020 Switch", "I020"},1337 {"O003", "I021 Switch", "I021"},1338 {"O002", "I070 Switch", "I070"},1339 {"O003", "I071 Switch", "I071"},1340 1341 {"O034", "I000 Switch", "I000"},1342 {"O035", "I001 Switch", "I001"},1343 {"O034", "I002 Switch", "I002"},1344 {"O035", "I003 Switch", "I003"},1345 {"O034", "I012 Switch", "I012"},1346 {"O035", "I013 Switch", "I013"},1347 {"O034", "I020 Switch", "I020"},1348 {"O035", "I021 Switch", "I021"},1349 {"O034", "I070 Switch", "I070"},1350 {"O035", "I071 Switch", "I071"},1351 {"O034", "I072 Switch", "I072"},1352 {"O035", "I073 Switch", "I073"},1353 1354 {"O036", "I000 Switch", "I000"},1355 {"O037", "I001 Switch", "I001"},1356 {"O036", "I012 Switch", "I012"},1357 {"O037", "I013 Switch", "I013"},1358 {"O036", "I020 Switch", "I020"},1359 {"O037", "I021 Switch", "I021"},1360 {"O036", "I070 Switch", "I070"},1361 {"O037", "I071 Switch", "I071"},1362 {"O036", "I168 Switch", "I168"},1363 {"O037", "I169 Switch", "I169"},1364 1365 {"O038", "I022 Switch", "I022"},1366 {"O039", "I023 Switch", "I023"},1367 {"O182", "I024 Switch", "I024"},1368 {"O183", "I025 Switch", "I025"},1369 1370 {"O040", "I022 Switch", "I022"},1371 {"O041", "I023 Switch", "I023"},1372 {"O042", "I024 Switch", "I024"},1373 {"O043", "I025 Switch", "I025"},1374 {"O044", "I026 Switch", "I026"},1375 {"O045", "I027 Switch", "I027"},1376 {"O046", "I028 Switch", "I028"},1377 {"O047", "I029 Switch", "I029"},1378 1379 {"O040", "I002 Switch", "I002"},1380 {"O041", "I003 Switch", "I003"},1381 {"O002", "I012 Switch", "I012"},1382 {"O003", "I013 Switch", "I013"},1383 {"O004", "I014 Switch", "I014"},1384 {"O005", "I015 Switch", "I015"},1385 {"O006", "I016 Switch", "I016"},1386 {"O007", "I017 Switch", "I017"},1387 {"O008", "I018 Switch", "I018"},1388 {"O009", "I019 Switch", "I019"},1389 1390 {"O040", "I012 Switch", "I012"},1391 {"O041", "I013 Switch", "I013"},1392 {"O042", "I014 Switch", "I014"},1393 {"O043", "I015 Switch", "I015"},1394 {"O044", "I016 Switch", "I016"},1395 {"O045", "I017 Switch", "I017"},1396 {"O046", "I018 Switch", "I018"},1397 {"O047", "I019 Switch", "I019"},1398 1399 {"O002", "I072 Switch", "I072"},1400 {"O003", "I073 Switch", "I073"},1401 {"O004", "I074 Switch", "I074"},1402 {"O005", "I075 Switch", "I075"},1403 {"O006", "I076 Switch", "I076"},1404 {"O007", "I077 Switch", "I077"},1405 {"O008", "I078 Switch", "I078"},1406 {"O009", "I079 Switch", "I079"},1407 1408 {"O010", "I072 Switch", "I072"},1409 {"O011", "I073 Switch", "I073"},1410 {"O012", "I074 Switch", "I074"},1411 {"O013", "I075 Switch", "I075"},1412 {"O014", "I076 Switch", "I076"},1413 {"O015", "I077 Switch", "I077"},1414 {"O016", "I078 Switch", "I078"},1415 {"O017", "I079 Switch", "I079"},1416 {"O018", "I080 Switch", "I080"},1417 {"O019", "I081 Switch", "I081"},1418 {"O020", "I082 Switch", "I082"},1419 {"O021", "I083 Switch", "I083"},1420 {"O022", "I084 Switch", "I084"},1421 {"O023", "I085 Switch", "I085"},1422 {"O024", "I086 Switch", "I086"},1423 {"O025", "I087 Switch", "I087"},1424 {"O026", "I088 Switch", "I088"},1425 {"O027", "I089 Switch", "I089"},1426 {"O028", "I090 Switch", "I090"},1427 {"O029", "I091 Switch", "I091"},1428 {"O030", "I092 Switch", "I092"},1429 {"O031", "I093 Switch", "I093"},1430 {"O032", "I094 Switch", "I094"},1431 {"O033", "I095 Switch", "I095"},1432 1433 {"O002", "I168 Switch", "I168"},1434 {"O003", "I169 Switch", "I169"},1435 {"O004", "I170 Switch", "I170"},1436 {"O005", "I171 Switch", "I171"},1437 1438 {"O034", "I168 Switch", "I168"},1439 {"O035", "I168 Switch", "I168"},1440 {"O035", "I169 Switch", "I169"},1441 1442 {"O034", "I170 Switch", "I170"},1443 {"O035", "I170 Switch", "I170"},1444 {"O035", "I171 Switch", "I171"},1445 1446 {"O040", "I168 Switch", "I168"},1447 {"O041", "I169 Switch", "I169"},1448 {"O042", "I170 Switch", "I170"},1449 {"O043", "I171 Switch", "I171"},1450};1451 1452static const char * const mt8195_afe_1x_en_sel_text[] = {1453 "a1sys_a2sys", "a3sys", "a4sys",1454};1455 1456static const unsigned int mt8195_afe_1x_en_sel_values[] = {1457 0, 1, 2,1458};1459 1460static int mt8195_memif_1x_en_sel_put(struct snd_kcontrol *kcontrol,1461 struct snd_ctl_elem_value *ucontrol)1462{1463 struct snd_soc_component *component =1464 snd_soc_kcontrol_component(kcontrol);1465 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(component);1466 struct mt8195_afe_private *afe_priv = afe->platform_priv;1467 struct mtk_dai_memif_priv *memif_priv;1468 unsigned int dai_id = kcontrol->id.device;1469 long val = ucontrol->value.integer.value[0];1470 int ret = 0;1471 1472 memif_priv = afe_priv->dai_priv[dai_id];1473 1474 if (val == memif_priv->asys_timing_sel)1475 return 0;1476 1477 ret = snd_soc_put_enum_double(kcontrol, ucontrol);1478 1479 memif_priv->asys_timing_sel = val;1480 1481 return ret;1482}1483 1484static int mt8195_asys_irq_1x_en_sel_put(struct snd_kcontrol *kcontrol,1485 struct snd_ctl_elem_value *ucontrol)1486{1487 struct snd_soc_component *component =1488 snd_soc_kcontrol_component(kcontrol);1489 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(component);1490 struct mt8195_afe_private *afe_priv = afe->platform_priv;1491 unsigned int id = kcontrol->id.device;1492 long val = ucontrol->value.integer.value[0];1493 int ret = 0;1494 1495 if (val == afe_priv->irq_priv[id].asys_timing_sel)1496 return 0;1497 1498 ret = snd_soc_put_enum_double(kcontrol, ucontrol);1499 1500 afe_priv->irq_priv[id].asys_timing_sel = val;1501 1502 return ret;1503}1504 1505static SOC_VALUE_ENUM_SINGLE_DECL(dl2_1x_en_sel_enum,1506 A3_A4_TIMING_SEL1, 18, 0x3,1507 mt8195_afe_1x_en_sel_text,1508 mt8195_afe_1x_en_sel_values);1509static SOC_VALUE_ENUM_SINGLE_DECL(dl3_1x_en_sel_enum,1510 A3_A4_TIMING_SEL1, 20, 0x3,1511 mt8195_afe_1x_en_sel_text,1512 mt8195_afe_1x_en_sel_values);1513static SOC_VALUE_ENUM_SINGLE_DECL(dl6_1x_en_sel_enum,1514 A3_A4_TIMING_SEL1, 22, 0x3,1515 mt8195_afe_1x_en_sel_text,1516 mt8195_afe_1x_en_sel_values);1517static SOC_VALUE_ENUM_SINGLE_DECL(dl7_1x_en_sel_enum,1518 A3_A4_TIMING_SEL1, 24, 0x3,1519 mt8195_afe_1x_en_sel_text,1520 mt8195_afe_1x_en_sel_values);1521static SOC_VALUE_ENUM_SINGLE_DECL(dl8_1x_en_sel_enum,1522 A3_A4_TIMING_SEL1, 26, 0x3,1523 mt8195_afe_1x_en_sel_text,1524 mt8195_afe_1x_en_sel_values);1525static SOC_VALUE_ENUM_SINGLE_DECL(dl10_1x_en_sel_enum,1526 A3_A4_TIMING_SEL1, 28, 0x3,1527 mt8195_afe_1x_en_sel_text,1528 mt8195_afe_1x_en_sel_values);1529static SOC_VALUE_ENUM_SINGLE_DECL(dl11_1x_en_sel_enum,1530 A3_A4_TIMING_SEL1, 30, 0x3,1531 mt8195_afe_1x_en_sel_text,1532 mt8195_afe_1x_en_sel_values);1533static SOC_VALUE_ENUM_SINGLE_DECL(ul1_1x_en_sel_enum,1534 A3_A4_TIMING_SEL1, 0, 0x3,1535 mt8195_afe_1x_en_sel_text,1536 mt8195_afe_1x_en_sel_values);1537static SOC_VALUE_ENUM_SINGLE_DECL(ul2_1x_en_sel_enum,1538 A3_A4_TIMING_SEL1, 2, 0x3,1539 mt8195_afe_1x_en_sel_text,1540 mt8195_afe_1x_en_sel_values);1541static SOC_VALUE_ENUM_SINGLE_DECL(ul3_1x_en_sel_enum,1542 A3_A4_TIMING_SEL1, 4, 0x3,1543 mt8195_afe_1x_en_sel_text,1544 mt8195_afe_1x_en_sel_values);1545static SOC_VALUE_ENUM_SINGLE_DECL(ul4_1x_en_sel_enum,1546 A3_A4_TIMING_SEL1, 6, 0x3,1547 mt8195_afe_1x_en_sel_text,1548 mt8195_afe_1x_en_sel_values);1549static SOC_VALUE_ENUM_SINGLE_DECL(ul5_1x_en_sel_enum,1550 A3_A4_TIMING_SEL1, 8, 0x3,1551 mt8195_afe_1x_en_sel_text,1552 mt8195_afe_1x_en_sel_values);1553static SOC_VALUE_ENUM_SINGLE_DECL(ul6_1x_en_sel_enum,1554 A3_A4_TIMING_SEL1, 10, 0x3,1555 mt8195_afe_1x_en_sel_text,1556 mt8195_afe_1x_en_sel_values);1557static SOC_VALUE_ENUM_SINGLE_DECL(ul8_1x_en_sel_enum,1558 A3_A4_TIMING_SEL1, 12, 0x3,1559 mt8195_afe_1x_en_sel_text,1560 mt8195_afe_1x_en_sel_values);1561static SOC_VALUE_ENUM_SINGLE_DECL(ul9_1x_en_sel_enum,1562 A3_A4_TIMING_SEL1, 14, 0x3,1563 mt8195_afe_1x_en_sel_text,1564 mt8195_afe_1x_en_sel_values);1565static SOC_VALUE_ENUM_SINGLE_DECL(ul10_1x_en_sel_enum,1566 A3_A4_TIMING_SEL1, 16, 0x3,1567 mt8195_afe_1x_en_sel_text,1568 mt8195_afe_1x_en_sel_values);1569 1570static SOC_VALUE_ENUM_SINGLE_DECL(asys_irq1_1x_en_sel_enum,1571 A3_A4_TIMING_SEL6, 0, 0x3,1572 mt8195_afe_1x_en_sel_text,1573 mt8195_afe_1x_en_sel_values);1574static SOC_VALUE_ENUM_SINGLE_DECL(asys_irq2_1x_en_sel_enum,1575 A3_A4_TIMING_SEL6, 2, 0x3,1576 mt8195_afe_1x_en_sel_text,1577 mt8195_afe_1x_en_sel_values);1578static SOC_VALUE_ENUM_SINGLE_DECL(asys_irq3_1x_en_sel_enum,1579 A3_A4_TIMING_SEL6, 4, 0x3,1580 mt8195_afe_1x_en_sel_text,1581 mt8195_afe_1x_en_sel_values);1582static SOC_VALUE_ENUM_SINGLE_DECL(asys_irq4_1x_en_sel_enum,1583 A3_A4_TIMING_SEL6, 6, 0x3,1584 mt8195_afe_1x_en_sel_text,1585 mt8195_afe_1x_en_sel_values);1586static SOC_VALUE_ENUM_SINGLE_DECL(asys_irq5_1x_en_sel_enum,1587 A3_A4_TIMING_SEL6, 8, 0x3,1588 mt8195_afe_1x_en_sel_text,1589 mt8195_afe_1x_en_sel_values);1590static SOC_VALUE_ENUM_SINGLE_DECL(asys_irq6_1x_en_sel_enum,1591 A3_A4_TIMING_SEL6, 10, 0x3,1592 mt8195_afe_1x_en_sel_text,1593 mt8195_afe_1x_en_sel_values);1594static SOC_VALUE_ENUM_SINGLE_DECL(asys_irq7_1x_en_sel_enum,1595 A3_A4_TIMING_SEL6, 12, 0x3,1596 mt8195_afe_1x_en_sel_text,1597 mt8195_afe_1x_en_sel_values);1598static SOC_VALUE_ENUM_SINGLE_DECL(asys_irq8_1x_en_sel_enum,1599 A3_A4_TIMING_SEL6, 14, 0x3,1600 mt8195_afe_1x_en_sel_text,1601 mt8195_afe_1x_en_sel_values);1602static SOC_VALUE_ENUM_SINGLE_DECL(asys_irq9_1x_en_sel_enum,1603 A3_A4_TIMING_SEL6, 16, 0x3,1604 mt8195_afe_1x_en_sel_text,1605 mt8195_afe_1x_en_sel_values);1606static SOC_VALUE_ENUM_SINGLE_DECL(asys_irq10_1x_en_sel_enum,1607 A3_A4_TIMING_SEL6, 18, 0x3,1608 mt8195_afe_1x_en_sel_text,1609 mt8195_afe_1x_en_sel_values);1610static SOC_VALUE_ENUM_SINGLE_DECL(asys_irq11_1x_en_sel_enum,1611 A3_A4_TIMING_SEL6, 20, 0x3,1612 mt8195_afe_1x_en_sel_text,1613 mt8195_afe_1x_en_sel_values);1614static SOC_VALUE_ENUM_SINGLE_DECL(asys_irq12_1x_en_sel_enum,1615 A3_A4_TIMING_SEL6, 22, 0x3,1616 mt8195_afe_1x_en_sel_text,1617 mt8195_afe_1x_en_sel_values);1618static SOC_VALUE_ENUM_SINGLE_DECL(asys_irq13_1x_en_sel_enum,1619 A3_A4_TIMING_SEL6, 24, 0x3,1620 mt8195_afe_1x_en_sel_text,1621 mt8195_afe_1x_en_sel_values);1622static SOC_VALUE_ENUM_SINGLE_DECL(asys_irq14_1x_en_sel_enum,1623 A3_A4_TIMING_SEL6, 26, 0x3,1624 mt8195_afe_1x_en_sel_text,1625 mt8195_afe_1x_en_sel_values);1626static SOC_VALUE_ENUM_SINGLE_DECL(asys_irq15_1x_en_sel_enum,1627 A3_A4_TIMING_SEL6, 28, 0x3,1628 mt8195_afe_1x_en_sel_text,1629 mt8195_afe_1x_en_sel_values);1630static SOC_VALUE_ENUM_SINGLE_DECL(asys_irq16_1x_en_sel_enum,1631 A3_A4_TIMING_SEL6, 30, 0x3,1632 mt8195_afe_1x_en_sel_text,1633 mt8195_afe_1x_en_sel_values);1634 1635static const struct snd_kcontrol_new mt8195_memif_controls[] = {1636 MT8195_SOC_ENUM_EXT("dl2_1x_en_sel",1637 dl2_1x_en_sel_enum,1638 snd_soc_get_enum_double,1639 mt8195_memif_1x_en_sel_put,1640 MT8195_AFE_MEMIF_DL2),1641 MT8195_SOC_ENUM_EXT("dl3_1x_en_sel",1642 dl3_1x_en_sel_enum,1643 snd_soc_get_enum_double,1644 mt8195_memif_1x_en_sel_put,1645 MT8195_AFE_MEMIF_DL3),1646 MT8195_SOC_ENUM_EXT("dl6_1x_en_sel",1647 dl6_1x_en_sel_enum,1648 snd_soc_get_enum_double,1649 mt8195_memif_1x_en_sel_put,1650 MT8195_AFE_MEMIF_DL6),1651 MT8195_SOC_ENUM_EXT("dl7_1x_en_sel",1652 dl7_1x_en_sel_enum,1653 snd_soc_get_enum_double,1654 mt8195_memif_1x_en_sel_put,1655 MT8195_AFE_MEMIF_DL7),1656 MT8195_SOC_ENUM_EXT("dl8_1x_en_sel",1657 dl8_1x_en_sel_enum,1658 snd_soc_get_enum_double,1659 mt8195_memif_1x_en_sel_put,1660 MT8195_AFE_MEMIF_DL8),1661 MT8195_SOC_ENUM_EXT("dl10_1x_en_sel",1662 dl10_1x_en_sel_enum,1663 snd_soc_get_enum_double,1664 mt8195_memif_1x_en_sel_put,1665 MT8195_AFE_MEMIF_DL10),1666 MT8195_SOC_ENUM_EXT("dl11_1x_en_sel",1667 dl11_1x_en_sel_enum,1668 snd_soc_get_enum_double,1669 mt8195_memif_1x_en_sel_put,1670 MT8195_AFE_MEMIF_DL11),1671 MT8195_SOC_ENUM_EXT("ul1_1x_en_sel",1672 ul1_1x_en_sel_enum,1673 snd_soc_get_enum_double,1674 mt8195_memif_1x_en_sel_put,1675 MT8195_AFE_MEMIF_UL1),1676 MT8195_SOC_ENUM_EXT("ul2_1x_en_sel",1677 ul2_1x_en_sel_enum,1678 snd_soc_get_enum_double,1679 mt8195_memif_1x_en_sel_put,1680 MT8195_AFE_MEMIF_UL2),1681 MT8195_SOC_ENUM_EXT("ul3_1x_en_sel",1682 ul3_1x_en_sel_enum,1683 snd_soc_get_enum_double,1684 mt8195_memif_1x_en_sel_put,1685 MT8195_AFE_MEMIF_UL3),1686 MT8195_SOC_ENUM_EXT("ul4_1x_en_sel",1687 ul4_1x_en_sel_enum,1688 snd_soc_get_enum_double,1689 mt8195_memif_1x_en_sel_put,1690 MT8195_AFE_MEMIF_UL4),1691 MT8195_SOC_ENUM_EXT("ul5_1x_en_sel",1692 ul5_1x_en_sel_enum,1693 snd_soc_get_enum_double,1694 mt8195_memif_1x_en_sel_put,1695 MT8195_AFE_MEMIF_UL5),1696 MT8195_SOC_ENUM_EXT("ul6_1x_en_sel",1697 ul6_1x_en_sel_enum,1698 snd_soc_get_enum_double,1699 mt8195_memif_1x_en_sel_put,1700 MT8195_AFE_MEMIF_UL6),1701 MT8195_SOC_ENUM_EXT("ul8_1x_en_sel",1702 ul8_1x_en_sel_enum,1703 snd_soc_get_enum_double,1704 mt8195_memif_1x_en_sel_put,1705 MT8195_AFE_MEMIF_UL8),1706 MT8195_SOC_ENUM_EXT("ul9_1x_en_sel",1707 ul9_1x_en_sel_enum,1708 snd_soc_get_enum_double,1709 mt8195_memif_1x_en_sel_put,1710 MT8195_AFE_MEMIF_UL9),1711 MT8195_SOC_ENUM_EXT("ul10_1x_en_sel",1712 ul10_1x_en_sel_enum,1713 snd_soc_get_enum_double,1714 mt8195_memif_1x_en_sel_put,1715 MT8195_AFE_MEMIF_UL10),1716 MT8195_SOC_ENUM_EXT("asys_irq1_1x_en_sel",1717 asys_irq1_1x_en_sel_enum,1718 snd_soc_get_enum_double,1719 mt8195_asys_irq_1x_en_sel_put,1720 MT8195_AFE_IRQ_13),1721 MT8195_SOC_ENUM_EXT("asys_irq2_1x_en_sel",1722 asys_irq2_1x_en_sel_enum,1723 snd_soc_get_enum_double,1724 mt8195_asys_irq_1x_en_sel_put,1725 MT8195_AFE_IRQ_14),1726 MT8195_SOC_ENUM_EXT("asys_irq3_1x_en_sel",1727 asys_irq3_1x_en_sel_enum,1728 snd_soc_get_enum_double,1729 mt8195_asys_irq_1x_en_sel_put,1730 MT8195_AFE_IRQ_15),1731 MT8195_SOC_ENUM_EXT("asys_irq4_1x_en_sel",1732 asys_irq4_1x_en_sel_enum,1733 snd_soc_get_enum_double,1734 mt8195_asys_irq_1x_en_sel_put,1735 MT8195_AFE_IRQ_16),1736 MT8195_SOC_ENUM_EXT("asys_irq5_1x_en_sel",1737 asys_irq5_1x_en_sel_enum,1738 snd_soc_get_enum_double,1739 mt8195_asys_irq_1x_en_sel_put,1740 MT8195_AFE_IRQ_17),1741 MT8195_SOC_ENUM_EXT("asys_irq6_1x_en_sel",1742 asys_irq6_1x_en_sel_enum,1743 snd_soc_get_enum_double,1744 mt8195_asys_irq_1x_en_sel_put,1745 MT8195_AFE_IRQ_18),1746 MT8195_SOC_ENUM_EXT("asys_irq7_1x_en_sel",1747 asys_irq7_1x_en_sel_enum,1748 snd_soc_get_enum_double,1749 mt8195_asys_irq_1x_en_sel_put,1750 MT8195_AFE_IRQ_19),1751 MT8195_SOC_ENUM_EXT("asys_irq8_1x_en_sel",1752 asys_irq8_1x_en_sel_enum,1753 snd_soc_get_enum_double,1754 mt8195_asys_irq_1x_en_sel_put,1755 MT8195_AFE_IRQ_20),1756 MT8195_SOC_ENUM_EXT("asys_irq9_1x_en_sel",1757 asys_irq9_1x_en_sel_enum,1758 snd_soc_get_enum_double,1759 mt8195_asys_irq_1x_en_sel_put,1760 MT8195_AFE_IRQ_21),1761 MT8195_SOC_ENUM_EXT("asys_irq10_1x_en_sel",1762 asys_irq10_1x_en_sel_enum,1763 snd_soc_get_enum_double,1764 mt8195_asys_irq_1x_en_sel_put,1765 MT8195_AFE_IRQ_22),1766 MT8195_SOC_ENUM_EXT("asys_irq11_1x_en_sel",1767 asys_irq11_1x_en_sel_enum,1768 snd_soc_get_enum_double,1769 mt8195_asys_irq_1x_en_sel_put,1770 MT8195_AFE_IRQ_23),1771 MT8195_SOC_ENUM_EXT("asys_irq12_1x_en_sel",1772 asys_irq12_1x_en_sel_enum,1773 snd_soc_get_enum_double,1774 mt8195_asys_irq_1x_en_sel_put,1775 MT8195_AFE_IRQ_24),1776 MT8195_SOC_ENUM_EXT("asys_irq13_1x_en_sel",1777 asys_irq13_1x_en_sel_enum,1778 snd_soc_get_enum_double,1779 mt8195_asys_irq_1x_en_sel_put,1780 MT8195_AFE_IRQ_25),1781 MT8195_SOC_ENUM_EXT("asys_irq14_1x_en_sel",1782 asys_irq14_1x_en_sel_enum,1783 snd_soc_get_enum_double,1784 mt8195_asys_irq_1x_en_sel_put,1785 MT8195_AFE_IRQ_26),1786 MT8195_SOC_ENUM_EXT("asys_irq15_1x_en_sel",1787 asys_irq15_1x_en_sel_enum,1788 snd_soc_get_enum_double,1789 mt8195_asys_irq_1x_en_sel_put,1790 MT8195_AFE_IRQ_27),1791 MT8195_SOC_ENUM_EXT("asys_irq16_1x_en_sel",1792 asys_irq16_1x_en_sel_enum,1793 snd_soc_get_enum_double,1794 mt8195_asys_irq_1x_en_sel_put,1795 MT8195_AFE_IRQ_28),1796};1797 1798static const struct mtk_base_memif_data memif_data[MT8195_AFE_MEMIF_NUM] = {1799 [MT8195_AFE_MEMIF_DL2] = {1800 .name = "DL2",1801 .id = MT8195_AFE_MEMIF_DL2,1802 .reg_ofs_base = AFE_DL2_BASE,1803 .reg_ofs_cur = AFE_DL2_CUR,1804 .reg_ofs_end = AFE_DL2_END,1805 .fs_reg = AFE_MEMIF_AGENT_FS_CON0,1806 .fs_shift = 10,1807 .fs_maskbit = 0x1f,1808 .mono_reg = -1,1809 .mono_shift = 0,1810 .int_odd_flag_reg = -1,1811 .int_odd_flag_shift = 0,1812 .enable_reg = AFE_DAC_CON0,1813 .enable_shift = 18,1814 .hd_reg = AFE_DL2_CON0,1815 .hd_shift = 5,1816 .agent_disable_reg = AUDIO_TOP_CON5,1817 .agent_disable_shift = 18,1818 .ch_num_reg = AFE_DL2_CON0,1819 .ch_num_shift = 0,1820 .ch_num_maskbit = 0x1f,1821 .msb_reg = AFE_NORMAL_BASE_ADR_MSB,1822 .msb_shift = 18,1823 .msb_end_reg = AFE_NORMAL_END_ADR_MSB,1824 .msb_end_shift = 18,1825 },1826 [MT8195_AFE_MEMIF_DL3] = {1827 .name = "DL3",1828 .id = MT8195_AFE_MEMIF_DL3,1829 .reg_ofs_base = AFE_DL3_BASE,1830 .reg_ofs_cur = AFE_DL3_CUR,1831 .reg_ofs_end = AFE_DL3_END,1832 .fs_reg = AFE_MEMIF_AGENT_FS_CON0,1833 .fs_shift = 15,1834 .fs_maskbit = 0x1f,1835 .mono_reg = -1,1836 .mono_shift = 0,1837 .int_odd_flag_reg = -1,1838 .int_odd_flag_shift = 0,1839 .enable_reg = AFE_DAC_CON0,1840 .enable_shift = 19,1841 .hd_reg = AFE_DL3_CON0,1842 .hd_shift = 5,1843 .agent_disable_reg = AUDIO_TOP_CON5,1844 .agent_disable_shift = 19,1845 .ch_num_reg = AFE_DL3_CON0,1846 .ch_num_shift = 0,1847 .ch_num_maskbit = 0x1f,1848 .msb_reg = AFE_NORMAL_BASE_ADR_MSB,1849 .msb_shift = 19,1850 .msb_end_reg = AFE_NORMAL_END_ADR_MSB,1851 .msb_end_shift = 19,1852 },1853 [MT8195_AFE_MEMIF_DL6] = {1854 .name = "DL6",1855 .id = MT8195_AFE_MEMIF_DL6,1856 .reg_ofs_base = AFE_DL6_BASE,1857 .reg_ofs_cur = AFE_DL6_CUR,1858 .reg_ofs_end = AFE_DL6_END,1859 .fs_reg = AFE_MEMIF_AGENT_FS_CON1,1860 .fs_shift = 0,1861 .fs_maskbit = 0x1f,1862 .mono_reg = -1,1863 .mono_shift = 0,1864 .int_odd_flag_reg = -1,1865 .int_odd_flag_shift = 0,1866 .enable_reg = AFE_DAC_CON0,1867 .enable_shift = 22,1868 .hd_reg = AFE_DL6_CON0,1869 .hd_shift = 5,1870 .agent_disable_reg = AUDIO_TOP_CON5,1871 .agent_disable_shift = 22,1872 .ch_num_reg = AFE_DL6_CON0,1873 .ch_num_shift = 0,1874 .ch_num_maskbit = 0x1f,1875 .msb_reg = AFE_NORMAL_BASE_ADR_MSB,1876 .msb_shift = 22,1877 .msb_end_reg = AFE_NORMAL_END_ADR_MSB,1878 .msb_end_shift = 22,1879 },1880 [MT8195_AFE_MEMIF_DL7] = {1881 .name = "DL7",1882 .id = MT8195_AFE_MEMIF_DL7,1883 .reg_ofs_base = AFE_DL7_BASE,1884 .reg_ofs_cur = AFE_DL7_CUR,1885 .reg_ofs_end = AFE_DL7_END,1886 .fs_reg = -1,1887 .fs_shift = 0,1888 .fs_maskbit = 0,1889 .mono_reg = -1,1890 .mono_shift = 0,1891 .int_odd_flag_reg = -1,1892 .int_odd_flag_shift = 0,1893 .enable_reg = AFE_DAC_CON0,1894 .enable_shift = 23,1895 .hd_reg = AFE_DL7_CON0,1896 .hd_shift = 5,1897 .agent_disable_reg = AUDIO_TOP_CON5,1898 .agent_disable_shift = 23,1899 .ch_num_reg = AFE_DL7_CON0,1900 .ch_num_shift = 0,1901 .ch_num_maskbit = 0x1f,1902 .msb_reg = AFE_NORMAL_BASE_ADR_MSB,1903 .msb_shift = 23,1904 .msb_end_reg = AFE_NORMAL_END_ADR_MSB,1905 .msb_end_shift = 23,1906 },1907 [MT8195_AFE_MEMIF_DL8] = {1908 .name = "DL8",1909 .id = MT8195_AFE_MEMIF_DL8,1910 .reg_ofs_base = AFE_DL8_BASE,1911 .reg_ofs_cur = AFE_DL8_CUR,1912 .reg_ofs_end = AFE_DL8_END,1913 .fs_reg = AFE_MEMIF_AGENT_FS_CON1,1914 .fs_shift = 10,1915 .fs_maskbit = 0x1f,1916 .mono_reg = -1,1917 .mono_shift = 0,1918 .int_odd_flag_reg = -1,1919 .int_odd_flag_shift = 0,1920 .enable_reg = AFE_DAC_CON0,1921 .enable_shift = 24,1922 .hd_reg = AFE_DL8_CON0,1923 .hd_shift = 6,1924 .agent_disable_reg = -1,1925 .agent_disable_shift = 0,1926 .ch_num_reg = AFE_DL8_CON0,1927 .ch_num_shift = 0,1928 .ch_num_maskbit = 0x3f,1929 .msb_reg = AFE_NORMAL_BASE_ADR_MSB,1930 .msb_shift = 24,1931 .msb_end_reg = AFE_NORMAL_END_ADR_MSB,1932 .msb_end_shift = 24,1933 },1934 [MT8195_AFE_MEMIF_DL10] = {1935 .name = "DL10",1936 .id = MT8195_AFE_MEMIF_DL10,1937 .reg_ofs_base = AFE_DL10_BASE,1938 .reg_ofs_cur = AFE_DL10_CUR,1939 .reg_ofs_end = AFE_DL10_END,1940 .fs_reg = AFE_MEMIF_AGENT_FS_CON1,1941 .fs_shift = 20,1942 .fs_maskbit = 0x1f,1943 .mono_reg = -1,1944 .mono_shift = 0,1945 .int_odd_flag_reg = -1,1946 .int_odd_flag_shift = 0,1947 .enable_reg = AFE_DAC_CON0,1948 .enable_shift = 26,1949 .hd_reg = AFE_DL10_CON0,1950 .hd_shift = 5,1951 .agent_disable_reg = -1,1952 .agent_disable_shift = 0,1953 .ch_num_reg = AFE_DL10_CON0,1954 .ch_num_shift = 0,1955 .ch_num_maskbit = 0x1f,1956 .msb_reg = AFE_NORMAL_BASE_ADR_MSB,1957 .msb_shift = 26,1958 .msb_end_reg = AFE_NORMAL_END_ADR_MSB,1959 .msb_end_shift = 26,1960 },1961 [MT8195_AFE_MEMIF_DL11] = {1962 .name = "DL11",1963 .id = MT8195_AFE_MEMIF_DL11,1964 .reg_ofs_base = AFE_DL11_BASE,1965 .reg_ofs_cur = AFE_DL11_CUR,1966 .reg_ofs_end = AFE_DL11_END,1967 .fs_reg = AFE_MEMIF_AGENT_FS_CON1,1968 .fs_shift = 25,1969 .fs_maskbit = 0x1f,1970 .mono_reg = -1,1971 .mono_shift = 0,1972 .int_odd_flag_reg = -1,1973 .int_odd_flag_shift = 0,1974 .enable_reg = AFE_DAC_CON0,1975 .enable_shift = 27,1976 .hd_reg = AFE_DL11_CON0,1977 .hd_shift = 7,1978 .agent_disable_reg = AUDIO_TOP_CON5,1979 .agent_disable_shift = 27,1980 .ch_num_reg = AFE_DL11_CON0,1981 .ch_num_shift = 0,1982 .ch_num_maskbit = 0x7f,1983 .msb_reg = AFE_NORMAL_BASE_ADR_MSB,1984 .msb_shift = 27,1985 .msb_end_reg = AFE_NORMAL_END_ADR_MSB,1986 .msb_end_shift = 27,1987 },1988 [MT8195_AFE_MEMIF_UL1] = {1989 .name = "UL1",1990 .id = MT8195_AFE_MEMIF_UL1,1991 .reg_ofs_base = AFE_UL1_BASE,1992 .reg_ofs_cur = AFE_UL1_CUR,1993 .reg_ofs_end = AFE_UL1_END,1994 .fs_reg = -1,1995 .fs_shift = 0,1996 .fs_maskbit = 0,1997 .mono_reg = AFE_UL1_CON0,1998 .mono_shift = 1,1999 .int_odd_flag_reg = AFE_UL1_CON0,2000 .int_odd_flag_shift = 0,2001 .enable_reg = AFE_DAC_CON0,2002 .enable_shift = 1,2003 .hd_reg = AFE_UL1_CON0,2004 .hd_shift = 5,2005 .agent_disable_reg = AUDIO_TOP_CON5,2006 .agent_disable_shift = 0,2007 .ch_num_reg = -1,2008 .ch_num_shift = 0,2009 .ch_num_maskbit = 0,2010 .msb_reg = AFE_NORMAL_BASE_ADR_MSB,2011 .msb_shift = 0,2012 .msb_end_reg = AFE_NORMAL_END_ADR_MSB,2013 .msb_end_shift = 0,2014 },2015 [MT8195_AFE_MEMIF_UL2] = {2016 .name = "UL2",2017 .id = MT8195_AFE_MEMIF_UL2,2018 .reg_ofs_base = AFE_UL2_BASE,2019 .reg_ofs_cur = AFE_UL2_CUR,2020 .reg_ofs_end = AFE_UL2_END,2021 .fs_reg = AFE_MEMIF_AGENT_FS_CON2,2022 .fs_shift = 5,2023 .fs_maskbit = 0x1f,2024 .mono_reg = AFE_UL2_CON0,2025 .mono_shift = 1,2026 .int_odd_flag_reg = AFE_UL2_CON0,2027 .int_odd_flag_shift = 0,2028 .enable_reg = AFE_DAC_CON0,2029 .enable_shift = 2,2030 .hd_reg = AFE_UL2_CON0,2031 .hd_shift = 5,2032 .agent_disable_reg = AUDIO_TOP_CON5,2033 .agent_disable_shift = 1,2034 .ch_num_reg = -1,2035 .ch_num_shift = 0,2036 .ch_num_maskbit = 0,2037 .msb_reg = AFE_NORMAL_BASE_ADR_MSB,2038 .msb_shift = 1,2039 .msb_end_reg = AFE_NORMAL_END_ADR_MSB,2040 .msb_end_shift = 1,2041 },2042 [MT8195_AFE_MEMIF_UL3] = {2043 .name = "UL3",2044 .id = MT8195_AFE_MEMIF_UL3,2045 .reg_ofs_base = AFE_UL3_BASE,2046 .reg_ofs_cur = AFE_UL3_CUR,2047 .reg_ofs_end = AFE_UL3_END,2048 .fs_reg = AFE_MEMIF_AGENT_FS_CON2,2049 .fs_shift = 10,2050 .fs_maskbit = 0x1f,2051 .mono_reg = AFE_UL3_CON0,2052 .mono_shift = 1,2053 .int_odd_flag_reg = AFE_UL3_CON0,2054 .int_odd_flag_shift = 0,2055 .enable_reg = AFE_DAC_CON0,2056 .enable_shift = 3,2057 .hd_reg = AFE_UL3_CON0,2058 .hd_shift = 5,2059 .agent_disable_reg = AUDIO_TOP_CON5,2060 .agent_disable_shift = 2,2061 .ch_num_reg = -1,2062 .ch_num_shift = 0,2063 .ch_num_maskbit = 0,2064 .msb_reg = AFE_NORMAL_BASE_ADR_MSB,2065 .msb_shift = 2,2066 .msb_end_reg = AFE_NORMAL_END_ADR_MSB,2067 .msb_end_shift = 2,2068 },2069 [MT8195_AFE_MEMIF_UL4] = {2070 .name = "UL4",2071 .id = MT8195_AFE_MEMIF_UL4,2072 .reg_ofs_base = AFE_UL4_BASE,2073 .reg_ofs_cur = AFE_UL4_CUR,2074 .reg_ofs_end = AFE_UL4_END,2075 .fs_reg = AFE_MEMIF_AGENT_FS_CON2,2076 .fs_shift = 15,2077 .fs_maskbit = 0x1f,2078 .mono_reg = AFE_UL4_CON0,2079 .mono_shift = 1,2080 .int_odd_flag_reg = AFE_UL4_CON0,2081 .int_odd_flag_shift = 0,2082 .enable_reg = AFE_DAC_CON0,2083 .enable_shift = 4,2084 .hd_reg = AFE_UL4_CON0,2085 .hd_shift = 5,2086 .agent_disable_reg = AUDIO_TOP_CON5,2087 .agent_disable_shift = 3,2088 .ch_num_reg = -1,2089 .ch_num_shift = 0,2090 .ch_num_maskbit = 0,2091 .msb_reg = AFE_NORMAL_BASE_ADR_MSB,2092 .msb_shift = 3,2093 .msb_end_reg = AFE_NORMAL_END_ADR_MSB,2094 .msb_end_shift = 3,2095 },2096 [MT8195_AFE_MEMIF_UL5] = {2097 .name = "UL5",2098 .id = MT8195_AFE_MEMIF_UL5,2099 .reg_ofs_base = AFE_UL5_BASE,2100 .reg_ofs_cur = AFE_UL5_CUR,2101 .reg_ofs_end = AFE_UL5_END,2102 .fs_reg = AFE_MEMIF_AGENT_FS_CON2,2103 .fs_shift = 20,2104 .fs_maskbit = 0x1f,2105 .mono_reg = AFE_UL5_CON0,2106 .mono_shift = 1,2107 .int_odd_flag_reg = AFE_UL5_CON0,2108 .int_odd_flag_shift = 0,2109 .enable_reg = AFE_DAC_CON0,2110 .enable_shift = 5,2111 .hd_reg = AFE_UL5_CON0,2112 .hd_shift = 5,2113 .agent_disable_reg = AUDIO_TOP_CON5,2114 .agent_disable_shift = 4,2115 .ch_num_reg = -1,2116 .ch_num_shift = 0,2117 .ch_num_maskbit = 0,2118 .msb_reg = AFE_NORMAL_BASE_ADR_MSB,2119 .msb_shift = 4,2120 .msb_end_reg = AFE_NORMAL_END_ADR_MSB,2121 .msb_end_shift = 4,2122 },2123 [MT8195_AFE_MEMIF_UL6] = {2124 .name = "UL6",2125 .id = MT8195_AFE_MEMIF_UL6,2126 .reg_ofs_base = AFE_UL6_BASE,2127 .reg_ofs_cur = AFE_UL6_CUR,2128 .reg_ofs_end = AFE_UL6_END,2129 .fs_reg = -1,2130 .fs_shift = 0,2131 .fs_maskbit = 0,2132 .mono_reg = AFE_UL6_CON0,2133 .mono_shift = 1,2134 .int_odd_flag_reg = AFE_UL6_CON0,2135 .int_odd_flag_shift = 0,2136 .enable_reg = AFE_DAC_CON0,2137 .enable_shift = 6,2138 .hd_reg = AFE_UL6_CON0,2139 .hd_shift = 5,2140 .agent_disable_reg = AUDIO_TOP_CON5,2141 .agent_disable_shift = 5,2142 .ch_num_reg = -1,2143 .ch_num_shift = 0,2144 .ch_num_maskbit = 0,2145 .msb_reg = AFE_NORMAL_BASE_ADR_MSB,2146 .msb_shift = 5,2147 .msb_end_reg = AFE_NORMAL_END_ADR_MSB,2148 .msb_end_shift = 5,2149 },2150 [MT8195_AFE_MEMIF_UL8] = {2151 .name = "UL8",2152 .id = MT8195_AFE_MEMIF_UL8,2153 .reg_ofs_base = AFE_UL8_BASE,2154 .reg_ofs_cur = AFE_UL8_CUR,2155 .reg_ofs_end = AFE_UL8_END,2156 .fs_reg = AFE_MEMIF_AGENT_FS_CON3,2157 .fs_shift = 5,2158 .fs_maskbit = 0x1f,2159 .mono_reg = AFE_UL8_CON0,2160 .mono_shift = 1,2161 .int_odd_flag_reg = AFE_UL8_CON0,2162 .int_odd_flag_shift = 0,2163 .enable_reg = AFE_DAC_CON0,2164 .enable_shift = 8,2165 .hd_reg = AFE_UL8_CON0,2166 .hd_shift = 5,2167 .agent_disable_reg = AUDIO_TOP_CON5,2168 .agent_disable_shift = 7,2169 .ch_num_reg = -1,2170 .ch_num_shift = 0,2171 .ch_num_maskbit = 0,2172 .msb_reg = AFE_NORMAL_BASE_ADR_MSB,2173 .msb_shift = 7,2174 .msb_end_reg = AFE_NORMAL_END_ADR_MSB,2175 .msb_end_shift = 7,2176 },2177 [MT8195_AFE_MEMIF_UL9] = {2178 .name = "UL9",2179 .id = MT8195_AFE_MEMIF_UL9,2180 .reg_ofs_base = AFE_UL9_BASE,2181 .reg_ofs_cur = AFE_UL9_CUR,2182 .reg_ofs_end = AFE_UL9_END,2183 .fs_reg = AFE_MEMIF_AGENT_FS_CON3,2184 .fs_shift = 10,2185 .fs_maskbit = 0x1f,2186 .mono_reg = AFE_UL9_CON0,2187 .mono_shift = 1,2188 .int_odd_flag_reg = AFE_UL9_CON0,2189 .int_odd_flag_shift = 0,2190 .enable_reg = AFE_DAC_CON0,2191 .enable_shift = 9,2192 .hd_reg = AFE_UL9_CON0,2193 .hd_shift = 5,2194 .agent_disable_reg = AUDIO_TOP_CON5,2195 .agent_disable_shift = 8,2196 .ch_num_reg = -1,2197 .ch_num_shift = 0,2198 .ch_num_maskbit = 0,2199 .msb_reg = AFE_NORMAL_BASE_ADR_MSB,2200 .msb_shift = 8,2201 .msb_end_reg = AFE_NORMAL_END_ADR_MSB,2202 .msb_end_shift = 8,2203 },2204 [MT8195_AFE_MEMIF_UL10] = {2205 .name = "UL10",2206 .id = MT8195_AFE_MEMIF_UL10,2207 .reg_ofs_base = AFE_UL10_BASE,2208 .reg_ofs_cur = AFE_UL10_CUR,2209 .reg_ofs_end = AFE_UL10_END,2210 .fs_reg = AFE_MEMIF_AGENT_FS_CON3,2211 .fs_shift = 15,2212 .fs_maskbit = 0x1f,2213 .mono_reg = AFE_UL10_CON0,2214 .mono_shift = 1,2215 .int_odd_flag_reg = AFE_UL10_CON0,2216 .int_odd_flag_shift = 0,2217 .enable_reg = AFE_DAC_CON0,2218 .enable_shift = 10,2219 .hd_reg = AFE_UL10_CON0,2220 .hd_shift = 5,2221 .agent_disable_reg = AUDIO_TOP_CON5,2222 .agent_disable_shift = 9,2223 .ch_num_reg = -1,2224 .ch_num_shift = 0,2225 .ch_num_maskbit = 0,2226 .msb_reg = AFE_NORMAL_BASE_ADR_MSB,2227 .msb_shift = 9,2228 .msb_end_reg = AFE_NORMAL_END_ADR_MSB,2229 .msb_end_shift = 9,2230 },2231};2232 2233static const struct mtk_base_irq_data irq_data_array[MT8195_AFE_IRQ_NUM] = {2234 [MT8195_AFE_IRQ_1] = {2235 .id = MT8195_AFE_IRQ_1,2236 .irq_cnt_reg = -1,2237 .irq_cnt_shift = 0,2238 .irq_cnt_maskbit = 0,2239 .irq_fs_reg = -1,2240 .irq_fs_shift = 0,2241 .irq_fs_maskbit = 0,2242 .irq_en_reg = AFE_IRQ1_CON,2243 .irq_en_shift = 31,2244 .irq_clr_reg = AFE_IRQ_MCU_CLR,2245 .irq_clr_shift = 0,2246 .irq_status_shift = 16,2247 },2248 [MT8195_AFE_IRQ_2] = {2249 .id = MT8195_AFE_IRQ_2,2250 .irq_cnt_reg = -1,2251 .irq_cnt_shift = 0,2252 .irq_cnt_maskbit = 0,2253 .irq_fs_reg = -1,2254 .irq_fs_shift = 0,2255 .irq_fs_maskbit = 0,2256 .irq_en_reg = AFE_IRQ2_CON,2257 .irq_en_shift = 31,2258 .irq_clr_reg = AFE_IRQ_MCU_CLR,2259 .irq_clr_shift = 1,2260 .irq_status_shift = 17,2261 },2262 [MT8195_AFE_IRQ_3] = {2263 .id = MT8195_AFE_IRQ_3,2264 .irq_cnt_reg = AFE_IRQ3_CON,2265 .irq_cnt_shift = 0,2266 .irq_cnt_maskbit = 0xffffff,2267 .irq_fs_reg = -1,2268 .irq_fs_shift = 0,2269 .irq_fs_maskbit = 0,2270 .irq_en_reg = AFE_IRQ3_CON,2271 .irq_en_shift = 31,2272 .irq_clr_reg = AFE_IRQ_MCU_CLR,2273 .irq_clr_shift = 2,2274 .irq_status_shift = 18,2275 },2276 [MT8195_AFE_IRQ_8] = {2277 .id = MT8195_AFE_IRQ_8,2278 .irq_cnt_reg = -1,2279 .irq_cnt_shift = 0,2280 .irq_cnt_maskbit = 0,2281 .irq_fs_reg = -1,2282 .irq_fs_shift = 0,2283 .irq_fs_maskbit = 0,2284 .irq_en_reg = AFE_IRQ8_CON,2285 .irq_en_shift = 31,2286 .irq_clr_reg = AFE_IRQ_MCU_CLR,2287 .irq_clr_shift = 7,2288 .irq_status_shift = 23,2289 },2290 [MT8195_AFE_IRQ_9] = {2291 .id = MT8195_AFE_IRQ_9,2292 .irq_cnt_reg = AFE_IRQ9_CON,2293 .irq_cnt_shift = 0,2294 .irq_cnt_maskbit = 0xffffff,2295 .irq_fs_reg = -1,2296 .irq_fs_shift = 0,2297 .irq_fs_maskbit = 0,2298 .irq_en_reg = AFE_IRQ9_CON,2299 .irq_en_shift = 31,2300 .irq_clr_reg = AFE_IRQ_MCU_CLR,2301 .irq_clr_shift = 8,2302 .irq_status_shift = 24,2303 },2304 [MT8195_AFE_IRQ_10] = {2305 .id = MT8195_AFE_IRQ_10,2306 .irq_cnt_reg = -1,2307 .irq_cnt_shift = 0,2308 .irq_cnt_maskbit = 0,2309 .irq_fs_reg = -1,2310 .irq_fs_shift = 0,2311 .irq_fs_maskbit = 0,2312 .irq_en_reg = AFE_IRQ10_CON,2313 .irq_en_shift = 31,2314 .irq_clr_reg = AFE_IRQ_MCU_CLR,2315 .irq_clr_shift = 9,2316 .irq_status_shift = 25,2317 },2318 [MT8195_AFE_IRQ_13] = {2319 .id = MT8195_AFE_IRQ_13,2320 .irq_cnt_reg = ASYS_IRQ1_CON,2321 .irq_cnt_shift = 0,2322 .irq_cnt_maskbit = 0xffffff,2323 .irq_fs_reg = ASYS_IRQ1_CON,2324 .irq_fs_shift = 24,2325 .irq_fs_maskbit = 0x1ffff,2326 .irq_en_reg = ASYS_IRQ1_CON,2327 .irq_en_shift = 31,2328 .irq_clr_reg = ASYS_IRQ_CLR,2329 .irq_clr_shift = 0,2330 .irq_status_shift = 0,2331 },2332 [MT8195_AFE_IRQ_14] = {2333 .id = MT8195_AFE_IRQ_14,2334 .irq_cnt_reg = ASYS_IRQ2_CON,2335 .irq_cnt_shift = 0,2336 .irq_cnt_maskbit = 0xffffff,2337 .irq_fs_reg = ASYS_IRQ2_CON,2338 .irq_fs_shift = 24,2339 .irq_fs_maskbit = 0x1ffff,2340 .irq_en_reg = ASYS_IRQ2_CON,2341 .irq_en_shift = 31,2342 .irq_clr_reg = ASYS_IRQ_CLR,2343 .irq_clr_shift = 1,2344 .irq_status_shift = 1,2345 },2346 [MT8195_AFE_IRQ_15] = {2347 .id = MT8195_AFE_IRQ_15,2348 .irq_cnt_reg = ASYS_IRQ3_CON,2349 .irq_cnt_shift = 0,2350 .irq_cnt_maskbit = 0xffffff,2351 .irq_fs_reg = ASYS_IRQ3_CON,2352 .irq_fs_shift = 24,2353 .irq_fs_maskbit = 0x1ffff,2354 .irq_en_reg = ASYS_IRQ3_CON,2355 .irq_en_shift = 31,2356 .irq_clr_reg = ASYS_IRQ_CLR,2357 .irq_clr_shift = 2,2358 .irq_status_shift = 2,2359 },2360 [MT8195_AFE_IRQ_16] = {2361 .id = MT8195_AFE_IRQ_16,2362 .irq_cnt_reg = ASYS_IRQ4_CON,2363 .irq_cnt_shift = 0,2364 .irq_cnt_maskbit = 0xffffff,2365 .irq_fs_reg = ASYS_IRQ4_CON,2366 .irq_fs_shift = 24,2367 .irq_fs_maskbit = 0x1ffff,2368 .irq_en_reg = ASYS_IRQ4_CON,2369 .irq_en_shift = 31,2370 .irq_clr_reg = ASYS_IRQ_CLR,2371 .irq_clr_shift = 3,2372 .irq_status_shift = 3,2373 },2374 [MT8195_AFE_IRQ_17] = {2375 .id = MT8195_AFE_IRQ_17,2376 .irq_cnt_reg = ASYS_IRQ5_CON,2377 .irq_cnt_shift = 0,2378 .irq_cnt_maskbit = 0xffffff,2379 .irq_fs_reg = ASYS_IRQ5_CON,2380 .irq_fs_shift = 24,2381 .irq_fs_maskbit = 0x1ffff,2382 .irq_en_reg = ASYS_IRQ5_CON,2383 .irq_en_shift = 31,2384 .irq_clr_reg = ASYS_IRQ_CLR,2385 .irq_clr_shift = 4,2386 .irq_status_shift = 4,2387 },2388 [MT8195_AFE_IRQ_18] = {2389 .id = MT8195_AFE_IRQ_18,2390 .irq_cnt_reg = ASYS_IRQ6_CON,2391 .irq_cnt_shift = 0,2392 .irq_cnt_maskbit = 0xffffff,2393 .irq_fs_reg = ASYS_IRQ6_CON,2394 .irq_fs_shift = 24,2395 .irq_fs_maskbit = 0x1ffff,2396 .irq_en_reg = ASYS_IRQ6_CON,2397 .irq_en_shift = 31,2398 .irq_clr_reg = ASYS_IRQ_CLR,2399 .irq_clr_shift = 5,2400 .irq_status_shift = 5,2401 },2402 [MT8195_AFE_IRQ_19] = {2403 .id = MT8195_AFE_IRQ_19,2404 .irq_cnt_reg = ASYS_IRQ7_CON,2405 .irq_cnt_shift = 0,2406 .irq_cnt_maskbit = 0xffffff,2407 .irq_fs_reg = ASYS_IRQ7_CON,2408 .irq_fs_shift = 24,2409 .irq_fs_maskbit = 0x1ffff,2410 .irq_en_reg = ASYS_IRQ7_CON,2411 .irq_en_shift = 31,2412 .irq_clr_reg = ASYS_IRQ_CLR,2413 .irq_clr_shift = 6,2414 .irq_status_shift = 6,2415 },2416 [MT8195_AFE_IRQ_20] = {2417 .id = MT8195_AFE_IRQ_20,2418 .irq_cnt_reg = ASYS_IRQ8_CON,2419 .irq_cnt_shift = 0,2420 .irq_cnt_maskbit = 0xffffff,2421 .irq_fs_reg = ASYS_IRQ8_CON,2422 .irq_fs_shift = 24,2423 .irq_fs_maskbit = 0x1ffff,2424 .irq_en_reg = ASYS_IRQ8_CON,2425 .irq_en_shift = 31,2426 .irq_clr_reg = ASYS_IRQ_CLR,2427 .irq_clr_shift = 7,2428 .irq_status_shift = 7,2429 },2430 [MT8195_AFE_IRQ_21] = {2431 .id = MT8195_AFE_IRQ_21,2432 .irq_cnt_reg = ASYS_IRQ9_CON,2433 .irq_cnt_shift = 0,2434 .irq_cnt_maskbit = 0xffffff,2435 .irq_fs_reg = ASYS_IRQ9_CON,2436 .irq_fs_shift = 24,2437 .irq_fs_maskbit = 0x1ffff,2438 .irq_en_reg = ASYS_IRQ9_CON,2439 .irq_en_shift = 31,2440 .irq_clr_reg = ASYS_IRQ_CLR,2441 .irq_clr_shift = 8,2442 .irq_status_shift = 8,2443 },2444 [MT8195_AFE_IRQ_22] = {2445 .id = MT8195_AFE_IRQ_22,2446 .irq_cnt_reg = ASYS_IRQ10_CON,2447 .irq_cnt_shift = 0,2448 .irq_cnt_maskbit = 0xffffff,2449 .irq_fs_reg = ASYS_IRQ10_CON,2450 .irq_fs_shift = 24,2451 .irq_fs_maskbit = 0x1ffff,2452 .irq_en_reg = ASYS_IRQ10_CON,2453 .irq_en_shift = 31,2454 .irq_clr_reg = ASYS_IRQ_CLR,2455 .irq_clr_shift = 9,2456 .irq_status_shift = 9,2457 },2458 [MT8195_AFE_IRQ_23] = {2459 .id = MT8195_AFE_IRQ_23,2460 .irq_cnt_reg = ASYS_IRQ11_CON,2461 .irq_cnt_shift = 0,2462 .irq_cnt_maskbit = 0xffffff,2463 .irq_fs_reg = ASYS_IRQ11_CON,2464 .irq_fs_shift = 24,2465 .irq_fs_maskbit = 0x1ffff,2466 .irq_en_reg = ASYS_IRQ11_CON,2467 .irq_en_shift = 31,2468 .irq_clr_reg = ASYS_IRQ_CLR,2469 .irq_clr_shift = 10,2470 .irq_status_shift = 10,2471 },2472 [MT8195_AFE_IRQ_24] = {2473 .id = MT8195_AFE_IRQ_24,2474 .irq_cnt_reg = ASYS_IRQ12_CON,2475 .irq_cnt_shift = 0,2476 .irq_cnt_maskbit = 0xffffff,2477 .irq_fs_reg = ASYS_IRQ12_CON,2478 .irq_fs_shift = 24,2479 .irq_fs_maskbit = 0x1ffff,2480 .irq_en_reg = ASYS_IRQ12_CON,2481 .irq_en_shift = 31,2482 .irq_clr_reg = ASYS_IRQ_CLR,2483 .irq_clr_shift = 11,2484 .irq_status_shift = 11,2485 },2486 [MT8195_AFE_IRQ_25] = {2487 .id = MT8195_AFE_IRQ_25,2488 .irq_cnt_reg = ASYS_IRQ13_CON,2489 .irq_cnt_shift = 0,2490 .irq_cnt_maskbit = 0xffffff,2491 .irq_fs_reg = ASYS_IRQ13_CON,2492 .irq_fs_shift = 24,2493 .irq_fs_maskbit = 0x1ffff,2494 .irq_en_reg = ASYS_IRQ13_CON,2495 .irq_en_shift = 31,2496 .irq_clr_reg = ASYS_IRQ_CLR,2497 .irq_clr_shift = 12,2498 .irq_status_shift = 12,2499 },2500 [MT8195_AFE_IRQ_26] = {2501 .id = MT8195_AFE_IRQ_26,2502 .irq_cnt_reg = ASYS_IRQ14_CON,2503 .irq_cnt_shift = 0,2504 .irq_cnt_maskbit = 0xffffff,2505 .irq_fs_reg = ASYS_IRQ14_CON,2506 .irq_fs_shift = 24,2507 .irq_fs_maskbit = 0x1ffff,2508 .irq_en_reg = ASYS_IRQ14_CON,2509 .irq_en_shift = 31,2510 .irq_clr_reg = ASYS_IRQ_CLR,2511 .irq_clr_shift = 13,2512 .irq_status_shift = 13,2513 },2514 [MT8195_AFE_IRQ_27] = {2515 .id = MT8195_AFE_IRQ_27,2516 .irq_cnt_reg = ASYS_IRQ15_CON,2517 .irq_cnt_shift = 0,2518 .irq_cnt_maskbit = 0xffffff,2519 .irq_fs_reg = ASYS_IRQ15_CON,2520 .irq_fs_shift = 24,2521 .irq_fs_maskbit = 0x1ffff,2522 .irq_en_reg = ASYS_IRQ15_CON,2523 .irq_en_shift = 31,2524 .irq_clr_reg = ASYS_IRQ_CLR,2525 .irq_clr_shift = 14,2526 .irq_status_shift = 14,2527 },2528 [MT8195_AFE_IRQ_28] = {2529 .id = MT8195_AFE_IRQ_28,2530 .irq_cnt_reg = ASYS_IRQ16_CON,2531 .irq_cnt_shift = 0,2532 .irq_cnt_maskbit = 0xffffff,2533 .irq_fs_reg = ASYS_IRQ16_CON,2534 .irq_fs_shift = 24,2535 .irq_fs_maskbit = 0x1ffff,2536 .irq_en_reg = ASYS_IRQ16_CON,2537 .irq_en_shift = 31,2538 .irq_clr_reg = ASYS_IRQ_CLR,2539 .irq_clr_shift = 15,2540 .irq_status_shift = 15,2541 },2542};2543 2544static const int mt8195_afe_memif_const_irqs[MT8195_AFE_MEMIF_NUM] = {2545 [MT8195_AFE_MEMIF_DL2] = MT8195_AFE_IRQ_13,2546 [MT8195_AFE_MEMIF_DL3] = MT8195_AFE_IRQ_14,2547 [MT8195_AFE_MEMIF_DL6] = MT8195_AFE_IRQ_15,2548 [MT8195_AFE_MEMIF_DL7] = MT8195_AFE_IRQ_1,2549 [MT8195_AFE_MEMIF_DL8] = MT8195_AFE_IRQ_16,2550 [MT8195_AFE_MEMIF_DL10] = MT8195_AFE_IRQ_17,2551 [MT8195_AFE_MEMIF_DL11] = MT8195_AFE_IRQ_18,2552 [MT8195_AFE_MEMIF_UL1] = MT8195_AFE_IRQ_3,2553 [MT8195_AFE_MEMIF_UL2] = MT8195_AFE_IRQ_19,2554 [MT8195_AFE_MEMIF_UL3] = MT8195_AFE_IRQ_20,2555 [MT8195_AFE_MEMIF_UL4] = MT8195_AFE_IRQ_21,2556 [MT8195_AFE_MEMIF_UL5] = MT8195_AFE_IRQ_22,2557 [MT8195_AFE_MEMIF_UL6] = MT8195_AFE_IRQ_9,2558 [MT8195_AFE_MEMIF_UL8] = MT8195_AFE_IRQ_23,2559 [MT8195_AFE_MEMIF_UL9] = MT8195_AFE_IRQ_24,2560 [MT8195_AFE_MEMIF_UL10] = MT8195_AFE_IRQ_25,2561};2562 2563static bool mt8195_is_volatile_reg(struct device *dev, unsigned int reg)2564{2565 /* these auto-gen reg has read-only bit, so put it as volatile */2566 /* volatile reg cannot be cached, so cannot be set when power off */2567 switch (reg) {2568 case AUDIO_TOP_CON0:2569 case AUDIO_TOP_CON1:2570 case AUDIO_TOP_CON3:2571 case AUDIO_TOP_CON4:2572 case AUDIO_TOP_CON5:2573 case AUDIO_TOP_CON6:2574 case ASYS_IRQ_CLR:2575 case ASYS_IRQ_STATUS:2576 case ASYS_IRQ_MON1:2577 case ASYS_IRQ_MON2:2578 case AFE_IRQ_MCU_CLR:2579 case AFE_IRQ_STATUS:2580 case AFE_IRQ3_CON_MON:2581 case AFE_IRQ_MCU_MON2:2582 case ADSP_IRQ_STATUS:2583 case AUDIO_TOP_STA0:2584 case AUDIO_TOP_STA1:2585 case AFE_GAIN1_CUR:2586 case AFE_GAIN2_CUR:2587 case AFE_IEC_BURST_INFO:2588 case AFE_IEC_CHL_STAT0:2589 case AFE_IEC_CHL_STAT1:2590 case AFE_IEC_CHR_STAT0:2591 case AFE_IEC_CHR_STAT1:2592 case AFE_SPDIFIN_CHSTS1:2593 case AFE_SPDIFIN_CHSTS2:2594 case AFE_SPDIFIN_CHSTS3:2595 case AFE_SPDIFIN_CHSTS4:2596 case AFE_SPDIFIN_CHSTS5:2597 case AFE_SPDIFIN_CHSTS6:2598 case AFE_SPDIFIN_DEBUG1:2599 case AFE_SPDIFIN_DEBUG2:2600 case AFE_SPDIFIN_DEBUG3:2601 case AFE_SPDIFIN_DEBUG4:2602 case AFE_SPDIFIN_EC:2603 case AFE_SPDIFIN_CKLOCK_CFG:2604 case AFE_SPDIFIN_BR_DBG1:2605 case AFE_SPDIFIN_CKFBDIV:2606 case AFE_SPDIFIN_INT_EXT:2607 case AFE_SPDIFIN_INT_EXT2:2608 case SPDIFIN_FREQ_STATUS:2609 case SPDIFIN_USERCODE1:2610 case SPDIFIN_USERCODE2:2611 case SPDIFIN_USERCODE3:2612 case SPDIFIN_USERCODE4:2613 case SPDIFIN_USERCODE5:2614 case SPDIFIN_USERCODE6:2615 case SPDIFIN_USERCODE7:2616 case SPDIFIN_USERCODE8:2617 case SPDIFIN_USERCODE9:2618 case SPDIFIN_USERCODE10:2619 case SPDIFIN_USERCODE11:2620 case SPDIFIN_USERCODE12:2621 case AFE_LINEIN_APLL_TUNER_MON:2622 case AFE_EARC_APLL_TUNER_MON:2623 case AFE_CM0_MON:2624 case AFE_CM1_MON:2625 case AFE_CM2_MON:2626 case AFE_MPHONE_MULTI_DET_MON0:2627 case AFE_MPHONE_MULTI_DET_MON1:2628 case AFE_MPHONE_MULTI_DET_MON2:2629 case AFE_MPHONE_MULTI2_DET_MON0:2630 case AFE_MPHONE_MULTI2_DET_MON1:2631 case AFE_MPHONE_MULTI2_DET_MON2:2632 case AFE_ADDA_MTKAIF_MON0:2633 case AFE_ADDA_MTKAIF_MON1:2634 case AFE_AUD_PAD_TOP:2635 case AFE_ADDA6_MTKAIF_MON0:2636 case AFE_ADDA6_MTKAIF_MON1:2637 case AFE_ADDA6_SRC_DEBUG_MON0:2638 case AFE_ADDA6_UL_SRC_MON0:2639 case AFE_ADDA6_UL_SRC_MON1:2640 case AFE_ASRC11_NEW_CON8:2641 case AFE_ASRC11_NEW_CON9:2642 case AFE_ASRC12_NEW_CON8:2643 case AFE_ASRC12_NEW_CON9:2644 case AFE_LRCK_CNT:2645 case AFE_DAC_MON0:2646 case AFE_DL2_CUR:2647 case AFE_DL3_CUR:2648 case AFE_DL6_CUR:2649 case AFE_DL7_CUR:2650 case AFE_DL8_CUR:2651 case AFE_DL10_CUR:2652 case AFE_DL11_CUR:2653 case AFE_UL1_CUR:2654 case AFE_UL2_CUR:2655 case AFE_UL3_CUR:2656 case AFE_UL4_CUR:2657 case AFE_UL5_CUR:2658 case AFE_UL6_CUR:2659 case AFE_UL8_CUR:2660 case AFE_UL9_CUR:2661 case AFE_UL10_CUR:2662 case AFE_DL8_CHK_SUM1:2663 case AFE_DL8_CHK_SUM2:2664 case AFE_DL8_CHK_SUM3:2665 case AFE_DL8_CHK_SUM4:2666 case AFE_DL8_CHK_SUM5:2667 case AFE_DL8_CHK_SUM6:2668 case AFE_DL10_CHK_SUM1:2669 case AFE_DL10_CHK_SUM2:2670 case AFE_DL10_CHK_SUM3:2671 case AFE_DL10_CHK_SUM4:2672 case AFE_DL10_CHK_SUM5:2673 case AFE_DL10_CHK_SUM6:2674 case AFE_DL11_CHK_SUM1:2675 case AFE_DL11_CHK_SUM2:2676 case AFE_DL11_CHK_SUM3:2677 case AFE_DL11_CHK_SUM4:2678 case AFE_DL11_CHK_SUM5:2679 case AFE_DL11_CHK_SUM6:2680 case AFE_UL1_CHK_SUM1:2681 case AFE_UL1_CHK_SUM2:2682 case AFE_UL2_CHK_SUM1:2683 case AFE_UL2_CHK_SUM2:2684 case AFE_UL3_CHK_SUM1:2685 case AFE_UL3_CHK_SUM2:2686 case AFE_UL4_CHK_SUM1:2687 case AFE_UL4_CHK_SUM2:2688 case AFE_UL5_CHK_SUM1:2689 case AFE_UL5_CHK_SUM2:2690 case AFE_UL6_CHK_SUM1:2691 case AFE_UL6_CHK_SUM2:2692 case AFE_UL8_CHK_SUM1:2693 case AFE_UL8_CHK_SUM2:2694 case AFE_DL2_CHK_SUM1:2695 case AFE_DL2_CHK_SUM2:2696 case AFE_DL3_CHK_SUM1:2697 case AFE_DL3_CHK_SUM2:2698 case AFE_DL6_CHK_SUM1:2699 case AFE_DL6_CHK_SUM2:2700 case AFE_DL7_CHK_SUM1:2701 case AFE_DL7_CHK_SUM2:2702 case AFE_UL9_CHK_SUM1:2703 case AFE_UL9_CHK_SUM2:2704 case AFE_BUS_MON1:2705 case UL1_MOD2AGT_CNT_LAT:2706 case UL2_MOD2AGT_CNT_LAT:2707 case UL3_MOD2AGT_CNT_LAT:2708 case UL4_MOD2AGT_CNT_LAT:2709 case UL5_MOD2AGT_CNT_LAT:2710 case UL6_MOD2AGT_CNT_LAT:2711 case UL8_MOD2AGT_CNT_LAT:2712 case UL9_MOD2AGT_CNT_LAT:2713 case UL10_MOD2AGT_CNT_LAT:2714 case AFE_MEMIF_BUF_FULL_MON:2715 case AFE_MEMIF_BUF_MON1:2716 case AFE_MEMIF_BUF_MON3:2717 case AFE_MEMIF_BUF_MON4:2718 case AFE_MEMIF_BUF_MON5:2719 case AFE_MEMIF_BUF_MON6:2720 case AFE_MEMIF_BUF_MON7:2721 case AFE_MEMIF_BUF_MON8:2722 case AFE_MEMIF_BUF_MON9:2723 case AFE_MEMIF_BUF_MON10:2724 case DL2_AGENT2MODULE_CNT:2725 case DL3_AGENT2MODULE_CNT:2726 case DL6_AGENT2MODULE_CNT:2727 case DL7_AGENT2MODULE_CNT:2728 case DL8_AGENT2MODULE_CNT:2729 case DL10_AGENT2MODULE_CNT:2730 case DL11_AGENT2MODULE_CNT:2731 case UL1_MODULE2AGENT_CNT:2732 case UL2_MODULE2AGENT_CNT:2733 case UL3_MODULE2AGENT_CNT:2734 case UL4_MODULE2AGENT_CNT:2735 case UL5_MODULE2AGENT_CNT:2736 case UL6_MODULE2AGENT_CNT:2737 case UL8_MODULE2AGENT_CNT:2738 case UL9_MODULE2AGENT_CNT:2739 case UL10_MODULE2AGENT_CNT:2740 case AFE_DMIC0_SRC_DEBUG_MON0:2741 case AFE_DMIC0_UL_SRC_MON0:2742 case AFE_DMIC0_UL_SRC_MON1:2743 case AFE_DMIC1_SRC_DEBUG_MON0:2744 case AFE_DMIC1_UL_SRC_MON0:2745 case AFE_DMIC1_UL_SRC_MON1:2746 case AFE_DMIC2_SRC_DEBUG_MON0:2747 case AFE_DMIC2_UL_SRC_MON0:2748 case AFE_DMIC2_UL_SRC_MON1:2749 case AFE_DMIC3_SRC_DEBUG_MON0:2750 case AFE_DMIC3_UL_SRC_MON0:2751 case AFE_DMIC3_UL_SRC_MON1:2752 case DMIC_GAIN1_CUR:2753 case DMIC_GAIN2_CUR:2754 case DMIC_GAIN3_CUR:2755 case DMIC_GAIN4_CUR:2756 case ETDM_IN1_MONITOR:2757 case ETDM_IN2_MONITOR:2758 case ETDM_OUT1_MONITOR:2759 case ETDM_OUT2_MONITOR:2760 case ETDM_OUT3_MONITOR:2761 case AFE_ADDA_SRC_DEBUG_MON0:2762 case AFE_ADDA_SRC_DEBUG_MON1:2763 case AFE_ADDA_DL_SDM_FIFO_MON:2764 case AFE_ADDA_DL_SRC_LCH_MON:2765 case AFE_ADDA_DL_SRC_RCH_MON:2766 case AFE_ADDA_DL_SDM_OUT_MON:2767 case AFE_GASRC0_NEW_CON8:2768 case AFE_GASRC0_NEW_CON9:2769 case AFE_GASRC0_NEW_CON12:2770 case AFE_GASRC1_NEW_CON8:2771 case AFE_GASRC1_NEW_CON9:2772 case AFE_GASRC1_NEW_CON12:2773 case AFE_GASRC2_NEW_CON8:2774 case AFE_GASRC2_NEW_CON9:2775 case AFE_GASRC2_NEW_CON12:2776 case AFE_GASRC3_NEW_CON8:2777 case AFE_GASRC3_NEW_CON9:2778 case AFE_GASRC3_NEW_CON12:2779 case AFE_GASRC4_NEW_CON8:2780 case AFE_GASRC4_NEW_CON9:2781 case AFE_GASRC4_NEW_CON12:2782 case AFE_GASRC5_NEW_CON8:2783 case AFE_GASRC5_NEW_CON9:2784 case AFE_GASRC5_NEW_CON12:2785 case AFE_GASRC6_NEW_CON8:2786 case AFE_GASRC6_NEW_CON9:2787 case AFE_GASRC6_NEW_CON12:2788 case AFE_GASRC7_NEW_CON8:2789 case AFE_GASRC7_NEW_CON9:2790 case AFE_GASRC7_NEW_CON12:2791 case AFE_GASRC8_NEW_CON8:2792 case AFE_GASRC8_NEW_CON9:2793 case AFE_GASRC8_NEW_CON12:2794 case AFE_GASRC9_NEW_CON8:2795 case AFE_GASRC9_NEW_CON9:2796 case AFE_GASRC9_NEW_CON12:2797 case AFE_GASRC10_NEW_CON8:2798 case AFE_GASRC10_NEW_CON9:2799 case AFE_GASRC10_NEW_CON12:2800 case AFE_GASRC11_NEW_CON8:2801 case AFE_GASRC11_NEW_CON9:2802 case AFE_GASRC11_NEW_CON12:2803 case AFE_GASRC12_NEW_CON8:2804 case AFE_GASRC12_NEW_CON9:2805 case AFE_GASRC12_NEW_CON12:2806 case AFE_GASRC13_NEW_CON8:2807 case AFE_GASRC13_NEW_CON9:2808 case AFE_GASRC13_NEW_CON12:2809 case AFE_GASRC14_NEW_CON8:2810 case AFE_GASRC14_NEW_CON9:2811 case AFE_GASRC14_NEW_CON12:2812 case AFE_GASRC15_NEW_CON8:2813 case AFE_GASRC15_NEW_CON9:2814 case AFE_GASRC15_NEW_CON12:2815 case AFE_GASRC16_NEW_CON8:2816 case AFE_GASRC16_NEW_CON9:2817 case AFE_GASRC16_NEW_CON12:2818 case AFE_GASRC17_NEW_CON8:2819 case AFE_GASRC17_NEW_CON9:2820 case AFE_GASRC17_NEW_CON12:2821 case AFE_GASRC18_NEW_CON8:2822 case AFE_GASRC18_NEW_CON9:2823 case AFE_GASRC18_NEW_CON12:2824 case AFE_GASRC19_NEW_CON8:2825 case AFE_GASRC19_NEW_CON9:2826 case AFE_GASRC19_NEW_CON12:2827 return true;2828 default:2829 return false;2830 };2831}2832 2833static const struct regmap_config mt8195_afe_regmap_config = {2834 .reg_bits = 32,2835 .reg_stride = 4,2836 .val_bits = 32,2837 .volatile_reg = mt8195_is_volatile_reg,2838 .max_register = AFE_MAX_REGISTER,2839 .num_reg_defaults_raw = ((AFE_MAX_REGISTER / 4) + 1),2840 .cache_type = REGCACHE_FLAT,2841};2842 2843#define AFE_IRQ_CLR_BITS (0x387)2844#define ASYS_IRQ_CLR_BITS (0xffff)2845 2846static irqreturn_t mt8195_afe_irq_handler(int irq_id, void *dev_id)2847{2848 struct mtk_base_afe *afe = dev_id;2849 unsigned int val = 0;2850 unsigned int asys_irq_clr_bits = 0;2851 unsigned int afe_irq_clr_bits = 0;2852 unsigned int irq_status_bits = 0;2853 unsigned int irq_clr_bits = 0;2854 unsigned int mcu_irq_mask = 0;2855 int i = 0;2856 int ret = 0;2857 2858 ret = regmap_read(afe->regmap, AFE_IRQ_STATUS, &val);2859 if (ret) {2860 dev_info(afe->dev, "%s irq status err\n", __func__);2861 afe_irq_clr_bits = AFE_IRQ_CLR_BITS;2862 asys_irq_clr_bits = ASYS_IRQ_CLR_BITS;2863 goto err_irq;2864 }2865 2866 ret = regmap_read(afe->regmap, AFE_IRQ_MASK, &mcu_irq_mask);2867 if (ret) {2868 dev_info(afe->dev, "%s read irq mask err\n", __func__);2869 afe_irq_clr_bits = AFE_IRQ_CLR_BITS;2870 asys_irq_clr_bits = ASYS_IRQ_CLR_BITS;2871 goto err_irq;2872 }2873 2874 /* only clr cpu irq */2875 val &= mcu_irq_mask;2876 2877 for (i = 0; i < MT8195_AFE_MEMIF_NUM; i++) {2878 struct mtk_base_afe_memif *memif = &afe->memif[i];2879 struct mtk_base_irq_data const *irq_data;2880 2881 if (memif->irq_usage < 0)2882 continue;2883 2884 irq_data = afe->irqs[memif->irq_usage].irq_data;2885 2886 irq_status_bits = BIT(irq_data->irq_status_shift);2887 irq_clr_bits = BIT(irq_data->irq_clr_shift);2888 2889 if (!(val & irq_status_bits))2890 continue;2891 2892 if (irq_data->irq_clr_reg == ASYS_IRQ_CLR)2893 asys_irq_clr_bits |= irq_clr_bits;2894 else2895 afe_irq_clr_bits |= irq_clr_bits;2896 2897 snd_pcm_period_elapsed(memif->substream);2898 }2899 2900err_irq:2901 /* clear irq */2902 if (asys_irq_clr_bits)2903 regmap_write(afe->regmap, ASYS_IRQ_CLR, asys_irq_clr_bits);2904 if (afe_irq_clr_bits)2905 regmap_write(afe->regmap, AFE_IRQ_MCU_CLR, afe_irq_clr_bits);2906 2907 return IRQ_HANDLED;2908}2909 2910static int mt8195_afe_runtime_suspend(struct device *dev)2911{2912 struct mtk_base_afe *afe = dev_get_drvdata(dev);2913 struct mt8195_afe_private *afe_priv = afe->platform_priv;2914 2915 if (!afe->regmap || afe_priv->pm_runtime_bypass_reg_ctl)2916 goto skip_regmap;2917 2918 mt8195_afe_disable_main_clock(afe);2919 2920 regcache_cache_only(afe->regmap, true);2921 regcache_mark_dirty(afe->regmap);2922 2923skip_regmap:2924 mt8195_afe_disable_reg_rw_clk(afe);2925 2926 return 0;2927}2928 2929static int mt8195_afe_runtime_resume(struct device *dev)2930{2931 struct mtk_base_afe *afe = dev_get_drvdata(dev);2932 struct mt8195_afe_private *afe_priv = afe->platform_priv;2933 2934 mt8195_afe_enable_reg_rw_clk(afe);2935 2936 if (!afe->regmap || afe_priv->pm_runtime_bypass_reg_ctl)2937 goto skip_regmap;2938 2939 regcache_cache_only(afe->regmap, false);2940 regcache_sync(afe->regmap);2941 2942 mt8195_afe_enable_main_clock(afe);2943skip_regmap:2944 return 0;2945}2946 2947static int init_memif_priv_data(struct mtk_base_afe *afe)2948{2949 struct mt8195_afe_private *afe_priv = afe->platform_priv;2950 struct mtk_dai_memif_priv *memif_priv;2951 int i;2952 2953 for (i = MT8195_AFE_MEMIF_START; i < MT8195_AFE_MEMIF_END; i++) {2954 memif_priv = devm_kzalloc(afe->dev,2955 sizeof(struct mtk_dai_memif_priv),2956 GFP_KERNEL);2957 if (!memif_priv)2958 return -ENOMEM;2959 2960 afe_priv->dai_priv[i] = memif_priv;2961 }2962 2963 return 0;2964}2965 2966static int mt8195_dai_memif_register(struct mtk_base_afe *afe)2967{2968 struct mtk_base_afe_dai *dai;2969 2970 dai = devm_kzalloc(afe->dev, sizeof(*dai), GFP_KERNEL);2971 if (!dai)2972 return -ENOMEM;2973 2974 list_add(&dai->list, &afe->sub_dais);2975 2976 dai->dai_drivers = mt8195_memif_dai_driver;2977 dai->num_dai_drivers = ARRAY_SIZE(mt8195_memif_dai_driver);2978 2979 dai->dapm_widgets = mt8195_memif_widgets;2980 dai->num_dapm_widgets = ARRAY_SIZE(mt8195_memif_widgets);2981 dai->dapm_routes = mt8195_memif_routes;2982 dai->num_dapm_routes = ARRAY_SIZE(mt8195_memif_routes);2983 dai->controls = mt8195_memif_controls;2984 dai->num_controls = ARRAY_SIZE(mt8195_memif_controls);2985 2986 return init_memif_priv_data(afe);2987}2988 2989typedef int (*dai_register_cb)(struct mtk_base_afe *);2990static const dai_register_cb dai_register_cbs[] = {2991 mt8195_dai_adda_register,2992 mt8195_dai_etdm_register,2993 mt8195_dai_pcm_register,2994 mt8195_dai_memif_register,2995};2996 2997static const struct reg_sequence mt8195_afe_reg_defaults[] = {2998 { AFE_IRQ_MASK, 0x387ffff },2999 { AFE_IRQ3_CON, BIT(30) },3000 { AFE_IRQ9_CON, BIT(30) },3001 { ETDM_IN1_CON4, 0x12000100 },3002 { ETDM_IN2_CON4, 0x12000100 },3003};3004 3005static const struct reg_sequence mt8195_cg_patch[] = {3006 { AUDIO_TOP_CON0, 0xfffffffb },3007 { AUDIO_TOP_CON1, 0xfffffff8 },3008};3009 3010static int mt8195_afe_pcm_dev_probe(struct platform_device *pdev)3011{3012 struct mtk_base_afe *afe;3013 struct mt8195_afe_private *afe_priv;3014 struct device *dev = &pdev->dev;3015 struct reset_control *rstc;3016 int i, irq_id, ret;3017 3018 ret = of_reserved_mem_device_init(dev);3019 if (ret)3020 return dev_err_probe(dev, ret, "failed to assign memory region\n");3021 3022 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(33));3023 if (ret)3024 return ret;3025 3026 afe = devm_kzalloc(dev, sizeof(*afe), GFP_KERNEL);3027 if (!afe)3028 return -ENOMEM;3029 3030 afe->platform_priv = devm_kzalloc(dev, sizeof(*afe_priv),3031 GFP_KERNEL);3032 if (!afe->platform_priv)3033 return -ENOMEM;3034 3035 afe_priv = afe->platform_priv;3036 afe->dev = &pdev->dev;3037 3038 afe->base_addr = devm_platform_ioremap_resource(pdev, 0);3039 if (IS_ERR(afe->base_addr))3040 return PTR_ERR(afe->base_addr);3041 3042 /* initial audio related clock */3043 ret = mt8195_afe_init_clock(afe);3044 if (ret)3045 return dev_err_probe(dev, ret, "init clock error\n");3046 3047 /* reset controller to reset audio regs before regmap cache */3048 rstc = devm_reset_control_get_exclusive(dev, "audiosys");3049 if (IS_ERR(rstc))3050 return dev_err_probe(dev, PTR_ERR(rstc), "could not get audiosys reset\n");3051 3052 ret = reset_control_reset(rstc);3053 if (ret)3054 return dev_err_probe(dev, ret, "failed to trigger audio reset\n");3055 3056 spin_lock_init(&afe_priv->afe_ctrl_lock);3057 3058 mutex_init(&afe->irq_alloc_lock);3059 3060 /* irq initialize */3061 afe->irqs_size = MT8195_AFE_IRQ_NUM;3062 afe->irqs = devm_kcalloc(dev, afe->irqs_size, sizeof(*afe->irqs),3063 GFP_KERNEL);3064 if (!afe->irqs)3065 return -ENOMEM;3066 3067 for (i = 0; i < afe->irqs_size; i++)3068 afe->irqs[i].irq_data = &irq_data_array[i];3069 3070 /* init memif */3071 afe->memif_size = MT8195_AFE_MEMIF_NUM;3072 afe->memif = devm_kcalloc(dev, afe->memif_size, sizeof(*afe->memif),3073 GFP_KERNEL);3074 if (!afe->memif)3075 return -ENOMEM;3076 3077 for (i = 0; i < afe->memif_size; i++) {3078 afe->memif[i].data = &memif_data[i];3079 afe->memif[i].irq_usage = mt8195_afe_memif_const_irqs[i];3080 afe->memif[i].const_irq = 1;3081 afe->irqs[afe->memif[i].irq_usage].irq_occupyed = true;3082 }3083 3084 /* request irq */3085 irq_id = platform_get_irq(pdev, 0);3086 if (irq_id < 0)3087 return -ENXIO;3088 3089 ret = devm_request_irq(dev, irq_id, mt8195_afe_irq_handler,3090 IRQF_TRIGGER_NONE, "asys-isr", (void *)afe);3091 if (ret)3092 return dev_err_probe(dev, ret, "could not request_irq for asys-isr\n");3093 3094 /* init sub_dais */3095 INIT_LIST_HEAD(&afe->sub_dais);3096 3097 for (i = 0; i < ARRAY_SIZE(dai_register_cbs); i++) {3098 ret = dai_register_cbs[i](afe);3099 if (ret)3100 return dev_err_probe(dev, ret, "dai cb%i register fail\n", i);3101 }3102 3103 /* init dai_driver and component_driver */3104 ret = mtk_afe_combine_sub_dai(afe);3105 if (ret)3106 return dev_err_probe(dev, ret, "mtk_afe_combine_sub_dai fail\n");3107 3108 afe->mtk_afe_hardware = &mt8195_afe_hardware;3109 afe->memif_fs = mt8195_memif_fs;3110 afe->irq_fs = mt8195_irq_fs;3111 3112 afe->runtime_resume = mt8195_afe_runtime_resume;3113 afe->runtime_suspend = mt8195_afe_runtime_suspend;3114 3115 platform_set_drvdata(pdev, afe);3116 3117 afe_priv->topckgen = syscon_regmap_lookup_by_phandle(dev->of_node, "mediatek,topckgen");3118 if (IS_ERR(afe_priv->topckgen))3119 dev_dbg(afe->dev, "Cannot find topckgen controller: %ld\n",3120 PTR_ERR(afe_priv->topckgen));3121 3122 /* enable clock for regcache get default value from hw */3123 afe_priv->pm_runtime_bypass_reg_ctl = true;3124 3125 ret = devm_pm_runtime_enable(dev);3126 if (ret)3127 return ret;3128 3129 ret = pm_runtime_resume_and_get(dev);3130 if (ret)3131 return dev_err_probe(dev, ret, "Failed to resume device\n");3132 3133 afe->regmap = devm_regmap_init_mmio(&pdev->dev, afe->base_addr,3134 &mt8195_afe_regmap_config);3135 if (IS_ERR(afe->regmap)) {3136 ret = PTR_ERR(afe->regmap);3137 goto err_pm_put;3138 }3139 3140 ret = regmap_register_patch(afe->regmap, mt8195_cg_patch,3141 ARRAY_SIZE(mt8195_cg_patch));3142 if (ret < 0) {3143 dev_err(dev, "Failed to apply cg patch\n");3144 goto err_pm_put;3145 }3146 3147 /* register component */3148 ret = devm_snd_soc_register_component(dev, &mtk_afe_pcm_platform,3149 afe->dai_drivers, afe->num_dai_drivers);3150 if (ret) {3151 dev_warn(dev, "err_platform\n");3152 goto err_pm_put;3153 }3154 3155 ret = regmap_multi_reg_write(afe->regmap, mt8195_afe_reg_defaults,3156 ARRAY_SIZE(mt8195_afe_reg_defaults));3157 if (ret)3158 goto err_pm_put;3159 3160 ret = pm_runtime_put_sync(dev);3161 if (ret)3162 return dev_err_probe(dev, ret, "Failed to suspend device\n");3163 3164 afe_priv->pm_runtime_bypass_reg_ctl = false;3165 3166 regcache_cache_only(afe->regmap, true);3167 regcache_mark_dirty(afe->regmap);3168 3169 return 0;3170 3171err_pm_put:3172 pm_runtime_put_sync(dev);3173 3174 return ret;3175}3176 3177static void mt8195_afe_pcm_dev_remove(struct platform_device *pdev)3178{3179 pm_runtime_disable(&pdev->dev);3180 if (!pm_runtime_status_suspended(&pdev->dev))3181 mt8195_afe_runtime_suspend(&pdev->dev);3182}3183 3184static const struct of_device_id mt8195_afe_pcm_dt_match[] = {3185 {.compatible = "mediatek,mt8195-audio", },3186 {},3187};3188MODULE_DEVICE_TABLE(of, mt8195_afe_pcm_dt_match);3189 3190static const struct dev_pm_ops mt8195_afe_pm_ops = {3191 SET_RUNTIME_PM_OPS(mt8195_afe_runtime_suspend,3192 mt8195_afe_runtime_resume, NULL)3193};3194 3195static struct platform_driver mt8195_afe_pcm_driver = {3196 .driver = {3197 .name = "mt8195-audio",3198 .of_match_table = mt8195_afe_pcm_dt_match,3199 .pm = &mt8195_afe_pm_ops,3200 },3201 .probe = mt8195_afe_pcm_dev_probe,3202 .remove = mt8195_afe_pcm_dev_remove,3203};3204 3205module_platform_driver(mt8195_afe_pcm_driver);3206 3207MODULE_DESCRIPTION("Mediatek ALSA SoC AFE platform driver for 8195");3208MODULE_AUTHOR("Bicycle Tsai <bicycle.tsai@mediatek.com>");3209MODULE_LICENSE("GPL v2");3210