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1/* SPDX-License-Identifier: GPL-2.02 *3 * MediaTek 8365 audio driver common definitions4 *5 * Copyright (c) 2024 MediaTek Inc.6 * Authors: Jia Zeng <jia.zeng@mediatek.com>7 * Alexandre Mergnat <amergnat@baylibre.com>8 */9 10#ifndef _MT8365_AFE_COMMON_H_11#define _MT8365_AFE_COMMON_H_12 13#include <linux/clk.h>14#include <linux/list.h>15#include <linux/regmap.h>16#include <sound/soc.h>17#include <sound/asound.h>18#include "../common/mtk-base-afe.h"19#include "mt8365-reg.h"20 21enum {22 MT8365_AFE_MEMIF_DL1,23 MT8365_AFE_MEMIF_DL2,24 MT8365_AFE_MEMIF_TDM_OUT,25 /*26 * MT8365_AFE_MEMIF_SPDIF_OUT,27 */28 MT8365_AFE_MEMIF_AWB,29 MT8365_AFE_MEMIF_VUL,30 MT8365_AFE_MEMIF_VUL2,31 MT8365_AFE_MEMIF_VUL3,32 MT8365_AFE_MEMIF_TDM_IN,33 /*34 * MT8365_AFE_MEMIF_SPDIF_IN,35 */36 MT8365_AFE_MEMIF_NUM,37 MT8365_AFE_BACKEND_BASE = MT8365_AFE_MEMIF_NUM,38 MT8365_AFE_IO_TDM_OUT = MT8365_AFE_BACKEND_BASE,39 MT8365_AFE_IO_TDM_IN,40 MT8365_AFE_IO_I2S,41 MT8365_AFE_IO_2ND_I2S,42 MT8365_AFE_IO_PCM1,43 MT8365_AFE_IO_VIRTUAL_DL_SRC,44 MT8365_AFE_IO_VIRTUAL_TDM_OUT_SRC,45 MT8365_AFE_IO_VIRTUAL_FM,46 MT8365_AFE_IO_DMIC,47 MT8365_AFE_IO_INT_ADDA,48 MT8365_AFE_IO_GASRC1,49 MT8365_AFE_IO_GASRC2,50 MT8365_AFE_IO_TDM_ASRC,51 MT8365_AFE_IO_HW_GAIN1,52 MT8365_AFE_IO_HW_GAIN2,53 MT8365_AFE_BACKEND_END,54 MT8365_AFE_BACKEND_NUM = (MT8365_AFE_BACKEND_END -55 MT8365_AFE_BACKEND_BASE),56};57 58enum {59 MT8365_AFE_IRQ1,60 MT8365_AFE_IRQ2,61 MT8365_AFE_IRQ3,62 MT8365_AFE_IRQ4,63 MT8365_AFE_IRQ5,64 MT8365_AFE_IRQ6,65 MT8365_AFE_IRQ7,66 MT8365_AFE_IRQ8,67 MT8365_AFE_IRQ9,68 MT8365_AFE_IRQ10,69 MT8365_AFE_IRQ_NUM,70};71 72enum {73 MT8365_TOP_CG_AFE,74 MT8365_TOP_CG_I2S_IN,75 MT8365_TOP_CG_22M,76 MT8365_TOP_CG_24M,77 MT8365_TOP_CG_INTDIR_CK,78 MT8365_TOP_CG_APLL2_TUNER,79 MT8365_TOP_CG_APLL_TUNER,80 MT8365_TOP_CG_SPDIF,81 MT8365_TOP_CG_TDM_OUT,82 MT8365_TOP_CG_TDM_IN,83 MT8365_TOP_CG_ADC,84 MT8365_TOP_CG_DAC,85 MT8365_TOP_CG_DAC_PREDIS,86 MT8365_TOP_CG_TML,87 MT8365_TOP_CG_I2S1_BCLK,88 MT8365_TOP_CG_I2S2_BCLK,89 MT8365_TOP_CG_I2S3_BCLK,90 MT8365_TOP_CG_I2S4_BCLK,91 MT8365_TOP_CG_DMIC0_ADC,92 MT8365_TOP_CG_DMIC1_ADC,93 MT8365_TOP_CG_DMIC2_ADC,94 MT8365_TOP_CG_DMIC3_ADC,95 MT8365_TOP_CG_CONNSYS_I2S_ASRC,96 MT8365_TOP_CG_GENERAL1_ASRC,97 MT8365_TOP_CG_GENERAL2_ASRC,98 MT8365_TOP_CG_TDM_ASRC,99 MT8365_TOP_CG_NUM100};101 102enum {103 MT8365_CLK_TOP_AUD_SEL,104 MT8365_CLK_AUD_I2S0_M,105 MT8365_CLK_AUD_I2S1_M,106 MT8365_CLK_AUD_I2S2_M,107 MT8365_CLK_AUD_I2S3_M,108 MT8365_CLK_ENGEN1,109 MT8365_CLK_ENGEN2,110 MT8365_CLK_AUD1,111 MT8365_CLK_AUD2,112 MT8365_CLK_I2S0_M_SEL,113 MT8365_CLK_I2S1_M_SEL,114 MT8365_CLK_I2S2_M_SEL,115 MT8365_CLK_I2S3_M_SEL,116 MT8365_CLK_CLK26M,117 MT8365_CLK_NUM118};119 120enum {121 MT8365_AFE_APLL1 = 0,122 MT8365_AFE_APLL2,123 MT8365_AFE_APLL_NUM,124};125 126enum {127 MT8365_AFE_1ST_I2S = 0,128 MT8365_AFE_2ND_I2S,129 MT8365_AFE_I2S_SETS,130};131 132enum {133 MT8365_AFE_I2S_SEPARATE_CLOCK = 0,134 MT8365_AFE_I2S_SHARED_CLOCK,135};136 137enum {138 MT8365_AFE_TDM_OUT_I2S = 0,139 MT8365_AFE_TDM_OUT_TDM,140 MT8365_AFE_TDM_OUT_I2S_32BITS,141};142 143enum mt8365_afe_tdm_ch_start {144 AFE_TDM_CH_START_O28_O29 = 0,145 AFE_TDM_CH_START_O30_O31,146 AFE_TDM_CH_START_O32_O33,147 AFE_TDM_CH_START_O34_O35,148 AFE_TDM_CH_ZERO,149};150 151enum {152 MT8365_PCM_FORMAT_I2S = 0,153 MT8365_PCM_FORMAT_EIAJ,154 MT8365_PCM_FORMAT_PCMA,155 MT8365_PCM_FORMAT_PCMB,156};157 158enum {159 MT8365_FS_8K = 0,160 MT8365_FS_11D025K,161 MT8365_FS_12K,162 MT8365_FS_384K,163 MT8365_FS_16K,164 MT8365_FS_22D05K,165 MT8365_FS_24K,166 MT8365_FS_130K,167 MT8365_FS_32K,168 MT8365_FS_44D1K,169 MT8365_FS_48K,170 MT8365_FS_88D2K,171 MT8365_FS_96K,172 MT8365_FS_176D4K,173 MT8365_FS_192K,174};175 176enum {177 FS_8000HZ = 0, /* 0000b */178 FS_11025HZ = 1, /* 0001b */179 FS_12000HZ = 2, /* 0010b */180 FS_384000HZ = 3, /* 0011b */181 FS_16000HZ = 4, /* 0100b */182 FS_22050HZ = 5, /* 0101b */183 FS_24000HZ = 6, /* 0110b */184 FS_130000HZ = 7, /* 0111b */185 FS_32000HZ = 8, /* 1000b */186 FS_44100HZ = 9, /* 1001b */187 FS_48000HZ = 10, /* 1010b */188 FS_88200HZ = 11, /* 1011b */189 FS_96000HZ = 12, /* 1100b */190 FS_176400HZ = 13, /* 1101b */191 FS_192000HZ = 14, /* 1110b */192 FS_260000HZ = 15, /* 1111b */193};194 195enum {196 MT8365_AFE_DEBUGFS_AFE,197 MT8365_AFE_DEBUGFS_MEMIF,198 MT8365_AFE_DEBUGFS_IRQ,199 MT8365_AFE_DEBUGFS_CONN,200 MT8365_AFE_DEBUGFS_DBG,201 MT8365_AFE_DEBUGFS_NUM,202};203 204enum {205 MT8365_AFE_IRQ_DIR_MCU = 0,206 MT8365_AFE_IRQ_DIR_DSP,207 MT8365_AFE_IRQ_DIR_BOTH,208};209 210/* MCLK */211enum {212 MT8365_I2S0_MCK = 0,213 MT8365_I2S3_MCK,214 MT8365_MCK_NUM,215};216 217struct mt8365_fe_dai_data {218 bool use_sram;219 unsigned int sram_phy_addr;220 void __iomem *sram_vir_addr;221 unsigned int sram_size;222};223 224struct mt8365_be_dai_data {225 bool prepared[SNDRV_PCM_STREAM_LAST + 1];226 unsigned int fmt_mode;227};228 229#define MT8365_CLK_26M 26000000230#define MT8365_CLK_24M 24000000231#define MT8365_CLK_22M 22000000232#define MT8365_CM_UPDATA_CNT_SET 8233 234enum mt8365_cm_num {235 MT8365_CM1 = 0,236 MT8365_CM2,237 MT8365_CM_NUM,238};239 240enum mt8365_cm2_mux_in {241 MT8365_FROM_GASRC1 = 1,242 MT8365_FROM_GASRC2,243 MT8365_FROM_TDM_ASRC,244 MT8365_CM_MUX_NUM,245};246 247enum cm2_mux_conn_in {248 GENERAL2_ASRC_OUT_LCH = 0,249 GENERAL2_ASRC_OUT_RCH = 1,250 TDM_IN_CH0 = 2,251 TDM_IN_CH1 = 3,252 TDM_IN_CH2 = 4,253 TDM_IN_CH3 = 5,254 TDM_IN_CH4 = 6,255 TDM_IN_CH5 = 7,256 TDM_IN_CH6 = 8,257 TDM_IN_CH7 = 9,258 GENERAL1_ASRC_OUT_LCH = 10,259 GENERAL1_ASRC_OUT_RCH = 11,260 TDM_OUT_ASRC_CH0 = 12,261 TDM_OUT_ASRC_CH1 = 13,262 TDM_OUT_ASRC_CH2 = 14,263 TDM_OUT_ASRC_CH3 = 15,264 TDM_OUT_ASRC_CH4 = 16,265 TDM_OUT_ASRC_CH5 = 17,266 TDM_OUT_ASRC_CH6 = 18,267 TDM_OUT_ASRC_CH7 = 19268};269 270struct mt8365_cm_ctrl_reg {271 unsigned int con0;272 unsigned int con1;273 unsigned int con2;274 unsigned int con3;275 unsigned int con4;276};277 278struct mt8365_control_data {279 bool bypass_cm1;280 bool bypass_cm2;281 unsigned int loopback_type;282};283 284enum dmic_input_mode {285 DMIC_MODE_3P25M = 0,286 DMIC_MODE_1P625M,287 DMIC_MODE_812P5K,288 DMIC_MODE_406P25K,289};290 291enum iir_mode {292 IIR_MODE0 = 0,293 IIR_MODE1,294 IIR_MODE2,295 IIR_MODE3,296 IIR_MODE4,297 IIR_MODE5,298};299 300enum {301 MT8365_GASRC1 = 0,302 MT8365_GASRC2,303 MT8365_GASRC_NUM,304 MT8365_TDM_ASRC1 = MT8365_GASRC_NUM,305 MT8365_TDM_ASRC2,306 MT8365_TDM_ASRC3,307 MT8365_TDM_ASRC4,308 MT8365_TDM_ASRC_NUM,309};310 311struct mt8365_gasrc_ctrl_reg {312 unsigned int con0;313 unsigned int con2;314 unsigned int con3;315 unsigned int con4;316 unsigned int con5;317 unsigned int con6;318 unsigned int con9;319 unsigned int con10;320 unsigned int con12;321 unsigned int con13;322};323 324struct mt8365_gasrc_data {325 bool duplex;326 bool tx_mode;327 bool cali_on;328 bool tdm_asrc_out_cm2;329 bool iir_on;330};331 332struct mt8365_afe_private {333 struct clk *clocks[MT8365_CLK_NUM];334 struct regmap *topckgen;335 struct mt8365_fe_dai_data fe_data[MT8365_AFE_MEMIF_NUM];336 struct mt8365_be_dai_data be_data[MT8365_AFE_BACKEND_NUM];337 struct mt8365_control_data ctrl_data;338 struct mt8365_gasrc_data gasrc_data[MT8365_TDM_ASRC_NUM];339 int afe_on_ref_cnt;340 int top_cg_ref_cnt[MT8365_TOP_CG_NUM];341 void __iomem *afe_sram_vir_addr;342 unsigned int afe_sram_phy_addr;343 unsigned int afe_sram_size;344 /* locks */345 spinlock_t afe_ctrl_lock;346 struct mutex afe_clk_mutex; /* Protect & sync APLL TUNER registers access*/347#ifdef CONFIG_DEBUG_FS348 struct dentry *debugfs_dentry[MT8365_AFE_DEBUGFS_NUM];349#endif350 int apll_tuner_ref_cnt[MT8365_AFE_APLL_NUM];351 unsigned int tdm_out_mode;352 unsigned int cm2_mux_input;353 354 /* dai */355 bool dai_on[MT8365_AFE_BACKEND_END];356 void *dai_priv[MT8365_AFE_BACKEND_END];357};358 359static inline u32 rx_frequency_palette(unsigned int fs)360{361 /* *362 * A = (26M / fs) * 64363 * B = 8125 / A364 * return = DEC2HEX(B * 2^23)365 */366 switch (fs) {367 case FS_8000HZ: return 0x050000;368 case FS_11025HZ: return 0x06E400;369 case FS_12000HZ: return 0x078000;370 case FS_16000HZ: return 0x0A0000;371 case FS_22050HZ: return 0x0DC800;372 case FS_24000HZ: return 0x0F0000;373 case FS_32000HZ: return 0x140000;374 case FS_44100HZ: return 0x1B9000;375 case FS_48000HZ: return 0x1E0000;376 case FS_88200HZ: return 0x372000;377 case FS_96000HZ: return 0x3C0000;378 case FS_176400HZ: return 0x6E4000;379 case FS_192000HZ: return 0x780000;380 default: return 0x0;381 }382}383 384static inline u32 AutoRstThHi(unsigned int fs)385{386 switch (fs) {387 case FS_8000HZ: return 0x36000;388 case FS_11025HZ: return 0x27000;389 case FS_12000HZ: return 0x24000;390 case FS_16000HZ: return 0x1B000;391 case FS_22050HZ: return 0x14000;392 case FS_24000HZ: return 0x12000;393 case FS_32000HZ: return 0x0D800;394 case FS_44100HZ: return 0x09D00;395 case FS_48000HZ: return 0x08E00;396 case FS_88200HZ: return 0x04E00;397 case FS_96000HZ: return 0x04800;398 case FS_176400HZ: return 0x02700;399 case FS_192000HZ: return 0x02400;400 default: return 0x0;401 }402}403 404static inline u32 AutoRstThLo(unsigned int fs)405{406 switch (fs) {407 case FS_8000HZ: return 0x30000;408 case FS_11025HZ: return 0x23000;409 case FS_12000HZ: return 0x20000;410 case FS_16000HZ: return 0x18000;411 case FS_22050HZ: return 0x11000;412 case FS_24000HZ: return 0x0FE00;413 case FS_32000HZ: return 0x0BE00;414 case FS_44100HZ: return 0x08A00;415 case FS_48000HZ: return 0x07F00;416 case FS_88200HZ: return 0x04500;417 case FS_96000HZ: return 0x04000;418 case FS_176400HZ: return 0x02300;419 case FS_192000HZ: return 0x02000;420 default: return 0x0;421 }422}423 424bool mt8365_afe_rate_supported(unsigned int rate, unsigned int id);425bool mt8365_afe_channel_supported(unsigned int channel, unsigned int id);426 427int mt8365_dai_i2s_register(struct mtk_base_afe *afe);428int mt8365_dai_set_priv(struct mtk_base_afe *afe,429 int id,430 int priv_size,431 const void *priv_data);432 433int mt8365_afe_fs_timing(unsigned int rate);434 435void mt8365_afe_set_i2s_out_enable(struct mtk_base_afe *afe, bool enable);436int mt8365_afe_set_i2s_out(struct mtk_base_afe *afe, unsigned int rate, int bit_width);437 438int mt8365_dai_adda_register(struct mtk_base_afe *afe);439int mt8365_dai_enable_adda_on(struct mtk_base_afe *afe);440int mt8365_dai_disable_adda_on(struct mtk_base_afe *afe);441 442int mt8365_dai_dmic_register(struct mtk_base_afe *afe);443 444int mt8365_dai_pcm_register(struct mtk_base_afe *afe);445 446int mt8365_dai_tdm_register(struct mtk_base_afe *afe);447 448#endif449