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1/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */2/*3 * Copyright (c) 2018 BayLibre, SAS.4 * Author: Jerome Brunet <jbrunet@baylibre.com>5 */6 7#ifndef _MESON_AXG_FIFO_H8#define _MESON_AXG_FIFO_H9 10struct clk;11struct platform_device;12struct reg_field;13struct regmap;14struct regmap_field;15struct reset_control;16 17struct snd_soc_component_driver;18struct snd_soc_dai;19struct snd_soc_dai_driver;20 21struct snd_soc_pcm_runtime;22 23#define AXG_FIFO_CH_MAX 12824#define AXG_FIFO_FORMATS (SNDRV_PCM_FMTBIT_S8 | \25 SNDRV_PCM_FMTBIT_S16_LE | \26 SNDRV_PCM_FMTBIT_S20_LE | \27 SNDRV_PCM_FMTBIT_S24_LE | \28 SNDRV_PCM_FMTBIT_S32_LE | \29 SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE)30 31#define AXG_FIFO_BURST 832 33#define FIFO_INT_ADDR_FINISH BIT(0)34#define FIFO_INT_ADDR_INT BIT(1)35#define FIFO_INT_COUNT_REPEAT BIT(2)36#define FIFO_INT_COUNT_ONCE BIT(3)37#define FIFO_INT_FIFO_ZERO BIT(4)38#define FIFO_INT_FIFO_DEPTH BIT(5)39#define FIFO_INT_MASK GENMASK(7, 0)40 41#define FIFO_CTRL0 0x0042#define CTRL0_DMA_EN BIT(31)43#define CTRL0_INT_EN GENMASK(23, 16)44#define CTRL0_SEL_MASK GENMASK(2, 0)45#define CTRL0_SEL_SHIFT 046#define FIFO_CTRL1 0x0447#define CTRL1_INT_CLR GENMASK(7, 0)48#define CTRL1_STATUS2_SEL GENMASK(11, 8)49#define STATUS2_SEL_DDR_READ 050#define CTRL1_FRDDR_DEPTH GENMASK(31, 24)51#define FIFO_START_ADDR 0x0852#define FIFO_FINISH_ADDR 0x0c53#define FIFO_INT_ADDR 0x1054#define FIFO_STATUS1 0x1455#define STATUS1_INT_STS GENMASK(7, 0)56#define FIFO_STATUS2 0x1857#define FIFO_INIT_ADDR 0x2458#define FIFO_CTRL2 0x2859 60struct axg_fifo {61 struct regmap *map;62 struct clk *pclk;63 struct reset_control *arb;64 struct regmap_field *field_threshold;65 unsigned int depth;66 int irq;67};68 69struct axg_fifo_match_data {70 const struct snd_soc_component_driver *component_drv;71 struct snd_soc_dai_driver *dai_drv;72 struct reg_field field_threshold;73};74 75int axg_fifo_pcm_open(struct snd_soc_component *component,76 struct snd_pcm_substream *ss);77int axg_fifo_pcm_close(struct snd_soc_component *component,78 struct snd_pcm_substream *ss);79int axg_fifo_pcm_hw_params(struct snd_soc_component *component,80 struct snd_pcm_substream *ss,81 struct snd_pcm_hw_params *params);82int g12a_fifo_pcm_hw_params(struct snd_soc_component *component,83 struct snd_pcm_substream *ss,84 struct snd_pcm_hw_params *params);85int axg_fifo_pcm_hw_free(struct snd_soc_component *component,86 struct snd_pcm_substream *ss);87snd_pcm_uframes_t axg_fifo_pcm_pointer(struct snd_soc_component *component,88 struct snd_pcm_substream *ss);89int axg_fifo_pcm_trigger(struct snd_soc_component *component,90 struct snd_pcm_substream *ss, int cmd);91 92int axg_fifo_pcm_new(struct snd_soc_pcm_runtime *rtd, unsigned int type);93int axg_fifo_probe(struct platform_device *pdev);94 95#endif /* _MESON_AXG_FIFO_H */96