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1/* SPDX-License-Identifier: GPL-2.0-or-later */2/*3 * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.4 */5 6 7#ifndef _MXS_SAIF_H8#define _MXS_SAIF_H9 10#define SAIF_CTRL 0x011#define SAIF_STAT 0x1012#define SAIF_DATA 0x2013#define SAIF_VERSION 0X3014 15/* SAIF_CTRL */16#define BM_SAIF_CTRL_SFTRST 0x8000000017#define BM_SAIF_CTRL_CLKGATE 0x4000000018#define BP_SAIF_CTRL_BITCLK_MULT_RATE 2719#define BM_SAIF_CTRL_BITCLK_MULT_RATE 0x3800000020#define BF_SAIF_CTRL_BITCLK_MULT_RATE(v) \21 (((v) << 27) & BM_SAIF_CTRL_BITCLK_MULT_RATE)22#define BM_SAIF_CTRL_BITCLK_BASE_RATE 0x0400000023#define BM_SAIF_CTRL_FIFO_ERROR_IRQ_EN 0x0200000024#define BM_SAIF_CTRL_FIFO_SERVICE_IRQ_EN 0x0100000025#define BP_SAIF_CTRL_RSRVD2 2126#define BM_SAIF_CTRL_RSRVD2 0x00E0000027 28#define BP_SAIF_CTRL_DMAWAIT_COUNT 1629#define BM_SAIF_CTRL_DMAWAIT_COUNT 0x001F000030#define BF_SAIF_CTRL_DMAWAIT_COUNT(v) \31 (((v) << 16) & BM_SAIF_CTRL_DMAWAIT_COUNT)32#define BP_SAIF_CTRL_CHANNEL_NUM_SELECT 1433#define BM_SAIF_CTRL_CHANNEL_NUM_SELECT 0x0000C00034#define BF_SAIF_CTRL_CHANNEL_NUM_SELECT(v) \35 (((v) << 14) & BM_SAIF_CTRL_CHANNEL_NUM_SELECT)36#define BM_SAIF_CTRL_LRCLK_PULSE 0x0000200037#define BM_SAIF_CTRL_BIT_ORDER 0x0000100038#define BM_SAIF_CTRL_DELAY 0x0000080039#define BM_SAIF_CTRL_JUSTIFY 0x0000040040#define BM_SAIF_CTRL_LRCLK_POLARITY 0x0000020041#define BM_SAIF_CTRL_BITCLK_EDGE 0x0000010042#define BP_SAIF_CTRL_WORD_LENGTH 443#define BM_SAIF_CTRL_WORD_LENGTH 0x000000F044#define BF_SAIF_CTRL_WORD_LENGTH(v) \45 (((v) << 4) & BM_SAIF_CTRL_WORD_LENGTH)46#define BM_SAIF_CTRL_BITCLK_48XFS_ENABLE 0x0000000847#define BM_SAIF_CTRL_SLAVE_MODE 0x0000000448#define BM_SAIF_CTRL_READ_MODE 0x0000000249#define BM_SAIF_CTRL_RUN 0x0000000150 51/* SAIF_STAT */52#define BM_SAIF_STAT_PRESENT 0x8000000053#define BP_SAIF_STAT_RSRVD2 1754#define BM_SAIF_STAT_RSRVD2 0x7FFE000055#define BF_SAIF_STAT_RSRVD2(v) \56 (((v) << 17) & BM_SAIF_STAT_RSRVD2)57#define BM_SAIF_STAT_DMA_PREQ 0x0001000058#define BP_SAIF_STAT_RSRVD1 759#define BM_SAIF_STAT_RSRVD1 0x0000FF8060#define BF_SAIF_STAT_RSRVD1(v) \61 (((v) << 7) & BM_SAIF_STAT_RSRVD1)62 63#define BM_SAIF_STAT_FIFO_UNDERFLOW_IRQ 0x0000004064#define BM_SAIF_STAT_FIFO_OVERFLOW_IRQ 0x0000002065#define BM_SAIF_STAT_FIFO_SERVICE_IRQ 0x0000001066#define BP_SAIF_STAT_RSRVD0 167#define BM_SAIF_STAT_RSRVD0 0x0000000E68#define BF_SAIF_STAT_RSRVD0(v) \69 (((v) << 1) & BM_SAIF_STAT_RSRVD0)70#define BM_SAIF_STAT_BUSY 0x0000000171 72/* SAFI_DATA */73#define BP_SAIF_DATA_PCM_RIGHT 1674#define BM_SAIF_DATA_PCM_RIGHT 0xFFFF000075#define BF_SAIF_DATA_PCM_RIGHT(v) \76 (((v) << 16) & BM_SAIF_DATA_PCM_RIGHT)77#define BP_SAIF_DATA_PCM_LEFT 078#define BM_SAIF_DATA_PCM_LEFT 0x0000FFFF79#define BF_SAIF_DATA_PCM_LEFT(v) \80 (((v) << 0) & BM_SAIF_DATA_PCM_LEFT)81 82/* SAIF_VERSION */83#define BP_SAIF_VERSION_MAJOR 2484#define BM_SAIF_VERSION_MAJOR 0xFF00000085#define BF_SAIF_VERSION_MAJOR(v) \86 (((v) << 24) & BM_SAIF_VERSION_MAJOR)87#define BP_SAIF_VERSION_MINOR 1688#define BM_SAIF_VERSION_MINOR 0x00FF000089#define BF_SAIF_VERSION_MINOR(v) \90 (((v) << 16) & BM_SAIF_VERSION_MINOR)91#define BP_SAIF_VERSION_STEP 092#define BM_SAIF_VERSION_STEP 0x0000FFFF93#define BF_SAIF_VERSION_STEP(v) \94 (((v) << 0) & BM_SAIF_VERSION_STEP)95 96#define MXS_SAIF_MCLK 097 98#include "mxs-pcm.h"99 100struct mxs_saif {101 struct device *dev;102 struct clk *clk;103 unsigned int mclk;104 unsigned int mclk_in_use;105 void __iomem *base;106 unsigned int id;107 unsigned int master_id;108 unsigned int cur_rate;109 unsigned int ongoing;110 111 u32 fifo_underrun;112 u32 fifo_overrun;113 114 enum {115 MXS_SAIF_STATE_STOPPED,116 MXS_SAIF_STATE_RUNNING,117 } state;118};119 120extern int mxs_saif_put_mclk(unsigned int saif_id);121extern int mxs_saif_get_mclk(unsigned int saif_id, unsigned int mclk,122 unsigned int rate);123#endif124