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1/* SPDX-License-Identifier: GPL-2.0 */2 3#ifndef __Q6AFE_H__4#define __Q6AFE_H__5 6#define AFE_PORT_MAX 1297 8#define MSM_AFE_PORT_TYPE_RX 09#define MSM_AFE_PORT_TYPE_TX 110#define AFE_MAX_PORTS AFE_PORT_MAX11 12#define Q6AFE_MAX_MI2S_LINES 413 14#define AFE_MAX_CHAN_COUNT 815#define AFE_PORT_MAX_AUDIO_CHAN_CNT 0x816 17#define Q6AFE_LPASS_CLK_SRC_INTERNAL 118#define Q6AFE_LPASS_CLK_ROOT_DEFAULT 019 20#define LPAIF_DIG_CLK 121#define LPAIF_BIT_CLK 222#define LPAIF_OSR_CLK 323 24/* Clock ID for Primary I2S IBIT */25#define Q6AFE_LPASS_CLK_ID_PRI_MI2S_IBIT 0x10026/* Clock ID for Primary I2S EBIT */27#define Q6AFE_LPASS_CLK_ID_PRI_MI2S_EBIT 0x10128/* Clock ID for Secondary I2S IBIT */29#define Q6AFE_LPASS_CLK_ID_SEC_MI2S_IBIT 0x10230/* Clock ID for Secondary I2S EBIT */31#define Q6AFE_LPASS_CLK_ID_SEC_MI2S_EBIT 0x10332/* Clock ID for Tertiary I2S IBIT */33#define Q6AFE_LPASS_CLK_ID_TER_MI2S_IBIT 0x10434/* Clock ID for Tertiary I2S EBIT */35#define Q6AFE_LPASS_CLK_ID_TER_MI2S_EBIT 0x10536/* Clock ID for Quartnery I2S IBIT */37#define Q6AFE_LPASS_CLK_ID_QUAD_MI2S_IBIT 0x10638/* Clock ID for Quartnery I2S EBIT */39#define Q6AFE_LPASS_CLK_ID_QUAD_MI2S_EBIT 0x10740/* Clock ID for Speaker I2S IBIT */41#define Q6AFE_LPASS_CLK_ID_SPEAKER_I2S_IBIT 0x10842/* Clock ID for Speaker I2S EBIT */43#define Q6AFE_LPASS_CLK_ID_SPEAKER_I2S_EBIT 0x10944/* Clock ID for Speaker I2S OSR */45#define Q6AFE_LPASS_CLK_ID_SPEAKER_I2S_OSR 0x10A46 47/* Clock ID for QUINARY I2S IBIT */48#define Q6AFE_LPASS_CLK_ID_QUI_MI2S_IBIT 0x10B49/* Clock ID for QUINARY I2S EBIT */50#define Q6AFE_LPASS_CLK_ID_QUI_MI2S_EBIT 0x10C51/* Clock ID for SENARY I2S IBIT */52#define Q6AFE_LPASS_CLK_ID_SEN_MI2S_IBIT 0x10D53/* Clock ID for SENARY I2S EBIT */54#define Q6AFE_LPASS_CLK_ID_SEN_MI2S_EBIT 0x10E55/* Clock ID for INT0 I2S IBIT */56#define Q6AFE_LPASS_CLK_ID_INT0_MI2S_IBIT 0x10F57/* Clock ID for INT1 I2S IBIT */58#define Q6AFE_LPASS_CLK_ID_INT1_MI2S_IBIT 0x11059/* Clock ID for INT2 I2S IBIT */60#define Q6AFE_LPASS_CLK_ID_INT2_MI2S_IBIT 0x11161/* Clock ID for INT3 I2S IBIT */62#define Q6AFE_LPASS_CLK_ID_INT3_MI2S_IBIT 0x11263/* Clock ID for INT4 I2S IBIT */64#define Q6AFE_LPASS_CLK_ID_INT4_MI2S_IBIT 0x11365/* Clock ID for INT5 I2S IBIT */66#define Q6AFE_LPASS_CLK_ID_INT5_MI2S_IBIT 0x11467/* Clock ID for INT6 I2S IBIT */68#define Q6AFE_LPASS_CLK_ID_INT6_MI2S_IBIT 0x11569 70/* Clock ID for QUINARY MI2S OSR CLK */71#define Q6AFE_LPASS_CLK_ID_QUI_MI2S_OSR 0x11672 73/* Clock ID for Primary PCM IBIT */74#define Q6AFE_LPASS_CLK_ID_PRI_PCM_IBIT 0x20075/* Clock ID for Primary PCM EBIT */76#define Q6AFE_LPASS_CLK_ID_PRI_PCM_EBIT 0x20177/* Clock ID for Secondary PCM IBIT */78#define Q6AFE_LPASS_CLK_ID_SEC_PCM_IBIT 0x20279/* Clock ID for Secondary PCM EBIT */80#define Q6AFE_LPASS_CLK_ID_SEC_PCM_EBIT 0x20381/* Clock ID for Tertiary PCM IBIT */82#define Q6AFE_LPASS_CLK_ID_TER_PCM_IBIT 0x20483/* Clock ID for Tertiary PCM EBIT */84#define Q6AFE_LPASS_CLK_ID_TER_PCM_EBIT 0x20585/* Clock ID for Quartery PCM IBIT */86#define Q6AFE_LPASS_CLK_ID_QUAD_PCM_IBIT 0x20687/* Clock ID for Quartery PCM EBIT */88#define Q6AFE_LPASS_CLK_ID_QUAD_PCM_EBIT 0x20789/* Clock ID for Quinary PCM IBIT */90#define Q6AFE_LPASS_CLK_ID_QUIN_PCM_IBIT 0x20891/* Clock ID for Quinary PCM EBIT */92#define Q6AFE_LPASS_CLK_ID_QUIN_PCM_EBIT 0x20993/* Clock ID for QUINARY PCM OSR */94#define Q6AFE_LPASS_CLK_ID_QUI_PCM_OSR 0x20A95 96/** Clock ID for Primary TDM IBIT */97#define Q6AFE_LPASS_CLK_ID_PRI_TDM_IBIT 0x20098/** Clock ID for Primary TDM EBIT */99#define Q6AFE_LPASS_CLK_ID_PRI_TDM_EBIT 0x201100/** Clock ID for Secondary TDM IBIT */101#define Q6AFE_LPASS_CLK_ID_SEC_TDM_IBIT 0x202102/** Clock ID for Secondary TDM EBIT */103#define Q6AFE_LPASS_CLK_ID_SEC_TDM_EBIT 0x203104/** Clock ID for Tertiary TDM IBIT */105#define Q6AFE_LPASS_CLK_ID_TER_TDM_IBIT 0x204106/** Clock ID for Tertiary TDM EBIT */107#define Q6AFE_LPASS_CLK_ID_TER_TDM_EBIT 0x205108/** Clock ID for Quartery TDM IBIT */109#define Q6AFE_LPASS_CLK_ID_QUAD_TDM_IBIT 0x206110/** Clock ID for Quartery TDM EBIT */111#define Q6AFE_LPASS_CLK_ID_QUAD_TDM_EBIT 0x207112/** Clock ID for Quinary TDM IBIT */113#define Q6AFE_LPASS_CLK_ID_QUIN_TDM_IBIT 0x208114/** Clock ID for Quinary TDM EBIT */115#define Q6AFE_LPASS_CLK_ID_QUIN_TDM_EBIT 0x209116/** Clock ID for Quinary TDM OSR */117#define Q6AFE_LPASS_CLK_ID_QUIN_TDM_OSR 0x20A118 119/* Clock ID for MCLK1 */120#define Q6AFE_LPASS_CLK_ID_MCLK_1 0x300121/* Clock ID for MCLK2 */122#define Q6AFE_LPASS_CLK_ID_MCLK_2 0x301123/* Clock ID for MCLK3 */124#define Q6AFE_LPASS_CLK_ID_MCLK_3 0x302125/* Clock ID for MCLK4 */126#define Q6AFE_LPASS_CLK_ID_MCLK_4 0x304127/* Clock ID for Internal Digital Codec Core */128#define Q6AFE_LPASS_CLK_ID_INTERNAL_DIGITAL_CODEC_CORE 0x303129/* Clock ID for INT MCLK0 */130#define Q6AFE_LPASS_CLK_ID_INT_MCLK_0 0x305131/* Clock ID for INT MCLK1 */132#define Q6AFE_LPASS_CLK_ID_INT_MCLK_1 0x306133 134#define Q6AFE_LPASS_CLK_ID_WSA_CORE_MCLK 0x309135#define Q6AFE_LPASS_CLK_ID_WSA_CORE_NPL_MCLK 0x30a136#define Q6AFE_LPASS_CLK_ID_TX_CORE_MCLK 0x30c137#define Q6AFE_LPASS_CLK_ID_TX_CORE_NPL_MCLK 0x30d138#define Q6AFE_LPASS_CLK_ID_RX_CORE_MCLK 0x30e139#define Q6AFE_LPASS_CLK_ID_RX_CORE_NPL_MCLK 0x30f140#define Q6AFE_LPASS_CLK_ID_VA_CORE_MCLK 0x30b141#define Q6AFE_LPASS_CLK_ID_VA_CORE_2X_MCLK 0x310142 143#define Q6AFE_LPASS_CORE_AVTIMER_BLOCK 0x2144#define Q6AFE_LPASS_CORE_HW_MACRO_BLOCK 0x3145#define Q6AFE_LPASS_CORE_HW_DCODEC_BLOCK 0x4146 147/* Clock attribute for invalid use (reserved for internal usage) */148#define Q6AFE_LPASS_CLK_ATTRIBUTE_INVALID 0x0149/* Clock attribute for no couple case */150#define Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO 0x1151/* Clock attribute for dividend couple case */152#define Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_DIVIDEND 0x2153/* Clock attribute for divisor couple case */154#define Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_DIVISOR 0x3155/* Clock attribute for invert and no couple case */156#define Q6AFE_LPASS_CLK_ATTRIBUTE_INVERT_COUPLE_NO 0x4157 158#define Q6AFE_CMAP_INVALID 0xFFFF159 160struct q6afe_hdmi_cfg {161 u16 datatype;162 u16 channel_allocation;163 u32 sample_rate;164 u16 bit_width;165};166 167struct q6afe_slim_cfg {168 u32 sample_rate;169 u16 bit_width;170 u16 data_format;171 u16 num_channels;172 u8 ch_mapping[AFE_MAX_CHAN_COUNT];173};174 175struct q6afe_i2s_cfg {176 u32 sample_rate;177 u16 bit_width;178 u16 data_format;179 u16 num_channels;180 u32 sd_line_mask;181 int fmt;182};183 184struct q6afe_tdm_cfg {185 u16 num_channels;186 u32 sample_rate;187 u16 bit_width;188 u16 data_format;189 u16 sync_mode;190 u16 sync_src;191 u16 nslots_per_frame;192 u16 slot_width;193 u16 slot_mask;194 u32 data_align_type;195 u16 ch_mapping[AFE_MAX_CHAN_COUNT];196};197 198struct q6afe_cdc_dma_cfg {199 u16 sample_rate;200 u16 bit_width;201 u16 data_format;202 u16 num_channels;203 u16 active_channels_mask;204};205 206 207struct q6afe_port_config {208 struct q6afe_hdmi_cfg hdmi;209 struct q6afe_slim_cfg slim;210 struct q6afe_i2s_cfg i2s_cfg;211 struct q6afe_tdm_cfg tdm;212 struct q6afe_cdc_dma_cfg dma_cfg;213};214 215struct q6afe_port;216 217struct q6afe_port *q6afe_port_get_from_id(struct device *dev, int id);218int q6afe_port_start(struct q6afe_port *port);219int q6afe_port_stop(struct q6afe_port *port);220void q6afe_port_put(struct q6afe_port *port);221int q6afe_get_port_id(int index);222void q6afe_hdmi_port_prepare(struct q6afe_port *port,223 struct q6afe_hdmi_cfg *cfg);224void q6afe_slim_port_prepare(struct q6afe_port *port,225 struct q6afe_slim_cfg *cfg);226int q6afe_i2s_port_prepare(struct q6afe_port *port, struct q6afe_i2s_cfg *cfg);227void q6afe_tdm_port_prepare(struct q6afe_port *port, struct q6afe_tdm_cfg *cfg);228void q6afe_cdc_dma_port_prepare(struct q6afe_port *port,229 struct q6afe_cdc_dma_cfg *cfg);230 231int q6afe_port_set_sysclk(struct q6afe_port *port, int clk_id,232 int clk_src, int clk_root,233 unsigned int freq, int dir);234int q6afe_set_lpass_clock(struct device *dev, int clk_id, int attri,235 int clk_root, unsigned int freq);236int q6afe_vote_lpass_core_hw(struct device *dev, uint32_t hw_block_id,237 const char *client_name, uint32_t *client_handle);238int q6afe_unvote_lpass_core_hw(struct device *dev, uint32_t hw_block_id,239 uint32_t client_handle);240#endif /* __Q6AFE_H__ */241