98 lines · c
1/* SPDX-License-Identifier: GPL-2.0 */2 3#ifndef __Q6PRM_H__4#define __Q6PRM_H__5 6/* Clock ID for Primary I2S IBIT */7#define Q6PRM_LPASS_CLK_ID_PRI_MI2S_IBIT 0x1008/* Clock ID for Primary I2S EBIT */9#define Q6PRM_LPASS_CLK_ID_PRI_MI2S_EBIT 0x10110/* Clock ID for Secondary I2S IBIT */11#define Q6PRM_LPASS_CLK_ID_SEC_MI2S_IBIT 0x10212/* Clock ID for Secondary I2S EBIT */13#define Q6PRM_LPASS_CLK_ID_SEC_MI2S_EBIT 0x10314/* Clock ID for Tertiary I2S IBIT */15#define Q6PRM_LPASS_CLK_ID_TER_MI2S_IBIT 0x10416/* Clock ID for Tertiary I2S EBIT */17#define Q6PRM_LPASS_CLK_ID_TER_MI2S_EBIT 0x10518/* Clock ID for Quartnery I2S IBIT */19#define Q6PRM_LPASS_CLK_ID_QUAD_MI2S_IBIT 0x10620/* Clock ID for Quartnery I2S EBIT */21#define Q6PRM_LPASS_CLK_ID_QUAD_MI2S_EBIT 0x10722/* Clock ID for Speaker I2S IBIT */23#define Q6PRM_LPASS_CLK_ID_SPEAKER_I2S_IBIT 0x10824/* Clock ID for Speaker I2S EBIT */25#define Q6PRM_LPASS_CLK_ID_SPEAKER_I2S_EBIT 0x10926/* Clock ID for Speaker I2S OSR */27#define Q6PRM_LPASS_CLK_ID_SPEAKER_I2S_OSR 0x10A28 29/* Clock ID for QUINARY I2S IBIT */30#define Q6PRM_LPASS_CLK_ID_QUI_MI2S_IBIT 0x10B31/* Clock ID for QUINARY I2S EBIT */32#define Q6PRM_LPASS_CLK_ID_QUI_MI2S_EBIT 0x10C33/* Clock ID for SENARY I2S IBIT */34#define Q6PRM_LPASS_CLK_ID_SEN_MI2S_IBIT 0x10D35/* Clock ID for SENARY I2S EBIT */36#define Q6PRM_LPASS_CLK_ID_SEN_MI2S_EBIT 0x10E37/* Clock ID for INT0 I2S IBIT */38#define Q6PRM_LPASS_CLK_ID_INT0_MI2S_IBIT 0x10F39/* Clock ID for INT1 I2S IBIT */40#define Q6PRM_LPASS_CLK_ID_INT1_MI2S_IBIT 0x11041/* Clock ID for INT2 I2S IBIT */42#define Q6PRM_LPASS_CLK_ID_INT2_MI2S_IBIT 0x11143/* Clock ID for INT3 I2S IBIT */44#define Q6PRM_LPASS_CLK_ID_INT3_MI2S_IBIT 0x11245/* Clock ID for INT4 I2S IBIT */46#define Q6PRM_LPASS_CLK_ID_INT4_MI2S_IBIT 0x11347/* Clock ID for INT5 I2S IBIT */48#define Q6PRM_LPASS_CLK_ID_INT5_MI2S_IBIT 0x11449/* Clock ID for INT6 I2S IBIT */50#define Q6PRM_LPASS_CLK_ID_INT6_MI2S_IBIT 0x11551 52/* Clock ID for QUINARY MI2S OSR CLK */53#define Q6PRM_LPASS_CLK_ID_QUI_MI2S_OSR 0x11654 55#define Q6PRM_LPASS_CLK_ID_WSA_CORE_MCLK 0x30556#define Q6PRM_LPASS_CLK_ID_WSA_CORE_NPL_MCLK 0x30657 58#define Q6PRM_LPASS_CLK_ID_VA_CORE_MCLK 0x30759#define Q6PRM_LPASS_CLK_ID_VA_CORE_2X_MCLK 0x30860 61#define Q6PRM_LPASS_CLK_ID_TX_CORE_MCLK 0x30c62#define Q6PRM_LPASS_CLK_ID_TX_CORE_NPL_MCLK 0x30d63 64#define Q6PRM_LPASS_CLK_ID_RX_CORE_MCLK 0x30e65#define Q6PRM_LPASS_CLK_ID_RX_CORE_NPL_MCLK 0x30f66 67/* Clock ID for MCLK for WSA2 core */68#define Q6PRM_LPASS_CLK_ID_WSA2_CORE_MCLK 0x31069/* Clock ID for NPL MCLK for WSA2 core */70#define Q6PRM_LPASS_CLK_ID_WSA2_CORE_2X_MCLK 0x31171/* Clock ID for RX Core TX MCLK */72#define Q6PRM_LPASS_CLK_ID_RX_CORE_TX_MCLK 0x31273/* Clock ID for RX CORE TX 2X MCLK */74#define Q6PRM_LPASS_CLK_ID_RX_CORE_TX_2X_MCLK 0x31375/* Clock ID for WSA core TX MCLK */76#define Q6PRM_LPASS_CLK_ID_WSA_CORE_TX_MCLK 0x31477/* Clock ID for WSA core TX 2X MCLK */78#define Q6PRM_LPASS_CLK_ID_WSA_CORE_TX_2X_MCLK 0x31579/* Clock ID for WSA2 core TX MCLK */80#define Q6PRM_LPASS_CLK_ID_WSA2_CORE_TX_MCLK 0x31681/* Clock ID for WSA2 core TX 2X MCLK */82#define Q6PRM_LPASS_CLK_ID_WSA2_CORE_TX_2X_MCLK 0x31783/* Clock ID for RX CORE MCLK2 2X MCLK */84#define Q6PRM_LPASS_CLK_ID_RX_CORE_MCLK2_2X_MCLK 0x31885 86#define Q6PRM_LPASS_CLK_SRC_INTERNAL 187#define Q6PRM_LPASS_CLK_ROOT_DEFAULT 088#define Q6PRM_HW_CORE_ID_LPASS 189#define Q6PRM_HW_CORE_ID_DCODEC 290 91int q6prm_set_lpass_clock(struct device *dev, int clk_id, int clk_attr,92 int clk_root, unsigned int freq);93int q6prm_vote_lpass_core_hw(struct device *dev, uint32_t hw_block_id,94 const char *client_name, uint32_t *client_handle);95int q6prm_unvote_lpass_core_hw(struct device *dev, uint32_t hw_block_id,96 uint32_t client_handle);97#endif /* __Q6PRM_H__ */98