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1/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */2/*3 * This file is provided under a dual BSD/GPLv2 license. When using or4 * redistributing this file, you may do so under either license.5 *6 * Copyright(c) 2021, 2023, 2024 Advanced Micro Devices, Inc. All rights reserved.7 *8 * Author: Ajit Kumar Pandey <AjitKumar.Pandey@amd.com>9 */10 11#ifndef _ACP_DSP_IP_OFFSET_H12#define _ACP_DSP_IP_OFFSET_H13 14/* Registers from ACP_DMA_0 block */15#define ACP_DMA_CNTL_0 0x0016#define ACP_DMA_DSCR_STRT_IDX_0 0x2017#define ACP_DMA_DSCR_CNT_0 0x4018#define ACP_DMA_PRIO_0 0x6019#define ACP_DMA_CUR_DSCR_0 0x8020#define ACP_DMA_ERR_STS_0 0xC021#define ACP_DMA_DESC_BASE_ADDR 0xE022#define ACP_DMA_DESC_MAX_NUM_DSCR 0xE423#define ACP_DMA_CH_STS 0xE824#define ACP_DMA_CH_GROUP 0xEC25#define ACP_DMA_CH_RST_STS 0xF026#define ACP70_DMA_CNTL_0 0x0027#define ACP70_DMA_DSCR_STRT_IDX_0 0x2828#define ACP70_DMA_DSCR_CNT_0 0x5029#define ACP70_DMA_PRIO_0 0x7830#define ACP70_DMA_CUR_DSCR_0 0xA031#define ACP70_DMA_ERR_STS_0 0xF032#define ACP70_DMA_DESC_BASE_ADDR 0x11833#define ACP70_DMA_DESC_MAX_NUM_DSCR 0x11C34#define ACP70_DMA_CH_STS 0x12035#define ACP70_DMA_CH_GROUP 0x12436#define ACP70_DMA_CH_RST_STS 0x12837 38/* Registers from ACP_DSP_0 block */39#define ACP_DSP0_RUNSTALL 0x41440 41/* Registers from ACP_AXI2AXIATU block */42#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_1 0xC0043#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_1 0xC0444#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_2 0xC0845#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_2 0xC0C46#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_3 0xC1047#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_3 0xC1448#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_4 0xC1849#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_4 0xC1C50#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_5 0xC2051#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_5 0xC2452#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_6 0xC2853#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_6 0xC2C54#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_7 0xC3055#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_7 0xC3456#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_8 0xC3857#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_8 0xC3C58#define ACPAXI2AXI_ATU_CTRL 0xC4059#define ACP_SOFT_RESET 0x100060#define ACP_CONTROL 0x100461 62#define ACP3X_I2S_PIN_CONFIG 0x140063#define ACP5X_I2S_PIN_CONFIG 0x140064#define ACP6X_I2S_PIN_CONFIG 0x144065 66/* Registers offsets from ACP_PGFSM block */67#define ACP3X_PGFSM_BASE 0x141C68#define ACP5X_PGFSM_BASE 0x142469#define ACP6X_PGFSM_BASE 0x102470#define ACP70_PGFSM_BASE ACP6X_PGFSM_BASE71#define PGFSM_CONTROL_OFFSET 0x072#define PGFSM_STATUS_OFFSET 0x473#define ACP3X_CLKMUX_SEL 0x142474#define ACP5X_CLKMUX_SEL 0x142C75#define ACP6X_CLKMUX_SEL 0x102C76#define ACP70_CLKMUX_SEL ACP6X_CLKMUX_SEL77 78/* Registers from ACP_INTR block */79#define ACP3X_EXT_INTR_STAT 0x180880#define ACP5X_EXT_INTR_STAT 0x180881#define ACP6X_EXTERNAL_INTR_ENB 0x1A0082#define ACP6X_EXTERNAL_INTR_CNTL 0x1A0483#define ACP6X_EXT_INTR_STAT 0x1A0C84#define ACP6X_EXT_INTR_STAT1 0x1A1085#define ACP70_EXTERNAL_INTR_ENB ACP6X_EXTERNAL_INTR_ENB86#define ACP70_EXTERNAL_INTR_CNTL ACP6X_EXTERNAL_INTR_CNTL87#define ACP70_EXT_INTR_STAT ACP6X_EXT_INTR_STAT88#define ACP70_EXT_INTR_STAT1 ACP6X_EXT_INTR_STAT189 90#define ACP3X_DSP_SW_INTR_BASE 0x181491#define ACP5X_DSP_SW_INTR_BASE 0x181492#define ACP6X_DSP_SW_INTR_BASE 0x180893#define ACP70_DSP_SW_INTR_BASE ACP6X_DSP_SW_INTR_BASE94#define DSP_SW_INTR_CNTL_OFFSET 0x095#define DSP_SW_INTR_STAT_OFFSET 0x496#define DSP_SW_INTR_TRIG_OFFSET 0x897#define ACP3X_ERROR_STATUS 0x18C498#define ACP6X_ERROR_STATUS 0x1A4C99#define ACP70_ERROR_STATUS ACP6X_ERROR_STATUS100#define ACP3X_AXI2DAGB_SEM_0 0x1880101#define ACP5X_AXI2DAGB_SEM_0 0x1884102#define ACP6X_AXI2DAGB_SEM_0 0x1874103#define ACP70_AXI2DAGB_SEM_0 ACP6X_AXI2DAGB_SEM_0104 105/* ACP common registers to report errors related to I2S & SoundWire interfaces */106#define ACP3X_SW_I2S_ERROR_REASON 0x18C8107#define ACP6X_SW0_I2S_ERROR_REASON 0x18B4108#define ACP7X_SW0_I2S_ERROR_REASON ACP6X_SW0_I2S_ERROR_REASON109#define ACP_SW1_I2S_ERROR_REASON 0x1A50110 111/* Registers from ACP_SHA block */112#define ACP_SHA_DSP_FW_QUALIFIER 0x1C70113#define ACP_SHA_DMA_CMD 0x1CB0114#define ACP_SHA_MSG_LENGTH 0x1CB4115#define ACP_SHA_DMA_STRT_ADDR 0x1CB8116#define ACP_SHA_DMA_DESTINATION_ADDR 0x1CBC117#define ACP_SHA_DMA_CMD_STS 0x1CC0118#define ACP_SHA_DMA_ERR_STATUS 0x1CC4119#define ACP_SHA_TRANSFER_BYTE_CNT 0x1CC8120#define ACP_SHA_DMA_INCLUDE_HDR 0x1CCC121#define ACP_SHA_PSP_ACK 0x1C74122 123#define ACP_SCRATCH_REG_0 0x10000124#define ACP6X_DSP_FUSION_RUNSTALL 0x0644125#define ACP70_DSP_FUSION_RUNSTALL ACP6X_DSP_FUSION_RUNSTALL126 127/* Cache window registers */128#define ACP_DSP0_CACHE_OFFSET0 0x0420129#define ACP_DSP0_CACHE_SIZE0 0x0424130 131#define ACP_SW0_EN 0x3000132#define ACP_SW1_EN 0x3C00133#endif134