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1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)2//3// This file is provided under a dual BSD/GPLv2 license. When using or4// redistributing this file, you may do so under either license.5//6// Copyright(c) 2021, 2023 Advanced Micro Devices, Inc. All rights reserved.7//8// Authors: Vijendar Mukunda <Vijendar.Mukunda@amd.com>9// Ajit Kumar Pandey <AjitKumar.Pandey@amd.com>10 11/*12 * Hardware interface for generic AMD ACP processor13 */14 15#include <linux/io.h>16#include <linux/module.h>17#include <linux/pci.h>18 19#include "../ops.h"20#include "acp.h"21#include "acp-dsp-offset.h"22 23static bool enable_fw_debug;24module_param(enable_fw_debug, bool, 0444);25MODULE_PARM_DESC(enable_fw_debug, "Enable Firmware debug");26 27static struct acp_quirk_entry quirk_valve_galileo = {28 .signed_fw_image = true,29 .skip_iram_dram_size_mod = true,30};31 32const struct dmi_system_id acp_sof_quirk_table[] = {33 {34 /* Steam Deck OLED device */35 .matches = {36 DMI_MATCH(DMI_SYS_VENDOR, "Valve"),37 DMI_MATCH(DMI_PRODUCT_NAME, "Galileo"),38 },39 .driver_data = &quirk_valve_galileo,40 },41 {}42};43EXPORT_SYMBOL_GPL(acp_sof_quirk_table);44 45static int smn_write(struct pci_dev *dev, u32 smn_addr, u32 data)46{47 pci_write_config_dword(dev, 0x60, smn_addr);48 pci_write_config_dword(dev, 0x64, data);49 50 return 0;51}52 53static int smn_read(struct pci_dev *dev, u32 smn_addr)54{55 u32 data = 0;56 57 pci_write_config_dword(dev, 0x60, smn_addr);58 pci_read_config_dword(dev, 0x64, &data);59 60 return data;61}62 63static void init_dma_descriptor(struct acp_dev_data *adata)64{65 struct snd_sof_dev *sdev = adata->dev;66 const struct sof_amd_acp_desc *desc = get_chip_info(sdev->pdata);67 struct acp_dev_data *acp_data = sdev->pdata->hw_pdata;68 unsigned int addr;69 unsigned int acp_dma_desc_base_addr, acp_dma_desc_max_num_dscr;70 71 addr = desc->sram_pte_offset + sdev->debug_box.offset +72 offsetof(struct scratch_reg_conf, dma_desc);73 74 switch (acp_data->pci_rev) {75 case ACP70_PCI_ID:76 acp_dma_desc_base_addr = ACP70_DMA_DESC_BASE_ADDR;77 acp_dma_desc_max_num_dscr = ACP70_DMA_DESC_MAX_NUM_DSCR;78 break;79 default:80 acp_dma_desc_base_addr = ACP_DMA_DESC_BASE_ADDR;81 acp_dma_desc_max_num_dscr = ACP_DMA_DESC_MAX_NUM_DSCR;82 }83 snd_sof_dsp_write(sdev, ACP_DSP_BAR, acp_dma_desc_base_addr, addr);84 snd_sof_dsp_write(sdev, ACP_DSP_BAR, acp_dma_desc_max_num_dscr, ACP_MAX_DESC_CNT);85}86 87static void configure_dma_descriptor(struct acp_dev_data *adata, unsigned short idx,88 struct dma_descriptor *dscr_info)89{90 struct snd_sof_dev *sdev = adata->dev;91 unsigned int offset;92 93 offset = ACP_SCRATCH_REG_0 + sdev->debug_box.offset +94 offsetof(struct scratch_reg_conf, dma_desc) +95 idx * sizeof(struct dma_descriptor);96 97 snd_sof_dsp_write(sdev, ACP_DSP_BAR, offset, dscr_info->src_addr);98 snd_sof_dsp_write(sdev, ACP_DSP_BAR, offset + 0x4, dscr_info->dest_addr);99 snd_sof_dsp_write(sdev, ACP_DSP_BAR, offset + 0x8, dscr_info->tx_cnt.u32_all);100}101 102static int config_dma_channel(struct acp_dev_data *adata, unsigned int ch,103 unsigned int idx, unsigned int dscr_count)104{105 struct snd_sof_dev *sdev = adata->dev;106 struct acp_dev_data *acp_data = sdev->pdata->hw_pdata;107 const struct sof_amd_acp_desc *desc = get_chip_info(sdev->pdata);108 unsigned int val, status;109 unsigned int acp_dma_cntl_0, acp_dma_ch_rst_sts, acp_dma_dscr_err_sts_0;110 unsigned int acp_dma_dscr_cnt_0, acp_dma_prio_0, acp_dma_dscr_strt_idx_0;111 int ret;112 113 switch (acp_data->pci_rev) {114 case ACP70_PCI_ID:115 acp_dma_cntl_0 = ACP70_DMA_CNTL_0;116 acp_dma_ch_rst_sts = ACP70_DMA_CH_RST_STS;117 acp_dma_dscr_err_sts_0 = ACP70_DMA_ERR_STS_0;118 acp_dma_dscr_cnt_0 = ACP70_DMA_DSCR_CNT_0;119 acp_dma_prio_0 = ACP70_DMA_PRIO_0;120 acp_dma_dscr_strt_idx_0 = ACP70_DMA_DSCR_STRT_IDX_0;121 break;122 default:123 acp_dma_cntl_0 = ACP_DMA_CNTL_0;124 acp_dma_ch_rst_sts = ACP_DMA_CH_RST_STS;125 acp_dma_dscr_err_sts_0 = ACP_DMA_ERR_STS_0;126 acp_dma_dscr_cnt_0 = ACP_DMA_DSCR_CNT_0;127 acp_dma_prio_0 = ACP_DMA_PRIO_0;128 acp_dma_dscr_strt_idx_0 = ACP_DMA_DSCR_STRT_IDX_0;129 }130 131 snd_sof_dsp_write(sdev, ACP_DSP_BAR, acp_dma_cntl_0 + ch * sizeof(u32),132 ACP_DMA_CH_RST | ACP_DMA_CH_GRACEFUL_RST_EN);133 134 ret = snd_sof_dsp_read_poll_timeout(sdev, ACP_DSP_BAR, acp_dma_ch_rst_sts, val,135 val & (1 << ch), ACP_REG_POLL_INTERVAL,136 ACP_REG_POLL_TIMEOUT_US);137 if (ret < 0) {138 status = snd_sof_dsp_read(sdev, ACP_DSP_BAR, desc->acp_error_stat);139 val = snd_sof_dsp_read(sdev, ACP_DSP_BAR, acp_dma_dscr_err_sts_0 +140 ch * sizeof(u32));141 142 dev_err(sdev->dev, "ACP_DMA_ERR_STS :0x%x ACP_ERROR_STATUS :0x%x\n", val, status);143 return ret;144 }145 146 snd_sof_dsp_write(sdev, ACP_DSP_BAR, (acp_dma_cntl_0 + ch * sizeof(u32)), 0);147 snd_sof_dsp_write(sdev, ACP_DSP_BAR, acp_dma_dscr_cnt_0 + ch * sizeof(u32), dscr_count);148 snd_sof_dsp_write(sdev, ACP_DSP_BAR, acp_dma_dscr_strt_idx_0 + ch * sizeof(u32), idx);149 snd_sof_dsp_write(sdev, ACP_DSP_BAR, acp_dma_prio_0 + ch * sizeof(u32), 0);150 snd_sof_dsp_write(sdev, ACP_DSP_BAR, acp_dma_cntl_0 + ch * sizeof(u32), ACP_DMA_CH_RUN);151 152 return ret;153}154 155static int acpbus_dma_start(struct acp_dev_data *adata, unsigned int ch,156 unsigned int dscr_count, struct dma_descriptor *dscr_info)157{158 struct snd_sof_dev *sdev = adata->dev;159 int ret;160 u16 dscr;161 162 if (!dscr_info || !dscr_count)163 return -EINVAL;164 165 for (dscr = 0; dscr < dscr_count; dscr++)166 configure_dma_descriptor(adata, dscr, dscr_info++);167 168 ret = config_dma_channel(adata, ch, 0, dscr_count);169 if (ret < 0)170 dev_err(sdev->dev, "config dma ch failed:%d\n", ret);171 172 return ret;173}174 175int configure_and_run_dma(struct acp_dev_data *adata, unsigned int src_addr,176 unsigned int dest_addr, int dsp_data_size)177{178 struct snd_sof_dev *sdev = adata->dev;179 unsigned int desc_count, index;180 int ret;181 182 for (desc_count = 0; desc_count < ACP_MAX_DESC && dsp_data_size >= 0;183 desc_count++, dsp_data_size -= ACP_PAGE_SIZE) {184 adata->dscr_info[desc_count].src_addr = src_addr + desc_count * ACP_PAGE_SIZE;185 adata->dscr_info[desc_count].dest_addr = dest_addr + desc_count * ACP_PAGE_SIZE;186 adata->dscr_info[desc_count].tx_cnt.bits.count = ACP_PAGE_SIZE;187 if (dsp_data_size < ACP_PAGE_SIZE)188 adata->dscr_info[desc_count].tx_cnt.bits.count = dsp_data_size;189 }190 191 ret = acpbus_dma_start(adata, 0, desc_count, adata->dscr_info);192 if (ret)193 dev_err(sdev->dev, "acpbus_dma_start failed\n");194 195 /* Clear descriptor array */196 for (index = 0; index < desc_count; index++)197 memset(&adata->dscr_info[index], 0x00, sizeof(struct dma_descriptor));198 199 return ret;200}201 202/*203 * psp_mbox_ready- function to poll ready bit of psp mbox204 * @adata: acp device data205 * @ack: bool variable to check ready bit status or psp ack206 */207 208static int psp_mbox_ready(struct acp_dev_data *adata, bool ack)209{210 struct snd_sof_dev *sdev = adata->dev;211 int ret;212 u32 data;213 214 ret = read_poll_timeout(smn_read, data, data & MBOX_READY_MASK, MBOX_DELAY_US,215 ACP_PSP_TIMEOUT_US, false, adata->smn_dev, MP0_C2PMSG_114_REG);216 if (!ret)217 return 0;218 219 dev_err(sdev->dev, "PSP error status %x\n", data & MBOX_STATUS_MASK);220 221 if (ack)222 return -ETIMEDOUT;223 224 return -EBUSY;225}226 227/*228 * psp_send_cmd - function to send psp command over mbox229 * @adata: acp device data230 * @cmd: non zero integer value for command type231 */232 233static int psp_send_cmd(struct acp_dev_data *adata, int cmd)234{235 struct snd_sof_dev *sdev = adata->dev;236 int ret;237 u32 data;238 239 if (!cmd)240 return -EINVAL;241 242 /* Get a non-zero Doorbell value from PSP */243 ret = read_poll_timeout(smn_read, data, data, MBOX_DELAY_US, ACP_PSP_TIMEOUT_US, false,244 adata->smn_dev, MP0_C2PMSG_73_REG);245 246 if (ret) {247 dev_err(sdev->dev, "Failed to get Doorbell from MBOX %x\n", MP0_C2PMSG_73_REG);248 return ret;249 }250 251 /* Check if PSP is ready for new command */252 ret = psp_mbox_ready(adata, 0);253 if (ret)254 return ret;255 256 smn_write(adata->smn_dev, MP0_C2PMSG_114_REG, cmd);257 258 /* Ring the Doorbell for PSP */259 smn_write(adata->smn_dev, MP0_C2PMSG_73_REG, data);260 261 /* Check MBOX ready as PSP ack */262 ret = psp_mbox_ready(adata, 1);263 264 return ret;265}266 267int configure_and_run_sha_dma(struct acp_dev_data *adata, void *image_addr,268 unsigned int start_addr, unsigned int dest_addr,269 unsigned int image_length)270{271 struct snd_sof_dev *sdev = adata->dev;272 unsigned int tx_count, fw_qualifier, val;273 int ret;274 275 if (!image_addr) {276 dev_err(sdev->dev, "SHA DMA image address is NULL\n");277 return -EINVAL;278 }279 280 val = snd_sof_dsp_read(sdev, ACP_DSP_BAR, ACP_SHA_DMA_CMD);281 if (val & ACP_SHA_RUN) {282 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SHA_DMA_CMD, ACP_SHA_RESET);283 ret = snd_sof_dsp_read_poll_timeout(sdev, ACP_DSP_BAR, ACP_SHA_DMA_CMD_STS,284 val, val & ACP_SHA_RESET,285 ACP_REG_POLL_INTERVAL,286 ACP_REG_POLL_TIMEOUT_US);287 if (ret < 0) {288 dev_err(sdev->dev, "SHA DMA Failed to Reset\n");289 return ret;290 }291 }292 293 if (adata->quirks && adata->quirks->signed_fw_image)294 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SHA_DMA_INCLUDE_HDR, ACP_SHA_HEADER);295 296 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SHA_DMA_STRT_ADDR, start_addr);297 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SHA_DMA_DESTINATION_ADDR, dest_addr);298 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SHA_MSG_LENGTH, image_length);299 300 /* psp_send_cmd only required for vangogh platform */301 if (adata->pci_rev == ACP_VANGOGH_PCI_ID &&302 !(adata->quirks && adata->quirks->skip_iram_dram_size_mod)) {303 /* Modify IRAM and DRAM size */304 ret = psp_send_cmd(adata, MBOX_ACP_IRAM_DRAM_FENCE_COMMAND | IRAM_DRAM_FENCE_2);305 if (ret)306 return ret;307 ret = psp_send_cmd(adata, MBOX_ACP_IRAM_DRAM_FENCE_COMMAND | MBOX_ISREADY_FLAG);308 if (ret)309 return ret;310 }311 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SHA_DMA_CMD, ACP_SHA_RUN);312 313 ret = snd_sof_dsp_read_poll_timeout(sdev, ACP_DSP_BAR, ACP_SHA_TRANSFER_BYTE_CNT,314 tx_count, tx_count == image_length,315 ACP_REG_POLL_INTERVAL, ACP_DMA_COMPLETE_TIMEOUT_US);316 if (ret < 0) {317 dev_err(sdev->dev, "SHA DMA Failed to Transfer Length %x\n", tx_count);318 return ret;319 }320 321 /* psp_send_cmd only required for renoir platform*/322 if (adata->pci_rev == ACP_RN_PCI_ID) {323 ret = psp_send_cmd(adata, MBOX_ACP_SHA_DMA_COMMAND);324 if (ret)325 return ret;326 }327 328 ret = snd_sof_dsp_read_poll_timeout(sdev, ACP_DSP_BAR, ACP_SHA_DSP_FW_QUALIFIER,329 fw_qualifier, fw_qualifier & DSP_FW_RUN_ENABLE,330 ACP_REG_POLL_INTERVAL, ACP_DMA_COMPLETE_TIMEOUT_US);331 if (ret < 0) {332 val = snd_sof_dsp_read(sdev, ACP_DSP_BAR, ACP_SHA_PSP_ACK);333 dev_err(sdev->dev, "PSP validation failed: fw_qualifier = %#x, ACP_SHA_PSP_ACK = %#x\n",334 fw_qualifier, val);335 return ret;336 }337 338 return 0;339}340 341int acp_dma_status(struct acp_dev_data *adata, unsigned char ch)342{343 struct snd_sof_dev *sdev = adata->dev;344 unsigned int val;345 unsigned int acp_dma_ch_sts;346 int ret = 0;347 348 switch (adata->pci_rev) {349 case ACP70_PCI_ID:350 acp_dma_ch_sts = ACP70_DMA_CH_STS;351 break;352 default:353 acp_dma_ch_sts = ACP_DMA_CH_STS;354 }355 val = snd_sof_dsp_read(sdev, ACP_DSP_BAR, ACP_DMA_CNTL_0 + ch * sizeof(u32));356 if (val & ACP_DMA_CH_RUN) {357 ret = snd_sof_dsp_read_poll_timeout(sdev, ACP_DSP_BAR, acp_dma_ch_sts, val, !val,358 ACP_REG_POLL_INTERVAL,359 ACP_DMA_COMPLETE_TIMEOUT_US);360 if (ret < 0)361 dev_err(sdev->dev, "DMA_CHANNEL %d status timeout\n", ch);362 }363 364 return ret;365}366 367void memcpy_from_scratch(struct snd_sof_dev *sdev, u32 offset, unsigned int *dst, size_t bytes)368{369 unsigned int reg_offset = offset + ACP_SCRATCH_REG_0;370 int i, j;371 372 for (i = 0, j = 0; i < bytes; i = i + 4, j++)373 dst[j] = snd_sof_dsp_read(sdev, ACP_DSP_BAR, reg_offset + i);374}375 376void memcpy_to_scratch(struct snd_sof_dev *sdev, u32 offset, unsigned int *src, size_t bytes)377{378 unsigned int reg_offset = offset + ACP_SCRATCH_REG_0;379 int i, j;380 381 for (i = 0, j = 0; i < bytes; i = i + 4, j++)382 snd_sof_dsp_write(sdev, ACP_DSP_BAR, reg_offset + i, src[j]);383}384 385static int acp_memory_init(struct snd_sof_dev *sdev)386{387 struct acp_dev_data *adata = sdev->pdata->hw_pdata;388 const struct sof_amd_acp_desc *desc = get_chip_info(sdev->pdata);389 390 snd_sof_dsp_update_bits(sdev, ACP_DSP_BAR, desc->dsp_intr_base + DSP_SW_INTR_CNTL_OFFSET,391 ACP_DSP_INTR_EN_MASK, ACP_DSP_INTR_EN_MASK);392 init_dma_descriptor(adata);393 394 return 0;395}396 397static irqreturn_t acp_irq_thread(int irq, void *context)398{399 struct snd_sof_dev *sdev = context;400 const struct sof_amd_acp_desc *desc = get_chip_info(sdev->pdata);401 unsigned int count = ACP_HW_SEM_RETRY_COUNT;402 403 spin_lock_irq(&sdev->ipc_lock);404 /* Wait until acquired HW Semaphore lock or timeout */405 while (snd_sof_dsp_read(sdev, ACP_DSP_BAR, desc->hw_semaphore_offset) && --count)406 ;407 spin_unlock_irq(&sdev->ipc_lock);408 409 if (!count) {410 dev_err(sdev->dev, "%s: Failed to acquire HW lock\n", __func__);411 return IRQ_NONE;412 }413 414 sof_ops(sdev)->irq_thread(irq, sdev);415 /* Unlock or Release HW Semaphore */416 snd_sof_dsp_write(sdev, ACP_DSP_BAR, desc->hw_semaphore_offset, 0x0);417 418 return IRQ_HANDLED;419};420 421static irqreturn_t acp_irq_handler(int irq, void *dev_id)422{423 struct amd_sdw_manager *amd_manager;424 struct snd_sof_dev *sdev = dev_id;425 const struct sof_amd_acp_desc *desc = get_chip_info(sdev->pdata);426 struct acp_dev_data *adata = sdev->pdata->hw_pdata;427 unsigned int base = desc->dsp_intr_base;428 unsigned int val;429 int irq_flag = 0;430 431 val = snd_sof_dsp_read(sdev, ACP_DSP_BAR, base + DSP_SW_INTR_STAT_OFFSET);432 if (val & ACP_DSP_TO_HOST_IRQ) {433 snd_sof_dsp_write(sdev, ACP_DSP_BAR, base + DSP_SW_INTR_STAT_OFFSET,434 ACP_DSP_TO_HOST_IRQ);435 return IRQ_WAKE_THREAD;436 }437 438 val = snd_sof_dsp_read(sdev, ACP_DSP_BAR, desc->ext_intr_stat);439 if (val & ACP_SDW0_IRQ_MASK) {440 amd_manager = dev_get_drvdata(&adata->sdw->pdev[0]->dev);441 snd_sof_dsp_write(sdev, ACP_DSP_BAR, desc->ext_intr_stat, ACP_SDW0_IRQ_MASK);442 if (amd_manager)443 schedule_work(&amd_manager->amd_sdw_irq_thread);444 irq_flag = 1;445 }446 447 if (val & ACP_ERROR_IRQ_MASK) {448 snd_sof_dsp_write(sdev, ACP_DSP_BAR, desc->ext_intr_stat, ACP_ERROR_IRQ_MASK);449 snd_sof_dsp_write(sdev, ACP_DSP_BAR, desc->acp_sw0_i2s_err_reason, 0);450 /* ACP_SW1_I2S_ERROR_REASON is newly added register from rmb platform onwards */451 if (adata->pci_rev >= ACP_RMB_PCI_ID)452 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SW1_I2S_ERROR_REASON, 0);453 snd_sof_dsp_write(sdev, ACP_DSP_BAR, desc->acp_error_stat, 0);454 irq_flag = 1;455 }456 457 if (desc->ext_intr_stat1) {458 val = snd_sof_dsp_read(sdev, ACP_DSP_BAR, desc->ext_intr_stat1);459 if (val & ACP_SDW1_IRQ_MASK) {460 amd_manager = dev_get_drvdata(&adata->sdw->pdev[1]->dev);461 snd_sof_dsp_write(sdev, ACP_DSP_BAR, desc->ext_intr_stat1,462 ACP_SDW1_IRQ_MASK);463 if (amd_manager)464 schedule_work(&amd_manager->amd_sdw_irq_thread);465 irq_flag = 1;466 }467 }468 if (irq_flag)469 return IRQ_HANDLED;470 else471 return IRQ_NONE;472}473 474static int acp_power_on(struct snd_sof_dev *sdev)475{476 const struct sof_amd_acp_desc *desc = get_chip_info(sdev->pdata);477 struct acp_dev_data *adata = sdev->pdata->hw_pdata;478 unsigned int base = desc->pgfsm_base;479 unsigned int val;480 unsigned int acp_pgfsm_status_mask, acp_pgfsm_cntl_mask;481 int ret;482 483 val = snd_sof_dsp_read(sdev, ACP_DSP_BAR, base + PGFSM_STATUS_OFFSET);484 485 if (val == ACP_POWERED_ON)486 return 0;487 488 switch (adata->pci_rev) {489 case ACP_RN_PCI_ID:490 case ACP_VANGOGH_PCI_ID:491 acp_pgfsm_status_mask = ACP3X_PGFSM_STATUS_MASK;492 acp_pgfsm_cntl_mask = ACP3X_PGFSM_CNTL_POWER_ON_MASK;493 break;494 case ACP_RMB_PCI_ID:495 case ACP63_PCI_ID:496 acp_pgfsm_status_mask = ACP6X_PGFSM_STATUS_MASK;497 acp_pgfsm_cntl_mask = ACP6X_PGFSM_CNTL_POWER_ON_MASK;498 break;499 case ACP70_PCI_ID:500 acp_pgfsm_status_mask = ACP70_PGFSM_STATUS_MASK;501 acp_pgfsm_cntl_mask = ACP70_PGFSM_CNTL_POWER_ON_MASK;502 break;503 default:504 return -EINVAL;505 }506 507 if (val & acp_pgfsm_status_mask)508 snd_sof_dsp_write(sdev, ACP_DSP_BAR, base + PGFSM_CONTROL_OFFSET,509 acp_pgfsm_cntl_mask);510 511 ret = snd_sof_dsp_read_poll_timeout(sdev, ACP_DSP_BAR, base + PGFSM_STATUS_OFFSET, val,512 !val, ACP_REG_POLL_INTERVAL, ACP_REG_POLL_TIMEOUT_US);513 if (ret < 0)514 dev_err(sdev->dev, "timeout in ACP_PGFSM_STATUS read\n");515 516 return ret;517}518 519static int acp_reset(struct snd_sof_dev *sdev)520{521 const struct sof_amd_acp_desc *desc = get_chip_info(sdev->pdata);522 unsigned int val;523 int ret;524 525 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SOFT_RESET, ACP_ASSERT_RESET);526 527 ret = snd_sof_dsp_read_poll_timeout(sdev, ACP_DSP_BAR, ACP_SOFT_RESET, val,528 val & ACP_SOFT_RESET_DONE_MASK,529 ACP_REG_POLL_INTERVAL, ACP_REG_POLL_TIMEOUT_US);530 if (ret < 0) {531 dev_err(sdev->dev, "timeout asserting reset\n");532 return ret;533 }534 535 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SOFT_RESET, ACP_RELEASE_RESET);536 537 ret = snd_sof_dsp_read_poll_timeout(sdev, ACP_DSP_BAR, ACP_SOFT_RESET, val, !val,538 ACP_REG_POLL_INTERVAL, ACP_REG_POLL_TIMEOUT_US);539 if (ret < 0)540 dev_err(sdev->dev, "timeout in releasing reset\n");541 542 if (desc->acp_clkmux_sel)543 snd_sof_dsp_write(sdev, ACP_DSP_BAR, desc->acp_clkmux_sel, ACP_CLOCK_ACLK);544 545 if (desc->ext_intr_enb)546 snd_sof_dsp_write(sdev, ACP_DSP_BAR, desc->ext_intr_enb, 0x01);547 548 if (desc->ext_intr_cntl)549 snd_sof_dsp_write(sdev, ACP_DSP_BAR, desc->ext_intr_cntl, ACP_ERROR_IRQ_MASK);550 return ret;551}552 553static int acp_dsp_reset(struct snd_sof_dev *sdev)554{555 unsigned int val;556 int ret;557 558 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SOFT_RESET, ACP_DSP_ASSERT_RESET);559 560 ret = snd_sof_dsp_read_poll_timeout(sdev, ACP_DSP_BAR, ACP_SOFT_RESET, val,561 val & ACP_DSP_SOFT_RESET_DONE_MASK,562 ACP_REG_POLL_INTERVAL, ACP_REG_POLL_TIMEOUT_US);563 if (ret < 0) {564 dev_err(sdev->dev, "timeout asserting reset\n");565 return ret;566 }567 568 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SOFT_RESET, ACP_DSP_RELEASE_RESET);569 570 ret = snd_sof_dsp_read_poll_timeout(sdev, ACP_DSP_BAR, ACP_SOFT_RESET, val, !val,571 ACP_REG_POLL_INTERVAL, ACP_REG_POLL_TIMEOUT_US);572 if (ret < 0)573 dev_err(sdev->dev, "timeout in releasing reset\n");574 575 return ret;576}577 578static int acp_init(struct snd_sof_dev *sdev)579{580 int ret;581 582 /* power on */583 ret = acp_power_on(sdev);584 if (ret) {585 dev_err(sdev->dev, "ACP power on failed\n");586 return ret;587 }588 589 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_CONTROL, 0x01);590 /* Reset */591 return acp_reset(sdev);592}593 594static bool check_acp_sdw_enable_status(struct snd_sof_dev *sdev)595{596 struct acp_dev_data *acp_data;597 u32 sdw0_en, sdw1_en;598 599 acp_data = sdev->pdata->hw_pdata;600 if (!acp_data->sdw)601 return false;602 603 sdw0_en = snd_sof_dsp_read(sdev, ACP_DSP_BAR, ACP_SW0_EN);604 sdw1_en = snd_sof_dsp_read(sdev, ACP_DSP_BAR, ACP_SW1_EN);605 acp_data->sdw_en_stat = sdw0_en || sdw1_en;606 return acp_data->sdw_en_stat;607}608 609int amd_sof_acp_suspend(struct snd_sof_dev *sdev, u32 target_state)610{611 struct acp_dev_data *acp_data;612 int ret;613 bool enable = false;614 615 acp_data = sdev->pdata->hw_pdata;616 /* When acp_reset() function is invoked, it will apply ACP SOFT reset and617 * DSP reset. ACP Soft reset sequence will cause all ACP IP registers will618 * be reset to default values which will break the ClockStop Mode functionality.619 * Add a condition check to apply DSP reset when SoundWire ClockStop mode620 * is selected. For the rest of the scenarios, apply acp reset sequence.621 */622 if (check_acp_sdw_enable_status(sdev))623 return acp_dsp_reset(sdev);624 625 ret = acp_reset(sdev);626 if (ret) {627 dev_err(sdev->dev, "ACP Reset failed\n");628 return ret;629 }630 if (acp_data->pci_rev == ACP70_PCI_ID)631 enable = true;632 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_CONTROL, enable);633 634 return 0;635}636EXPORT_SYMBOL_NS(amd_sof_acp_suspend, SND_SOC_SOF_AMD_COMMON);637 638int amd_sof_acp_resume(struct snd_sof_dev *sdev)639{640 int ret;641 struct acp_dev_data *acp_data;642 643 acp_data = sdev->pdata->hw_pdata;644 if (!acp_data->sdw_en_stat) {645 ret = acp_init(sdev);646 if (ret) {647 dev_err(sdev->dev, "ACP Init failed\n");648 return ret;649 }650 return acp_memory_init(sdev);651 } else {652 return acp_dsp_reset(sdev);653 }654}655EXPORT_SYMBOL_NS(amd_sof_acp_resume, SND_SOC_SOF_AMD_COMMON);656 657#if IS_ENABLED(CONFIG_SND_SOC_SOF_AMD_SOUNDWIRE)658static int acp_sof_scan_sdw_devices(struct snd_sof_dev *sdev, u64 addr)659{660 struct acpi_device *sdw_dev;661 struct acp_dev_data *acp_data;662 const struct sof_amd_acp_desc *desc = get_chip_info(sdev->pdata);663 664 if (!addr)665 return -ENODEV;666 667 acp_data = sdev->pdata->hw_pdata;668 sdw_dev = acpi_find_child_device(ACPI_COMPANION(sdev->dev), addr, 0);669 if (!sdw_dev)670 return -ENODEV;671 672 acp_data->info.handle = sdw_dev->handle;673 acp_data->info.count = desc->sdw_max_link_count;674 675 return amd_sdw_scan_controller(&acp_data->info);676}677 678static int amd_sof_sdw_probe(struct snd_sof_dev *sdev)679{680 struct acp_dev_data *acp_data;681 struct sdw_amd_res sdw_res;682 int ret;683 684 acp_data = sdev->pdata->hw_pdata;685 686 memset(&sdw_res, 0, sizeof(sdw_res));687 sdw_res.addr = acp_data->addr;688 sdw_res.reg_range = acp_data->reg_range;689 sdw_res.handle = acp_data->info.handle;690 sdw_res.parent = sdev->dev;691 sdw_res.dev = sdev->dev;692 sdw_res.acp_lock = &acp_data->acp_lock;693 sdw_res.count = acp_data->info.count;694 sdw_res.link_mask = acp_data->info.link_mask;695 sdw_res.mmio_base = sdev->bar[ACP_DSP_BAR];696 697 ret = sdw_amd_probe(&sdw_res, &acp_data->sdw);698 if (ret)699 dev_err(sdev->dev, "SoundWire probe failed\n");700 return ret;701}702 703static int amd_sof_sdw_exit(struct snd_sof_dev *sdev)704{705 struct acp_dev_data *acp_data;706 707 acp_data = sdev->pdata->hw_pdata;708 if (acp_data->sdw)709 sdw_amd_exit(acp_data->sdw);710 acp_data->sdw = NULL;711 712 return 0;713}714 715#else716static int acp_sof_scan_sdw_devices(struct snd_sof_dev *sdev, u64 addr)717{718 return 0;719}720 721static int amd_sof_sdw_probe(struct snd_sof_dev *sdev)722{723 return 0;724}725 726static int amd_sof_sdw_exit(struct snd_sof_dev *sdev)727{728 return 0;729}730#endif731 732int amd_sof_acp_probe(struct snd_sof_dev *sdev)733{734 struct pci_dev *pci = to_pci_dev(sdev->dev);735 struct acp_dev_data *adata;736 const struct sof_amd_acp_desc *chip;737 const struct dmi_system_id *dmi_id;738 unsigned int addr;739 int ret;740 741 chip = get_chip_info(sdev->pdata);742 if (!chip) {743 dev_err(sdev->dev, "no such device supported, chip id:%x\n", pci->device);744 return -EIO;745 }746 adata = devm_kzalloc(sdev->dev, sizeof(struct acp_dev_data),747 GFP_KERNEL);748 if (!adata)749 return -ENOMEM;750 751 adata->dev = sdev;752 adata->dmic_dev = platform_device_register_data(sdev->dev, "dmic-codec",753 PLATFORM_DEVID_NONE, NULL, 0);754 if (IS_ERR(adata->dmic_dev)) {755 dev_err(sdev->dev, "failed to register platform for dmic codec\n");756 return PTR_ERR(adata->dmic_dev);757 }758 addr = pci_resource_start(pci, ACP_DSP_BAR);759 sdev->bar[ACP_DSP_BAR] = devm_ioremap(sdev->dev, addr, pci_resource_len(pci, ACP_DSP_BAR));760 if (!sdev->bar[ACP_DSP_BAR]) {761 dev_err(sdev->dev, "ioremap error\n");762 ret = -ENXIO;763 goto unregister_dev;764 }765 766 pci_set_master(pci);767 adata->addr = addr;768 adata->reg_range = chip->reg_end_addr - chip->reg_start_addr;769 adata->pci_rev = pci->revision;770 mutex_init(&adata->acp_lock);771 sdev->pdata->hw_pdata = adata;772 adata->smn_dev = pci_get_device(PCI_VENDOR_ID_AMD, chip->host_bridge_id, NULL);773 if (!adata->smn_dev) {774 dev_err(sdev->dev, "Failed to get host bridge device\n");775 ret = -ENODEV;776 goto unregister_dev;777 }778 779 ret = acp_init(sdev);780 if (ret < 0)781 goto free_smn_dev;782 783 sdev->ipc_irq = pci->irq;784 ret = request_threaded_irq(sdev->ipc_irq, acp_irq_handler, acp_irq_thread,785 IRQF_SHARED, "AudioDSP", sdev);786 if (ret < 0) {787 dev_err(sdev->dev, "failed to register IRQ %d\n",788 sdev->ipc_irq);789 goto free_smn_dev;790 }791 792 /* scan SoundWire capabilities exposed by DSDT */793 ret = acp_sof_scan_sdw_devices(sdev, chip->sdw_acpi_dev_addr);794 if (ret < 0) {795 dev_dbg(sdev->dev, "skipping SoundWire, not detected with ACPI scan\n");796 goto skip_soundwire;797 }798 ret = amd_sof_sdw_probe(sdev);799 if (ret < 0) {800 dev_err(sdev->dev, "error: SoundWire probe error\n");801 free_irq(sdev->ipc_irq, sdev);802 pci_dev_put(adata->smn_dev);803 return ret;804 }805 806skip_soundwire:807 sdev->dsp_box.offset = 0;808 sdev->dsp_box.size = BOX_SIZE_512;809 810 sdev->host_box.offset = sdev->dsp_box.offset + sdev->dsp_box.size;811 sdev->host_box.size = BOX_SIZE_512;812 813 sdev->debug_box.offset = sdev->host_box.offset + sdev->host_box.size;814 sdev->debug_box.size = BOX_SIZE_1024;815 816 dmi_id = dmi_first_match(acp_sof_quirk_table);817 if (dmi_id) {818 adata->quirks = dmi_id->driver_data;819 820 if (adata->quirks->signed_fw_image) {821 adata->fw_code_bin = devm_kasprintf(sdev->dev, GFP_KERNEL,822 "sof-%s-code.bin",823 chip->name);824 if (!adata->fw_code_bin) {825 ret = -ENOMEM;826 goto free_ipc_irq;827 }828 829 adata->fw_data_bin = devm_kasprintf(sdev->dev, GFP_KERNEL,830 "sof-%s-data.bin",831 chip->name);832 if (!adata->fw_data_bin) {833 ret = -ENOMEM;834 goto free_ipc_irq;835 }836 }837 }838 839 adata->enable_fw_debug = enable_fw_debug;840 acp_memory_init(sdev);841 842 acp_dsp_stream_init(sdev);843 844 return 0;845 846free_ipc_irq:847 free_irq(sdev->ipc_irq, sdev);848free_smn_dev:849 pci_dev_put(adata->smn_dev);850unregister_dev:851 platform_device_unregister(adata->dmic_dev);852 return ret;853}854EXPORT_SYMBOL_NS(amd_sof_acp_probe, SND_SOC_SOF_AMD_COMMON);855 856void amd_sof_acp_remove(struct snd_sof_dev *sdev)857{858 struct acp_dev_data *adata = sdev->pdata->hw_pdata;859 860 if (adata->smn_dev)861 pci_dev_put(adata->smn_dev);862 863 if (adata->sdw)864 amd_sof_sdw_exit(sdev);865 866 if (sdev->ipc_irq)867 free_irq(sdev->ipc_irq, sdev);868 869 if (adata->dmic_dev)870 platform_device_unregister(adata->dmic_dev);871 872 acp_reset(sdev);873}874EXPORT_SYMBOL_NS(amd_sof_acp_remove, SND_SOC_SOF_AMD_COMMON);875 876MODULE_LICENSE("Dual BSD/GPL");877MODULE_DESCRIPTION("AMD ACP sof driver");878MODULE_IMPORT_NS(SOUNDWIRE_AMD_INIT);879MODULE_IMPORT_NS(SND_AMD_SOUNDWIRE_ACPI);880