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1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)2//3// Copyright 2020 NXP4//5// Author: Daniel Baluta <daniel.baluta@nxp.com>6//7// Hardware interface for audio DSP on i.MX8M8 9#include <linux/bits.h>10#include <linux/firmware.h>11#include <linux/mfd/syscon.h>12#include <linux/of_platform.h>13#include <linux/of_address.h>14#include <linux/of_irq.h>15#include <linux/regmap.h>16 17#include <linux/module.h>18#include <sound/sof.h>19#include <sound/sof/xtensa.h>20#include <linux/firmware/imx/dsp.h>21 22#include "../ops.h"23#include "../sof-of-dev.h"24#include "imx-common.h"25 26#define MBOX_OFFSET 0x80000027#define MBOX_SIZE 0x100028 29/* DAP registers */30#define IMX8M_DAP_DEBUG 0x2880000031#define IMX8M_DAP_DEBUG_SIZE (64 * 1024)32#define IMX8M_DAP_PWRCTL (0x4000 + 0x3020)33#define IMX8M_PWRCTL_CORERESET BIT(16)34 35/* DSP audio mix registers */36#define AudioDSP_REG0 0x10037#define AudioDSP_REG1 0x10438#define AudioDSP_REG2 0x10839#define AudioDSP_REG3 0x10c40 41#define AudioDSP_REG2_RUNSTALL BIT(5)42 43struct imx8m_priv {44 struct device *dev;45 struct snd_sof_dev *sdev;46 47 /* DSP IPC handler */48 struct imx_dsp_ipc *dsp_ipc;49 struct platform_device *ipc_dev;50 51 struct clk_bulk_data *clks;52 int clk_num;53 54 void __iomem *dap;55 struct regmap *regmap;56};57 58static int imx8m_get_mailbox_offset(struct snd_sof_dev *sdev)59{60 return MBOX_OFFSET;61}62 63static int imx8m_get_window_offset(struct snd_sof_dev *sdev, u32 id)64{65 return MBOX_OFFSET;66}67 68static void imx8m_dsp_handle_reply(struct imx_dsp_ipc *ipc)69{70 struct imx8m_priv *priv = imx_dsp_get_data(ipc);71 unsigned long flags;72 73 spin_lock_irqsave(&priv->sdev->ipc_lock, flags);74 snd_sof_ipc_process_reply(priv->sdev, 0);75 spin_unlock_irqrestore(&priv->sdev->ipc_lock, flags);76}77 78static void imx8m_dsp_handle_request(struct imx_dsp_ipc *ipc)79{80 struct imx8m_priv *priv = imx_dsp_get_data(ipc);81 u32 p; /* Panic code */82 83 /* Read the message from the debug box. */84 sof_mailbox_read(priv->sdev, priv->sdev->debug_box.offset + 4, &p, sizeof(p));85 86 /* Check to see if the message is a panic code (0x0dead***) */87 if ((p & SOF_IPC_PANIC_MAGIC_MASK) == SOF_IPC_PANIC_MAGIC)88 snd_sof_dsp_panic(priv->sdev, p, true);89 else90 snd_sof_ipc_msgs_rx(priv->sdev);91}92 93static struct imx_dsp_ops imx8m_dsp_ops = {94 .handle_reply = imx8m_dsp_handle_reply,95 .handle_request = imx8m_dsp_handle_request,96};97 98static int imx8m_send_msg(struct snd_sof_dev *sdev, struct snd_sof_ipc_msg *msg)99{100 struct imx8m_priv *priv = sdev->pdata->hw_pdata;101 102 sof_mailbox_write(sdev, sdev->host_box.offset, msg->msg_data,103 msg->msg_size);104 imx_dsp_ring_doorbell(priv->dsp_ipc, 0);105 106 return 0;107}108 109/*110 * DSP control.111 */112static int imx8m_run(struct snd_sof_dev *sdev)113{114 struct imx8m_priv *priv = (struct imx8m_priv *)sdev->pdata->hw_pdata;115 116 regmap_update_bits(priv->regmap, AudioDSP_REG2, AudioDSP_REG2_RUNSTALL, 0);117 118 return 0;119}120 121static int imx8m_reset(struct snd_sof_dev *sdev)122{123 struct imx8m_priv *priv = (struct imx8m_priv *)sdev->pdata->hw_pdata;124 u32 pwrctl;125 126 /* put DSP into reset and stall */127 pwrctl = readl(priv->dap + IMX8M_DAP_PWRCTL);128 pwrctl |= IMX8M_PWRCTL_CORERESET;129 writel(pwrctl, priv->dap + IMX8M_DAP_PWRCTL);130 131 /* keep reset asserted for 10 cycles */132 usleep_range(1, 2);133 134 regmap_update_bits(priv->regmap, AudioDSP_REG2,135 AudioDSP_REG2_RUNSTALL, AudioDSP_REG2_RUNSTALL);136 137 /* take the DSP out of reset and keep stalled for FW loading */138 pwrctl = readl(priv->dap + IMX8M_DAP_PWRCTL);139 pwrctl &= ~IMX8M_PWRCTL_CORERESET;140 writel(pwrctl, priv->dap + IMX8M_DAP_PWRCTL);141 142 return 0;143}144 145static int imx8m_probe(struct snd_sof_dev *sdev)146{147 struct platform_device *pdev =148 container_of(sdev->dev, struct platform_device, dev);149 struct device_node *np = pdev->dev.of_node;150 struct device_node *res_node;151 struct resource *mmio;152 struct imx8m_priv *priv;153 struct resource res;154 u32 base, size;155 int ret = 0;156 157 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);158 if (!priv)159 return -ENOMEM;160 161 sdev->num_cores = 1;162 sdev->pdata->hw_pdata = priv;163 priv->dev = sdev->dev;164 priv->sdev = sdev;165 166 priv->ipc_dev = platform_device_register_data(sdev->dev, "imx-dsp",167 PLATFORM_DEVID_NONE,168 pdev, sizeof(*pdev));169 if (IS_ERR(priv->ipc_dev))170 return PTR_ERR(priv->ipc_dev);171 172 priv->dsp_ipc = dev_get_drvdata(&priv->ipc_dev->dev);173 if (!priv->dsp_ipc) {174 /* DSP IPC driver not probed yet, try later */175 ret = -EPROBE_DEFER;176 dev_err(sdev->dev, "Failed to get drvdata\n");177 goto exit_pdev_unregister;178 }179 180 imx_dsp_set_data(priv->dsp_ipc, priv);181 priv->dsp_ipc->ops = &imx8m_dsp_ops;182 183 /* DSP base */184 mmio = platform_get_resource(pdev, IORESOURCE_MEM, 0);185 if (mmio) {186 base = mmio->start;187 size = resource_size(mmio);188 } else {189 dev_err(sdev->dev, "error: failed to get DSP base at idx 0\n");190 ret = -EINVAL;191 goto exit_pdev_unregister;192 }193 194 priv->dap = devm_ioremap(sdev->dev, IMX8M_DAP_DEBUG, IMX8M_DAP_DEBUG_SIZE);195 if (!priv->dap) {196 dev_err(sdev->dev, "error: failed to map DAP debug memory area");197 ret = -ENODEV;198 goto exit_pdev_unregister;199 }200 201 sdev->bar[SOF_FW_BLK_TYPE_IRAM] = devm_ioremap(sdev->dev, base, size);202 if (!sdev->bar[SOF_FW_BLK_TYPE_IRAM]) {203 dev_err(sdev->dev, "failed to ioremap base 0x%x size 0x%x\n",204 base, size);205 ret = -ENODEV;206 goto exit_pdev_unregister;207 }208 sdev->mmio_bar = SOF_FW_BLK_TYPE_IRAM;209 210 res_node = of_parse_phandle(np, "memory-region", 0);211 if (!res_node) {212 dev_err(&pdev->dev, "failed to get memory region node\n");213 ret = -ENODEV;214 goto exit_pdev_unregister;215 }216 217 ret = of_address_to_resource(res_node, 0, &res);218 of_node_put(res_node);219 if (ret) {220 dev_err(&pdev->dev, "failed to get reserved region address\n");221 goto exit_pdev_unregister;222 }223 224 sdev->bar[SOF_FW_BLK_TYPE_SRAM] = devm_ioremap_wc(sdev->dev, res.start,225 resource_size(&res));226 if (!sdev->bar[SOF_FW_BLK_TYPE_SRAM]) {227 dev_err(sdev->dev, "failed to ioremap mem 0x%x size 0x%x\n",228 base, size);229 ret = -ENOMEM;230 goto exit_pdev_unregister;231 }232 sdev->mailbox_bar = SOF_FW_BLK_TYPE_SRAM;233 234 /* set default mailbox offset for FW ready message */235 sdev->dsp_box.offset = MBOX_OFFSET;236 237 priv->regmap = syscon_regmap_lookup_by_phandle(np, "fsl,dsp-ctrl");238 if (IS_ERR(priv->regmap)) {239 dev_err(sdev->dev, "cannot find dsp-ctrl registers");240 ret = PTR_ERR(priv->regmap);241 goto exit_pdev_unregister;242 }243 244 ret = devm_clk_bulk_get_all(sdev->dev, &priv->clks);245 if (ret < 0) {246 dev_err(sdev->dev, "failed to fetch clocks: %d\n", ret);247 goto exit_pdev_unregister;248 }249 priv->clk_num = ret;250 251 ret = clk_bulk_prepare_enable(priv->clk_num, priv->clks);252 if (ret < 0) {253 dev_err(sdev->dev, "failed to enable clocks: %d\n", ret);254 goto exit_pdev_unregister;255 }256 257 return 0;258 259exit_pdev_unregister:260 platform_device_unregister(priv->ipc_dev);261 return ret;262}263 264static void imx8m_remove(struct snd_sof_dev *sdev)265{266 struct imx8m_priv *priv = sdev->pdata->hw_pdata;267 268 clk_bulk_disable_unprepare(priv->clk_num, priv->clks);269 platform_device_unregister(priv->ipc_dev);270}271 272/* on i.MX8 there is 1 to 1 match between type and BAR idx */273static int imx8m_get_bar_index(struct snd_sof_dev *sdev, u32 type)274{275 /* Only IRAM and SRAM bars are valid */276 switch (type) {277 case SOF_FW_BLK_TYPE_IRAM:278 case SOF_FW_BLK_TYPE_SRAM:279 return type;280 default:281 return -EINVAL;282 }283}284 285static struct snd_soc_dai_driver imx8m_dai[] = {286{287 .name = "sai1",288 .playback = {289 .channels_min = 1,290 .channels_max = 32,291 },292 .capture = {293 .channels_min = 1,294 .channels_max = 32,295 },296},297{298 .name = "sai3",299 .playback = {300 .channels_min = 1,301 .channels_max = 32,302 },303 .capture = {304 .channels_min = 1,305 .channels_max = 32,306 },307},308{309 .name = "micfil",310 .capture = {311 .channels_min = 1,312 .channels_max = 8,313 },314},315};316 317static int imx8m_dsp_set_power_state(struct snd_sof_dev *sdev,318 const struct sof_dsp_power_state *target_state)319{320 sdev->dsp_power_state = *target_state;321 322 return 0;323}324 325static int imx8m_resume(struct snd_sof_dev *sdev)326{327 struct imx8m_priv *priv = (struct imx8m_priv *)sdev->pdata->hw_pdata;328 int ret;329 int i;330 331 ret = clk_bulk_prepare_enable(priv->clk_num, priv->clks);332 if (ret < 0) {333 dev_err(sdev->dev, "failed to enable clocks: %d\n", ret);334 return ret;335 }336 337 for (i = 0; i < DSP_MU_CHAN_NUM; i++)338 imx_dsp_request_channel(priv->dsp_ipc, i);339 340 return 0;341}342 343static void imx8m_suspend(struct snd_sof_dev *sdev)344{345 struct imx8m_priv *priv = (struct imx8m_priv *)sdev->pdata->hw_pdata;346 int i;347 348 for (i = 0; i < DSP_MU_CHAN_NUM; i++)349 imx_dsp_free_channel(priv->dsp_ipc, i);350 351 clk_bulk_disable_unprepare(priv->clk_num, priv->clks);352}353 354static int imx8m_dsp_runtime_resume(struct snd_sof_dev *sdev)355{356 int ret;357 const struct sof_dsp_power_state target_dsp_state = {358 .state = SOF_DSP_PM_D0,359 };360 361 ret = imx8m_resume(sdev);362 if (ret < 0)363 return ret;364 365 return snd_sof_dsp_set_power_state(sdev, &target_dsp_state);366}367 368static int imx8m_dsp_runtime_suspend(struct snd_sof_dev *sdev)369{370 const struct sof_dsp_power_state target_dsp_state = {371 .state = SOF_DSP_PM_D3,372 };373 374 imx8m_suspend(sdev);375 376 return snd_sof_dsp_set_power_state(sdev, &target_dsp_state);377}378 379static int imx8m_dsp_resume(struct snd_sof_dev *sdev)380{381 int ret;382 const struct sof_dsp_power_state target_dsp_state = {383 .state = SOF_DSP_PM_D0,384 };385 386 ret = imx8m_resume(sdev);387 if (ret < 0)388 return ret;389 390 if (pm_runtime_suspended(sdev->dev)) {391 pm_runtime_disable(sdev->dev);392 pm_runtime_set_active(sdev->dev);393 pm_runtime_mark_last_busy(sdev->dev);394 pm_runtime_enable(sdev->dev);395 pm_runtime_idle(sdev->dev);396 }397 398 return snd_sof_dsp_set_power_state(sdev, &target_dsp_state);399}400 401static int imx8m_dsp_suspend(struct snd_sof_dev *sdev, unsigned int target_state)402{403 const struct sof_dsp_power_state target_dsp_state = {404 .state = target_state,405 };406 407 if (!pm_runtime_suspended(sdev->dev))408 imx8m_suspend(sdev);409 410 return snd_sof_dsp_set_power_state(sdev, &target_dsp_state);411}412 413/* i.MX8 ops */414static const struct snd_sof_dsp_ops sof_imx8m_ops = {415 /* probe and remove */416 .probe = imx8m_probe,417 .remove = imx8m_remove,418 /* DSP core boot */419 .run = imx8m_run,420 .reset = imx8m_reset,421 422 /* Block IO */423 .block_read = sof_block_read,424 .block_write = sof_block_write,425 426 /* Mailbox IO */427 .mailbox_read = sof_mailbox_read,428 .mailbox_write = sof_mailbox_write,429 430 /* ipc */431 .send_msg = imx8m_send_msg,432 .get_mailbox_offset = imx8m_get_mailbox_offset,433 .get_window_offset = imx8m_get_window_offset,434 435 .ipc_msg_data = sof_ipc_msg_data,436 .set_stream_data_offset = sof_set_stream_data_offset,437 438 .get_bar_index = imx8m_get_bar_index,439 440 /* firmware loading */441 .load_firmware = snd_sof_load_firmware_memcpy,442 443 /* Debug information */444 .dbg_dump = imx8_dump,445 .debugfs_add_region_item = snd_sof_debugfs_add_region_item_iomem,446 447 /* stream callbacks */448 .pcm_open = sof_stream_pcm_open,449 .pcm_close = sof_stream_pcm_close,450 /* Firmware ops */451 .dsp_arch_ops = &sof_xtensa_arch_ops,452 453 /* DAI drivers */454 .drv = imx8m_dai,455 .num_drv = ARRAY_SIZE(imx8m_dai),456 457 .suspend = imx8m_dsp_suspend,458 .resume = imx8m_dsp_resume,459 460 .runtime_suspend = imx8m_dsp_runtime_suspend,461 .runtime_resume = imx8m_dsp_runtime_resume,462 463 .set_power_state = imx8m_dsp_set_power_state,464 465 .hw_info = SNDRV_PCM_INFO_MMAP |466 SNDRV_PCM_INFO_MMAP_VALID |467 SNDRV_PCM_INFO_INTERLEAVED |468 SNDRV_PCM_INFO_PAUSE |469 SNDRV_PCM_INFO_BATCH |470 SNDRV_PCM_INFO_NO_PERIOD_WAKEUP,471};472 473static struct snd_sof_of_mach sof_imx8mp_machs[] = {474 {475 .compatible = "fsl,imx8mp-evk",476 .sof_tplg_filename = "sof-imx8mp-wm8960.tplg",477 .drv_name = "asoc-audio-graph-card2",478 },479 {}480};481 482static struct sof_dev_desc sof_of_imx8mp_desc = {483 .of_machines = sof_imx8mp_machs,484 .ipc_supported_mask = BIT(SOF_IPC_TYPE_3),485 .ipc_default = SOF_IPC_TYPE_3,486 .default_fw_path = {487 [SOF_IPC_TYPE_3] = "imx/sof",488 },489 .default_tplg_path = {490 [SOF_IPC_TYPE_3] = "imx/sof-tplg",491 },492 .default_fw_filename = {493 [SOF_IPC_TYPE_3] = "sof-imx8m.ri",494 },495 .nocodec_tplg_filename = "sof-imx8-nocodec.tplg",496 .ops = &sof_imx8m_ops,497};498 499static const struct of_device_id sof_of_imx8m_ids[] = {500 { .compatible = "fsl,imx8mp-dsp", .data = &sof_of_imx8mp_desc},501 { }502};503MODULE_DEVICE_TABLE(of, sof_of_imx8m_ids);504 505/* DT driver definition */506static struct platform_driver snd_sof_of_imx8m_driver = {507 .probe = sof_of_probe,508 .remove = sof_of_remove,509 .driver = {510 .name = "sof-audio-of-imx8m",511 .pm = &sof_of_pm,512 .of_match_table = sof_of_imx8m_ids,513 },514};515module_platform_driver(snd_sof_of_imx8m_driver);516 517MODULE_LICENSE("Dual BSD/GPL");518MODULE_DESCRIPTION("SOF support for IMX8M platforms");519MODULE_IMPORT_NS(SND_SOC_SOF_XTENSA);520