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1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)2//3// This file is provided under a dual BSD/GPLv2 license. When using or4// redistributing this file, you may do so under either license.5//6// Copyright(c) 2018 Intel Corporation7//8// Authors: Liam Girdwood <liam.r.girdwood@linux.intel.com>9// Ranjani Sridharan <ranjani.sridharan@linux.intel.com>10// Rander Wang <rander.wang@intel.com>11// Keyon Jie <yang.jie@linux.intel.com>12//13 14/*15 * Hardware interface for audio DSP on Apollolake and GeminiLake16 */17 18#include <sound/sof/ext_manifest4.h>19#include "../ipc4-priv.h"20#include "../sof-priv.h"21#include "hda.h"22#include "../sof-audio.h"23 24static const struct snd_sof_debugfs_map apl_dsp_debugfs[] = {25 {"hda", HDA_DSP_HDA_BAR, 0, 0x4000, SOF_DEBUGFS_ACCESS_ALWAYS},26 {"pp", HDA_DSP_PP_BAR, 0, 0x1000, SOF_DEBUGFS_ACCESS_ALWAYS},27 {"dsp", HDA_DSP_BAR, 0, 0x10000, SOF_DEBUGFS_ACCESS_ALWAYS},28};29 30/* apollolake ops */31struct snd_sof_dsp_ops sof_apl_ops;32 33int sof_apl_ops_init(struct snd_sof_dev *sdev)34{35 /* common defaults */36 memcpy(&sof_apl_ops, &sof_hda_common_ops, sizeof(struct snd_sof_dsp_ops));37 38 /* probe/remove/shutdown */39 sof_apl_ops.shutdown = hda_dsp_shutdown;40 41 if (sdev->pdata->ipc_type == SOF_IPC_TYPE_3) {42 /* doorbell */43 sof_apl_ops.irq_thread = hda_dsp_ipc_irq_thread;44 45 /* ipc */46 sof_apl_ops.send_msg = hda_dsp_ipc_send_msg;47 48 /* debug */49 sof_apl_ops.ipc_dump = hda_ipc_dump;50 51 sof_apl_ops.set_power_state = hda_dsp_set_power_state_ipc3;52 }53 54 if (sdev->pdata->ipc_type == SOF_IPC_TYPE_4) {55 struct sof_ipc4_fw_data *ipc4_data;56 57 sdev->private = kzalloc(sizeof(*ipc4_data), GFP_KERNEL);58 if (!sdev->private)59 return -ENOMEM;60 61 ipc4_data = sdev->private;62 ipc4_data->manifest_fw_hdr_offset = SOF_MAN4_FW_HDR_OFFSET;63 64 ipc4_data->mtrace_type = SOF_IPC4_MTRACE_INTEL_CAVS_1_5;65 66 /* External library loading support */67 ipc4_data->load_library = hda_dsp_ipc4_load_library;68 69 /* doorbell */70 sof_apl_ops.irq_thread = hda_dsp_ipc4_irq_thread;71 72 /* ipc */73 sof_apl_ops.send_msg = hda_dsp_ipc4_send_msg;74 75 /* debug */76 sof_apl_ops.ipc_dump = hda_ipc4_dump;77 78 sof_apl_ops.set_power_state = hda_dsp_set_power_state_ipc4;79 }80 81 /* set DAI driver ops */82 hda_set_dai_drv_ops(sdev, &sof_apl_ops);83 84 /* debug */85 sof_apl_ops.debug_map = apl_dsp_debugfs;86 sof_apl_ops.debug_map_count = ARRAY_SIZE(apl_dsp_debugfs);87 88 /* firmware run */89 sof_apl_ops.run = hda_dsp_cl_boot_firmware;90 91 /* pre/post fw run */92 sof_apl_ops.post_fw_run = hda_dsp_post_fw_run;93 94 /* dsp core get/put */95 sof_apl_ops.core_get = hda_dsp_core_get;96 97 return 0;98};99 100const struct sof_intel_dsp_desc apl_chip_info = {101 /* Apollolake */102 .cores_num = 2,103 .init_core_mask = 1,104 .host_managed_cores_mask = GENMASK(1, 0),105 .ipc_req = HDA_DSP_REG_HIPCI,106 .ipc_req_mask = HDA_DSP_REG_HIPCI_BUSY,107 .ipc_ack = HDA_DSP_REG_HIPCIE,108 .ipc_ack_mask = HDA_DSP_REG_HIPCIE_DONE,109 .ipc_ctl = HDA_DSP_REG_HIPCCTL,110 .rom_status_reg = HDA_DSP_SRAM_REG_ROM_STATUS,111 .rom_init_timeout = 150,112 .ssp_count = APL_SSP_COUNT,113 .ssp_base_offset = APL_SSP_BASE_OFFSET,114 .d0i3_offset = SOF_HDA_VS_D0I3C,115 .quirks = SOF_INTEL_PROCEN_FMT_QUIRK,116 .check_ipc_irq = hda_dsp_check_ipc_irq,117 .cl_init = cl_dsp_init,118 .power_down_dsp = hda_power_down_dsp,119 .disable_interrupts = hda_dsp_disable_interrupts,120 .hw_ip_version = SOF_INTEL_CAVS_1_5_PLUS,121};122