75 lines · c
1/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */2/*3 * This file is provided under a dual BSD/GPLv2 license. When using or4 * redistributing this file, you may do so under either license.5 *6 * Copyright(c) 2017-2021 Intel Corporation7 *8 * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>9 */10 11#ifndef __SOF_INTEL_ATOM_H12#define __SOF_INTEL_ATOM_H13 14/* DSP memories */15#define IRAM_OFFSET 0x0C000016#define IRAM_SIZE (80 * 1024)17#define DRAM_OFFSET 0x10000018#define DRAM_SIZE (160 * 1024)19#define SHIM_OFFSET 0x14000020#define SHIM_SIZE_BYT 0x10021#define SHIM_SIZE_CHT 0x11822#define MBOX_OFFSET 0x14400023#define MBOX_SIZE 0x100024#define EXCEPT_OFFSET 0x80025#define EXCEPT_MAX_HDR_SIZE 0x40026 27/* DSP peripherals */28#define DMAC0_OFFSET 0x09800029#define DMAC1_OFFSET 0x09c00030#define DMAC2_OFFSET 0x09400031#define DMAC_SIZE 0x42032#define SSP0_OFFSET 0x0a000033#define SSP1_OFFSET 0x0a100034#define SSP2_OFFSET 0x0a200035#define SSP3_OFFSET 0x0a400036#define SSP4_OFFSET 0x0a500037#define SSP5_OFFSET 0x0a600038#define SSP_SIZE 0x10039 40#define STACK_DUMP_SIZE 3241 42#define PCI_BAR_SIZE 0x20000043 44#define PANIC_OFFSET(x) (((x) & GENMASK_ULL(47, 32)) >> 32)45 46/*47 * Debug48 */49 50#define MBOX_DUMP_SIZE 0x3051 52/* BARs */53#define DSP_BAR 054#define PCI_BAR 155#define IMR_BAR 256 57irqreturn_t atom_irq_handler(int irq, void *context);58irqreturn_t atom_irq_thread(int irq, void *context);59 60int atom_send_msg(struct snd_sof_dev *sdev, struct snd_sof_ipc_msg *msg);61int atom_get_mailbox_offset(struct snd_sof_dev *sdev);62int atom_get_window_offset(struct snd_sof_dev *sdev, u32 id);63 64int atom_run(struct snd_sof_dev *sdev);65int atom_reset(struct snd_sof_dev *sdev);66void atom_dump(struct snd_sof_dev *sdev, u32 flags);67 68struct snd_soc_acpi_mach *atom_machine_select(struct snd_sof_dev *sdev);69void atom_set_mach_params(struct snd_soc_acpi_mach *mach,70 struct snd_sof_dev *sdev);71 72extern struct snd_soc_dai_driver atom_dai[];73 74#endif75