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1/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */2/*3 * This file is provided under a dual BSD/GPLv2 license. When using or4 * redistributing this file, you may do so under either license.5 *6 * Copyright(c) 2019 Intel Corporation7 *8 * Author: Keyon Jie <yang.jie@linux.intel.com>9 */10 11#ifndef __SOF_INTEL_HDA_IPC_H12#define __SOF_INTEL_HDA_IPC_H13 14/*15 * Primary register, mapped to16 * - DIPCTDR (HIPCIDR) in sideband IPC (cAVS 1.8+)17 * - DIPCT in cAVS 1.5 IPC18 *19 * Secondary register, mapped to:20 * - DIPCTDD (HIPCIDD) in sideband IPC (cAVS 1.8+)21 * - DIPCTE in cAVS 1.5 IPC22 */23 24/* Common bits in primary register */25 26/* Reserved for doorbell */27#define HDA_IPC_RSVD_31 BIT(31)28/* Target, 0 - normal message, 1 - compact message(cAVS compatible) */29#define HDA_IPC_MSG_COMPACT BIT(30)30/* Direction, 0 - request, 1 - response */31#define HDA_IPC_RSP BIT(29)32 33#define HDA_IPC_TYPE_SHIFT 2434#define HDA_IPC_TYPE_MASK GENMASK(28, 24)35#define HDA_IPC_TYPE(x) ((x) << HDA_IPC_TYPE_SHIFT)36 37#define HDA_IPC_PM_GATE HDA_IPC_TYPE(0x8U)38 39/* Command specific payload bits in secondary register */40 41/* Disable DMA tracing (0 - keep tracing, 1 - to disable DMA trace) */42#define HDA_PM_NO_DMA_TRACE BIT(4)43/* Prevent clock gating (0 - cg allowed, 1 - DSP clock always on) */44#define HDA_PM_PCG BIT(3)45/* Prevent power gating (0 - deep power state transitions allowed) */46#define HDA_PM_PPG BIT(2)47/* Indicates whether streaming is active */48#define HDA_PM_PG_STREAMING BIT(1)49#define HDA_PM_PG_RSVD BIT(0)50 51irqreturn_t cnl_ipc_irq_thread(int irq, void *context);52int cnl_ipc_send_msg(struct snd_sof_dev *sdev, struct snd_sof_ipc_msg *msg);53void cnl_ipc_dump(struct snd_sof_dev *sdev);54void cnl_ipc4_dump(struct snd_sof_dev *sdev);55 56#endif57