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1/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */2 3/*4 * Copyright (c) 2022 MediaTek Corporation. All rights reserved.5 *6 * Header file for the mt8186 DSP register definition7 */8 9#ifndef __MT8186_H10#define __MT8186_H11 12struct mtk_adsp_chip_info;13struct snd_sof_dev;14 15#define DSP_REG_BAR 416#define DSP_SECREG_BAR 517#define DSP_BUSREG_BAR 618 19/*****************************************************************************20 * R E G I S T E R TABLE21 *****************************************************************************/22/* dsp cfg */23#define ADSP_CFGREG_SW_RSTN 0x000024#define SW_DBG_RSTN_C0 BIT(0)25#define SW_RSTN_C0 BIT(4)26#define ADSP_HIFI_IO_CONFIG 0x000C27#define TRACEMEMREADY BIT(15)28#define RUNSTALL BIT(31)29#define ADSP_IRQ_MASK 0x003030#define ADSP_DVFSRC_REQ 0x004031#define ADSP_DDREN_REQ_0 0x004432#define ADSP_SEMAPHORE 0x006433#define ADSP_WDT_CON_C0 0x007C34#define ADSP_MBOX_IRQ_EN 0x009C35#define DSP_MBOX0_IRQ_EN BIT(0)36#define DSP_MBOX1_IRQ_EN BIT(1)37#define DSP_MBOX2_IRQ_EN BIT(2)38#define DSP_MBOX3_IRQ_EN BIT(3)39#define DSP_MBOX4_IRQ_EN BIT(4)40#define DSP_PDEBUGPC 0x013C41#define DSP_PDEBUGDATA 0x014042#define DSP_PDEBUGINST 0x014443#define DSP_PDEBUGLS0STAT 0x014844#define DSP_PDEBUGSTATUS 0x014C45#define DSP_PFAULTINFO 0x015046#define ADSP_CK_EN 0x100047#define CORE_CLK_EN BIT(0)48#define COREDBG_EN BIT(1)49#define TIMER_EN BIT(3)50#define DMA_EN BIT(4)51#define UART_EN BIT(5)52#define ADSP_UART_CTRL 0x101053#define UART_BCLK_CG BIT(0)54#define UART_RSTN BIT(3)55 56/* dsp sec */57#define ADSP_PRID 0x058#define ADSP_ALTVEC_C0 0x0459#define ADSP_ALTVECSEL 0x0C60#define MT8188_ADSP_ALTVECSEL_C0 BIT(0)61#define MT8186_ADSP_ALTVECSEL_C0 BIT(1)62 63/*64 * On MT8188, BIT(1) is not evaluated and on MT8186 BIT(0) is not evaluated:65 * We can simplify the driver by safely setting both bits regardless of the SoC.66 */67#define ADSP_ALTVECSEL_C0 (MT8188_ADSP_ALTVECSEL_C0 | \68 MT8186_ADSP_ALTVECSEL_C0)69 70/* dsp bus */71#define ADSP_SRAM_POOL_CON 0x19072#define DSP_SRAM_POOL_PD_MASK 0xF00F /* [0:3] and [12:15] */73#define DSP_C0_EMI_MAP_ADDR 0xA00 /* ADSP Core0 To EMI Address Remap */74#define DSP_C0_DMAEMI_MAP_ADDR 0xA08 /* DMA0 To EMI Address Remap */75 76/* DSP memories */77#define MBOX_OFFSET 0x500000 /* DRAM */78#define MBOX_SIZE 0x1000 /* consistent with which in memory.h of sof fw */79#define DSP_DRAM_SIZE 0xA00000 /* 16M */80 81/*remap dram between AP and DSP view, 4KB aligned*/82#define SRAM_PHYS_BASE_FROM_DSP_VIEW 0x4E100000 /* MT8186 DSP view */83#define DRAM_PHYS_BASE_FROM_DSP_VIEW 0x60000000 /* MT8186 DSP view */84#define DRAM_REMAP_SHIFT 1285#define DRAM_REMAP_MASK 0xFFF86 87#define SIZE_SHARED_DRAM_DL 0x40000 /*Shared buffer for Downlink*/88#define SIZE_SHARED_DRAM_UL 0x40000 /*Shared buffer for Uplink*/89#define TOTAL_SIZE_SHARED_DRAM_FROM_TAIL (SIZE_SHARED_DRAM_DL + SIZE_SHARED_DRAM_UL)90 91void mt8186_sof_hifixdsp_boot_sequence(struct snd_sof_dev *sdev, u32 boot_addr);92void mt8186_sof_hifixdsp_shutdown(struct snd_sof_dev *sdev);93#endif94