629 lines · c
1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)2//3// Copyright(c) 2021 Mediatek Inc. All rights reserved.4//5// Author: YC Hung <yc.hung@mediatek.com>6//7 8/*9 * Hardware interface for audio DSP on mt819510 */11 12#include <linux/delay.h>13#include <linux/firmware.h>14#include <linux/io.h>15#include <linux/of_address.h>16#include <linux/of_irq.h>17#include <linux/of_platform.h>18#include <linux/of_reserved_mem.h>19#include <linux/module.h>20 21#include <sound/sof.h>22#include <sound/sof/xtensa.h>23#include "../../ops.h"24#include "../../sof-of-dev.h"25#include "../../sof-audio.h"26#include "../adsp_helper.h"27#include "../mtk-adsp-common.h"28#include "mt8195.h"29#include "mt8195-clk.h"30 31static int mt8195_get_mailbox_offset(struct snd_sof_dev *sdev)32{33 return MBOX_OFFSET;34}35 36static int mt8195_get_window_offset(struct snd_sof_dev *sdev, u32 id)37{38 return MBOX_OFFSET;39}40 41static int mt8195_send_msg(struct snd_sof_dev *sdev,42 struct snd_sof_ipc_msg *msg)43{44 struct adsp_priv *priv = sdev->pdata->hw_pdata;45 46 sof_mailbox_write(sdev, sdev->host_box.offset, msg->msg_data,47 msg->msg_size);48 49 return mtk_adsp_ipc_send(priv->dsp_ipc, MTK_ADSP_IPC_REQ, MTK_ADSP_IPC_OP_REQ);50}51 52static void mt8195_dsp_handle_reply(struct mtk_adsp_ipc *ipc)53{54 struct adsp_priv *priv = mtk_adsp_ipc_get_data(ipc);55 unsigned long flags;56 57 spin_lock_irqsave(&priv->sdev->ipc_lock, flags);58 snd_sof_ipc_process_reply(priv->sdev, 0);59 spin_unlock_irqrestore(&priv->sdev->ipc_lock, flags);60}61 62static void mt8195_dsp_handle_request(struct mtk_adsp_ipc *ipc)63{64 struct adsp_priv *priv = mtk_adsp_ipc_get_data(ipc);65 u32 p; /* panic code */66 int ret;67 68 /* Read the message from the debug box. */69 sof_mailbox_read(priv->sdev, priv->sdev->debug_box.offset + 4,70 &p, sizeof(p));71 72 /* Check to see if the message is a panic code 0x0dead*** */73 if ((p & SOF_IPC_PANIC_MAGIC_MASK) == SOF_IPC_PANIC_MAGIC) {74 snd_sof_dsp_panic(priv->sdev, p, true);75 } else {76 snd_sof_ipc_msgs_rx(priv->sdev);77 78 /* tell DSP cmd is done */79 ret = mtk_adsp_ipc_send(priv->dsp_ipc, MTK_ADSP_IPC_RSP, MTK_ADSP_IPC_OP_RSP);80 if (ret)81 dev_err(priv->dev, "request send ipc failed");82 }83}84 85static const struct mtk_adsp_ipc_ops dsp_ops = {86 .handle_reply = mt8195_dsp_handle_reply,87 .handle_request = mt8195_dsp_handle_request,88};89 90static int platform_parse_resource(struct platform_device *pdev, void *data)91{92 struct resource *mmio;93 struct resource res;94 struct device_node *mem_region;95 struct device *dev = &pdev->dev;96 struct mtk_adsp_chip_info *adsp = data;97 int ret;98 99 ret = of_reserved_mem_device_init(dev);100 if (ret) {101 dev_err(dev, "of_reserved_mem_device_init failed\n");102 return ret;103 }104 105 mem_region = of_parse_phandle(dev->of_node, "memory-region", 1);106 if (!mem_region) {107 dev_err(dev, "no memory-region sysmem phandle\n");108 return -ENODEV;109 }110 111 ret = of_address_to_resource(mem_region, 0, &res);112 of_node_put(mem_region);113 if (ret) {114 dev_err(dev, "of_address_to_resource sysmem failed\n");115 return ret;116 }117 118 adsp->pa_dram = (phys_addr_t)res.start;119 adsp->dramsize = resource_size(&res);120 if (adsp->pa_dram & DRAM_REMAP_MASK) {121 dev_err(dev, "adsp memory(%#x) is not 4K-aligned\n",122 (u32)adsp->pa_dram);123 return -EINVAL;124 }125 126 if (adsp->dramsize < TOTAL_SIZE_SHARED_DRAM_FROM_TAIL) {127 dev_err(dev, "adsp memory(%#x) is not enough for share\n",128 adsp->dramsize);129 return -EINVAL;130 }131 132 dev_dbg(dev, "dram pbase=%pa, dramsize=%#x\n",133 &adsp->pa_dram, adsp->dramsize);134 135 /* Parse CFG base */136 mmio = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cfg");137 if (!mmio) {138 dev_err(dev, "no ADSP-CFG register resource\n");139 return -ENXIO;140 }141 /* remap for DSP register accessing */142 adsp->va_cfgreg = devm_ioremap_resource(dev, mmio);143 if (IS_ERR(adsp->va_cfgreg))144 return PTR_ERR(adsp->va_cfgreg);145 146 adsp->pa_cfgreg = (phys_addr_t)mmio->start;147 adsp->cfgregsize = resource_size(mmio);148 149 dev_dbg(dev, "cfgreg-vbase=%p, cfgregsize=%#x\n",150 adsp->va_cfgreg, adsp->cfgregsize);151 152 /* Parse SRAM */153 mmio = platform_get_resource_byname(pdev, IORESOURCE_MEM, "sram");154 if (!mmio) {155 dev_err(dev, "no SRAM resource\n");156 return -ENXIO;157 }158 159 adsp->pa_sram = (phys_addr_t)mmio->start;160 adsp->sramsize = resource_size(mmio);161 162 dev_dbg(dev, "sram pbase=%pa,%#x\n", &adsp->pa_sram, adsp->sramsize);163 164 return ret;165}166 167static int adsp_sram_power_on(struct device *dev, bool on)168{169 void __iomem *va_dspsysreg;170 u32 srampool_con;171 172 va_dspsysreg = ioremap(ADSP_SRAM_POOL_CON, 0x4);173 if (!va_dspsysreg) {174 dev_err(dev, "failed to ioremap sram pool base %#x\n",175 ADSP_SRAM_POOL_CON);176 return -ENOMEM;177 }178 179 srampool_con = readl(va_dspsysreg);180 if (on)181 writel(srampool_con & ~DSP_SRAM_POOL_PD_MASK, va_dspsysreg);182 else183 writel(srampool_con | DSP_SRAM_POOL_PD_MASK, va_dspsysreg);184 185 iounmap(va_dspsysreg);186 return 0;187}188 189/* Init the basic DSP DRAM address */190static int adsp_memory_remap_init(struct device *dev, struct mtk_adsp_chip_info *adsp)191{192 void __iomem *vaddr_emi_map;193 int offset;194 195 if (!adsp)196 return -ENXIO;197 198 vaddr_emi_map = devm_ioremap(dev, DSP_EMI_MAP_ADDR, 0x4);199 if (!vaddr_emi_map) {200 dev_err(dev, "failed to ioremap emi map base %#x\n",201 DSP_EMI_MAP_ADDR);202 return -ENOMEM;203 }204 205 offset = adsp->pa_dram - DRAM_PHYS_BASE_FROM_DSP_VIEW;206 adsp->dram_offset = offset;207 offset >>= DRAM_REMAP_SHIFT;208 dev_dbg(dev, "adsp->pa_dram %pa, offset %#x\n", &adsp->pa_dram, offset);209 writel(offset, vaddr_emi_map);210 if (offset != readl(vaddr_emi_map)) {211 dev_err(dev, "write emi map fail : %#x\n", readl(vaddr_emi_map));212 return -EIO;213 }214 215 return 0;216}217 218static int mt8195_run(struct snd_sof_dev *sdev)219{220 u32 adsp_bootup_addr;221 222 adsp_bootup_addr = SRAM_PHYS_BASE_FROM_DSP_VIEW;223 dev_dbg(sdev->dev, "HIFIxDSP boot from base : 0x%08X\n", adsp_bootup_addr);224 sof_hifixdsp_boot_sequence(sdev, adsp_bootup_addr);225 226 return 0;227}228 229static int mt8195_dsp_probe(struct snd_sof_dev *sdev)230{231 struct platform_device *pdev = container_of(sdev->dev, struct platform_device, dev);232 struct adsp_priv *priv;233 int ret;234 235 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);236 if (!priv)237 return -ENOMEM;238 239 sdev->pdata->hw_pdata = priv;240 priv->dev = sdev->dev;241 priv->sdev = sdev;242 243 priv->adsp = devm_kzalloc(&pdev->dev, sizeof(struct mtk_adsp_chip_info), GFP_KERNEL);244 if (!priv->adsp)245 return -ENOMEM;246 247 ret = platform_parse_resource(pdev, priv->adsp);248 if (ret)249 return ret;250 251 ret = mt8195_adsp_init_clock(sdev);252 if (ret) {253 dev_err(sdev->dev, "mt8195_adsp_init_clock failed\n");254 return -EINVAL;255 }256 257 ret = adsp_clock_on(sdev);258 if (ret) {259 dev_err(sdev->dev, "adsp_clock_on fail!\n");260 return -EINVAL;261 }262 263 ret = adsp_sram_power_on(sdev->dev, true);264 if (ret) {265 dev_err(sdev->dev, "adsp_sram_power_on fail!\n");266 goto exit_clk_disable;267 }268 269 ret = adsp_memory_remap_init(&pdev->dev, priv->adsp);270 if (ret) {271 dev_err(sdev->dev, "adsp_memory_remap_init fail!\n");272 goto err_adsp_sram_power_off;273 }274 275 sdev->bar[SOF_FW_BLK_TYPE_IRAM] = devm_ioremap(sdev->dev,276 priv->adsp->pa_sram,277 priv->adsp->sramsize);278 if (!sdev->bar[SOF_FW_BLK_TYPE_IRAM]) {279 dev_err(sdev->dev, "failed to ioremap base %pa size %#x\n",280 &priv->adsp->pa_sram, priv->adsp->sramsize);281 ret = -EINVAL;282 goto err_adsp_sram_power_off;283 }284 285 priv->adsp->va_sram = sdev->bar[SOF_FW_BLK_TYPE_IRAM];286 287 sdev->bar[SOF_FW_BLK_TYPE_SRAM] = devm_ioremap(sdev->dev,288 priv->adsp->pa_dram,289 priv->adsp->dramsize);290 if (!sdev->bar[SOF_FW_BLK_TYPE_SRAM]) {291 dev_err(sdev->dev, "failed to ioremap base %pa size %#x\n",292 &priv->adsp->pa_dram, priv->adsp->dramsize);293 ret = -EINVAL;294 goto err_adsp_sram_power_off;295 }296 priv->adsp->va_dram = sdev->bar[SOF_FW_BLK_TYPE_SRAM];297 298 sdev->bar[DSP_REG_BAR] = priv->adsp->va_cfgreg;299 300 sdev->mmio_bar = SOF_FW_BLK_TYPE_SRAM;301 sdev->mailbox_bar = SOF_FW_BLK_TYPE_SRAM;302 303 /* set default mailbox offset for FW ready message */304 sdev->dsp_box.offset = mt8195_get_mailbox_offset(sdev);305 306 priv->ipc_dev = platform_device_register_data(&pdev->dev, "mtk-adsp-ipc",307 PLATFORM_DEVID_NONE,308 pdev, sizeof(*pdev));309 if (IS_ERR(priv->ipc_dev)) {310 ret = PTR_ERR(priv->ipc_dev);311 dev_err(sdev->dev, "failed to register mtk-adsp-ipc device\n");312 goto err_adsp_sram_power_off;313 }314 315 priv->dsp_ipc = dev_get_drvdata(&priv->ipc_dev->dev);316 if (!priv->dsp_ipc) {317 ret = -EPROBE_DEFER;318 dev_err(sdev->dev, "failed to get drvdata\n");319 goto exit_pdev_unregister;320 }321 322 mtk_adsp_ipc_set_data(priv->dsp_ipc, priv);323 priv->dsp_ipc->ops = &dsp_ops;324 325 return 0;326 327exit_pdev_unregister:328 platform_device_unregister(priv->ipc_dev);329err_adsp_sram_power_off:330 adsp_sram_power_on(&pdev->dev, false);331exit_clk_disable:332 adsp_clock_off(sdev);333 334 return ret;335}336 337static int mt8195_dsp_shutdown(struct snd_sof_dev *sdev)338{339 return snd_sof_suspend(sdev->dev);340}341 342static void mt8195_dsp_remove(struct snd_sof_dev *sdev)343{344 struct platform_device *pdev = container_of(sdev->dev, struct platform_device, dev);345 struct adsp_priv *priv = sdev->pdata->hw_pdata;346 347 platform_device_unregister(priv->ipc_dev);348 adsp_sram_power_on(&pdev->dev, false);349 adsp_clock_off(sdev);350}351 352static int mt8195_dsp_suspend(struct snd_sof_dev *sdev, u32 target_state)353{354 struct platform_device *pdev = container_of(sdev->dev, struct platform_device, dev);355 int ret;356 u32 reset_sw, dbg_pc;357 358 /* wait dsp enter idle, timeout is 1 second */359 ret = snd_sof_dsp_read_poll_timeout(sdev, DSP_REG_BAR,360 DSP_RESET_SW, reset_sw,361 ((reset_sw & ADSP_PWAIT) == ADSP_PWAIT),362 SUSPEND_DSP_IDLE_POLL_INTERVAL_US,363 SUSPEND_DSP_IDLE_TIMEOUT_US);364 if (ret < 0) {365 dbg_pc = snd_sof_dsp_read(sdev, DSP_REG_BAR, DSP_PDEBUGPC);366 dev_warn(sdev->dev, "dsp not idle, powering off anyway : swrest %#x, pc %#x, ret %d\n",367 reset_sw, dbg_pc, ret);368 }369 370 /* stall and reset dsp */371 sof_hifixdsp_shutdown(sdev);372 373 /* power down adsp sram */374 ret = adsp_sram_power_on(&pdev->dev, false);375 if (ret) {376 dev_err(sdev->dev, "adsp_sram_power_off fail!\n");377 return ret;378 }379 380 /* turn off adsp clock */381 return adsp_clock_off(sdev);382}383 384static int mt8195_dsp_resume(struct snd_sof_dev *sdev)385{386 int ret;387 388 /* turn on adsp clock */389 ret = adsp_clock_on(sdev);390 if (ret) {391 dev_err(sdev->dev, "adsp_clock_on fail!\n");392 return ret;393 }394 395 /* power on adsp sram */396 ret = adsp_sram_power_on(sdev->dev, true);397 if (ret)398 dev_err(sdev->dev, "adsp_sram_power_on fail!\n");399 400 return ret;401}402 403/* on mt8195 there is 1 to 1 match between type and BAR idx */404static int mt8195_get_bar_index(struct snd_sof_dev *sdev, u32 type)405{406 return type;407}408 409static int mt8195_pcm_hw_params(struct snd_sof_dev *sdev,410 struct snd_pcm_substream *substream,411 struct snd_pcm_hw_params *params,412 struct snd_sof_platform_stream_params *platform_params)413{414 platform_params->cont_update_posn = 1;415 416 return 0;417}418 419static snd_pcm_uframes_t mt8195_pcm_pointer(struct snd_sof_dev *sdev,420 struct snd_pcm_substream *substream)421{422 int ret;423 snd_pcm_uframes_t pos;424 struct snd_sof_pcm *spcm;425 struct sof_ipc_stream_posn posn;426 struct snd_sof_pcm_stream *stream;427 struct snd_soc_component *scomp = sdev->component;428 struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream);429 430 spcm = snd_sof_find_spcm_dai(scomp, rtd);431 if (!spcm) {432 dev_warn_ratelimited(sdev->dev, "warn: can't find PCM with DAI ID %d\n",433 rtd->dai_link->id);434 return 0;435 }436 437 stream = &spcm->stream[substream->stream];438 ret = snd_sof_ipc_msg_data(sdev, stream, &posn, sizeof(posn));439 if (ret < 0) {440 dev_warn(sdev->dev, "failed to read stream position: %d\n", ret);441 return 0;442 }443 444 memcpy(&stream->posn, &posn, sizeof(posn));445 pos = spcm->stream[substream->stream].posn.host_posn;446 pos = bytes_to_frames(substream->runtime, pos);447 448 return pos;449}450 451static void mt8195_adsp_dump(struct snd_sof_dev *sdev, u32 flags)452{453 u32 dbg_pc, dbg_data, dbg_bus0, dbg_bus1, dbg_inst;454 u32 dbg_ls0stat, dbg_ls1stat, faultbus, faultinfo, swrest;455 456 /* dump debug registers */457 dbg_pc = snd_sof_dsp_read(sdev, DSP_REG_BAR, DSP_PDEBUGPC);458 dbg_data = snd_sof_dsp_read(sdev, DSP_REG_BAR, DSP_PDEBUGDATA);459 dbg_bus0 = snd_sof_dsp_read(sdev, DSP_REG_BAR, DSP_PDEBUGBUS0);460 dbg_bus1 = snd_sof_dsp_read(sdev, DSP_REG_BAR, DSP_PDEBUGBUS1);461 dbg_inst = snd_sof_dsp_read(sdev, DSP_REG_BAR, DSP_PDEBUGINST);462 dbg_ls0stat = snd_sof_dsp_read(sdev, DSP_REG_BAR, DSP_PDEBUGLS0STAT);463 dbg_ls1stat = snd_sof_dsp_read(sdev, DSP_REG_BAR, DSP_PDEBUGLS1STAT);464 faultbus = snd_sof_dsp_read(sdev, DSP_REG_BAR, DSP_PFAULTBUS);465 faultinfo = snd_sof_dsp_read(sdev, DSP_REG_BAR, DSP_PFAULTINFO);466 swrest = snd_sof_dsp_read(sdev, DSP_REG_BAR, DSP_RESET_SW);467 468 dev_info(sdev->dev, "adsp dump : pc %#x, data %#x, bus0 %#x, bus1 %#x, swrest %#x",469 dbg_pc, dbg_data, dbg_bus0, dbg_bus1, swrest);470 dev_info(sdev->dev, "dbg_inst %#x, ls0stat %#x, ls1stat %#x, faultbus %#x, faultinfo %#x",471 dbg_inst, dbg_ls0stat, dbg_ls1stat, faultbus, faultinfo);472 473 mtk_adsp_dump(sdev, flags);474}475 476static struct snd_soc_dai_driver mt8195_dai[] = {477{478 .name = "SOF_DL2",479 .playback = {480 .channels_min = 1,481 .channels_max = 2,482 },483},484{485 .name = "SOF_DL3",486 .playback = {487 .channels_min = 1,488 .channels_max = 2,489 },490},491{492 .name = "SOF_UL4",493 .capture = {494 .channels_min = 1,495 .channels_max = 2,496 },497},498{499 .name = "SOF_UL5",500 .capture = {501 .channels_min = 1,502 .channels_max = 2,503 },504},505};506 507/* mt8195 ops */508static const struct snd_sof_dsp_ops sof_mt8195_ops = {509 /* probe and remove */510 .probe = mt8195_dsp_probe,511 .remove = mt8195_dsp_remove,512 .shutdown = mt8195_dsp_shutdown,513 514 /* DSP core boot */515 .run = mt8195_run,516 517 /* Block IO */518 .block_read = sof_block_read,519 .block_write = sof_block_write,520 521 /* Mailbox IO */522 .mailbox_read = sof_mailbox_read,523 .mailbox_write = sof_mailbox_write,524 525 /* Register IO */526 .write = sof_io_write,527 .read = sof_io_read,528 .write64 = sof_io_write64,529 .read64 = sof_io_read64,530 531 /* ipc */532 .send_msg = mt8195_send_msg,533 .get_mailbox_offset = mt8195_get_mailbox_offset,534 .get_window_offset = mt8195_get_window_offset,535 .ipc_msg_data = sof_ipc_msg_data,536 .set_stream_data_offset = sof_set_stream_data_offset,537 538 /* misc */539 .get_bar_index = mt8195_get_bar_index,540 541 /* stream callbacks */542 .pcm_open = sof_stream_pcm_open,543 .pcm_hw_params = mt8195_pcm_hw_params,544 .pcm_pointer = mt8195_pcm_pointer,545 .pcm_close = sof_stream_pcm_close,546 547 /* firmware loading */548 .load_firmware = snd_sof_load_firmware_memcpy,549 550 /* Firmware ops */551 .dsp_arch_ops = &sof_xtensa_arch_ops,552 553 /* Debug information */554 .dbg_dump = mt8195_adsp_dump,555 .debugfs_add_region_item = snd_sof_debugfs_add_region_item_iomem,556 557 /* DAI drivers */558 .drv = mt8195_dai,559 .num_drv = ARRAY_SIZE(mt8195_dai),560 561 /* PM */562 .suspend = mt8195_dsp_suspend,563 .resume = mt8195_dsp_resume,564 565 /* ALSA HW info flags */566 .hw_info = SNDRV_PCM_INFO_MMAP |567 SNDRV_PCM_INFO_MMAP_VALID |568 SNDRV_PCM_INFO_INTERLEAVED |569 SNDRV_PCM_INFO_PAUSE |570 SNDRV_PCM_INFO_NO_PERIOD_WAKEUP,571};572 573static struct snd_sof_of_mach sof_mt8195_machs[] = {574 {575 .compatible = "google,tomato",576 .sof_tplg_filename = "sof-mt8195-mt6359-rt1019-rt5682.tplg"577 }, {578 .compatible = "google,dojo",579 .sof_tplg_filename = "sof-mt8195-mt6359-max98390-rt5682.tplg"580 }, {581 .compatible = "mediatek,mt8195",582 .sof_tplg_filename = "sof-mt8195.tplg"583 }, {584 /* sentinel */585 }586};587 588static const struct sof_dev_desc sof_of_mt8195_desc = {589 .of_machines = sof_mt8195_machs,590 .ipc_supported_mask = BIT(SOF_IPC_TYPE_3),591 .ipc_default = SOF_IPC_TYPE_3,592 .default_fw_path = {593 [SOF_IPC_TYPE_3] = "mediatek/sof",594 },595 .default_tplg_path = {596 [SOF_IPC_TYPE_3] = "mediatek/sof-tplg",597 },598 .default_fw_filename = {599 [SOF_IPC_TYPE_3] = "sof-mt8195.ri",600 },601 .nocodec_tplg_filename = "sof-mt8195-nocodec.tplg",602 .ops = &sof_mt8195_ops,603 .ipc_timeout = 1000,604};605 606static const struct of_device_id sof_of_mt8195_ids[] = {607 { .compatible = "mediatek,mt8195-dsp", .data = &sof_of_mt8195_desc},608 { }609};610MODULE_DEVICE_TABLE(of, sof_of_mt8195_ids);611 612/* DT driver definition */613static struct platform_driver snd_sof_of_mt8195_driver = {614 .probe = sof_of_probe,615 .remove = sof_of_remove,616 .shutdown = sof_of_shutdown,617 .driver = {618 .name = "sof-audio-of-mt8195",619 .pm = &sof_of_pm,620 .of_match_table = sof_of_mt8195_ids,621 },622};623module_platform_driver(snd_sof_of_mt8195_driver);624 625MODULE_LICENSE("Dual BSD/GPL");626MODULE_DESCRIPTION("SOF support for MTL 8195 platforms");627MODULE_IMPORT_NS(SND_SOC_SOF_XTENSA);628MODULE_IMPORT_NS(SND_SOC_SOF_MTK_COMMON);629