162 lines · c
1/* SPDX-License-Identifier: GPL-2.0 */2 3/*4 * Copyright (c) 2021 MediaTek Corporation. All rights reserved.5 *6 * Header file for the mt8195 DSP register definition7 */8 9#ifndef __MT8195_H10#define __MT8195_H11 12struct mtk_adsp_chip_info;13struct snd_sof_dev;14 15#define DSP_REG_BASE 0x1080300016#define SCP_CFGREG_BASE 0x1072400017#define DSP_SYSAO_BASE 0x1080C00018 19/*****************************************************************************20 * R E G I S T E R TABLE21 *****************************************************************************/22#define DSP_JTAGMUX 0x000023#define DSP_ALTRESETVEC 0x000424#define DSP_PDEBUGDATA 0x000825#define DSP_PDEBUGBUS0 0x000c26#define PDEBUG_ENABLE BIT(0)27#define DSP_PDEBUGBUS1 0x001028#define DSP_PDEBUGINST 0x001429#define DSP_PDEBUGLS0STAT 0x001830#define DSP_PDEBUGLS1STAT 0x001c31#define DSP_PDEBUGPC 0x002032#define DSP_RESET_SW 0x0024 /*reset sw*/33#define ADSP_BRESET_SW BIT(0)34#define ADSP_DRESET_SW BIT(1)35#define ADSP_RUNSTALL BIT(3)36#define STATVECTOR_SEL BIT(4)37#define ADSP_PWAIT BIT(16)38#define DSP_PFAULTBUS 0x002839#define DSP_PFAULTINFO 0x002c40#define DSP_GPR00 0x003041#define DSP_GPR01 0x003442#define DSP_GPR02 0x003843#define DSP_GPR03 0x003c44#define DSP_GPR04 0x004045#define DSP_GPR05 0x004446#define DSP_GPR06 0x004847#define DSP_GPR07 0x004c48#define DSP_GPR08 0x005049#define DSP_GPR09 0x005450#define DSP_GPR0A 0x005851#define DSP_GPR0B 0x005c52#define DSP_GPR0C 0x006053#define DSP_GPR0D 0x006454#define DSP_GPR0E 0x006855#define DSP_GPR0F 0x006c56#define DSP_GPR10 0x007057#define DSP_GPR11 0x007458#define DSP_GPR12 0x007859#define DSP_GPR13 0x007c60#define DSP_GPR14 0x008061#define DSP_GPR15 0x008462#define DSP_GPR16 0x008863#define DSP_GPR17 0x008c64#define DSP_GPR18 0x009065#define DSP_GPR19 0x009466#define DSP_GPR1A 0x009867#define DSP_GPR1B 0x009c68#define DSP_GPR1C 0x00a069#define DSP_GPR1D 0x00a470#define DSP_GPR1E 0x00a871#define DSP_GPR1F 0x00ac72#define DSP_TCM_OFFSET 0x00b0 /* not used */73#define DSP_DDR_OFFSET 0x00b4 /* not used */74#define DSP_INTFDSP 0x00d075#define DSP_INTFDSP_CLR 0x00d476#define DSP_SRAM_PD_SW1 0x00d877#define DSP_SRAM_PD_SW2 0x00dc78#define DSP_OCD 0x00e079#define DSP_RG_DSP_IRQ_POL 0x00f0 /* not used */80#define DSP_DSP_IRQ_EN 0x00f4 /* not used */81#define DSP_DSP_IRQ_LEVEL 0x00f8 /* not used */82#define DSP_DSP_IRQ_STATUS 0x00fc /* not used */83#define DSP_RG_INT2CIRQ 0x011484#define DSP_RG_INT_POL_CTL0 0x012085#define DSP_RG_INT_EN_CTL0 0x013086#define DSP_RG_INT_LV_CTL0 0x014087#define DSP_RG_INT_STATUS0 0x015088#define DSP_PDEBUGSTATUS0 0x020089#define DSP_PDEBUGSTATUS1 0x020490#define DSP_PDEBUGSTATUS2 0x020891#define DSP_PDEBUGSTATUS3 0x020c92#define DSP_PDEBUGSTATUS4 0x021093#define DSP_PDEBUGSTATUS5 0x021494#define DSP_PDEBUGSTATUS6 0x021895#define DSP_PDEBUGSTATUS7 0x021c96#define DSP_DSP2PSRAM_PRIORITY 0x0220 /* not used */97#define DSP_AUDIO_DSP2SPM_INT 0x022498#define DSP_AUDIO_DSP2SPM_INT_ACK 0x022899#define DSP_AUDIO_DSP_DEBUG_SEL 0x022C100#define DSP_AUDIO_DSP_EMI_BASE_ADDR 0x02E0 /* not used */101#define DSP_AUDIO_DSP_SHARED_IRAM 0x02E4102#define DSP_AUDIO_DSP_CKCTRL_P2P_CK_CON 0x02F0103#define DSP_RG_SEMAPHORE00 0x0300104#define DSP_RG_SEMAPHORE01 0x0304105#define DSP_RG_SEMAPHORE02 0x0308106#define DSP_RG_SEMAPHORE03 0x030C107#define DSP_RG_SEMAPHORE04 0x0310108#define DSP_RG_SEMAPHORE05 0x0314109#define DSP_RG_SEMAPHORE06 0x0318110#define DSP_RG_SEMAPHORE07 0x031C111#define DSP_RESERVED_0 0x03F0112#define DSP_RESERVED_1 0x03F4113 114/* dsp wdt */115#define DSP_WDT_MODE 0x0400116 117/* dsp mbox */118#define DSP_MBOX_IN_CMD 0x00119#define DSP_MBOX_IN_CMD_CLR 0x04120#define DSP_MBOX_OUT_CMD 0x1c121#define DSP_MBOX_OUT_CMD_CLR 0x20122#define DSP_MBOX_IN_MSG0 0x08123#define DSP_MBOX_IN_MSG1 0x0C124#define DSP_MBOX_OUT_MSG0 0x24125#define DSP_MBOX_OUT_MSG1 0x28126 127/*dsp sys ao*/128#define ADSP_SRAM_POOL_CON (DSP_SYSAO_BASE + 0x30)129#define DSP_SRAM_POOL_PD_MASK 0xf130#define DSP_EMI_MAP_ADDR (DSP_SYSAO_BASE + 0x81c)131 132/* DSP memories */133#define MBOX_OFFSET 0x800000 /* DRAM */134#define MBOX_SIZE 0x1000 /* consistent with which in memory.h of sof fw */135#define DSP_DRAM_SIZE 0x1000000 /* 16M */136 137#define DSP_REG_BAR 4138#define DSP_MBOX0_BAR 5139#define DSP_MBOX1_BAR 6140#define DSP_MBOX2_BAR 7141 142#define SIZE_SHARED_DRAM_DL 0x40000 /*Shared buffer for Downlink*/143#define SIZE_SHARED_DRAM_UL 0x40000 /*Shared buffer for Uplink*/144 145#define TOTAL_SIZE_SHARED_DRAM_FROM_TAIL \146 (SIZE_SHARED_DRAM_DL + SIZE_SHARED_DRAM_UL)147 148#define SRAM_PHYS_BASE_FROM_DSP_VIEW 0x40000000 /* MT8195 DSP view */149#define DRAM_PHYS_BASE_FROM_DSP_VIEW 0x60000000 /* MT8195 DSP view */150 151/*remap dram between AP and DSP view, 4KB aligned*/152#define DRAM_REMAP_SHIFT 12153#define DRAM_REMAP_MASK (BIT(DRAM_REMAP_SHIFT) - 1)154 155/* suspend dsp idle check interval and timeout */156#define SUSPEND_DSP_IDLE_TIMEOUT_US 1000000 /* timeout to wait dsp idle, 1 sec */157#define SUSPEND_DSP_IDLE_POLL_INTERVAL_US 500 /* 0.5 msec */158 159void sof_hifixdsp_boot_sequence(struct snd_sof_dev *sdev, u32 boot_addr);160void sof_hifixdsp_shutdown(struct snd_sof_dev *sdev);161#endif162