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1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)2//3// This file is provided under a dual BSD/GPLv2 license. When using or4// redistributing this file, you may do so under either license.5//6// Copyright(c) 2018 Intel Corporation7//8// Author: Pan Xiuli <xiuli.pan@linux.intel.com>9//10 11#include <linux/module.h>12#include <sound/sof.h>13#include <sound/sof/xtensa.h>14#include "../sof-priv.h"15 16struct xtensa_exception_cause {17 u32 id;18 const char *msg;19 const char *description;20};21 22/*23 * From 4.4.1.5 table 4-64 Exception Causes of Xtensa24 * Instruction Set Architecture (ISA) Reference Manual25 */26static const struct xtensa_exception_cause xtensa_exception_causes[] = {27 {0, "IllegalInstructionCause", "Illegal instruction"},28 {1, "SyscallCause", "SYSCALL instruction"},29 {2, "InstructionFetchErrorCause",30 "Processor internal physical address or data error during instruction fetch"},31 {3, "LoadStoreErrorCause",32 "Processor internal physical address or data error during load or store"},33 {4, "Level1InterruptCause",34 "Level-1 interrupt as indicated by set level-1 bits in the INTERRUPT register"},35 {5, "AllocaCause",36 "MOVSP instruction, if caller’s registers are not in the register file"},37 {6, "IntegerDivideByZeroCause",38 "QUOS, QUOU, REMS, or REMU divisor operand is zero"},39 {8, "PrivilegedCause",40 "Attempt to execute a privileged operation when CRING ? 0"},41 {9, "LoadStoreAlignmentCause", "Load or store to an unaligned address"},42 {12, "InstrPIFDataErrorCause",43 "PIF data error during instruction fetch"},44 {13, "LoadStorePIFDataErrorCause",45 "Synchronous PIF data error during LoadStore access"},46 {14, "InstrPIFAddrErrorCause",47 "PIF address error during instruction fetch"},48 {15, "LoadStorePIFAddrErrorCause",49 "Synchronous PIF address error during LoadStore access"},50 {16, "InstTLBMissCause", "Error during Instruction TLB refill"},51 {17, "InstTLBMultiHitCause",52 "Multiple instruction TLB entries matched"},53 {18, "InstFetchPrivilegeCause",54 "An instruction fetch referenced a virtual address at a ring level less than CRING"},55 {20, "InstFetchProhibitedCause",56 "An instruction fetch referenced a page mapped with an attribute that does not permit instruction fetch"},57 {24, "LoadStoreTLBMissCause",58 "Error during TLB refill for a load or store"},59 {25, "LoadStoreTLBMultiHitCause",60 "Multiple TLB entries matched for a load or store"},61 {26, "LoadStorePrivilegeCause",62 "A load or store referenced a virtual address at a ring level less than CRING"},63 {28, "LoadProhibitedCause",64 "A load referenced a page mapped with an attribute that does not permit loads"},65 {32, "Coprocessor0Disabled",66 "Coprocessor 0 instruction when cp0 disabled"},67 {33, "Coprocessor1Disabled",68 "Coprocessor 1 instruction when cp1 disabled"},69 {34, "Coprocessor2Disabled",70 "Coprocessor 2 instruction when cp2 disabled"},71 {35, "Coprocessor3Disabled",72 "Coprocessor 3 instruction when cp3 disabled"},73 {36, "Coprocessor4Disabled",74 "Coprocessor 4 instruction when cp4 disabled"},75 {37, "Coprocessor5Disabled",76 "Coprocessor 5 instruction when cp5 disabled"},77 {38, "Coprocessor6Disabled",78 "Coprocessor 6 instruction when cp6 disabled"},79 {39, "Coprocessor7Disabled",80 "Coprocessor 7 instruction when cp7 disabled"},81};82 83/* only need xtensa atm */84static void xtensa_dsp_oops(struct snd_sof_dev *sdev, const char *level, void *oops)85{86 struct sof_ipc_dsp_oops_xtensa *xoops = oops;87 int i;88 89 dev_printk(level, sdev->dev, "error: DSP Firmware Oops\n");90 for (i = 0; i < ARRAY_SIZE(xtensa_exception_causes); i++) {91 if (xtensa_exception_causes[i].id == xoops->exccause) {92 dev_printk(level, sdev->dev,93 "error: Exception Cause: %s, %s\n",94 xtensa_exception_causes[i].msg,95 xtensa_exception_causes[i].description);96 }97 }98 dev_printk(level, sdev->dev,99 "EXCCAUSE 0x%8.8x EXCVADDR 0x%8.8x PS 0x%8.8x SAR 0x%8.8x\n",100 xoops->exccause, xoops->excvaddr, xoops->ps, xoops->sar);101 dev_printk(level, sdev->dev,102 "EPC1 0x%8.8x EPC2 0x%8.8x EPC3 0x%8.8x EPC4 0x%8.8x",103 xoops->epc1, xoops->epc2, xoops->epc3, xoops->epc4);104 dev_printk(level, sdev->dev,105 "EPC5 0x%8.8x EPC6 0x%8.8x EPC7 0x%8.8x DEPC 0x%8.8x",106 xoops->epc5, xoops->epc6, xoops->epc7, xoops->depc);107 dev_printk(level, sdev->dev,108 "EPS2 0x%8.8x EPS3 0x%8.8x EPS4 0x%8.8x EPS5 0x%8.8x",109 xoops->eps2, xoops->eps3, xoops->eps4, xoops->eps5);110 dev_printk(level, sdev->dev,111 "EPS6 0x%8.8x EPS7 0x%8.8x INTENABL 0x%8.8x INTERRU 0x%8.8x",112 xoops->eps6, xoops->eps7, xoops->intenable, xoops->interrupt);113}114 115static void xtensa_stack(struct snd_sof_dev *sdev, const char *level, void *oops,116 u32 *stack, u32 stack_words)117{118 struct sof_ipc_dsp_oops_xtensa *xoops = oops;119 u32 stack_ptr = xoops->plat_hdr.stackptr;120 /* 4 * 8chars + 3 ws + 1 terminating NUL */121 unsigned char buf[4 * 8 + 3 + 1];122 int i;123 124 dev_printk(level, sdev->dev, "stack dump from 0x%8.8x\n", stack_ptr);125 126 /*127 * example output:128 * 0x0049fbb0: 8000f2d0 0049fc00 6f6c6c61 00632e63129 */130 for (i = 0; i < stack_words; i += 4) {131 hex_dump_to_buffer(stack + i, 16, 16, 4,132 buf, sizeof(buf), false);133 dev_printk(level, sdev->dev, "0x%08x: %s\n", stack_ptr + i * 4, buf);134 }135 136 if (!xoops->plat_hdr.numaregs)137 return;138 139 dev_printk(level, sdev->dev, "AR registers:\n");140 /* the number of ar registers is a multiple of 4 */141 for (i = 0; i < xoops->plat_hdr.numaregs; i += 4) {142 hex_dump_to_buffer(xoops->ar + i, 16, 16, 4,143 buf, sizeof(buf), false);144 dev_printk(level, sdev->dev, "%#x: %s\n", i * 4, buf);145 }146}147 148const struct dsp_arch_ops sof_xtensa_arch_ops = {149 .dsp_oops = xtensa_dsp_oops,150 .dsp_stack = xtensa_stack,151};152EXPORT_SYMBOL_NS(sof_xtensa_arch_ops, SND_SOC_SOF_XTENSA);153 154MODULE_LICENSE("Dual BSD/GPL");155MODULE_DESCRIPTION("SOF Xtensa DSP support");156