113 lines · c
1/* SPDX-License-Identifier: GPL-2.0-only */2/*3 * tegra186_asrc.h - Definitions for Tegra186 ASRC driver4 *5 * Copyright (c) 2022, NVIDIA CORPORATION. All rights reserved.6 *7 */8 9#ifndef __TEGRA186_ASRC_H__10#define __TEGRA186_ASRC_H__11 12/* ASRC stream related offset */13#define TEGRA186_ASRC_CFG 0x014#define TEGRA186_ASRC_RATIO_INT_PART 0x415#define TEGRA186_ASRC_RATIO_FRAC_PART 0x816#define TEGRA186_ASRC_RATIO_LOCK_STATUS 0xc17#define TEGRA186_ASRC_MUTE_UNMUTE_DURATION 0x1018#define TEGRA186_ASRC_TX_THRESHOLD 0x1419#define TEGRA186_ASRC_RX_THRESHOLD 0x1820#define TEGRA186_ASRC_RATIO_COMP 0x1c21#define TEGRA186_ASRC_RX_STATUS 0x2022#define TEGRA186_ASRC_RX_CIF_CTRL 0x2423#define TEGRA186_ASRC_TX_STATUS 0x2c24#define TEGRA186_ASRC_TX_CIF_CTRL 0x3025#define TEGRA186_ASRC_ENABLE 0x3826#define TEGRA186_ASRC_SOFT_RESET 0x3c27#define TEGRA186_ASRC_STATUS 0x4c28#define TEGRA186_ASRC_STATEBUF_ADDR 0x5c29#define TEGRA186_ASRC_STATEBUF_CFG 0x6030#define TEGRA186_ASRC_INSAMPLEBUF_ADDR 0x6431#define TEGRA186_ASRC_INSAMPLEBUF_CFG 0x6832#define TEGRA186_ASRC_OUTSAMPLEBUF_ADDR 0x6c33#define TEGRA186_ASRC_OUTSAMPLEBUF_CFG 0x7034 35/* ASRC Global registers offset */36#define TEGRA186_ASRC_GLOBAL_ENB 0x2f437#define TEGRA186_ASRC_GLOBAL_SOFT_RESET 0x2f838#define TEGRA186_ASRC_GLOBAL_CG 0x2fc39#define TEGRA186_ASRC_GLOBAL_CFG 0x30040#define TEGRA186_ASRC_GLOBAL_SCRATCH_ADDR 0x30441#define TEGRA186_ASRC_GLOBAL_SCRATCH_CFG 0x30842#define TEGRA186_ASRC_RATIO_UPD_RX_CIF_CTRL 0x30c43#define TEGRA186_ASRC_RATIO_UPD_RX_STATUS 0x31044#define TEGRA186_ASRC_GLOBAL_STATUS 0x31445#define TEGRA186_ASRC_GLOBAL_STREAM_ENABLE_STATUS 0x31846#define TEGRA186_ASRC_GLOBAL_INT_STATUS 0x32447#define TEGRA186_ASRC_GLOBAL_INT_MASK 0x32848#define TEGRA186_ASRC_GLOBAL_INT_SET 0x32c49#define TEGRA186_ASRC_GLOBAL_INT_CLEAR 0x33050#define TEGRA186_ASRC_GLOBAL_TRANSFER_ERROR_LOG 0x33451#define TEGRA186_ASRC_GLOBAL_APR_CTRL 0x100052#define TEGRA186_ASRC_GLOBAL_APR_CTRL_ACCESS_CTRL 0x100453#define TEGRA186_ASRC_GLOBAL_DISARM_APR 0x100854#define TEGRA186_ASRC_GLOBAL_DISARM_APR_ACCESS_CTRL 0x100c55#define TEGRA186_ASRC_GLOBAL_RATIO_WR_ACCESS 0x101056#define TEGRA186_ASRC_GLOBAL_RATIO_WR_ACCESS_CTRL 0x101457#define TEGRA186_ASRC_CYA 0x101858 59#define TEGRA186_ASRC_STREAM_DEFAULT_HW_COMP_BIAS_VALUE 0xaaaa60#define TEGRA186_ASRC_STREAM_DEFAULT_INPUT_HW_COMP_THRESH_CFG 0x0020100261#define TEGRA186_ASRC_STREAM_DEFAULT_OUTPUT_HW_COMP_THRESH_CFG 0x0020100262 63#define TEGRA186_ASRC_GLOBAL_CFG_FRAC_28BIT_PRECISION 064#define TEGRA186_ASRC_GLOBAL_CFG_FRAC_32BIT_PRECISION 165 66#define TEGRA186_ASRC_STREAM_ENABLE_HW_RATIO_COMP_SHIFT 3167#define TEGRA186_ASRC_STREAM_ENABLE_HW_RATIO_COMP_MASK (1 << TEGRA186_ASRC_STREAM_ENABLE_HW_RATIO_COMP_SHIFT)68#define TEGRA186_ASRC_STREAM_ENABLE_HW_RATIO_COMP_ENABLE (1 << TEGRA186_ASRC_STREAM_ENABLE_HW_RATIO_COMP_SHIFT)69#define TEGRA186_ASRC_STREAM_ENABLE_HW_RATIO_COMP_DISABLE (0 << TEGRA186_ASRC_STREAM_ENABLE_HW_RATIO_COMP_SHIFT)70 71#define TEGRA186_ASRC_STREAM_RATIO_TYPE_SHIFT 072#define TEGRA186_ASRC_STREAM_RATIO_TYPE_MASK (1 << TEGRA186_ASRC_STREAM_RATIO_TYPE_SHIFT)73 74#define TEGRA186_ASRC_STREAM_EN_SHIFT 075#define TEGRA186_ASRC_STREAM_EN (1 << TEGRA186_ASRC_STREAM_EN_SHIFT)76#define TEGRA186_ASRC_GLOBAL_EN_SHIFT 077#define TEGRA186_ASRC_GLOBAL_EN (1 << TEGRA186_ASRC_GLOBAL_EN_SHIFT)78 79#define TEGRA186_ASRC_STREAM_STATEBUF_CFG_SIZE_SHIFT 080#define TEGRA186_ASRC_STREAM_STATEBUF_CFG_SIZE_MASK (0xffff << TEGRA186_ASRC_STREAM_STATEBUF_CFG_SIZE_SHIFT)81#define TEGRA186_ASRC_STREAM_INSAMPLEBUF_CFG_SIZE_SHIFT 082#define TEGRA186_ASRC_STREAM_INSAMPLEBUF_CFG_SIZE_MASK (0xffff << TEGRA186_ASRC_STREAM_INSAMPLEBUF_CFG_SIZE_SHIFT)83#define TEGRA186_ASRC_STREAM_OUTSAMPLEBUF_CFG_SIZE_SHIFT 084#define TEGRA186_ASRC_STREAM_OUTSAMPLEBUF_CFG_SIZE_MASK (0xffff << TEGRA186_ASRC_STREAM_OUTSAMPLEBUF_CFG_SIZE_SHIFT)85 86#define TEGRA186_ASRC_STREAM_RATIO_INT_PART_MASK 0x1f87#define TEGRA186_ASRC_STREAM_RATIO_FRAC_PART_MASK 0xffffffff88 89#define TEGRA186_ASRC_STREAM_STRIDE 0x8090#define TEGRA186_ASRC_STREAM_MAX 0x691#define TEGRA186_ASRC_STREAM_LIMIT 0x2f092 93#define TEGRA186_ASRC_RATIO_SOURCE_ARAD 0x094#define TEGRA186_ASRC_RATIO_SOURCE_SW 0x195 96#define TEGRA186_ASRC_ARAM_START_ADDR 0x3f80000097 98struct tegra186_asrc_lane {99 unsigned int int_part;100 unsigned int frac_part;101 unsigned int ratio_source;102 unsigned int hwcomp_disable;103 unsigned int input_thresh;104 unsigned int output_thresh;105};106 107struct tegra186_asrc {108 struct tegra186_asrc_lane lane[TEGRA186_ASRC_STREAM_MAX];109 struct regmap *regmap;110};111 112#endif113