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1/* SPDX-License-Identifier: GPL-2.0-only */2/*3 * tegra20_i2s.h - Definitions for Tegra20 I2S driver4 *5 * Author: Stephen Warren <swarren@nvidia.com>6 * Copyright (C) 2010,2012 - NVIDIA, Inc.7 *8 * Based on code copyright/by:9 *10 * Copyright (c) 2009-2010, NVIDIA Corporation.11 * Scott Peterson <speterson@nvidia.com>12 *13 * Copyright (C) 2010 Google, Inc.14 * Iliyan Malchev <malchev@google.com>15 */16 17#ifndef __TEGRA20_I2S_H__18#define __TEGRA20_I2S_H__19 20#include "tegra_pcm.h"21 22/* Register offsets from TEGRA20_I2S1_BASE and TEGRA20_I2S2_BASE */23 24#define TEGRA20_I2S_CTRL 0x0025#define TEGRA20_I2S_STATUS 0x0426#define TEGRA20_I2S_TIMING 0x0827#define TEGRA20_I2S_FIFO_SCR 0x0c28#define TEGRA20_I2S_PCM_CTRL 0x1029#define TEGRA20_I2S_NW_CTRL 0x1430#define TEGRA20_I2S_TDM_CTRL 0x2031#define TEGRA20_I2S_TDM_TX_RX_CTRL 0x2432#define TEGRA20_I2S_FIFO1 0x4033#define TEGRA20_I2S_FIFO2 0x8034 35/* Fields in TEGRA20_I2S_CTRL */36 37#define TEGRA20_I2S_CTRL_FIFO2_TX_ENABLE (1 << 30)38#define TEGRA20_I2S_CTRL_FIFO1_ENABLE (1 << 29)39#define TEGRA20_I2S_CTRL_FIFO2_ENABLE (1 << 28)40#define TEGRA20_I2S_CTRL_FIFO1_RX_ENABLE (1 << 27)41#define TEGRA20_I2S_CTRL_FIFO_LPBK_ENABLE (1 << 26)42#define TEGRA20_I2S_CTRL_MASTER_ENABLE (1 << 25)43 44#define TEGRA20_I2S_LRCK_LEFT_LOW 045#define TEGRA20_I2S_LRCK_RIGHT_LOW 146 47#define TEGRA20_I2S_CTRL_LRCK_SHIFT 2448#define TEGRA20_I2S_CTRL_LRCK_MASK (1 << TEGRA20_I2S_CTRL_LRCK_SHIFT)49#define TEGRA20_I2S_CTRL_LRCK_L_LOW (TEGRA20_I2S_LRCK_LEFT_LOW << TEGRA20_I2S_CTRL_LRCK_SHIFT)50#define TEGRA20_I2S_CTRL_LRCK_R_LOW (TEGRA20_I2S_LRCK_RIGHT_LOW << TEGRA20_I2S_CTRL_LRCK_SHIFT)51 52#define TEGRA20_I2S_BIT_FORMAT_I2S 053#define TEGRA20_I2S_BIT_FORMAT_RJM 154#define TEGRA20_I2S_BIT_FORMAT_LJM 255#define TEGRA20_I2S_BIT_FORMAT_DSP 356 57#define TEGRA20_I2S_CTRL_BIT_FORMAT_SHIFT 1058#define TEGRA20_I2S_CTRL_BIT_FORMAT_MASK (3 << TEGRA20_I2S_CTRL_BIT_FORMAT_SHIFT)59#define TEGRA20_I2S_CTRL_BIT_FORMAT_I2S (TEGRA20_I2S_BIT_FORMAT_I2S << TEGRA20_I2S_CTRL_BIT_FORMAT_SHIFT)60#define TEGRA20_I2S_CTRL_BIT_FORMAT_RJM (TEGRA20_I2S_BIT_FORMAT_RJM << TEGRA20_I2S_CTRL_BIT_FORMAT_SHIFT)61#define TEGRA20_I2S_CTRL_BIT_FORMAT_LJM (TEGRA20_I2S_BIT_FORMAT_LJM << TEGRA20_I2S_CTRL_BIT_FORMAT_SHIFT)62#define TEGRA20_I2S_CTRL_BIT_FORMAT_DSP (TEGRA20_I2S_BIT_FORMAT_DSP << TEGRA20_I2S_CTRL_BIT_FORMAT_SHIFT)63 64#define TEGRA20_I2S_BIT_SIZE_16 065#define TEGRA20_I2S_BIT_SIZE_20 166#define TEGRA20_I2S_BIT_SIZE_24 267#define TEGRA20_I2S_BIT_SIZE_32 368 69#define TEGRA20_I2S_CTRL_BIT_SIZE_SHIFT 870#define TEGRA20_I2S_CTRL_BIT_SIZE_MASK (3 << TEGRA20_I2S_CTRL_BIT_SIZE_SHIFT)71#define TEGRA20_I2S_CTRL_BIT_SIZE_16 (TEGRA20_I2S_BIT_SIZE_16 << TEGRA20_I2S_CTRL_BIT_SIZE_SHIFT)72#define TEGRA20_I2S_CTRL_BIT_SIZE_20 (TEGRA20_I2S_BIT_SIZE_20 << TEGRA20_I2S_CTRL_BIT_SIZE_SHIFT)73#define TEGRA20_I2S_CTRL_BIT_SIZE_24 (TEGRA20_I2S_BIT_SIZE_24 << TEGRA20_I2S_CTRL_BIT_SIZE_SHIFT)74#define TEGRA20_I2S_CTRL_BIT_SIZE_32 (TEGRA20_I2S_BIT_SIZE_32 << TEGRA20_I2S_CTRL_BIT_SIZE_SHIFT)75 76#define TEGRA20_I2S_FIFO_16_LSB 077#define TEGRA20_I2S_FIFO_20_LSB 178#define TEGRA20_I2S_FIFO_24_LSB 279#define TEGRA20_I2S_FIFO_32 380#define TEGRA20_I2S_FIFO_PACKED 781 82#define TEGRA20_I2S_CTRL_FIFO_FORMAT_SHIFT 483#define TEGRA20_I2S_CTRL_FIFO_FORMAT_MASK (7 << TEGRA20_I2S_CTRL_FIFO_FORMAT_SHIFT)84#define TEGRA20_I2S_CTRL_FIFO_FORMAT_16_LSB (TEGRA20_I2S_FIFO_16_LSB << TEGRA20_I2S_CTRL_FIFO_FORMAT_SHIFT)85#define TEGRA20_I2S_CTRL_FIFO_FORMAT_20_LSB (TEGRA20_I2S_FIFO_20_LSB << TEGRA20_I2S_CTRL_FIFO_FORMAT_SHIFT)86#define TEGRA20_I2S_CTRL_FIFO_FORMAT_24_LSB (TEGRA20_I2S_FIFO_24_LSB << TEGRA20_I2S_CTRL_FIFO_FORMAT_SHIFT)87#define TEGRA20_I2S_CTRL_FIFO_FORMAT_32 (TEGRA20_I2S_FIFO_32 << TEGRA20_I2S_CTRL_FIFO_FORMAT_SHIFT)88#define TEGRA20_I2S_CTRL_FIFO_FORMAT_PACKED (TEGRA20_I2S_FIFO_PACKED << TEGRA20_I2S_CTRL_FIFO_FORMAT_SHIFT)89 90#define TEGRA20_I2S_CTRL_IE_FIFO1_ERR (1 << 3)91#define TEGRA20_I2S_CTRL_IE_FIFO2_ERR (1 << 2)92#define TEGRA20_I2S_CTRL_QE_FIFO1 (1 << 1)93#define TEGRA20_I2S_CTRL_QE_FIFO2 (1 << 0)94 95/* Fields in TEGRA20_I2S_STATUS */96 97#define TEGRA20_I2S_STATUS_FIFO1_RDY (1 << 31)98#define TEGRA20_I2S_STATUS_FIFO2_RDY (1 << 30)99#define TEGRA20_I2S_STATUS_FIFO1_BSY (1 << 29)100#define TEGRA20_I2S_STATUS_FIFO2_BSY (1 << 28)101#define TEGRA20_I2S_STATUS_FIFO1_ERR (1 << 3)102#define TEGRA20_I2S_STATUS_FIFO2_ERR (1 << 2)103#define TEGRA20_I2S_STATUS_QS_FIFO1 (1 << 1)104#define TEGRA20_I2S_STATUS_QS_FIFO2 (1 << 0)105 106/* Fields in TEGRA20_I2S_TIMING */107 108#define TEGRA20_I2S_TIMING_NON_SYM_ENABLE (1 << 12)109#define TEGRA20_I2S_TIMING_CHANNEL_BIT_COUNT_SHIFT 0110#define TEGRA20_I2S_TIMING_CHANNEL_BIT_COUNT_MASK_US 0x7ff111#define TEGRA20_I2S_TIMING_CHANNEL_BIT_COUNT_MASK (TEGRA20_I2S_TIMING_CHANNEL_BIT_COUNT_MASK_US << TEGRA20_I2S_TIMING_CHANNEL_BIT_COUNT_SHIFT)112 113/* Fields in TEGRA20_I2S_FIFO_SCR */114 115#define TEGRA20_I2S_FIFO_SCR_FIFO2_FULL_EMPTY_COUNT_SHIFT 24116#define TEGRA20_I2S_FIFO_SCR_FIFO1_FULL_EMPTY_COUNT_SHIFT 16117#define TEGRA20_I2S_FIFO_SCR_FIFO_FULL_EMPTY_COUNT_MASK 0x3f118 119#define TEGRA20_I2S_FIFO_SCR_FIFO2_CLR (1 << 12)120#define TEGRA20_I2S_FIFO_SCR_FIFO1_CLR (1 << 8)121 122#define TEGRA20_I2S_FIFO_ATN_LVL_ONE_SLOT 0123#define TEGRA20_I2S_FIFO_ATN_LVL_FOUR_SLOTS 1124#define TEGRA20_I2S_FIFO_ATN_LVL_EIGHT_SLOTS 2125#define TEGRA20_I2S_FIFO_ATN_LVL_TWELVE_SLOTS 3126 127#define TEGRA20_I2S_FIFO_SCR_FIFO2_ATN_LVL_SHIFT 4128#define TEGRA20_I2S_FIFO_SCR_FIFO2_ATN_LVL_MASK (3 << TEGRA20_I2S_FIFO_SCR_FIFO2_ATN_LVL_SHIFT)129#define TEGRA20_I2S_FIFO_SCR_FIFO2_ATN_LVL_ONE_SLOT (TEGRA20_I2S_FIFO_ATN_LVL_ONE_SLOT << TEGRA20_I2S_FIFO_SCR_FIFO2_ATN_LVL_SHIFT)130#define TEGRA20_I2S_FIFO_SCR_FIFO2_ATN_LVL_FOUR_SLOTS (TEGRA20_I2S_FIFO_ATN_LVL_FOUR_SLOTS << TEGRA20_I2S_FIFO_SCR_FIFO2_ATN_LVL_SHIFT)131#define TEGRA20_I2S_FIFO_SCR_FIFO2_ATN_LVL_EIGHT_SLOTS (TEGRA20_I2S_FIFO_ATN_LVL_EIGHT_SLOTS << TEGRA20_I2S_FIFO_SCR_FIFO2_ATN_LVL_SHIFT)132#define TEGRA20_I2S_FIFO_SCR_FIFO2_ATN_LVL_TWELVE_SLOTS (TEGRA20_I2S_FIFO_ATN_LVL_TWELVE_SLOTS << TEGRA20_I2S_FIFO_SCR_FIFO2_ATN_LVL_SHIFT)133 134#define TEGRA20_I2S_FIFO_SCR_FIFO1_ATN_LVL_SHIFT 0135#define TEGRA20_I2S_FIFO_SCR_FIFO1_ATN_LVL_MASK (3 << TEGRA20_I2S_FIFO_SCR_FIFO1_ATN_LVL_SHIFT)136#define TEGRA20_I2S_FIFO_SCR_FIFO1_ATN_LVL_ONE_SLOT (TEGRA20_I2S_FIFO_ATN_LVL_ONE_SLOT << TEGRA20_I2S_FIFO_SCR_FIFO1_ATN_LVL_SHIFT)137#define TEGRA20_I2S_FIFO_SCR_FIFO1_ATN_LVL_FOUR_SLOTS (TEGRA20_I2S_FIFO_ATN_LVL_FOUR_SLOTS << TEGRA20_I2S_FIFO_SCR_FIFO1_ATN_LVL_SHIFT)138#define TEGRA20_I2S_FIFO_SCR_FIFO1_ATN_LVL_EIGHT_SLOTS (TEGRA20_I2S_FIFO_ATN_LVL_EIGHT_SLOTS << TEGRA20_I2S_FIFO_SCR_FIFO1_ATN_LVL_SHIFT)139#define TEGRA20_I2S_FIFO_SCR_FIFO1_ATN_LVL_TWELVE_SLOTS (TEGRA20_I2S_FIFO_ATN_LVL_TWELVE_SLOTS << TEGRA20_I2S_FIFO_SCR_FIFO1_ATN_LVL_SHIFT)140 141struct tegra20_i2s {142 struct snd_soc_dai_driver dai;143 struct clk *clk_i2s;144 struct snd_dmaengine_dai_dma_data capture_dma_data;145 struct snd_dmaengine_dai_dma_data playback_dma_data;146 struct regmap *regmap;147 struct reset_control *reset;148};149 150#endif151