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1/* SPDX-License-Identifier: GPL-2.0-only */2/*3 * tegra210_adx.h - Definitions for Tegra210 ADX driver4 *5 * Copyright (c) 2021, NVIDIA CORPORATION. All rights reserved.6 *7 */8 9#ifndef __TEGRA210_ADX_H__10#define __TEGRA210_ADX_H__11 12/* Register offsets from TEGRA210_ADX*_BASE */13#define TEGRA210_ADX_RX_STATUS 0x0c14#define TEGRA210_ADX_RX_INT_STATUS 0x1015#define TEGRA210_ADX_RX_INT_MASK 0x1416#define TEGRA210_ADX_RX_INT_SET 0x1817#define TEGRA210_ADX_RX_INT_CLEAR 0x1c18#define TEGRA210_ADX_RX_CIF_CTRL 0x2019#define TEGRA210_ADX_TX_STATUS 0x4c20#define TEGRA210_ADX_TX_INT_STATUS 0x5021#define TEGRA210_ADX_TX_INT_MASK 0x5422#define TEGRA210_ADX_TX_INT_SET 0x5823#define TEGRA210_ADX_TX_INT_CLEAR 0x5c24#define TEGRA210_ADX_TX1_CIF_CTRL 0x6025#define TEGRA210_ADX_TX2_CIF_CTRL 0x6426#define TEGRA210_ADX_TX3_CIF_CTRL 0x6827#define TEGRA210_ADX_TX4_CIF_CTRL 0x6c28#define TEGRA210_ADX_ENABLE 0x8029#define TEGRA210_ADX_SOFT_RESET 0x8430#define TEGRA210_ADX_CG 0x8831#define TEGRA210_ADX_STATUS 0x8c32#define TEGRA210_ADX_INT_STATUS 0x9033#define TEGRA210_ADX_CTRL 0xa434#define TEGRA210_ADX_IN_BYTE_EN0 0xa835#define TEGRA210_ADX_IN_BYTE_EN1 0xac36#define TEGRA210_ADX_CFG_RAM_CTRL 0xb837#define TEGRA210_ADX_CFG_RAM_DATA 0xbc38 39/* Fields in TEGRA210_ADX_ENABLE */40#define TEGRA210_ADX_ENABLE_SHIFT 041 42/* Fields in TEGRA210_ADX_CFG_RAM_CTRL */43#define TEGRA210_ADX_CFG_RAM_CTRL_RAM_ADDR_SHIFT 044 45#define TEGRA210_ADX_CFG_RAM_CTRL_RW_SHIFT 1446#define TEGRA210_ADX_CFG_RAM_CTRL_RW_WRITE (1 << TEGRA210_ADX_CFG_RAM_CTRL_RW_SHIFT)47 48#define TEGRA210_ADX_CFG_RAM_CTRL_ADDR_INIT_EN_SHIFT 1349#define TEGRA210_ADX_CFG_RAM_CTRL_ADDR_INIT_EN (1 << TEGRA210_ADX_CFG_RAM_CTRL_ADDR_INIT_EN_SHIFT)50 51#define TEGRA210_ADX_CFG_RAM_CTRL_SEQ_ACCESS_EN_SHIFT 1252#define TEGRA210_ADX_CFG_RAM_CTRL_SEQ_ACCESS_EN (1 << TEGRA210_ADX_CFG_RAM_CTRL_SEQ_ACCESS_EN_SHIFT)53 54/* Fields in TEGRA210_ADX_SOFT_RESET */55#define TEGRA210_ADX_SOFT_RESET_SOFT_RESET_SHIFT 056#define TEGRA210_ADX_SOFT_RESET_SOFT_RESET_MASK (1 << TEGRA210_ADX_SOFT_RESET_SOFT_RESET_SHIFT)57#define TEGRA210_ADX_SOFT_RESET_SOFT_EN (1 << TEGRA210_ADX_SOFT_RESET_SOFT_RESET_SHIFT)58#define TEGRA210_ADX_SOFT_RESET_SOFT_DEFAULT (0 << TEGRA210_ADX_SOFT_RESET_SOFT_RESET_SHIFT)59 60#define TEGRA210_ADX_AUDIOCIF_CH_STRIDE 461#define TEGRA210_ADX_RAM_DEPTH 1662#define TEGRA210_ADX_MAP_STREAM_NUMBER_SHIFT 663#define TEGRA210_ADX_MAP_WORD_NUMBER_SHIFT 264#define TEGRA210_ADX_MAP_BYTE_NUMBER_SHIFT 065 66struct tegra210_adx {67 struct regmap *regmap;68 unsigned int map[TEGRA210_ADX_RAM_DEPTH];69 unsigned int byte_mask[2];70};71 72#endif73