599 lines · c
1// SPDX-License-Identifier: GPL-2.0-only2//3// tegra210_amx.c - Tegra210 AMX driver4//5// Copyright (c) 2021-2023 NVIDIA CORPORATION. All rights reserved.6 7#include <linux/clk.h>8#include <linux/device.h>9#include <linux/io.h>10#include <linux/mod_devicetable.h>11#include <linux/module.h>12#include <linux/platform_device.h>13#include <linux/pm_runtime.h>14#include <linux/regmap.h>15#include <sound/core.h>16#include <sound/pcm.h>17#include <sound/pcm_params.h>18#include <sound/soc.h>19 20#include "tegra210_amx.h"21#include "tegra_cif.h"22 23/*24 * The counter is in terms of AHUB clock cycles. If a frame is not25 * received within these clock cycles, the AMX input channel gets26 * automatically disabled. For now the counter is calculated as a27 * function of sample rate (8 kHz) and AHUB clock (49.152 MHz).28 * If later an accurate number is needed, the counter needs to be29 * calculated at runtime.30 *31 * count = ahub_clk / sample_rate32 */33#define TEGRA194_MAX_FRAME_IDLE_COUNT 0x180034 35#define AMX_CH_REG(id, reg) ((reg) + ((id) * TEGRA210_AMX_AUDIOCIF_CH_STRIDE))36 37static const struct reg_default tegra210_amx_reg_defaults[] = {38 { TEGRA210_AMX_RX_INT_MASK, 0x0000000f},39 { TEGRA210_AMX_RX1_CIF_CTRL, 0x00007000},40 { TEGRA210_AMX_RX2_CIF_CTRL, 0x00007000},41 { TEGRA210_AMX_RX3_CIF_CTRL, 0x00007000},42 { TEGRA210_AMX_RX4_CIF_CTRL, 0x00007000},43 { TEGRA210_AMX_TX_INT_MASK, 0x00000001},44 { TEGRA210_AMX_TX_CIF_CTRL, 0x00007000},45 { TEGRA210_AMX_CG, 0x1},46 { TEGRA210_AMX_CFG_RAM_CTRL, 0x00004000},47};48 49static void tegra210_amx_write_map_ram(struct tegra210_amx *amx)50{51 int i;52 53 regmap_write(amx->regmap, TEGRA210_AMX_CFG_RAM_CTRL,54 TEGRA210_AMX_CFG_RAM_CTRL_SEQ_ACCESS_EN |55 TEGRA210_AMX_CFG_RAM_CTRL_ADDR_INIT_EN |56 TEGRA210_AMX_CFG_RAM_CTRL_RW_WRITE);57 58 for (i = 0; i < TEGRA210_AMX_RAM_DEPTH; i++)59 regmap_write(amx->regmap, TEGRA210_AMX_CFG_RAM_DATA,60 amx->map[i]);61 62 regmap_write(amx->regmap, TEGRA210_AMX_OUT_BYTE_EN0, amx->byte_mask[0]);63 regmap_write(amx->regmap, TEGRA210_AMX_OUT_BYTE_EN1, amx->byte_mask[1]);64}65 66static int tegra210_amx_startup(struct snd_pcm_substream *substream,67 struct snd_soc_dai *dai)68{69 struct tegra210_amx *amx = snd_soc_dai_get_drvdata(dai);70 unsigned int val;71 int err;72 73 /* Ensure if AMX is disabled */74 err = regmap_read_poll_timeout(amx->regmap, TEGRA210_AMX_STATUS, val,75 !(val & 0x1), 10, 10000);76 if (err < 0) {77 dev_err(dai->dev, "failed to stop AMX, err = %d\n", err);78 return err;79 }80 81 /*82 * Soft Reset: Below performs module soft reset which clears83 * all FSM logic, flushes flow control of FIFO and resets the84 * state register. It also brings module back to disabled85 * state (without flushing the data in the pipe).86 */87 regmap_update_bits(amx->regmap, TEGRA210_AMX_SOFT_RESET,88 TEGRA210_AMX_SOFT_RESET_SOFT_RESET_MASK,89 TEGRA210_AMX_SOFT_RESET_SOFT_EN);90 91 err = regmap_read_poll_timeout(amx->regmap, TEGRA210_AMX_SOFT_RESET,92 val, !(val & 0x1), 10, 10000);93 if (err < 0) {94 dev_err(dai->dev, "failed to reset AMX, err = %d\n", err);95 return err;96 }97 98 return 0;99}100 101static int __maybe_unused tegra210_amx_runtime_suspend(struct device *dev)102{103 struct tegra210_amx *amx = dev_get_drvdata(dev);104 105 regcache_cache_only(amx->regmap, true);106 regcache_mark_dirty(amx->regmap);107 108 return 0;109}110 111static int __maybe_unused tegra210_amx_runtime_resume(struct device *dev)112{113 struct tegra210_amx *amx = dev_get_drvdata(dev);114 115 regcache_cache_only(amx->regmap, false);116 regcache_sync(amx->regmap);117 118 regmap_update_bits(amx->regmap,119 TEGRA210_AMX_CTRL,120 TEGRA210_AMX_CTRL_RX_DEP_MASK,121 TEGRA210_AMX_WAIT_ON_ANY << TEGRA210_AMX_CTRL_RX_DEP_SHIFT);122 123 tegra210_amx_write_map_ram(amx);124 125 return 0;126}127 128static int tegra210_amx_set_audio_cif(struct snd_soc_dai *dai,129 struct snd_pcm_hw_params *params,130 unsigned int reg)131{132 struct tegra210_amx *amx = snd_soc_dai_get_drvdata(dai);133 int channels, audio_bits;134 struct tegra_cif_conf cif_conf;135 136 memset(&cif_conf, 0, sizeof(struct tegra_cif_conf));137 138 channels = params_channels(params);139 140 switch (params_format(params)) {141 case SNDRV_PCM_FORMAT_S8:142 audio_bits = TEGRA_ACIF_BITS_8;143 break;144 case SNDRV_PCM_FORMAT_S16_LE:145 audio_bits = TEGRA_ACIF_BITS_16;146 break;147 case SNDRV_PCM_FORMAT_S32_LE:148 audio_bits = TEGRA_ACIF_BITS_32;149 break;150 default:151 return -EINVAL;152 }153 154 cif_conf.audio_ch = channels;155 cif_conf.client_ch = channels;156 cif_conf.audio_bits = audio_bits;157 cif_conf.client_bits = audio_bits;158 159 tegra_set_cif(amx->regmap, reg, &cif_conf);160 161 return 0;162}163 164static int tegra210_amx_in_hw_params(struct snd_pcm_substream *substream,165 struct snd_pcm_hw_params *params,166 struct snd_soc_dai *dai)167{168 struct tegra210_amx *amx = snd_soc_dai_get_drvdata(dai);169 170 if (amx->soc_data->auto_disable) {171 regmap_write(amx->regmap,172 AMX_CH_REG(dai->id, TEGRA194_AMX_RX1_FRAME_PERIOD),173 TEGRA194_MAX_FRAME_IDLE_COUNT);174 regmap_write(amx->regmap, TEGRA210_AMX_CYA, 1);175 }176 177 return tegra210_amx_set_audio_cif(dai, params,178 AMX_CH_REG(dai->id, TEGRA210_AMX_RX1_CIF_CTRL));179}180 181static int tegra210_amx_out_hw_params(struct snd_pcm_substream *substream,182 struct snd_pcm_hw_params *params,183 struct snd_soc_dai *dai)184{185 return tegra210_amx_set_audio_cif(dai, params,186 TEGRA210_AMX_TX_CIF_CTRL);187}188 189static int tegra210_amx_get_byte_map(struct snd_kcontrol *kcontrol,190 struct snd_ctl_elem_value *ucontrol)191{192 struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);193 struct soc_mixer_control *mc =194 (struct soc_mixer_control *)kcontrol->private_value;195 struct tegra210_amx *amx = snd_soc_component_get_drvdata(cmpnt);196 unsigned char *bytes_map = (unsigned char *)&amx->map;197 int reg = mc->reg;198 int enabled;199 200 if (reg > 31)201 enabled = amx->byte_mask[1] & (1 << (reg - 32));202 else203 enabled = amx->byte_mask[0] & (1 << reg);204 205 /*206 * TODO: Simplify this logic to just return from bytes_map[]207 *208 * Presently below is required since bytes_map[] is209 * tightly packed and cannot store the control value of 256.210 * Byte mask state is used to know if 256 needs to be returned.211 * Note that for control value of 256, the put() call stores 0212 * in the bytes_map[] and disables the corresponding bit in213 * byte_mask[].214 */215 if (enabled)216 ucontrol->value.integer.value[0] = bytes_map[reg];217 else218 ucontrol->value.integer.value[0] = 256;219 220 return 0;221}222 223static int tegra210_amx_put_byte_map(struct snd_kcontrol *kcontrol,224 struct snd_ctl_elem_value *ucontrol)225{226 struct soc_mixer_control *mc =227 (struct soc_mixer_control *)kcontrol->private_value;228 struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);229 struct tegra210_amx *amx = snd_soc_component_get_drvdata(cmpnt);230 unsigned char *bytes_map = (unsigned char *)&amx->map;231 int reg = mc->reg;232 int value = ucontrol->value.integer.value[0];233 unsigned int mask_val = amx->byte_mask[reg / 32];234 235 if (value >= 0 && value <= 255)236 mask_val |= (1 << (reg % 32));237 else238 mask_val &= ~(1 << (reg % 32));239 240 if (mask_val == amx->byte_mask[reg / 32])241 return 0;242 243 /* Update byte map and slot */244 bytes_map[reg] = value % 256;245 amx->byte_mask[reg / 32] = mask_val;246 247 return 1;248}249 250static const struct snd_soc_dai_ops tegra210_amx_out_dai_ops = {251 .hw_params = tegra210_amx_out_hw_params,252 .startup = tegra210_amx_startup,253};254 255static const struct snd_soc_dai_ops tegra210_amx_in_dai_ops = {256 .hw_params = tegra210_amx_in_hw_params,257};258 259#define IN_DAI(id) \260 { \261 .name = "AMX-RX-CIF" #id, \262 .playback = { \263 .stream_name = "RX" #id "-CIF-Playback",\264 .channels_min = 1, \265 .channels_max = 16, \266 .rates = SNDRV_PCM_RATE_8000_192000, \267 .formats = SNDRV_PCM_FMTBIT_S8 | \268 SNDRV_PCM_FMTBIT_S16_LE | \269 SNDRV_PCM_FMTBIT_S32_LE, \270 }, \271 .capture = { \272 .stream_name = "RX" #id "-CIF-Capture", \273 .channels_min = 1, \274 .channels_max = 16, \275 .rates = SNDRV_PCM_RATE_8000_192000, \276 .formats = SNDRV_PCM_FMTBIT_S8 | \277 SNDRV_PCM_FMTBIT_S16_LE | \278 SNDRV_PCM_FMTBIT_S32_LE, \279 }, \280 .ops = &tegra210_amx_in_dai_ops, \281 }282 283#define OUT_DAI \284 { \285 .name = "AMX-TX-CIF", \286 .playback = { \287 .stream_name = "TX-CIF-Playback", \288 .channels_min = 1, \289 .channels_max = 16, \290 .rates = SNDRV_PCM_RATE_8000_192000, \291 .formats = SNDRV_PCM_FMTBIT_S8 | \292 SNDRV_PCM_FMTBIT_S16_LE | \293 SNDRV_PCM_FMTBIT_S32_LE, \294 }, \295 .capture = { \296 .stream_name = "TX-CIF-Capture", \297 .channels_min = 1, \298 .channels_max = 16, \299 .rates = SNDRV_PCM_RATE_8000_192000, \300 .formats = SNDRV_PCM_FMTBIT_S8 | \301 SNDRV_PCM_FMTBIT_S16_LE | \302 SNDRV_PCM_FMTBIT_S32_LE, \303 }, \304 .ops = &tegra210_amx_out_dai_ops, \305 }306 307static struct snd_soc_dai_driver tegra210_amx_dais[] = {308 IN_DAI(1),309 IN_DAI(2),310 IN_DAI(3),311 IN_DAI(4),312 OUT_DAI,313};314 315static const struct snd_soc_dapm_widget tegra210_amx_widgets[] = {316 SND_SOC_DAPM_AIF_IN("RX1", NULL, 0, TEGRA210_AMX_CTRL, 0, 0),317 SND_SOC_DAPM_AIF_IN("RX2", NULL, 0, TEGRA210_AMX_CTRL, 1, 0),318 SND_SOC_DAPM_AIF_IN("RX3", NULL, 0, TEGRA210_AMX_CTRL, 2, 0),319 SND_SOC_DAPM_AIF_IN("RX4", NULL, 0, TEGRA210_AMX_CTRL, 3, 0),320 SND_SOC_DAPM_AIF_OUT("TX", NULL, 0, TEGRA210_AMX_ENABLE,321 TEGRA210_AMX_ENABLE_SHIFT, 0),322};323 324#define STREAM_ROUTES(id, sname) \325 { "RX" #id " XBAR-" sname, NULL, "RX" #id " XBAR-TX" }, \326 { "RX" #id "-CIF-" sname, NULL, "RX" #id " XBAR-" sname },\327 { "RX" #id, NULL, "RX" #id "-CIF-" sname }, \328 { "TX", NULL, "RX" #id }, \329 { "TX-CIF-" sname, NULL, "TX" }, \330 { "XBAR-" sname, NULL, "TX-CIF-" sname }, \331 { "XBAR-RX", NULL, "XBAR-" sname }332 333#define AMX_ROUTES(id) \334 STREAM_ROUTES(id, "Playback"), \335 STREAM_ROUTES(id, "Capture")336 337static const struct snd_soc_dapm_route tegra210_amx_routes[] = {338 AMX_ROUTES(1),339 AMX_ROUTES(2),340 AMX_ROUTES(3),341 AMX_ROUTES(4),342};343 344#define TEGRA210_AMX_BYTE_MAP_CTRL(reg) \345 SOC_SINGLE_EXT("Byte Map " #reg, reg, 0, 256, 0, \346 tegra210_amx_get_byte_map, \347 tegra210_amx_put_byte_map)348 349static struct snd_kcontrol_new tegra210_amx_controls[] = {350 TEGRA210_AMX_BYTE_MAP_CTRL(0),351 TEGRA210_AMX_BYTE_MAP_CTRL(1),352 TEGRA210_AMX_BYTE_MAP_CTRL(2),353 TEGRA210_AMX_BYTE_MAP_CTRL(3),354 TEGRA210_AMX_BYTE_MAP_CTRL(4),355 TEGRA210_AMX_BYTE_MAP_CTRL(5),356 TEGRA210_AMX_BYTE_MAP_CTRL(6),357 TEGRA210_AMX_BYTE_MAP_CTRL(7),358 TEGRA210_AMX_BYTE_MAP_CTRL(8),359 TEGRA210_AMX_BYTE_MAP_CTRL(9),360 TEGRA210_AMX_BYTE_MAP_CTRL(10),361 TEGRA210_AMX_BYTE_MAP_CTRL(11),362 TEGRA210_AMX_BYTE_MAP_CTRL(12),363 TEGRA210_AMX_BYTE_MAP_CTRL(13),364 TEGRA210_AMX_BYTE_MAP_CTRL(14),365 TEGRA210_AMX_BYTE_MAP_CTRL(15),366 TEGRA210_AMX_BYTE_MAP_CTRL(16),367 TEGRA210_AMX_BYTE_MAP_CTRL(17),368 TEGRA210_AMX_BYTE_MAP_CTRL(18),369 TEGRA210_AMX_BYTE_MAP_CTRL(19),370 TEGRA210_AMX_BYTE_MAP_CTRL(20),371 TEGRA210_AMX_BYTE_MAP_CTRL(21),372 TEGRA210_AMX_BYTE_MAP_CTRL(22),373 TEGRA210_AMX_BYTE_MAP_CTRL(23),374 TEGRA210_AMX_BYTE_MAP_CTRL(24),375 TEGRA210_AMX_BYTE_MAP_CTRL(25),376 TEGRA210_AMX_BYTE_MAP_CTRL(26),377 TEGRA210_AMX_BYTE_MAP_CTRL(27),378 TEGRA210_AMX_BYTE_MAP_CTRL(28),379 TEGRA210_AMX_BYTE_MAP_CTRL(29),380 TEGRA210_AMX_BYTE_MAP_CTRL(30),381 TEGRA210_AMX_BYTE_MAP_CTRL(31),382 TEGRA210_AMX_BYTE_MAP_CTRL(32),383 TEGRA210_AMX_BYTE_MAP_CTRL(33),384 TEGRA210_AMX_BYTE_MAP_CTRL(34),385 TEGRA210_AMX_BYTE_MAP_CTRL(35),386 TEGRA210_AMX_BYTE_MAP_CTRL(36),387 TEGRA210_AMX_BYTE_MAP_CTRL(37),388 TEGRA210_AMX_BYTE_MAP_CTRL(38),389 TEGRA210_AMX_BYTE_MAP_CTRL(39),390 TEGRA210_AMX_BYTE_MAP_CTRL(40),391 TEGRA210_AMX_BYTE_MAP_CTRL(41),392 TEGRA210_AMX_BYTE_MAP_CTRL(42),393 TEGRA210_AMX_BYTE_MAP_CTRL(43),394 TEGRA210_AMX_BYTE_MAP_CTRL(44),395 TEGRA210_AMX_BYTE_MAP_CTRL(45),396 TEGRA210_AMX_BYTE_MAP_CTRL(46),397 TEGRA210_AMX_BYTE_MAP_CTRL(47),398 TEGRA210_AMX_BYTE_MAP_CTRL(48),399 TEGRA210_AMX_BYTE_MAP_CTRL(49),400 TEGRA210_AMX_BYTE_MAP_CTRL(50),401 TEGRA210_AMX_BYTE_MAP_CTRL(51),402 TEGRA210_AMX_BYTE_MAP_CTRL(52),403 TEGRA210_AMX_BYTE_MAP_CTRL(53),404 TEGRA210_AMX_BYTE_MAP_CTRL(54),405 TEGRA210_AMX_BYTE_MAP_CTRL(55),406 TEGRA210_AMX_BYTE_MAP_CTRL(56),407 TEGRA210_AMX_BYTE_MAP_CTRL(57),408 TEGRA210_AMX_BYTE_MAP_CTRL(58),409 TEGRA210_AMX_BYTE_MAP_CTRL(59),410 TEGRA210_AMX_BYTE_MAP_CTRL(60),411 TEGRA210_AMX_BYTE_MAP_CTRL(61),412 TEGRA210_AMX_BYTE_MAP_CTRL(62),413 TEGRA210_AMX_BYTE_MAP_CTRL(63),414};415 416static const struct snd_soc_component_driver tegra210_amx_cmpnt = {417 .dapm_widgets = tegra210_amx_widgets,418 .num_dapm_widgets = ARRAY_SIZE(tegra210_amx_widgets),419 .dapm_routes = tegra210_amx_routes,420 .num_dapm_routes = ARRAY_SIZE(tegra210_amx_routes),421 .controls = tegra210_amx_controls,422 .num_controls = ARRAY_SIZE(tegra210_amx_controls),423};424 425static bool tegra210_amx_wr_reg(struct device *dev, unsigned int reg)426{427 switch (reg) {428 case TEGRA210_AMX_RX_INT_MASK ... TEGRA210_AMX_RX4_CIF_CTRL:429 case TEGRA210_AMX_TX_INT_MASK ... TEGRA210_AMX_CG:430 case TEGRA210_AMX_CTRL ... TEGRA210_AMX_CYA:431 case TEGRA210_AMX_CFG_RAM_CTRL ... TEGRA210_AMX_CFG_RAM_DATA:432 return true;433 default:434 return false;435 }436}437 438static bool tegra194_amx_wr_reg(struct device *dev, unsigned int reg)439{440 switch (reg) {441 case TEGRA194_AMX_RX1_FRAME_PERIOD ... TEGRA194_AMX_RX4_FRAME_PERIOD:442 return true;443 default:444 return tegra210_amx_wr_reg(dev, reg);445 }446}447 448static bool tegra210_amx_rd_reg(struct device *dev, unsigned int reg)449{450 switch (reg) {451 case TEGRA210_AMX_RX_STATUS ... TEGRA210_AMX_CFG_RAM_DATA:452 return true;453 default:454 return false;455 }456}457 458static bool tegra194_amx_rd_reg(struct device *dev, unsigned int reg)459{460 switch (reg) {461 case TEGRA194_AMX_RX1_FRAME_PERIOD ... TEGRA194_AMX_RX4_FRAME_PERIOD:462 return true;463 default:464 return tegra210_amx_rd_reg(dev, reg);465 }466}467 468static bool tegra210_amx_volatile_reg(struct device *dev, unsigned int reg)469{470 switch (reg) {471 case TEGRA210_AMX_RX_STATUS:472 case TEGRA210_AMX_RX_INT_STATUS:473 case TEGRA210_AMX_RX_INT_SET:474 case TEGRA210_AMX_TX_STATUS:475 case TEGRA210_AMX_TX_INT_STATUS:476 case TEGRA210_AMX_TX_INT_SET:477 case TEGRA210_AMX_SOFT_RESET:478 case TEGRA210_AMX_STATUS:479 case TEGRA210_AMX_INT_STATUS:480 case TEGRA210_AMX_CFG_RAM_CTRL:481 case TEGRA210_AMX_CFG_RAM_DATA:482 return true;483 default:484 break;485 }486 487 return false;488}489 490static const struct regmap_config tegra210_amx_regmap_config = {491 .reg_bits = 32,492 .reg_stride = 4,493 .val_bits = 32,494 .max_register = TEGRA210_AMX_CFG_RAM_DATA,495 .writeable_reg = tegra210_amx_wr_reg,496 .readable_reg = tegra210_amx_rd_reg,497 .volatile_reg = tegra210_amx_volatile_reg,498 .reg_defaults = tegra210_amx_reg_defaults,499 .num_reg_defaults = ARRAY_SIZE(tegra210_amx_reg_defaults),500 .cache_type = REGCACHE_FLAT,501};502 503static const struct regmap_config tegra194_amx_regmap_config = {504 .reg_bits = 32,505 .reg_stride = 4,506 .val_bits = 32,507 .max_register = TEGRA194_AMX_RX4_LAST_FRAME_PERIOD,508 .writeable_reg = tegra194_amx_wr_reg,509 .readable_reg = tegra194_amx_rd_reg,510 .volatile_reg = tegra210_amx_volatile_reg,511 .reg_defaults = tegra210_amx_reg_defaults,512 .num_reg_defaults = ARRAY_SIZE(tegra210_amx_reg_defaults),513 .cache_type = REGCACHE_FLAT,514};515 516static const struct tegra210_amx_soc_data soc_data_tegra210 = {517 .regmap_conf = &tegra210_amx_regmap_config,518};519 520static const struct tegra210_amx_soc_data soc_data_tegra194 = {521 .regmap_conf = &tegra194_amx_regmap_config,522 .auto_disable = true,523};524 525static const struct of_device_id tegra210_amx_of_match[] = {526 { .compatible = "nvidia,tegra210-amx", .data = &soc_data_tegra210 },527 { .compatible = "nvidia,tegra194-amx", .data = &soc_data_tegra194 },528 {},529};530MODULE_DEVICE_TABLE(of, tegra210_amx_of_match);531 532static int tegra210_amx_platform_probe(struct platform_device *pdev)533{534 struct device *dev = &pdev->dev;535 struct tegra210_amx *amx;536 void __iomem *regs;537 int err;538 539 amx = devm_kzalloc(dev, sizeof(*amx), GFP_KERNEL);540 if (!amx)541 return -ENOMEM;542 543 amx->soc_data = device_get_match_data(dev);544 545 dev_set_drvdata(dev, amx);546 547 regs = devm_platform_ioremap_resource(pdev, 0);548 if (IS_ERR(regs))549 return PTR_ERR(regs);550 551 amx->regmap = devm_regmap_init_mmio(dev, regs,552 amx->soc_data->regmap_conf);553 if (IS_ERR(amx->regmap)) {554 dev_err(dev, "regmap init failed\n");555 return PTR_ERR(amx->regmap);556 }557 558 regcache_cache_only(amx->regmap, true);559 560 err = devm_snd_soc_register_component(dev, &tegra210_amx_cmpnt,561 tegra210_amx_dais,562 ARRAY_SIZE(tegra210_amx_dais));563 if (err) {564 dev_err(dev, "can't register AMX component, err: %d\n", err);565 return err;566 }567 568 pm_runtime_enable(dev);569 570 return 0;571}572 573static void tegra210_amx_platform_remove(struct platform_device *pdev)574{575 pm_runtime_disable(&pdev->dev);576}577 578static const struct dev_pm_ops tegra210_amx_pm_ops = {579 SET_RUNTIME_PM_OPS(tegra210_amx_runtime_suspend,580 tegra210_amx_runtime_resume, NULL)581 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,582 pm_runtime_force_resume)583};584 585static struct platform_driver tegra210_amx_driver = {586 .driver = {587 .name = "tegra210-amx",588 .of_match_table = tegra210_amx_of_match,589 .pm = &tegra210_amx_pm_ops,590 },591 .probe = tegra210_amx_platform_probe,592 .remove = tegra210_amx_platform_remove,593};594module_platform_driver(tegra210_amx_driver);595 596MODULE_AUTHOR("Songhee Baek <sbaek@nvidia.com>");597MODULE_DESCRIPTION("Tegra210 AMX ASoC driver");598MODULE_LICENSE("GPL v2");599